diff options
author | Richard Zhao <rizhao@nvidia.com> | 2017-12-06 19:25:21 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-12-11 19:42:08 -0500 |
commit | 3cb9cd5267074b42b7ecd7e1c21c61b2589b4932 (patch) | |
tree | 6d96809dea46b0f7f6c4b4f08a790fa23dfe1892 | |
parent | 258ae4471296bcee03987778e3b7c79d3a027e53 (diff) |
gpu: nvgpu: vgpu: remove PMU setup in gv11b hal
vgpu doesn't care about pmu. pmu is managed by RM server.
It also fixed the dump caused by reading fuse register.
Jira EVLR-1934
Change-Id: I779964950783ccf699cd99473fb30e811c5c2ed6
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1612774
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c | 51 |
1 files changed, 0 insertions, 51 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c index 079b4cb9..7372a956 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c | |||
@@ -559,8 +559,6 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
559 | int vgpu_gv11b_init_hal(struct gk20a *g) | 559 | int vgpu_gv11b_init_hal(struct gk20a *g) |
560 | { | 560 | { |
561 | struct gpu_ops *gops = &g->ops; | 561 | struct gpu_ops *gops = &g->ops; |
562 | u32 val; | ||
563 | bool priv_security; | ||
564 | 562 | ||
565 | gops->ltc = vgpu_gv11b_ops.ltc; | 563 | gops->ltc = vgpu_gv11b_ops.ltc; |
566 | gops->ce2 = vgpu_gv11b_ops.ce2; | 564 | gops->ce2 = vgpu_gv11b_ops.ce2; |
@@ -589,55 +587,6 @@ int vgpu_gv11b_init_hal(struct gk20a *g) | |||
589 | vgpu_gv11b_ops.chip_init_gpu_characteristics; | 587 | vgpu_gv11b_ops.chip_init_gpu_characteristics; |
590 | gops->get_litter_value = vgpu_gv11b_ops.get_litter_value; | 588 | gops->get_litter_value = vgpu_gv11b_ops.get_litter_value; |
591 | 589 | ||
592 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); | ||
593 | if (val) { | ||
594 | priv_security = true; | ||
595 | pr_err("priv security is enabled\n"); | ||
596 | } else { | ||
597 | priv_security = false; | ||
598 | pr_err("priv security is disabled\n"); | ||
599 | } | ||
600 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, false); | ||
601 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, priv_security); | ||
602 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, priv_security); | ||
603 | |||
604 | /* priv security dependent ops */ | ||
605 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { | ||
606 | /* Add in ops from gm20b acr */ | ||
607 | gops->pmu.prepare_ucode = gp106_prepare_ucode_blob, | ||
608 | gops->pmu.pmu_setup_hw_and_bootstrap = gv11b_bootstrap_hs_flcn, | ||
609 | gops->pmu.get_wpr = gm20b_wpr_info, | ||
610 | gops->pmu.alloc_blob_space = gm20b_alloc_blob_space, | ||
611 | gops->pmu.pmu_populate_loader_cfg = | ||
612 | gp106_pmu_populate_loader_cfg, | ||
613 | gops->pmu.flcn_populate_bl_dmem_desc = | ||
614 | gp106_flcn_populate_bl_dmem_desc, | ||
615 | gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt, | ||
616 | gops->pmu.falcon_clear_halt_interrupt_status = | ||
617 | clear_halt_interrupt_status, | ||
618 | gops->pmu.init_falcon_setup_hw = gv11b_init_pmu_setup_hw1, | ||
619 | |||
620 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; | ||
621 | gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; | ||
622 | gops->pmu.is_lazy_bootstrap = gv11b_is_lazy_bootstrap, | ||
623 | gops->pmu.is_priv_load = gv11b_is_priv_load, | ||
624 | |||
625 | gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode; | ||
626 | } else { | ||
627 | /* Inherit from gk20a */ | ||
628 | gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob, | ||
629 | gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1, | ||
630 | |||
631 | gops->pmu.load_lsfalcon_ucode = NULL; | ||
632 | gops->pmu.init_wpr_region = NULL; | ||
633 | gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1; | ||
634 | |||
635 | gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode; | ||
636 | } | ||
637 | |||
638 | __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); | ||
639 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; | ||
640 | |||
641 | g->name = "gv11b"; | 590 | g->name = "gv11b"; |
642 | 591 | ||
643 | return 0; | 592 | return 0; |