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authorTerje Bergstrom <tbergstrom@nvidia.com>2015-06-03 18:53:12 -0400
committerDeepak Nibade <dnibade@nvidia.com>2016-12-27 04:52:06 -0500
commit3b5a1295fa7b19296da4b370a08025d0bc6f5998 (patch)
tree590495aec1341edf041b90e2574ee6d28783c942
parent910bb6ad0d326e13b16da5ee0d06f4007cc9439e (diff)
gpu: nvgpu: gp10b: Disable RE suppression
Bug 1642669 Change-Id: I683338256b7f2a165a7933aa59de510eb109ea6f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/755150 Reviewed-by: Automatic_Commit_Validation_User
-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_gp10b.c5
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h16
2 files changed, 21 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 265cad66..1942b1e7 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -916,6 +916,11 @@ static int gr_gp10b_init_fs_state(struct gk20a *g)
916 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f()); 916 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f());
917 gk20a_writel(g, gr_gpcs_tpcs_sm_texio_control_r(), data); 917 gk20a_writel(g, gr_gpcs_tpcs_sm_texio_control_r(), data);
918 918
919 data = gk20a_readl(g, gr_gpcs_tpcs_sm_disp_ctrl_r());
920 data = set_field(data, gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(),
921 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f());
922 gk20a_writel(g, gr_gpcs_tpcs_sm_disp_ctrl_r(), data);
923
919 return gr_gm20b_ctx_state_floorsweep(g); 924 return gr_gm20b_ctx_state_floorsweep(g);
920} 925}
921 926
diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index 54d21eb3..6e4f7d1a 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -3766,8 +3766,24 @@ static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v)
3766{ 3766{
3767 return (v & 0x7) << 8; 3767 return (v & 0x7) << 8;
3768} 3768}
3769static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void)
3770{
3771 return 0x7 << 8;
3772}
3769static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void) 3773static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void)
3770{ 3774{
3771 return 0x100; 3775 return 0x100;
3772} 3776}
3777static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void)
3778{
3779 return 0x00419f78;
3780}
3781static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void)
3782{
3783 return 0x3 << 11;
3784}
3785static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void)
3786{
3787 return 0x1000;
3788}
3773#endif 3789#endif