gpu: nvgpu: Move FBPA interrupt HAL to MC

FBPA interrupt is reported via a register in MC. Move the HAL
dealing with that interrupt to MC.

JIRA NVGPU-954

Change-Id: Ic2b8439e82788f851536bcbb5cba6580f4d5ee7e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1813520
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 4 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/common/mc/mc_gp10b.c b/drivers/gpu/nvgpu/common/mc/mc_gp10b.c
index a0f26dd3..3dce9a09 100644
--- a/drivers/gpu/nvgpu/common/mc/mc_gp10b.c
+++ b/drivers/gpu/nvgpu/common/mc/mc_gp10b.c
@@ -144,8 +144,8 @@ void mc_gp10b_isr_stall(struct gk20a *g)
                         g->ops.mc.is_intr_nvlink_pending(g, mc_intr_0)) {
                 g->ops.nvlink.isr(g);
         }
-        if (mc_intr_0 & mc_intr_pfb_pending_f() && g->ops.fb.fbpa_isr) {
-                g->ops.fb.fbpa_isr(g);
+        if (mc_intr_0 & mc_intr_pfb_pending_f() && g->ops.mc.fbpa_isr) {
+                g->ops.mc.fbpa_isr(g);
         }
 
         nvgpu_log(g, gpu_dbg_intr, "stall intr done 0x%08x\n", mc_intr_0);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index 56b14245..0230709c 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -560,7 +560,7 @@ struct gpu_ops {
                 void (*enable_hub_intr)(struct gk20a *g);
                 void (*disable_hub_intr)(struct gk20a *g);
                 int (*init_fbpa)(struct gk20a *g);
-                void (*fbpa_isr)(struct gk20a *g);
+                void (*handle_fbpa_intr)(struct gk20a *g, u32 fbpa_id);
                 void (*write_mmu_fault_buffer_lo_hi)(struct gk20a *g, u32 index,
                         u32 addr_lo, u32 addr_hi);
                 void (*write_mmu_fault_buffer_get)(struct gk20a *g, u32 index,
@@ -1168,6 +1168,7 @@ struct gpu_ops {
                 void (*reset)(struct gk20a *g, u32 units);
                 bool (*is_intr1_pending)(struct gk20a *g, enum nvgpu_unit unit, u32 mc_intr_1);
                 void (*log_pending_intrs)(struct gk20a *g);
+                void (*fbpa_isr)(struct gk20a *g);
         } mc;
         struct {
                 void (*show_dump)(struct gk20a *g,