gpu: nvgpu: Add GM20B GPCPLL h/w definitions

Expanded GM20B GPCPLL definitions of DVFS registers.

Bug 1450787

Change-Id: I51d049be70badfedd8c451019b10770b4fb31e80
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/499487
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

1 files changed, 8 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/hw_trim_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_trim_gm20b.h
index bab9242c..e923e451 100644
--- a/drivers/gpu/nvgpu/gm20b/hw_trim_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/hw_trim_gm20b.h
@@ -318,6 +318,10 @@ static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_m(void)
 {
         return 0xff << 16;
 }
+static inline u32 trim_sys_gpcpll_cfg3_dfs_testout_v(u32 r)
+{
+        return (r >> 24) & 0x7f;
+}
 static inline u32 trim_sys_gpcpll_dvfs0_r(void)
 {
         return 0x00137010;
@@ -470,6 +474,10 @@ static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_syn
 {
         return (r >> 24) & 0x1;
 }
+static inline u32 trim_gpc_bcast_gpcpll_dvfs2_r(void)
+{
+        return 0x00132820;
+}
 static inline u32 trim_sys_bypassctrl_r(void)
 {
         return 0x00137340;