diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2017-03-17 18:40:34 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-03-28 18:55:48 -0400 |
commit | 3032acfc04f5c483dc08434f27f9912e7dee72c9 (patch) | |
tree | 0ea68160c645a22c7c7955f8a1276411669c2b2a | |
parent | 9773dbf905acd7dbb7ebfbbdfae529ff6f9f8ab8 (diff) |
gpu: nvgpu: Move programming of host registers to fifo
Move code that touches host registers to fifo HAL. This sorts out
some of the dependencies between fifo HAL and channel HAL.
Change-Id: I2bff0443ae1c1fa5608e620974b440696d1cfdc4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1323385
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index bb9def35..2044bb22 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |||
@@ -19,6 +19,7 @@ | |||
19 | #include <nvgpu/timers.h> | 19 | #include <nvgpu/timers.h> |
20 | 20 | ||
21 | #include "gk20a/gk20a.h" | 21 | #include "gk20a/gk20a.h" |
22 | #include "gk20a/fifo_gk20a.h" | ||
22 | 23 | ||
23 | #include "gp10b/fifo_gp10b.h" | 24 | #include "gp10b/fifo_gp10b.h" |
24 | 25 | ||
@@ -105,7 +106,8 @@ static void gv11b_userd_writeback_config(struct gk20a *g) | |||
105 | } | 106 | } |
106 | 107 | ||
107 | static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, | 108 | static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, |
108 | u64 gpfifo_base, u32 gpfifo_entries, u32 flags) | 109 | u64 gpfifo_base, u32 gpfifo_entries, |
110 | unsigned long acquire_timeout, u32 flags) | ||
109 | { | 111 | { |
110 | struct gk20a *g = c->g; | 112 | struct gk20a *g = c->g; |
111 | struct mem_desc *mem = &c->inst_block; | 113 | struct mem_desc *mem = &c->inst_block; |
@@ -145,7 +147,7 @@ static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, | |||
145 | pbdma_target_engine_sw_f()); | 147 | pbdma_target_engine_sw_f()); |
146 | 148 | ||
147 | gk20a_mem_wr32(g, mem, ram_fc_acquire_w(), | 149 | gk20a_mem_wr32(g, mem, ram_fc_acquire_w(), |
148 | channel_gk20a_pbdma_acquire_val(c)); | 150 | g->ops.fifo.pbdma_acquire_val(acquire_timeout)); |
149 | 151 | ||
150 | gk20a_mem_wr32(g, mem, ram_fc_runlist_timeslice_w(), | 152 | gk20a_mem_wr32(g, mem, ram_fc_runlist_timeslice_w(), |
151 | pbdma_runlist_timeslice_timeout_128_f() | | 153 | pbdma_runlist_timeslice_timeout_128_f() | |
@@ -165,7 +167,7 @@ static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, | |||
165 | gk20a_mem_wr32(g, mem, ram_fc_config_w(), | 167 | gk20a_mem_wr32(g, mem, ram_fc_config_w(), |
166 | pbdma_config_auth_level_privileged_f()); | 168 | pbdma_config_auth_level_privileged_f()); |
167 | 169 | ||
168 | gk20a_channel_setup_ramfc_for_privileged_channel(c); | 170 | gk20a_fifo_setup_ramfc_for_privileged_channel(c); |
169 | } | 171 | } |
170 | 172 | ||
171 | /* Enable userd writeback */ | 173 | /* Enable userd writeback */ |
@@ -213,7 +215,7 @@ static void channel_gv11b_unbind(struct channel_gk20a *ch) | |||
213 | { | 215 | { |
214 | gk20a_dbg_fn(""); | 216 | gk20a_dbg_fn(""); |
215 | 217 | ||
216 | channel_gk20a_unbind(ch); | 218 | gk20a_fifo_channel_unbind(ch); |
217 | } | 219 | } |
218 | 220 | ||
219 | static u32 gv11b_fifo_get_num_fifos(struct gk20a *g) | 221 | static u32 gv11b_fifo_get_num_fifos(struct gk20a *g) |