diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-02-28 15:12:38 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-03-01 16:46:43 -0500 |
commit | 2cc03def6a6427acdebd8a6053b1309280e5fe9b (patch) | |
tree | 4031336bf5aa0457ece4695d397a6c3b293c85fa | |
parent | 207e2ac7d12e62df476f4828136a4c15e156f8a6 (diff) |
gpu: nvgpu: gv11b: update headers
generate headers for pri ring, pbdma intr and gmmu
with updated reg generator
JIRA GV11B-47
JIRA GV11B-7
Change-Id: Id198fb338c03acc52c523754cfd07db01ff9bffd
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1312756
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
7 files changed, 174 insertions, 17 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h index d2f22afa..45cb0ad5 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -826,6 +826,10 @@ static inline u32 fb_mmu_fault_buffer_get_ptr_f(u32 v) | |||
826 | { | 826 | { |
827 | return (v & 0xfffff) << 0; | 827 | return (v & 0xfffff) << 0; |
828 | } | 828 | } |
829 | static inline u32 fb_mmu_fault_buffer_get_ptr_m(void) | ||
830 | { | ||
831 | return 0xfffff << 0; | ||
832 | } | ||
829 | static inline u32 fb_mmu_fault_buffer_get_ptr_v(u32 r) | 833 | static inline u32 fb_mmu_fault_buffer_get_ptr_v(u32 r) |
830 | { | 834 | { |
831 | return (r >> 0) & 0xfffff; | 835 | return (r >> 0) & 0xfffff; |
@@ -1330,6 +1334,10 @@ static inline u32 fb_mmu_fault_status_replayable_set_f(void) | |||
1330 | { | 1334 | { |
1331 | return 0x100; | 1335 | return 0x100; |
1332 | } | 1336 | } |
1337 | static inline u32 fb_mmu_fault_status_replayable_reset_f(void) | ||
1338 | { | ||
1339 | return 0x0; | ||
1340 | } | ||
1333 | static inline u32 fb_mmu_fault_status_non_replayable_f(u32 v) | 1341 | static inline u32 fb_mmu_fault_status_non_replayable_f(u32 v) |
1334 | { | 1342 | { |
1335 | return (v & 0x1) << 9; | 1343 | return (v & 0x1) << 9; |
@@ -1346,6 +1354,10 @@ static inline u32 fb_mmu_fault_status_non_replayable_set_f(void) | |||
1346 | { | 1354 | { |
1347 | return 0x200; | 1355 | return 0x200; |
1348 | } | 1356 | } |
1357 | static inline u32 fb_mmu_fault_status_non_replayable_reset_f(void) | ||
1358 | { | ||
1359 | return 0x0; | ||
1360 | } | ||
1349 | static inline u32 fb_mmu_fault_status_replayable_error_f(u32 v) | 1361 | static inline u32 fb_mmu_fault_status_replayable_error_f(u32 v) |
1350 | { | 1362 | { |
1351 | return (v & 0x1) << 10; | 1363 | return (v & 0x1) << 10; |
@@ -1362,6 +1374,10 @@ static inline u32 fb_mmu_fault_status_replayable_error_set_f(void) | |||
1362 | { | 1374 | { |
1363 | return 0x400; | 1375 | return 0x400; |
1364 | } | 1376 | } |
1377 | static inline u32 fb_mmu_fault_status_replayable_error_reset_f(void) | ||
1378 | { | ||
1379 | return 0x0; | ||
1380 | } | ||
1365 | static inline u32 fb_mmu_fault_status_non_replayable_error_f(u32 v) | 1381 | static inline u32 fb_mmu_fault_status_non_replayable_error_f(u32 v) |
1366 | { | 1382 | { |
1367 | return (v & 0x1) << 11; | 1383 | return (v & 0x1) << 11; |
@@ -1378,6 +1394,10 @@ static inline u32 fb_mmu_fault_status_non_replayable_error_set_f(void) | |||
1378 | { | 1394 | { |
1379 | return 0x800; | 1395 | return 0x800; |
1380 | } | 1396 | } |
1397 | static inline u32 fb_mmu_fault_status_non_replayable_error_reset_f(void) | ||
1398 | { | ||
1399 | return 0x0; | ||
1400 | } | ||
1381 | static inline u32 fb_mmu_fault_status_replayable_overflow_f(u32 v) | 1401 | static inline u32 fb_mmu_fault_status_replayable_overflow_f(u32 v) |
1382 | { | 1402 | { |
1383 | return (v & 0x1) << 12; | 1403 | return (v & 0x1) << 12; |
@@ -1394,6 +1414,10 @@ static inline u32 fb_mmu_fault_status_replayable_overflow_set_f(void) | |||
1394 | { | 1414 | { |
1395 | return 0x1000; | 1415 | return 0x1000; |
1396 | } | 1416 | } |
1417 | static inline u32 fb_mmu_fault_status_replayable_overflow_reset_f(void) | ||
1418 | { | ||
1419 | return 0x0; | ||
1420 | } | ||
1397 | static inline u32 fb_mmu_fault_status_non_replayable_overflow_f(u32 v) | 1421 | static inline u32 fb_mmu_fault_status_non_replayable_overflow_f(u32 v) |
1398 | { | 1422 | { |
1399 | return (v & 0x1) << 13; | 1423 | return (v & 0x1) << 13; |
@@ -1410,6 +1434,10 @@ static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_f(void) | |||
1410 | { | 1434 | { |
1411 | return 0x2000; | 1435 | return 0x2000; |
1412 | } | 1436 | } |
1437 | static inline u32 fb_mmu_fault_status_non_replayable_overflow_reset_f(void) | ||
1438 | { | ||
1439 | return 0x0; | ||
1440 | } | ||
1413 | static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_f(u32 v) | 1441 | static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_f(u32 v) |
1414 | { | 1442 | { |
1415 | return (v & 0x1) << 14; | 1443 | return (v & 0x1) << 14; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h index d68c823a..911efa43 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -266,14 +266,6 @@ static inline u32 fifo_intr_chsw_error_r(void) | |||
266 | { | 266 | { |
267 | return 0x0000256c; | 267 | return 0x0000256c; |
268 | } | 268 | } |
269 | static inline u32 fifo_gpc_v(void) | ||
270 | { | ||
271 | return 0x00000000; | ||
272 | } | ||
273 | static inline u32 fifo_hub_v(void) | ||
274 | { | ||
275 | return 0x00000001; | ||
276 | } | ||
277 | static inline u32 fifo_intr_pbdma_id_r(void) | 269 | static inline u32 fifo_intr_pbdma_id_r(void) |
278 | { | 270 | { |
279 | return 0x000025a0; | 271 | return 0x000025a0; |
@@ -306,10 +298,6 @@ static inline u32 fifo_fb_timeout_period_max_f(void) | |||
306 | { | 298 | { |
307 | return 0x3fffffff; | 299 | return 0x3fffffff; |
308 | } | 300 | } |
309 | static inline u32 fifo_error_sched_disable_r(void) | ||
310 | { | ||
311 | return 0x0000262c; | ||
312 | } | ||
313 | static inline u32 fifo_sched_disable_r(void) | 301 | static inline u32 fifo_sched_disable_r(void) |
314 | { | 302 | { |
315 | return 0x00002630; | 303 | return 0x00002630; |
@@ -406,6 +394,10 @@ static inline u32 fifo_engine_status_next_id_type_chid_v(void) | |||
406 | { | 394 | { |
407 | return 0x00000000; | 395 | return 0x00000000; |
408 | } | 396 | } |
397 | static inline u32 fifo_engine_status_eng_reload_v(u32 r) | ||
398 | { | ||
399 | return (r >> 29) & 0x1; | ||
400 | } | ||
409 | static inline u32 fifo_engine_status_faulted_v(u32 r) | 401 | static inline u32 fifo_engine_status_faulted_v(u32 r) |
410 | { | 402 | { |
411 | return (r >> 30) & 0x1; | 403 | return (r >> 30) & 0x1; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h index 1c523f87..dc8473a5 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -1274,6 +1274,26 @@ static inline u32 gmmu_pte_kind_s8_2s_v(void) | |||
1274 | { | 1274 | { |
1275 | return 0x0000002b; | 1275 | return 0x0000002b; |
1276 | } | 1276 | } |
1277 | static inline u32 gmmu_fault_client_type_gpc_v(void) | ||
1278 | { | ||
1279 | return 0x00000000; | ||
1280 | } | ||
1281 | static inline u32 gmmu_fault_client_type_hub_v(void) | ||
1282 | { | ||
1283 | return 0x00000001; | ||
1284 | } | ||
1285 | static inline u32 gmmu_fault_type_unbound_inst_block_v(void) | ||
1286 | { | ||
1287 | return 0x00000004; | ||
1288 | } | ||
1289 | static inline u32 gmmu_fault_mmu_eng_id_bar2_v(void) | ||
1290 | { | ||
1291 | return 0x00000005; | ||
1292 | } | ||
1293 | static inline u32 gmmu_fault_mmu_eng_id_physical_v(void) | ||
1294 | { | ||
1295 | return 0x0000001f; | ||
1296 | } | ||
1277 | static inline u32 gmmu_fault_buf_size_v(void) | 1297 | static inline u32 gmmu_fault_buf_size_v(void) |
1278 | { | 1298 | { |
1279 | return 0x00000020; | 1299 | return 0x00000020; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h index 7aea3870..9c2ba7c6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h | |||
@@ -454,6 +454,10 @@ static inline u32 pbdma_intr_0_pbcrc_pending_f(void) | |||
454 | { | 454 | { |
455 | return 0x80000; | 455 | return 0x80000; |
456 | } | 456 | } |
457 | static inline u32 pbdma_intr_0_clear_faulted_error_pending_f(void) | ||
458 | { | ||
459 | return 0x100000; | ||
460 | } | ||
457 | static inline u32 pbdma_intr_0_method_pending_f(void) | 461 | static inline u32 pbdma_intr_0_method_pending_f(void) |
458 | { | 462 | { |
459 | return 0x200000; | 463 | return 0x200000; |
@@ -466,6 +470,10 @@ static inline u32 pbdma_intr_0_device_pending_f(void) | |||
466 | { | 470 | { |
467 | return 0x800000; | 471 | return 0x800000; |
468 | } | 472 | } |
473 | static inline u32 pbdma_intr_0_eng_reset_pending_f(void) | ||
474 | { | ||
475 | return 0x1000000; | ||
476 | } | ||
469 | static inline u32 pbdma_intr_0_semaphore_pending_f(void) | 477 | static inline u32 pbdma_intr_0_semaphore_pending_f(void) |
470 | { | 478 | { |
471 | return 0x2000000; | 479 | return 0x2000000; |
@@ -514,6 +522,10 @@ static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) | |||
514 | { | 522 | { |
515 | return 0x100; | 523 | return 0x100; |
516 | } | 524 | } |
525 | static inline u32 pbdma_intr_stall_1_r(u32 i) | ||
526 | { | ||
527 | return 0x00040140 + i*8192; | ||
528 | } | ||
517 | static inline u32 pbdma_udma_nop_r(void) | 529 | static inline u32 pbdma_udma_nop_r(void) |
518 | { | 530 | { |
519 | return 0x00000008; | 531 | return 0x00000008; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h index 835366c1..ce9e53ee 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -102,6 +102,22 @@ static inline u32 pri_ringmaster_intr_status0_r(void) | |||
102 | { | 102 | { |
103 | return 0x00120058; | 103 | return 0x00120058; |
104 | } | 104 | } |
105 | static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r) | ||
106 | { | ||
107 | return (r >> 0) & 0x1; | ||
108 | } | ||
109 | static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r) | ||
110 | { | ||
111 | return (r >> 1) & 0x1; | ||
112 | } | ||
113 | static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r) | ||
114 | { | ||
115 | return (r >> 2) & 0x1; | ||
116 | } | ||
117 | static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r) | ||
118 | { | ||
119 | return (r >> 8) & 0x1; | ||
120 | } | ||
105 | static inline u32 pri_ringmaster_intr_status1_r(void) | 121 | static inline u32 pri_ringmaster_intr_status1_r(void) |
106 | { | 122 | { |
107 | return 0x0012005c; | 123 | return 0x0012005c; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h new file mode 100644 index 00000000..89abfa3c --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h | |||
@@ -0,0 +1,73 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_pri_ringstation_gpc_gv11b_h_ | ||
51 | #define _hw_pri_ringstation_gpc_gv11b_h_ | ||
52 | |||
53 | static inline u32 pri_ringstation_gpc_master_config_r(u32 i) | ||
54 | { | ||
55 | return 0x00128300 + i*4; | ||
56 | } | ||
57 | static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void) | ||
58 | { | ||
59 | return 0x00128120; | ||
60 | } | ||
61 | static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void) | ||
62 | { | ||
63 | return 0x00128124; | ||
64 | } | ||
65 | static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void) | ||
66 | { | ||
67 | return 0x00128128; | ||
68 | } | ||
69 | static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void) | ||
70 | { | ||
71 | return 0x0012812c; | ||
72 | } | ||
73 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h index e192bd13..ae6ad795 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -66,4 +66,20 @@ static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_starte | |||
66 | { | 66 | { |
67 | return 0x1; | 67 | return 0x1; |
68 | } | 68 | } |
69 | static inline u32 pri_ringstation_sys_priv_error_adr_r(void) | ||
70 | { | ||
71 | return 0x00122120; | ||
72 | } | ||
73 | static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void) | ||
74 | { | ||
75 | return 0x00122124; | ||
76 | } | ||
77 | static inline u32 pri_ringstation_sys_priv_error_info_r(void) | ||
78 | { | ||
79 | return 0x00122128; | ||
80 | } | ||
81 | static inline u32 pri_ringstation_sys_priv_error_code_r(void) | ||
82 | { | ||
83 | return 0x0012212c; | ||
84 | } | ||
69 | #endif | 85 | #endif |