gpu: nvgpu: add fault_ch to record_sm_error_state

fault_ch is needed by rm-server to send the notification to guest VM.
rm-server is going to use gr sources from linux

Jira VQRM-2982

Change-Id: Ifb6e8a9630a471d07b89ffaa7f2ceb309220fd21
Signed-off-by: Shashank Singh <shashsingh@nvidia.com>
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1661665
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

6 files changed, 11 insertions, 7 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index ea55c664..9a0cfd02 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -365,8 +365,8 @@ struct gpu_ops {
                 void (*enable_exceptions)(struct gk20a *g);
                 void (*create_gr_sysfs)(struct gk20a *g);
                 u32 (*get_lrf_tex_ltc_dram_override)(struct gk20a *g);
-                int (*record_sm_error_state)(struct gk20a *g,
-                                u32 gpc, u32 tpc);
+                int (*record_sm_error_state)(struct gk20a *g, u32 gpc,
+                                u32 tpc, struct channel_gk20a *fault_ch);
                 int (*update_sm_error_state)(struct gk20a *g,
                                 struct channel_gk20a *ch, u32 sm_id,
                                 struct nvgpu_gr_sm_error_state *sm_error_state);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 8a3f98af..a02c0e5d 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -5605,7 +5605,7 @@ int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
                   "sm hww global 0x%08x warp 0x%08x", global_esr, warp_esr);
 
         gr_gk20a_elpg_protected_call(g,
-                g->ops.gr.record_sm_error_state(g, gpc, tpc));
+                g->ops.gr.record_sm_error_state(g, gpc, tpc, fault_ch));
 
         if (g->ops.gr.pre_process_sm_exception) {
                 ret = g->ops.gr.pre_process_sm_exception(g, gpc, tpc, sm,
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index 66bb471a..08ac20e4 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -1271,7 +1271,8 @@ void gr_gm20b_get_access_map(struct gk20a *g,
         *num_entries = ARRAY_SIZE(wl_addr_gm20b);
 }
 
-int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc)
+int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc,
+                                struct channel_gk20a *fault_ch)
 {
         int sm_id;
         struct gr_gk20a *gr = &g->gr;
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
index bddf6412..3f604028 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
@@ -116,7 +116,8 @@ void gr_gm20b_enable_cde_in_fecs(struct gk20a *g, struct nvgpu_mem *mem);
 void gr_gm20b_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state);
 void gr_gm20b_get_access_map(struct gk20a *g,
                                    u32 **whitelist, int *num_entries);
-int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc);
+int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc,
+                u32 tpc, struct channel_gk20a *fault_ch);
 int gm20b_gr_update_sm_error_state(struct gk20a *g,
                 struct channel_gk20a *ch, u32 sm_id,
                 struct nvgpu_gr_sm_error_state *sm_error_state);
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index e697b491..4f517fa7 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -3101,7 +3101,8 @@ int gv11b_gr_set_sm_debug_mode(struct gk20a *g,
         return err;
 }
 
-int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc)
+int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc,
+                                struct channel_gk20a *fault_ch)
 {
         int sm_id;
         struct gr_gk20a *gr = &g->gr;
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
index 4615ff55..018938f6 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
@@ -166,7 +166,8 @@ int gv11b_gr_update_sm_error_state(struct gk20a *g,
                 struct nvgpu_gr_sm_error_state *sm_error_state);
 int gv11b_gr_set_sm_debug_mode(struct gk20a *g,
         struct channel_gk20a *ch, u64 sms, bool enable);
-int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc);
+int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc,
+                struct channel_gk20a *fault_ch);
 void gv11b_gr_set_hww_esr_report_mask(struct gk20a *g);
 bool gv11b_gr_sm_debugger_attached(struct gk20a *g);
 void gv11b_gr_suspend_single_sm(struct gk20a *g,