gpu: nvgpu: vgpu: add getting ltc constants

move below attributes to constants:
TEGRA_VGPU_ATTRIB_COMPTAG_LINES
TEGRA_VGPU_ATTRIB_L2_SIZE
TEGRA_VGPU_ATTRIB_CACHELINE_SIZE
TEGRA_VGPU_ATTRIB_COMPTAGS_PER_CACHELINE
TEGRA_VGPU_ATTRIB_SLICES_PER_LTC
TEGRA_VGPU_ATTRIB_LTC_COUNT

JIRA VFND-2103

Change-Id: Iecf9717ee553a16ffe8de445be5bfe5a99c3a094
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1190480
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>

2 files changed, 21 insertions, 33 deletions

diff --git a/drivers/gpu/nvgpu/vgpu/ltc_vgpu.c b/drivers/gpu/nvgpu/vgpu/ltc_vgpu.c
index 3e3f67c6..dc4d47cb 100644
--- a/drivers/gpu/nvgpu/vgpu/ltc_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/ltc_vgpu.c
@@ -17,39 +17,25 @@
 
 static int vgpu_determine_L2_size_bytes(struct gk20a *g)
 {
-        u32 cache_size = 0;
+        struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
 
         gk20a_dbg_fn("");
 
-        if (vgpu_get_attribute(vgpu_get_handle(g),
-                        TEGRA_VGPU_ATTRIB_L2_SIZE, &cache_size))
-                dev_err(dev_from_gk20a(g), "unable to get L2 size\n");
-
-        return cache_size;
+        return priv->constants.l2_size;
 }
 
 static int vgpu_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
 {
+        struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
         u32 max_comptag_lines = 0;
         int err;
 
         gk20a_dbg_fn("");
 
-        err = vgpu_get_attribute(vgpu_get_handle(g),
-                        TEGRA_VGPU_ATTRIB_CACHELINE_SIZE,
-                        &gr->cacheline_size);
-        err |= vgpu_get_attribute(vgpu_get_handle(g),
-                        TEGRA_VGPU_ATTRIB_COMPTAGS_PER_CACHELINE,
-                        &gr->comptags_per_cacheline);
-        err |= vgpu_get_attribute(vgpu_get_handle(g),
-                        TEGRA_VGPU_ATTRIB_SLICES_PER_LTC,
-                        &gr->slices_per_ltc);
-        err |= vgpu_get_attribute(vgpu_get_handle(g),
-                        TEGRA_VGPU_ATTRIB_COMPTAG_LINES, &max_comptag_lines);
-        if (err) {
-                dev_err(dev_from_gk20a(g), "failed to get ctags atributes\n");
-                return -ENXIO;
-        }
+        gr->cacheline_size = priv->constants.cacheline_size;
+        gr->comptags_per_cacheline = priv->constants.comptags_per_cacheline;
+        gr->slices_per_ltc = priv->constants.slices_per_ltc;
+        max_comptag_lines = priv->constants.comptag_lines;
 
         if (max_comptag_lines < 2)
                 return -ENXIO;
@@ -63,15 +49,11 @@ static int vgpu_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
 
 static void vgpu_ltc_init_fs_state(struct gk20a *g)
 {
-        u32 ltc_count = 0;
-        int err;
+        struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
 
         gk20a_dbg_fn("");
 
-        err = vgpu_get_attribute(vgpu_get_handle(g),
-                        TEGRA_VGPU_ATTRIB_LTC_COUNT, &ltc_count);
-        WARN_ON(err);
-        g->ltc_count = ltc_count;
+        g->ltc_count = priv->constants.ltc_count;
 }
 
 void vgpu_init_ltc_ops(struct gpu_ops *gops)
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h
index 504a31ad..ef4c36d9 100644
--- a/include/linux/tegra_vgpu.h
+++ b/include/linux/tegra_vgpu.h
@@ -114,22 +114,22 @@ enum {
         TEGRA_VGPU_ATTRIB_NUM_CHANNELS = 0, /*deprecated */
         TEGRA_VGPU_ATTRIB_GOLDEN_CTX_SIZE = 1, /* deprecated */
         TEGRA_VGPU_ATTRIB_ZCULL_CTX_SIZE = 2, /* deprecated */
-        TEGRA_VGPU_ATTRIB_COMPTAG_LINES = 3,
+        TEGRA_VGPU_ATTRIB_COMPTAG_LINES = 3, /* deprecated */
         TEGRA_VGPU_ATTRIB_GPC_COUNT = 4,
         TEGRA_VGPU_ATTRIB_MAX_TPC_PER_GPC_COUNT = 5,
         TEGRA_VGPU_ATTRIB_MAX_TPC_COUNT = 6,
         TEGRA_VGPU_ATTRIB_PMC_BOOT_0 = 7, /* deprecated */
-        TEGRA_VGPU_ATTRIB_L2_SIZE = 8,
+        TEGRA_VGPU_ATTRIB_L2_SIZE = 8, /* deprecated */
         TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH = 9,
         TEGRA_VGPU_ATTRIB_NUM_FBPS = 10,
         TEGRA_VGPU_ATTRIB_FBP_EN_MASK = 11,
         TEGRA_VGPU_ATTRIB_MAX_LTC_PER_FBP = 12,
         TEGRA_VGPU_ATTRIB_MAX_LTS_PER_LTC = 13,
         TEGRA_VGPU_ATTRIB_GPC0_TPC_MASK = 14,
-        TEGRA_VGPU_ATTRIB_CACHELINE_SIZE = 15,
-        TEGRA_VGPU_ATTRIB_COMPTAGS_PER_CACHELINE = 16,
-        TEGRA_VGPU_ATTRIB_SLICES_PER_LTC = 17,
-        TEGRA_VGPU_ATTRIB_LTC_COUNT = 18,
+        TEGRA_VGPU_ATTRIB_CACHELINE_SIZE = 15, /* deprecated */
+        TEGRA_VGPU_ATTRIB_COMPTAGS_PER_CACHELINE = 16, /* deprecated */
+        TEGRA_VGPU_ATTRIB_SLICES_PER_LTC = 17, /* deprecated */
+        TEGRA_VGPU_ATTRIB_LTC_COUNT = 18, /* deprecated */
         TEGRA_VGPU_ATTRIB_TPC_COUNT = 19,
         TEGRA_VGPU_ATTRIB_GPC0_TPC_COUNT = 20,
         TEGRA_VGPU_ATTRIB_MAX_FREQ = 21, /* deprecated */
@@ -411,6 +411,12 @@ struct tegra_vgpu_constants_params {
         u32 num_channels;
         u32 golden_ctx_size;
         u32 zcull_ctx_size;
+        u32 l2_size;
+        u32 ltc_count;
+        u32 cacheline_size;
+        u32 slices_per_ltc;
+        u32 comptags_per_cacheline;
+        u32 comptag_lines;
 };
 
 struct tegra_vgpu_cmd_msg {