diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2017-04-10 13:47:02 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-04-13 16:44:41 -0400 |
commit | 22426a5452ba943ac48867722fb0927baf66d4ac (patch) | |
tree | 4595c635cc920e4ba2d540a6e070b89e3037c28e | |
parent | a0fa2b0258dafcd7a2450ab5366a49663b1d2e89 (diff) |
gpu: nvgpu: gk20a: Use new delay APIs
Use platform agnostic delay functions instead of Linux kernel APIs.
This allows removing dependency to Linux header linux/delay.h. At the
same time remove #include lines for other unused Linux headers.
JIRA NVGPU-16
Change-Id: I46b9ccb80e0b67efb86ec85676e5a55ff835c0ec
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1460113
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/channel_gk20a.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/clk_gk20a.c | 20 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ctxsw_trace_gk20a.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fb_gk20a.c | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 11 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.c | 13 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 33 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ltc_common.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ltc_gk20a.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mc_gk20a.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mm_gk20a.c | 16 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 16 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/sched_gk20a.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/ltc_gm20b.c | 2 |
17 files changed, 58 insertions, 103 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c index 5b27953e..523ba4f6 100644 --- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | |||
@@ -17,12 +17,6 @@ | |||
17 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | 17 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
18 | */ | 18 | */ |
19 | 19 | ||
20 | /*TODO: remove uncecessary */ | ||
21 | #include <linux/delay.h> | ||
22 | #include <linux/scatterlist.h> | ||
23 | #include <trace/events/gk20a.h> | ||
24 | #include <linux/dma-mapping.h> | ||
25 | #include <linux/nvhost.h> | ||
26 | #include <linux/debugfs.h> | 20 | #include <linux/debugfs.h> |
27 | 21 | ||
28 | #include <nvgpu/kmem.h> | 22 | #include <nvgpu/kmem.h> |
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c index 8510c543..3cfb9914 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c | |||
@@ -16,8 +16,6 @@ | |||
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | 16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
17 | */ | 17 | */ |
18 | 18 | ||
19 | #include <linux/list.h> | ||
20 | #include <linux/delay.h> | ||
21 | #include <linux/kthread.h> | 19 | #include <linux/kthread.h> |
22 | #include <trace/events/gk20a.h> | 20 | #include <trace/events/gk20a.h> |
23 | #include <linux/dma-buf.h> | 21 | #include <linux/dma-buf.h> |
@@ -301,7 +299,7 @@ int gk20a_wait_channel_idle(struct channel_gk20a *ch) | |||
301 | if (channel_idle) | 299 | if (channel_idle) |
302 | break; | 300 | break; |
303 | 301 | ||
304 | usleep_range(1000, 3000); | 302 | nvgpu_usleep_range(1000, 3000); |
305 | } while (!nvgpu_timeout_expired(&timeout)); | 303 | } while (!nvgpu_timeout_expired(&timeout)); |
306 | 304 | ||
307 | if (!channel_idle) { | 305 | if (!channel_idle) { |
diff --git a/drivers/gpu/nvgpu/gk20a/clk_gk20a.c b/drivers/gpu/nvgpu/gk20a/clk_gk20a.c index 45af68ea..b69f74b2 100644 --- a/drivers/gpu/nvgpu/gk20a/clk_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/clk_gk20a.c | |||
@@ -17,7 +17,6 @@ | |||
17 | */ | 17 | */ |
18 | 18 | ||
19 | #include <linux/clk.h> | 19 | #include <linux/clk.h> |
20 | #include <linux/delay.h> /* for mdelay */ | ||
21 | #include <linux/module.h> | 20 | #include <linux/module.h> |
22 | #include <linux/debugfs.h> | 21 | #include <linux/debugfs.h> |
23 | #include <linux/clk/tegra.h> | 22 | #include <linux/clk/tegra.h> |
@@ -26,6 +25,7 @@ | |||
26 | 25 | ||
27 | #include <nvgpu/log.h> | 26 | #include <nvgpu/log.h> |
28 | #include <nvgpu/soc.h> | 27 | #include <nvgpu/soc.h> |
28 | #include <nvgpu/timers.h> | ||
29 | #include <nvgpu/bug.h> | 29 | #include <nvgpu/bug.h> |
30 | 30 | ||
31 | #include <nvgpu/hw/gk20a/hw_trim_gk20a.h> | 31 | #include <nvgpu/hw/gk20a/hw_trim_gk20a.h> |
@@ -223,7 +223,7 @@ static int clk_slide_gpc_pll(struct gk20a *g, u32 n) | |||
223 | coeff = gk20a_readl(g, trim_sys_gpcpll_coeff_r()); | 223 | coeff = gk20a_readl(g, trim_sys_gpcpll_coeff_r()); |
224 | coeff = set_field(coeff, trim_sys_gpcpll_coeff_ndiv_m(), | 224 | coeff = set_field(coeff, trim_sys_gpcpll_coeff_ndiv_m(), |
225 | trim_sys_gpcpll_coeff_ndiv_f(n)); | 225 | trim_sys_gpcpll_coeff_ndiv_f(n)); |
226 | udelay(1); | 226 | nvgpu_udelay(1); |
227 | gk20a_writel(g, trim_sys_gpcpll_coeff_r(), coeff); | 227 | gk20a_writel(g, trim_sys_gpcpll_coeff_r(), coeff); |
228 | 228 | ||
229 | /* dynamic ramp to new ndiv */ | 229 | /* dynamic ramp to new ndiv */ |
@@ -231,11 +231,11 @@ static int clk_slide_gpc_pll(struct gk20a *g, u32 n) | |||
231 | data = set_field(data, | 231 | data = set_field(data, |
232 | trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(), | 232 | trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(), |
233 | trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f()); | 233 | trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f()); |
234 | udelay(1); | 234 | nvgpu_udelay(1); |
235 | gk20a_writel(g, trim_sys_gpcpll_ndiv_slowdown_r(), data); | 235 | gk20a_writel(g, trim_sys_gpcpll_ndiv_slowdown_r(), data); |
236 | 236 | ||
237 | do { | 237 | do { |
238 | udelay(1); | 238 | nvgpu_udelay(1); |
239 | ramp_timeout--; | 239 | ramp_timeout--; |
240 | data = gk20a_readl( | 240 | data = gk20a_readl( |
241 | g, trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r()); | 241 | g, trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r()); |
@@ -304,7 +304,7 @@ static int clk_program_gpc_pll(struct gk20a *g, struct clk_gk20a *clk, | |||
304 | data = gk20a_readl(g, trim_sys_sel_vco_r()); | 304 | data = gk20a_readl(g, trim_sys_sel_vco_r()); |
305 | data = set_field(data, trim_sys_sel_vco_gpc2clk_out_m(), | 305 | data = set_field(data, trim_sys_sel_vco_gpc2clk_out_m(), |
306 | trim_sys_sel_vco_gpc2clk_out_bypass_f()); | 306 | trim_sys_sel_vco_gpc2clk_out_bypass_f()); |
307 | udelay(2); | 307 | nvgpu_udelay(2); |
308 | gk20a_writel(g, trim_sys_sel_vco_r(), data); | 308 | gk20a_writel(g, trim_sys_sel_vco_r(), data); |
309 | 309 | ||
310 | /* get out from IDDQ */ | 310 | /* get out from IDDQ */ |
@@ -314,7 +314,7 @@ static int clk_program_gpc_pll(struct gk20a *g, struct clk_gk20a *clk, | |||
314 | trim_sys_gpcpll_cfg_iddq_power_on_v()); | 314 | trim_sys_gpcpll_cfg_iddq_power_on_v()); |
315 | gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg); | 315 | gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg); |
316 | gk20a_readl(g, trim_sys_gpcpll_cfg_r()); | 316 | gk20a_readl(g, trim_sys_gpcpll_cfg_r()); |
317 | udelay(gpc_pll_params.iddq_exit_delay); | 317 | nvgpu_udelay(gpc_pll_params.iddq_exit_delay); |
318 | } | 318 | } |
319 | 319 | ||
320 | /* disable PLL before changing coefficients */ | 320 | /* disable PLL before changing coefficients */ |
@@ -353,7 +353,7 @@ static int clk_program_gpc_pll(struct gk20a *g, struct clk_gk20a *clk, | |||
353 | cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r()); | 353 | cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r()); |
354 | if (cfg & trim_sys_gpcpll_cfg_pll_lock_true_f()) | 354 | if (cfg & trim_sys_gpcpll_cfg_pll_lock_true_f()) |
355 | goto pll_locked; | 355 | goto pll_locked; |
356 | udelay(2); | 356 | nvgpu_udelay(2); |
357 | } while (--timeout > 0); | 357 | } while (--timeout > 0); |
358 | 358 | ||
359 | /* PLL is messed up. What can we do here? */ | 359 | /* PLL is messed up. What can we do here? */ |
@@ -372,7 +372,7 @@ pll_locked: | |||
372 | data = gk20a_readl(g, trim_sys_gpc2clk_out_r()); | 372 | data = gk20a_readl(g, trim_sys_gpc2clk_out_r()); |
373 | data = set_field(data, trim_sys_gpc2clk_out_vcodiv_m(), | 373 | data = set_field(data, trim_sys_gpc2clk_out_vcodiv_m(), |
374 | trim_sys_gpc2clk_out_vcodiv_by1_f()); | 374 | trim_sys_gpc2clk_out_vcodiv_by1_f()); |
375 | udelay(2); | 375 | nvgpu_udelay(2); |
376 | gk20a_writel(g, trim_sys_gpc2clk_out_r(), data); | 376 | gk20a_writel(g, trim_sys_gpc2clk_out_r(), data); |
377 | 377 | ||
378 | /* slide up to target NDIV */ | 378 | /* slide up to target NDIV */ |
@@ -791,10 +791,10 @@ static int monitor_get(void *data, u64 *val) | |||
791 | /* It should take about 8us to finish 100 cycle of 12MHz. | 791 | /* It should take about 8us to finish 100 cycle of 12MHz. |
792 | But longer than 100us delay is required here. */ | 792 | But longer than 100us delay is required here. */ |
793 | gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cfg_r(0)); | 793 | gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cfg_r(0)); |
794 | udelay(2000); | 794 | nvgpu_udelay(2000); |
795 | 795 | ||
796 | count1 = gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cnt_r(0)); | 796 | count1 = gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cnt_r(0)); |
797 | udelay(100); | 797 | nvgpu_udelay(100); |
798 | count2 = gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cnt_r(0)); | 798 | count2 = gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cnt_r(0)); |
799 | freq *= trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(count2); | 799 | freq *= trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(count2); |
800 | do_div(freq, ncycle); | 800 | do_div(freq, ncycle); |
diff --git a/drivers/gpu/nvgpu/gk20a/ctxsw_trace_gk20a.c b/drivers/gpu/nvgpu/gk20a/ctxsw_trace_gk20a.c index f60a4b0e..5b1dff17 100644 --- a/drivers/gpu/nvgpu/gk20a/ctxsw_trace_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ctxsw_trace_gk20a.c | |||
@@ -14,12 +14,10 @@ | |||
14 | #include <asm/barrier.h> | 14 | #include <asm/barrier.h> |
15 | #include <linux/kthread.h> | 15 | #include <linux/kthread.h> |
16 | #include <linux/circ_buf.h> | 16 | #include <linux/circ_buf.h> |
17 | #include <linux/delay.h> | ||
18 | #include <linux/wait.h> | 17 | #include <linux/wait.h> |
19 | #include <linux/ktime.h> | 18 | #include <linux/ktime.h> |
20 | #include <linux/hashtable.h> | 19 | #include <linux/hashtable.h> |
21 | #include <linux/debugfs.h> | 20 | #include <linux/debugfs.h> |
22 | #include <linux/log2.h> | ||
23 | #include <linux/uaccess.h> | 21 | #include <linux/uaccess.h> |
24 | #include <linux/poll.h> | 22 | #include <linux/poll.h> |
25 | #include <trace/events/gk20a.h> | 23 | #include <trace/events/gk20a.h> |
diff --git a/drivers/gpu/nvgpu/gk20a/fb_gk20a.c b/drivers/gpu/nvgpu/gk20a/fb_gk20a.c index b3c52852..214014ce 100644 --- a/drivers/gpu/nvgpu/gk20a/fb_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fb_gk20a.c | |||
@@ -14,12 +14,13 @@ | |||
14 | */ | 14 | */ |
15 | 15 | ||
16 | #include <trace/events/gk20a.h> | 16 | #include <trace/events/gk20a.h> |
17 | #include <linux/delay.h> | ||
18 | 17 | ||
19 | #include "gk20a.h" | 18 | #include "gk20a.h" |
20 | #include "kind_gk20a.h" | 19 | #include "kind_gk20a.h" |
21 | #include "fb_gk20a.h" | 20 | #include "fb_gk20a.h" |
22 | 21 | ||
22 | #include <nvgpu/timers.h> | ||
23 | |||
23 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> | 24 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> |
24 | #include <nvgpu/hw/gk20a/hw_fb_gk20a.h> | 25 | #include <nvgpu/hw/gk20a/hw_fb_gk20a.h> |
25 | 26 | ||
@@ -124,7 +125,7 @@ void gk20a_fb_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb) | |||
124 | data = gk20a_readl(g, fb_mmu_ctrl_r()); | 125 | data = gk20a_readl(g, fb_mmu_ctrl_r()); |
125 | if (fb_mmu_ctrl_pri_fifo_space_v(data) != 0) | 126 | if (fb_mmu_ctrl_pri_fifo_space_v(data) != 0) |
126 | break; | 127 | break; |
127 | udelay(2); | 128 | nvgpu_udelay(2); |
128 | } while (!nvgpu_timeout_expired_msg(&timeout, | 129 | } while (!nvgpu_timeout_expired_msg(&timeout, |
129 | "wait mmu fifo space")); | 130 | "wait mmu fifo space")); |
130 | 131 | ||
@@ -148,7 +149,7 @@ void gk20a_fb_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb) | |||
148 | if (fb_mmu_ctrl_pri_fifo_empty_v(data) != | 149 | if (fb_mmu_ctrl_pri_fifo_empty_v(data) != |
149 | fb_mmu_ctrl_pri_fifo_empty_false_f()) | 150 | fb_mmu_ctrl_pri_fifo_empty_false_f()) |
150 | break; | 151 | break; |
151 | udelay(2); | 152 | nvgpu_udelay(2); |
152 | } while (!nvgpu_timeout_expired_msg(&timeout, | 153 | } while (!nvgpu_timeout_expired_msg(&timeout, |
153 | "wait mmu invalidate")); | 154 | "wait mmu invalidate")); |
154 | 155 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c index 3e21dea4..316dcda4 100644 --- a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c | |||
@@ -14,13 +14,8 @@ | |||
14 | #include <asm/barrier.h> | 14 | #include <asm/barrier.h> |
15 | #include <linux/kthread.h> | 15 | #include <linux/kthread.h> |
16 | #include <linux/circ_buf.h> | 16 | #include <linux/circ_buf.h> |
17 | #include <linux/delay.h> | ||
18 | #include <linux/wait.h> | ||
19 | #include <linux/ktime.h> | ||
20 | #include <linux/hashtable.h> | 17 | #include <linux/hashtable.h> |
21 | #include <linux/debugfs.h> | 18 | #include <linux/debugfs.h> |
22 | #include <linux/log2.h> | ||
23 | #include <uapi/linux/nvgpu.h> | ||
24 | 19 | ||
25 | #include <nvgpu/kmem.h> | 20 | #include <nvgpu/kmem.h> |
26 | #include <nvgpu/dma.h> | 21 | #include <nvgpu/dma.h> |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 4e08ffea..c296be5b 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -17,10 +17,7 @@ | |||
17 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | 17 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
18 | */ | 18 | */ |
19 | 19 | ||
20 | #include <linux/delay.h> | ||
21 | #include <linux/scatterlist.h> | ||
22 | #include <trace/events/gk20a.h> | 20 | #include <trace/events/gk20a.h> |
23 | #include <linux/dma-mapping.h> | ||
24 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | 21 | #ifdef CONFIG_TEGRA_GK20A_NVHOST |
25 | #include <linux/nvhost.h> | 22 | #include <linux/nvhost.h> |
26 | #endif | 23 | #endif |
@@ -1735,7 +1732,7 @@ static void gk20a_fifo_trigger_mmu_fault(struct gk20a *g, | |||
1735 | fifo_intr_0_mmu_fault_pending_f()) | 1732 | fifo_intr_0_mmu_fault_pending_f()) |
1736 | break; | 1733 | break; |
1737 | 1734 | ||
1738 | usleep_range(delay, delay * 2); | 1735 | nvgpu_usleep_range(delay, delay * 2); |
1739 | delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); | 1736 | delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); |
1740 | } while (!nvgpu_timeout_expired_msg(&timeout, "mmu fault timeout")); | 1737 | } while (!nvgpu_timeout_expired_msg(&timeout, "mmu fault timeout")); |
1741 | 1738 | ||
@@ -2533,7 +2530,7 @@ int gk20a_fifo_is_preempt_pending(struct gk20a *g, u32 id, | |||
2533 | break; | 2530 | break; |
2534 | } | 2531 | } |
2535 | 2532 | ||
2536 | usleep_range(delay, delay * 2); | 2533 | nvgpu_usleep_range(delay, delay * 2); |
2537 | delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); | 2534 | delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); |
2538 | } while (!nvgpu_timeout_expired_msg(&timeout, "preempt timeout")); | 2535 | } while (!nvgpu_timeout_expired_msg(&timeout, "preempt timeout")); |
2539 | 2536 | ||
@@ -2901,7 +2898,7 @@ static int gk20a_fifo_runlist_wait_pending(struct gk20a *g, u32 runlist_id) | |||
2901 | break; | 2898 | break; |
2902 | } | 2899 | } |
2903 | 2900 | ||
2904 | usleep_range(delay, delay * 2); | 2901 | nvgpu_usleep_range(delay, delay * 2); |
2905 | delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); | 2902 | delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); |
2906 | } while (!nvgpu_timeout_expired(&timeout)); | 2903 | } while (!nvgpu_timeout_expired(&timeout)); |
2907 | 2904 | ||
@@ -3348,7 +3345,7 @@ int gk20a_fifo_wait_engine_idle(struct gk20a *g) | |||
3348 | break; | 3345 | break; |
3349 | } | 3346 | } |
3350 | 3347 | ||
3351 | usleep_range(delay, delay * 2); | 3348 | nvgpu_usleep_range(delay, delay * 2); |
3352 | delay = min_t(unsigned long, | 3349 | delay = min_t(unsigned long, |
3353 | delay << 1, GR_IDLE_CHECK_MAX); | 3350 | delay << 1, GR_IDLE_CHECK_MAX); |
3354 | } while (!nvgpu_timeout_expired(&timeout)); | 3351 | } while (!nvgpu_timeout_expired(&timeout)); |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index 339656c7..a50dfa0e 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c | |||
@@ -17,9 +17,7 @@ | |||
17 | */ | 17 | */ |
18 | 18 | ||
19 | #include <linux/module.h> | 19 | #include <linux/module.h> |
20 | #include <linux/dma-mapping.h> | ||
21 | #include <linux/string.h> | 20 | #include <linux/string.h> |
22 | #include <linux/delay.h> | ||
23 | #include <linux/interrupt.h> | 21 | #include <linux/interrupt.h> |
24 | #include <linux/irq.h> | 22 | #include <linux/irq.h> |
25 | #include <linux/export.h> | 23 | #include <linux/export.h> |
@@ -30,7 +28,6 @@ | |||
30 | #include <linux/thermal.h> | 28 | #include <linux/thermal.h> |
31 | #include <asm/cacheflush.h> | 29 | #include <asm/cacheflush.h> |
32 | #include <linux/debugfs.h> | 30 | #include <linux/debugfs.h> |
33 | #include <nvgpu/lock.h> | ||
34 | #include <linux/clk/tegra.h> | 31 | #include <linux/clk/tegra.h> |
35 | #include <linux/kthread.h> | 32 | #include <linux/kthread.h> |
36 | #include <linux/platform/tegra/common.h> | 33 | #include <linux/platform/tegra/common.h> |
@@ -1181,7 +1178,7 @@ int gk20a_wait_for_idle(struct device *dev) | |||
1181 | 1178 | ||
1182 | while ((atomic_read(&g->usage_count) != target_usage_count) | 1179 | while ((atomic_read(&g->usage_count) != target_usage_count) |
1183 | && (wait_length-- >= 0)) | 1180 | && (wait_length-- >= 0)) |
1184 | msleep(20); | 1181 | nvgpu_msleep(20); |
1185 | 1182 | ||
1186 | if (wait_length < 0) { | 1183 | if (wait_length < 0) { |
1187 | pr_warn("%s: Timed out waiting for idle (%d)!\n", | 1184 | pr_warn("%s: Timed out waiting for idle (%d)!\n", |
@@ -1336,7 +1333,7 @@ int __gk20a_do_idle(struct device *dev, bool force_reset) | |||
1336 | 1333 | ||
1337 | /* check and wait until GPU is idle (with a timeout) */ | 1334 | /* check and wait until GPU is idle (with a timeout) */ |
1338 | do { | 1335 | do { |
1339 | msleep(1); | 1336 | nvgpu_msleep(1); |
1340 | ref_cnt = atomic_read(&dev->power.usage_count); | 1337 | ref_cnt = atomic_read(&dev->power.usage_count); |
1341 | } while (ref_cnt != target_ref_cnt && !nvgpu_timeout_expired(&timeout)); | 1338 | } while (ref_cnt != target_ref_cnt && !nvgpu_timeout_expired(&timeout)); |
1342 | 1339 | ||
@@ -1362,11 +1359,11 @@ int __gk20a_do_idle(struct device *dev, bool force_reset) | |||
1362 | pm_runtime_put_sync(dev); | 1359 | pm_runtime_put_sync(dev); |
1363 | 1360 | ||
1364 | /* add sufficient delay to allow GPU to rail gate */ | 1361 | /* add sufficient delay to allow GPU to rail gate */ |
1365 | msleep(platform->railgate_delay); | 1362 | nvgpu_msleep(platform->railgate_delay); |
1366 | 1363 | ||
1367 | /* check in loop if GPU is railgated or not */ | 1364 | /* check in loop if GPU is railgated or not */ |
1368 | do { | 1365 | do { |
1369 | msleep(1); | 1366 | nvgpu_msleep(1); |
1370 | is_railgated = platform->is_railgated(dev); | 1367 | is_railgated = platform->is_railgated(dev); |
1371 | } while (!is_railgated && !nvgpu_timeout_expired(&timeout)); | 1368 | } while (!is_railgated && !nvgpu_timeout_expired(&timeout)); |
1372 | 1369 | ||
@@ -1397,7 +1394,7 @@ int __gk20a_do_idle(struct device *dev, bool force_reset) | |||
1397 | /* railgate GPU */ | 1394 | /* railgate GPU */ |
1398 | platform->railgate(dev); | 1395 | platform->railgate(dev); |
1399 | 1396 | ||
1400 | udelay(10); | 1397 | nvgpu_udelay(10); |
1401 | 1398 | ||
1402 | g->forced_reset = true; | 1399 | g->forced_reset = true; |
1403 | return 0; | 1400 | return 0; |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index d211242c..a4419885 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -17,14 +17,7 @@ | |||
17 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | 17 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
18 | */ | 18 | */ |
19 | 19 | ||
20 | #include <linux/delay.h> /* for udelay */ | ||
21 | #include <linux/mm.h> /* for totalram_pages */ | ||
22 | #include <linux/scatterlist.h> | ||
23 | #include <linux/debugfs.h> | ||
24 | #include <uapi/linux/nvgpu.h> | ||
25 | #include <linux/dma-mapping.h> | ||
26 | #include <linux/firmware.h> | 20 | #include <linux/firmware.h> |
27 | #include <linux/nvhost.h> | ||
28 | #include <trace/events/gk20a.h> | 21 | #include <trace/events/gk20a.h> |
29 | 22 | ||
30 | #include <nvgpu/dma.h> | 23 | #include <nvgpu/dma.h> |
@@ -370,7 +363,7 @@ int gr_gk20a_wait_idle(struct gk20a *g, unsigned long duration_ms, | |||
370 | return 0; | 363 | return 0; |
371 | } | 364 | } |
372 | 365 | ||
373 | usleep_range(delay, delay * 2); | 366 | nvgpu_usleep_range(delay, delay * 2); |
374 | delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); | 367 | delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); |
375 | 368 | ||
376 | } while (!nvgpu_timeout_expired(&timeout)); | 369 | } while (!nvgpu_timeout_expired(&timeout)); |
@@ -406,7 +399,7 @@ int gr_gk20a_wait_fe_idle(struct gk20a *g, unsigned long duration_ms, | |||
406 | return 0; | 399 | return 0; |
407 | } | 400 | } |
408 | 401 | ||
409 | usleep_range(delay, delay * 2); | 402 | nvgpu_usleep_range(delay, delay * 2); |
410 | delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); | 403 | delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); |
411 | } while (!nvgpu_timeout_expired(&timeout)); | 404 | } while (!nvgpu_timeout_expired(&timeout)); |
412 | 405 | ||
@@ -507,10 +500,10 @@ int gr_gk20a_ctx_wait_ucode(struct gk20a *g, u32 mailbox_id, | |||
507 | } | 500 | } |
508 | 501 | ||
509 | if (sleepduringwait) { | 502 | if (sleepduringwait) { |
510 | usleep_range(delay, delay * 2); | 503 | nvgpu_usleep_range(delay, delay * 2); |
511 | delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); | 504 | delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); |
512 | } else | 505 | } else |
513 | udelay(delay); | 506 | nvgpu_udelay(delay); |
514 | } | 507 | } |
515 | 508 | ||
516 | if (check == WAIT_UCODE_TIMEOUT) { | 509 | if (check == WAIT_UCODE_TIMEOUT) { |
@@ -1613,7 +1606,7 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g, | |||
1613 | u32 req = gr_fe_pwr_mode_req_v(gk20a_readl(g, gr_fe_pwr_mode_r())); | 1606 | u32 req = gr_fe_pwr_mode_req_v(gk20a_readl(g, gr_fe_pwr_mode_r())); |
1614 | if (req == gr_fe_pwr_mode_req_done_v()) | 1607 | if (req == gr_fe_pwr_mode_req_done_v()) |
1615 | break; | 1608 | break; |
1616 | udelay(FE_PWR_MODE_TIMEOUT_DEFAULT); | 1609 | nvgpu_udelay(FE_PWR_MODE_TIMEOUT_DEFAULT); |
1617 | } while (!nvgpu_timeout_expired_msg(&timeout, | 1610 | } while (!nvgpu_timeout_expired_msg(&timeout, |
1618 | "timeout forcing FE on")); | 1611 | "timeout forcing FE on")); |
1619 | } | 1612 | } |
@@ -1630,7 +1623,7 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g, | |||
1630 | gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f() | | 1623 | gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f() | |
1631 | gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f()); | 1624 | gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f()); |
1632 | gk20a_readl(g, gr_fecs_ctxsw_reset_ctl_r()); | 1625 | gk20a_readl(g, gr_fecs_ctxsw_reset_ctl_r()); |
1633 | udelay(10); | 1626 | nvgpu_udelay(10); |
1634 | 1627 | ||
1635 | gk20a_writel(g, gr_fecs_ctxsw_reset_ctl_r(), | 1628 | gk20a_writel(g, gr_fecs_ctxsw_reset_ctl_r(), |
1636 | gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f() | | 1629 | gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f() | |
@@ -1643,7 +1636,7 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g, | |||
1643 | gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f() | | 1636 | gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f() | |
1644 | gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f()); | 1637 | gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f()); |
1645 | gk20a_readl(g, gr_fecs_ctxsw_reset_ctl_r()); | 1638 | gk20a_readl(g, gr_fecs_ctxsw_reset_ctl_r()); |
1646 | udelay(10); | 1639 | nvgpu_udelay(10); |
1647 | 1640 | ||
1648 | if (!platform->is_fmodel) { | 1641 | if (!platform->is_fmodel) { |
1649 | struct nvgpu_timeout timeout; | 1642 | struct nvgpu_timeout timeout; |
@@ -1657,7 +1650,7 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g, | |||
1657 | u32 req = gr_fe_pwr_mode_req_v(gk20a_readl(g, gr_fe_pwr_mode_r())); | 1650 | u32 req = gr_fe_pwr_mode_req_v(gk20a_readl(g, gr_fe_pwr_mode_r())); |
1658 | if (req == gr_fe_pwr_mode_req_done_v()) | 1651 | if (req == gr_fe_pwr_mode_req_done_v()) |
1659 | break; | 1652 | break; |
1660 | udelay(FE_PWR_MODE_TIMEOUT_DEFAULT); | 1653 | nvgpu_udelay(FE_PWR_MODE_TIMEOUT_DEFAULT); |
1661 | } while (!nvgpu_timeout_expired_msg(&timeout, | 1654 | } while (!nvgpu_timeout_expired_msg(&timeout, |
1662 | "timeout setting FE power to auto")); | 1655 | "timeout setting FE power to auto")); |
1663 | } | 1656 | } |
@@ -2369,7 +2362,7 @@ void gr_gk20a_load_falcon_bind_instblk(struct gk20a *g) | |||
2369 | 2362 | ||
2370 | while ((gk20a_readl(g, gr_fecs_ctxsw_status_1_r()) & | 2363 | while ((gk20a_readl(g, gr_fecs_ctxsw_status_1_r()) & |
2371 | gr_fecs_ctxsw_status_1_arb_busy_m()) && retries) { | 2364 | gr_fecs_ctxsw_status_1_arb_busy_m()) && retries) { |
2372 | udelay(FECS_ARB_CMD_TIMEOUT_DEFAULT); | 2365 | nvgpu_udelay(FECS_ARB_CMD_TIMEOUT_DEFAULT); |
2373 | retries--; | 2366 | retries--; |
2374 | } | 2367 | } |
2375 | if (!retries) { | 2368 | if (!retries) { |
@@ -2400,7 +2393,7 @@ void gr_gk20a_load_falcon_bind_instblk(struct gk20a *g) | |||
2400 | retries = FECS_ARB_CMD_TIMEOUT_MAX / FECS_ARB_CMD_TIMEOUT_DEFAULT; | 2393 | retries = FECS_ARB_CMD_TIMEOUT_MAX / FECS_ARB_CMD_TIMEOUT_DEFAULT; |
2401 | val = gk20a_readl(g, gr_fecs_arb_ctx_cmd_r()); | 2394 | val = gk20a_readl(g, gr_fecs_arb_ctx_cmd_r()); |
2402 | while (gr_fecs_arb_ctx_cmd_cmd_v(val) && retries) { | 2395 | while (gr_fecs_arb_ctx_cmd_cmd_v(val) && retries) { |
2403 | udelay(FECS_ARB_CMD_TIMEOUT_DEFAULT); | 2396 | nvgpu_udelay(FECS_ARB_CMD_TIMEOUT_DEFAULT); |
2404 | retries--; | 2397 | retries--; |
2405 | val = gk20a_readl(g, gr_fecs_arb_ctx_cmd_r()); | 2398 | val = gk20a_readl(g, gr_fecs_arb_ctx_cmd_r()); |
2406 | } | 2399 | } |
@@ -2417,7 +2410,7 @@ void gr_gk20a_load_falcon_bind_instblk(struct gk20a *g) | |||
2417 | retries = FECS_ARB_CMD_TIMEOUT_MAX / FECS_ARB_CMD_TIMEOUT_DEFAULT; | 2410 | retries = FECS_ARB_CMD_TIMEOUT_MAX / FECS_ARB_CMD_TIMEOUT_DEFAULT; |
2418 | val = (gk20a_readl(g, gr_fecs_arb_ctx_cmd_r())); | 2411 | val = (gk20a_readl(g, gr_fecs_arb_ctx_cmd_r())); |
2419 | while (gr_fecs_arb_ctx_cmd_cmd_v(val) && retries) { | 2412 | while (gr_fecs_arb_ctx_cmd_cmd_v(val) && retries) { |
2420 | udelay(FECS_ARB_CMD_TIMEOUT_DEFAULT); | 2413 | nvgpu_udelay(FECS_ARB_CMD_TIMEOUT_DEFAULT); |
2421 | retries--; | 2414 | retries--; |
2422 | val = gk20a_readl(g, gr_fecs_arb_ctx_cmd_r()); | 2415 | val = gk20a_readl(g, gr_fecs_arb_ctx_cmd_r()); |
2423 | } | 2416 | } |
@@ -5021,7 +5014,7 @@ static int gr_gk20a_wait_mem_scrubbing(struct gk20a *g) | |||
5021 | return 0; | 5014 | return 0; |
5022 | } | 5015 | } |
5023 | 5016 | ||
5024 | udelay(CTXSW_MEM_SCRUBBING_TIMEOUT_DEFAULT); | 5017 | nvgpu_udelay(CTXSW_MEM_SCRUBBING_TIMEOUT_DEFAULT); |
5025 | } while (!nvgpu_timeout_expired(&timeout)); | 5018 | } while (!nvgpu_timeout_expired(&timeout)); |
5026 | 5019 | ||
5027 | nvgpu_err(g, "Falcon mem scrubbing timeout"); | 5020 | nvgpu_err(g, "Falcon mem scrubbing timeout"); |
@@ -8663,7 +8656,7 @@ int gk20a_gr_wait_for_sm_lock_down(struct gk20a *g, u32 gpc, u32 tpc, | |||
8663 | return -EFAULT; | 8656 | return -EFAULT; |
8664 | } | 8657 | } |
8665 | 8658 | ||
8666 | usleep_range(delay, delay * 2); | 8659 | nvgpu_usleep_range(delay, delay * 2); |
8667 | delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); | 8660 | delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); |
8668 | } while (!nvgpu_timeout_expired(&timeout)); | 8661 | } while (!nvgpu_timeout_expired(&timeout)); |
8669 | 8662 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/ltc_common.c b/drivers/gpu/nvgpu/gk20a/ltc_common.c index 03b12740..6162d420 100644 --- a/drivers/gpu/nvgpu/gk20a/ltc_common.c +++ b/drivers/gpu/nvgpu/gk20a/ltc_common.c | |||
@@ -18,9 +18,6 @@ | |||
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | 18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
19 | */ | 19 | */ |
20 | 20 | ||
21 | #include <linux/dma-mapping.h> | ||
22 | #include <linux/delay.h> | ||
23 | |||
24 | #include <nvgpu/dma.h> | 21 | #include <nvgpu/dma.h> |
25 | 22 | ||
26 | #include "gk20a.h" | 23 | #include "gk20a.h" |
diff --git a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c index 9da9dd6b..d8d9226c 100644 --- a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c | |||
@@ -155,7 +155,7 @@ static int gk20a_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op, | |||
155 | val = gk20a_readl(g, ctrl1); | 155 | val = gk20a_readl(g, ctrl1); |
156 | if (!(val & hw_op)) | 156 | if (!(val & hw_op)) |
157 | break; | 157 | break; |
158 | udelay(5); | 158 | nvgpu_udelay(5); |
159 | 159 | ||
160 | } while (!nvgpu_timeout_expired(&timeout)); | 160 | } while (!nvgpu_timeout_expired(&timeout)); |
161 | 161 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c index 32a6532f..ca7189cc 100644 --- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c | |||
@@ -13,12 +13,12 @@ | |||
13 | * more details. | 13 | * more details. |
14 | */ | 14 | */ |
15 | 15 | ||
16 | #include <linux/delay.h> | ||
17 | #include <trace/events/gk20a.h> | 16 | #include <trace/events/gk20a.h> |
18 | 17 | ||
19 | #include "gk20a.h" | 18 | #include "gk20a.h" |
20 | #include "mc_gk20a.h" | 19 | #include "mc_gk20a.h" |
21 | 20 | ||
21 | #include <nvgpu/timers.h> | ||
22 | #include <nvgpu/atomic.h> | 22 | #include <nvgpu/atomic.h> |
23 | 23 | ||
24 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> | 24 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> |
@@ -276,16 +276,16 @@ void gk20a_mc_enable(struct gk20a *g, u32 units) | |||
276 | gk20a_readl(g, mc_enable_r()); | 276 | gk20a_readl(g, mc_enable_r()); |
277 | nvgpu_spinlock_release(&g->mc_enable_lock); | 277 | nvgpu_spinlock_release(&g->mc_enable_lock); |
278 | 278 | ||
279 | udelay(20); | 279 | nvgpu_udelay(20); |
280 | } | 280 | } |
281 | 281 | ||
282 | void gk20a_mc_reset(struct gk20a *g, u32 units) | 282 | void gk20a_mc_reset(struct gk20a *g, u32 units) |
283 | { | 283 | { |
284 | g->ops.mc.disable(g, units); | 284 | g->ops.mc.disable(g, units); |
285 | if (units & gk20a_fifo_get_all_ce_engine_reset_mask(g)) | 285 | if (units & gk20a_fifo_get_all_ce_engine_reset_mask(g)) |
286 | udelay(500); | 286 | nvgpu_udelay(500); |
287 | else | 287 | else |
288 | udelay(20); | 288 | nvgpu_udelay(20); |
289 | g->ops.mc.enable(g, units); | 289 | g->ops.mc.enable(g, units); |
290 | } | 290 | } |
291 | 291 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c index 84171ae9..e16b77b7 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c | |||
@@ -16,12 +16,8 @@ | |||
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | 16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
17 | */ | 17 | */ |
18 | 18 | ||
19 | #include <linux/delay.h> | ||
20 | #include <linux/highmem.h> | ||
21 | #include <linux/log2.h> | 19 | #include <linux/log2.h> |
22 | #include <linux/nvhost.h> | ||
23 | #include <linux/scatterlist.h> | 20 | #include <linux/scatterlist.h> |
24 | #include <linux/nvmap.h> | ||
25 | #include <linux/dma-buf.h> | 21 | #include <linux/dma-buf.h> |
26 | #include <linux/dma-mapping.h> | 22 | #include <linux/dma-mapping.h> |
27 | #include <linux/dma-attrs.h> | 23 | #include <linux/dma-attrs.h> |
@@ -1231,7 +1227,7 @@ static void gk20a_vm_unmap_user(struct vm_gk20a *vm, u64 offset, | |||
1231 | do { | 1227 | do { |
1232 | if (atomic_read(&mapped_buffer->ref.refcount) == 1) | 1228 | if (atomic_read(&mapped_buffer->ref.refcount) == 1) |
1233 | break; | 1229 | break; |
1234 | udelay(5); | 1230 | nvgpu_udelay(5); |
1235 | } while (!nvgpu_timeout_expired_msg(&timeout, | 1231 | } while (!nvgpu_timeout_expired_msg(&timeout, |
1236 | "sync-unmap failed on 0x%llx")); | 1232 | "sync-unmap failed on 0x%llx")); |
1237 | 1233 | ||
@@ -1383,8 +1379,6 @@ static struct mapped_buffer_node *find_mapped_buffer_less_than_locked( | |||
1383 | return mapped_buffer_from_rbtree_node(node); | 1379 | return mapped_buffer_from_rbtree_node(node); |
1384 | } | 1380 | } |
1385 | 1381 | ||
1386 | #define BFR_ATTRS (sizeof(nvmap_bfr_param)/sizeof(nvmap_bfr_param[0])) | ||
1387 | |||
1388 | struct buffer_attrs { | 1382 | struct buffer_attrs { |
1389 | struct sg_table *sgt; | 1383 | struct sg_table *sgt; |
1390 | u64 size; | 1384 | u64 size; |
@@ -4403,7 +4397,7 @@ int gk20a_mm_fb_flush(struct gk20a *g) | |||
4403 | flush_fb_flush_pending_v(data) == | 4397 | flush_fb_flush_pending_v(data) == |
4404 | flush_fb_flush_pending_busy_v()) { | 4398 | flush_fb_flush_pending_busy_v()) { |
4405 | gk20a_dbg_info("fb_flush 0x%x", data); | 4399 | gk20a_dbg_info("fb_flush 0x%x", data); |
4406 | udelay(5); | 4400 | nvgpu_udelay(5); |
4407 | } else | 4401 | } else |
4408 | break; | 4402 | break; |
4409 | } while (!nvgpu_timeout_expired(&timeout)); | 4403 | } while (!nvgpu_timeout_expired(&timeout)); |
@@ -4446,7 +4440,7 @@ static void gk20a_mm_l2_invalidate_locked(struct gk20a *g) | |||
4446 | flush_l2_system_invalidate_pending_busy_v()) { | 4440 | flush_l2_system_invalidate_pending_busy_v()) { |
4447 | gk20a_dbg_info("l2_system_invalidate 0x%x", | 4441 | gk20a_dbg_info("l2_system_invalidate 0x%x", |
4448 | data); | 4442 | data); |
4449 | udelay(5); | 4443 | nvgpu_udelay(5); |
4450 | } else | 4444 | } else |
4451 | break; | 4445 | break; |
4452 | } while (!nvgpu_timeout_expired(&timeout)); | 4446 | } while (!nvgpu_timeout_expired(&timeout)); |
@@ -4500,7 +4494,7 @@ void gk20a_mm_l2_flush(struct gk20a *g, bool invalidate) | |||
4500 | flush_l2_flush_dirty_pending_v(data) == | 4494 | flush_l2_flush_dirty_pending_v(data) == |
4501 | flush_l2_flush_dirty_pending_busy_v()) { | 4495 | flush_l2_flush_dirty_pending_busy_v()) { |
4502 | gk20a_dbg_info("l2_flush_dirty 0x%x", data); | 4496 | gk20a_dbg_info("l2_flush_dirty 0x%x", data); |
4503 | udelay(5); | 4497 | nvgpu_udelay(5); |
4504 | } else | 4498 | } else |
4505 | break; | 4499 | break; |
4506 | } while (!nvgpu_timeout_expired_msg(&timeout, | 4500 | } while (!nvgpu_timeout_expired_msg(&timeout, |
@@ -4545,7 +4539,7 @@ void gk20a_mm_cbc_clean(struct gk20a *g) | |||
4545 | flush_l2_clean_comptags_pending_v(data) == | 4539 | flush_l2_clean_comptags_pending_v(data) == |
4546 | flush_l2_clean_comptags_pending_busy_v()) { | 4540 | flush_l2_clean_comptags_pending_busy_v()) { |
4547 | gk20a_dbg_info("l2_clean_comptags 0x%x", data); | 4541 | gk20a_dbg_info("l2_clean_comptags 0x%x", data); |
4548 | udelay(5); | 4542 | nvgpu_udelay(5); |
4549 | } else | 4543 | } else |
4550 | break; | 4544 | break; |
4551 | } while (!nvgpu_timeout_expired_msg(&timeout, | 4545 | } while (!nvgpu_timeout_expired_msg(&timeout, |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 3625b679..cb9e1ba1 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -16,11 +16,9 @@ | |||
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | 16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
17 | */ | 17 | */ |
18 | 18 | ||
19 | #include <linux/delay.h> /* for mdelay */ | ||
20 | #include <linux/firmware.h> | 19 | #include <linux/firmware.h> |
21 | #include <linux/module.h> | 20 | #include <linux/module.h> |
22 | #include <linux/debugfs.h> | 21 | #include <linux/debugfs.h> |
23 | #include <linux/dma-mapping.h> | ||
24 | #include <linux/uaccess.h> | 22 | #include <linux/uaccess.h> |
25 | 23 | ||
26 | #include <nvgpu/nvgpu_common.h> | 24 | #include <nvgpu/nvgpu_common.h> |
@@ -2326,7 +2324,7 @@ int pmu_idle(struct pmu_gk20a *pmu) | |||
2326 | idle_stat)) | 2324 | idle_stat)) |
2327 | return -EBUSY; | 2325 | return -EBUSY; |
2328 | 2326 | ||
2329 | usleep_range(100, 200); | 2327 | nvgpu_usleep_range(100, 200); |
2330 | } while (1); | 2328 | } while (1); |
2331 | 2329 | ||
2332 | gk20a_dbg_fn("done"); | 2330 | gk20a_dbg_fn("done"); |
@@ -2424,7 +2422,7 @@ int pmu_enable_hw(struct pmu_gk20a *pmu, bool enable) | |||
2424 | gk20a_dbg_fn("done"); | 2422 | gk20a_dbg_fn("done"); |
2425 | return 0; | 2423 | return 0; |
2426 | } | 2424 | } |
2427 | udelay(PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT); | 2425 | nvgpu_udelay(PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT); |
2428 | } while (!nvgpu_timeout_expired(&timeout)); | 2426 | } while (!nvgpu_timeout_expired(&timeout)); |
2429 | 2427 | ||
2430 | g->ops.mc.disable(g, mc_enable_pwr_enabled_f()); | 2428 | g->ops.mc.disable(g, mc_enable_pwr_enabled_f()); |
@@ -2785,7 +2783,7 @@ int pmu_mutex_acquire(struct pmu_gk20a *pmu, u32 id, u32 *token) | |||
2785 | nvgpu_warn(g, | 2783 | nvgpu_warn(g, |
2786 | "fail to generate mutex token: val 0x%08x", | 2784 | "fail to generate mutex token: val 0x%08x", |
2787 | owner); | 2785 | owner); |
2788 | usleep_range(20, 40); | 2786 | nvgpu_usleep_range(20, 40); |
2789 | continue; | 2787 | continue; |
2790 | } | 2788 | } |
2791 | 2789 | ||
@@ -2812,7 +2810,7 @@ int pmu_mutex_acquire(struct pmu_gk20a *pmu, u32 id, u32 *token) | |||
2812 | pwr_pmu_mutex_id_release_value_f(owner)); | 2810 | pwr_pmu_mutex_id_release_value_f(owner)); |
2813 | gk20a_writel(g, pwr_pmu_mutex_id_release_r(), data); | 2811 | gk20a_writel(g, pwr_pmu_mutex_id_release_r(), data); |
2814 | 2812 | ||
2815 | usleep_range(20, 40); | 2813 | nvgpu_usleep_range(20, 40); |
2816 | continue; | 2814 | continue; |
2817 | } | 2815 | } |
2818 | } while (max_retry-- > 0); | 2816 | } while (max_retry-- > 0); |
@@ -3448,7 +3446,7 @@ static void pmu_setup_hw_enable_elpg(struct gk20a *g) | |||
3448 | gk20a_pmu_enable_elpg(g); | 3446 | gk20a_pmu_enable_elpg(g); |
3449 | } | 3447 | } |
3450 | 3448 | ||
3451 | udelay(50); | 3449 | nvgpu_udelay(50); |
3452 | 3450 | ||
3453 | /* Enable AELPG */ | 3451 | /* Enable AELPG */ |
3454 | if (g->aelpg_enabled) { | 3452 | if (g->aelpg_enabled) { |
@@ -4335,7 +4333,7 @@ int pmu_wait_message_cond(struct pmu_gk20a *pmu, u32 timeout_ms, | |||
4335 | if (gk20a_readl(g, pwr_falcon_irqstat_r()) & servicedpmuint) | 4333 | if (gk20a_readl(g, pwr_falcon_irqstat_r()) & servicedpmuint) |
4336 | gk20a_pmu_isr(g); | 4334 | gk20a_pmu_isr(g); |
4337 | 4335 | ||
4338 | usleep_range(delay, delay * 2); | 4336 | nvgpu_usleep_range(delay, delay * 2); |
4339 | delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); | 4337 | delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); |
4340 | } while (!nvgpu_timeout_expired(&timeout)); | 4338 | } while (!nvgpu_timeout_expired(&timeout)); |
4341 | 4339 | ||
@@ -4689,7 +4687,7 @@ static int pmu_write_cmd(struct pmu_gk20a *pmu, struct pmu_cmd *cmd, | |||
4689 | do { | 4687 | do { |
4690 | err = pmu_queue_open_write(pmu, queue, cmd->hdr.size); | 4688 | err = pmu_queue_open_write(pmu, queue, cmd->hdr.size); |
4691 | if (err == -EAGAIN && !nvgpu_timeout_expired(&timeout)) | 4689 | if (err == -EAGAIN && !nvgpu_timeout_expired(&timeout)) |
4692 | usleep_range(1000, 2000); | 4690 | nvgpu_usleep_range(1000, 2000); |
4693 | else | 4691 | else |
4694 | break; | 4692 | break; |
4695 | } while (1); | 4693 | } while (1); |
diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c index 08198776..07cdc9e5 100644 --- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | |||
@@ -16,11 +16,10 @@ | |||
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | 16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
17 | */ | 17 | */ |
18 | 18 | ||
19 | #include <linux/delay.h> /* for mdelay */ | ||
20 | |||
21 | #include "gk20a.h" | 19 | #include "gk20a.h" |
22 | 20 | ||
23 | #include <nvgpu/log.h> | 21 | #include <nvgpu/log.h> |
22 | #include <nvgpu/timers.h> | ||
24 | 23 | ||
25 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> | 24 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> |
26 | #include <nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h> | 25 | #include <nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h> |
@@ -62,7 +61,7 @@ static void gk20a_reset_priv_ring(struct gk20a *g) | |||
62 | 61 | ||
63 | gk20a_writel(g, pri_ringmaster_global_ctl_r(), | 62 | gk20a_writel(g, pri_ringmaster_global_ctl_r(), |
64 | pri_ringmaster_global_ctl_ring_reset_asserted_f()); | 63 | pri_ringmaster_global_ctl_ring_reset_asserted_f()); |
65 | udelay(20); | 64 | nvgpu_udelay(20); |
66 | gk20a_writel(g, pri_ringmaster_global_ctl_r(), | 65 | gk20a_writel(g, pri_ringmaster_global_ctl_r(), |
67 | pri_ringmaster_global_ctl_ring_reset_deasserted_f()); | 66 | pri_ringmaster_global_ctl_ring_reset_deasserted_f()); |
68 | 67 | ||
@@ -119,7 +118,7 @@ void gk20a_priv_ring_isr(struct gk20a *g) | |||
119 | do { | 118 | do { |
120 | cmd = pri_ringmaster_command_cmd_v( | 119 | cmd = pri_ringmaster_command_cmd_v( |
121 | gk20a_readl(g, pri_ringmaster_command_r())); | 120 | gk20a_readl(g, pri_ringmaster_command_r())); |
122 | usleep_range(20, 40); | 121 | nvgpu_usleep_range(20, 40); |
123 | } while (cmd != pri_ringmaster_command_cmd_no_cmd_v() && --retry); | 122 | } while (cmd != pri_ringmaster_command_cmd_no_cmd_v() && --retry); |
124 | 123 | ||
125 | if (retry <= 0) | 124 | if (retry <= 0) |
diff --git a/drivers/gpu/nvgpu/gk20a/sched_gk20a.c b/drivers/gpu/nvgpu/gk20a/sched_gk20a.c index cd5df5bf..ff038b62 100644 --- a/drivers/gpu/nvgpu/gk20a/sched_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/sched_gk20a.c | |||
@@ -12,14 +12,8 @@ | |||
12 | */ | 12 | */ |
13 | 13 | ||
14 | #include <asm/barrier.h> | 14 | #include <asm/barrier.h> |
15 | #include <linux/kthread.h> | ||
16 | #include <linux/circ_buf.h> | ||
17 | #include <linux/delay.h> | ||
18 | #include <linux/wait.h> | 15 | #include <linux/wait.h> |
19 | #include <linux/ktime.h> | ||
20 | #include <linux/hashtable.h> | ||
21 | #include <linux/debugfs.h> | 16 | #include <linux/debugfs.h> |
22 | #include <linux/log2.h> | ||
23 | #include <linux/uaccess.h> | 17 | #include <linux/uaccess.h> |
24 | #include <linux/poll.h> | 18 | #include <linux/poll.h> |
25 | #include <uapi/linux/nvgpu.h> | 19 | #include <uapi/linux/nvgpu.h> |
diff --git a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c index d8e184ef..17882e72 100644 --- a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c | |||
@@ -150,7 +150,7 @@ int gm20b_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op, | |||
150 | val = gk20a_readl(g, ctrl1); | 150 | val = gk20a_readl(g, ctrl1); |
151 | if (!(val & hw_op)) | 151 | if (!(val & hw_op)) |
152 | break; | 152 | break; |
153 | udelay(5); | 153 | nvgpu_udelay(5); |
154 | } while (!nvgpu_timeout_expired(&timeout)); | 154 | } while (!nvgpu_timeout_expired(&timeout)); |
155 | 155 | ||
156 | if (nvgpu_timeout_peek_expired(&timeout)) { | 156 | if (nvgpu_timeout_peek_expired(&timeout)) { |