diff options
author | David Nieto <dmartineznie@nvidia.com> | 2017-05-12 14:07:00 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-05-24 07:55:42 -0400 |
commit | 2173add7ae7210606afdaa56995a61d012b9a2f1 (patch) | |
tree | 3e6f637ab0c4f2e28aa63823105764f39c774a85 | |
parent | 45ca7cb8c5774cfc15015973b1883faa1d93b9e6 (diff) |
gpu: nvgpu: per-chip GPCCS exception support
Adding support for ISR handling of GPCCS exceptions
and GCC ECC support
JIRA: GPUT19X-83
Change-Id: Ica749dc678f152d536052cf47f2ea2b205a231d6
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1480997
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 122 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 460 |
2 files changed, 580 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 014ba537..764374cc 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -634,6 +634,70 @@ static int gr_gv11b_handle_gcc_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
634 | return 0; | 634 | return 0; |
635 | } | 635 | } |
636 | 636 | ||
637 | static int gr_gv11b_handle_gpccs_ecc_exception(struct gk20a *g, u32 gpc, | ||
638 | u32 exception) | ||
639 | { | ||
640 | int ret = 0; | ||
641 | u32 ecc_status, ecc_addr, corrected_cnt, uncorrected_cnt; | ||
642 | int hww_esr; | ||
643 | u32 offset = proj_gpc_stride_v() * gpc; | ||
644 | |||
645 | hww_esr = gk20a_readl(g, gr_gpc0_gpccs_hww_esr_r() + offset); | ||
646 | |||
647 | if (!(hww_esr & (gr_gpc0_gpccs_hww_esr_ecc_uncorrected_m() | | ||
648 | gr_gpc0_gpccs_hww_esr_ecc_corrected_m()))) | ||
649 | return ret; | ||
650 | |||
651 | ecc_status = gk20a_readl(g, | ||
652 | gr_gpc0_gpccs_falcon_ecc_status_r() + offset); | ||
653 | ecc_addr = gk20a_readl(g, | ||
654 | gr_gpc0_gpccs_falcon_ecc_address_r() + offset); | ||
655 | corrected_cnt = gk20a_readl(g, | ||
656 | gr_gpc0_gpccs_falcon_ecc_corrected_err_count_r() + offset); | ||
657 | uncorrected_cnt = gk20a_readl(g, | ||
658 | gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_r() + offset); | ||
659 | |||
660 | /* clear the interrupt */ | ||
661 | gk20a_writel(g, gr_gpc0_gpccs_falcon_ecc_status_r() + offset, | ||
662 | gr_gpc0_gpccs_falcon_ecc_status_reset_task_f()); | ||
663 | |||
664 | nvgpu_log(g, gpu_dbg_intr, | ||
665 | "gppcs gpc:%d ecc interrupt intr: 0x%x", gpc, hww_esr); | ||
666 | |||
667 | if (ecc_status & gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_m()) | ||
668 | nvgpu_log(g, gpu_dbg_intr, "imem ecc error corrected"); | ||
669 | if (ecc_status & | ||
670 | gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_m()) | ||
671 | nvgpu_log(g, gpu_dbg_intr, "imem ecc error uncorrected"); | ||
672 | if (ecc_status & | ||
673 | gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_m()) | ||
674 | nvgpu_log(g, gpu_dbg_intr, "dmem ecc error corrected"); | ||
675 | if (ecc_status & | ||
676 | gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_m()) | ||
677 | nvgpu_log(g, gpu_dbg_intr, "dmem ecc error uncorrected"); | ||
678 | |||
679 | nvgpu_log(g, gpu_dbg_intr, | ||
680 | "ecc error row address: 0x%x", | ||
681 | gr_gpc0_gpccs_falcon_ecc_address_row_address_v(ecc_addr)); | ||
682 | |||
683 | nvgpu_log(g, gpu_dbg_intr, | ||
684 | "ecc error count corrected: %d, uncorrected %d", | ||
685 | gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_v(corrected_cnt), | ||
686 | gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_v(uncorrected_cnt)); | ||
687 | |||
688 | return ret; | ||
689 | } | ||
690 | |||
691 | static int gr_gv11b_handle_gpc_gpccs_exception(struct gk20a *g, u32 gpc, | ||
692 | u32 gpc_exception) | ||
693 | { | ||
694 | if (gpc_exception & gr_gpc0_gpccs_gpc_exception_gpccs_m()) | ||
695 | return gr_gv11b_handle_gpccs_ecc_exception(g, gpc, | ||
696 | gpc_exception); | ||
697 | |||
698 | return 0; | ||
699 | } | ||
700 | |||
637 | static void gr_gv11b_enable_gpc_exceptions(struct gk20a *g) | 701 | static void gr_gv11b_enable_gpc_exceptions(struct gk20a *g) |
638 | { | 702 | { |
639 | struct gr_gk20a *gr = &g->gr; | 703 | struct gr_gk20a *gr = &g->gr; |
@@ -646,7 +710,8 @@ static void gr_gv11b_enable_gpc_exceptions(struct gk20a *g) | |||
646 | gr_gpcs_gpccs_gpc_exception_en_tpc_f((1 << gr->tpc_count) - 1); | 710 | gr_gpcs_gpccs_gpc_exception_en_tpc_f((1 << gr->tpc_count) - 1); |
647 | 711 | ||
648 | gk20a_writel(g, gr_gpcs_gpccs_gpc_exception_en_r(), | 712 | gk20a_writel(g, gr_gpcs_gpccs_gpc_exception_en_r(), |
649 | (tpc_mask | gr_gpcs_gpccs_gpc_exception_en_gcc_f(1))); | 713 | (tpc_mask | gr_gpcs_gpccs_gpc_exception_en_gcc_f(1) |
714 | gr_gpcs_gpccs_gpc_exception_en_gpccs_f(1)); | ||
650 | } | 715 | } |
651 | 716 | ||
652 | static int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | 717 | static int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, |
@@ -1622,6 +1687,55 @@ static int gr_gv11b_get_cilp_preempt_pending_chid(struct gk20a *g, int *__chid) | |||
1622 | return ret; | 1687 | return ret; |
1623 | } | 1688 | } |
1624 | 1689 | ||
1690 | static void gr_gv11b_handle_fecs_ecc_error(struct gk20a *g, u32 intr) | ||
1691 | { | ||
1692 | u32 ecc_status, ecc_addr, corrected_cnt, uncorrected_cnt; | ||
1693 | |||
1694 | if (intr & (gr_fecs_host_int_status_ecc_uncorrected_m() | | ||
1695 | gr_fecs_host_int_status_ecc_corrected_m())) { | ||
1696 | ecc_status = gk20a_readl(g, gr_fecs_falcon_ecc_status_r()); | ||
1697 | ecc_addr = gk20a_readl(g, | ||
1698 | gr_fecs_falcon_ecc_address_r()); | ||
1699 | corrected_cnt = gk20a_readl(g, | ||
1700 | gr_fecs_falcon_ecc_corrected_err_count_r()); | ||
1701 | uncorrected_cnt = gk20a_readl(g, | ||
1702 | gr_fecs_falcon_ecc_uncorrected_err_count_r()); | ||
1703 | |||
1704 | /* clear the interrupt */ | ||
1705 | gk20a_writel(g, gr_fecs_falcon_ecc_status_r(), | ||
1706 | gr_fecs_falcon_ecc_status_reset_task_f()); | ||
1707 | |||
1708 | nvgpu_log(g, gpu_dbg_intr, | ||
1709 | "fecs ecc interrupt intr: 0x%x", intr); | ||
1710 | |||
1711 | if (ecc_status & | ||
1712 | gr_fecs_falcon_ecc_status_corrected_err_imem_m()) | ||
1713 | nvgpu_log(g, gpu_dbg_intr, "imem ecc error corrected"); | ||
1714 | if (ecc_status & | ||
1715 | gr_fecs_falcon_ecc_status_uncorrected_err_imem_m()) | ||
1716 | nvgpu_log(g, gpu_dbg_intr, | ||
1717 | "imem ecc error uncorrected"); | ||
1718 | if (ecc_status & | ||
1719 | gr_fecs_falcon_ecc_status_corrected_err_dmem_m()) | ||
1720 | nvgpu_log(g, gpu_dbg_intr, "dmem ecc error corrected"); | ||
1721 | if (ecc_status & | ||
1722 | gr_fecs_falcon_ecc_status_uncorrected_err_dmem_m()) | ||
1723 | nvgpu_log(g, gpu_dbg_intr, | ||
1724 | "dmem ecc error uncorrected"); | ||
1725 | |||
1726 | nvgpu_log(g, gpu_dbg_intr, | ||
1727 | "ecc error row address: 0x%x", | ||
1728 | gr_fecs_falcon_ecc_address_row_address_v(ecc_addr)); | ||
1729 | |||
1730 | nvgpu_log(g, gpu_dbg_intr, | ||
1731 | "ecc error count corrected: %d, uncorrected %d", | ||
1732 | gr_fecs_falcon_ecc_corrected_err_count_total_v( | ||
1733 | corrected_cnt), | ||
1734 | gr_fecs_falcon_ecc_uncorrected_err_count_total_v( | ||
1735 | uncorrected_cnt)); | ||
1736 | } | ||
1737 | } | ||
1738 | |||
1625 | static int gr_gv11b_handle_fecs_error(struct gk20a *g, | 1739 | static int gr_gv11b_handle_fecs_error(struct gk20a *g, |
1626 | struct channel_gk20a *__ch, | 1740 | struct channel_gk20a *__ch, |
1627 | struct gr_gk20a_isr_data *isr_data) | 1741 | struct gr_gk20a_isr_data *isr_data) |
@@ -1680,6 +1794,9 @@ static int gr_gv11b_handle_fecs_error(struct gk20a *g, | |||
1680 | gk20a_channel_put(ch); | 1794 | gk20a_channel_put(ch); |
1681 | } | 1795 | } |
1682 | 1796 | ||
1797 | /* Handle ECC errors */ | ||
1798 | gr_gv11b_handle_fecs_ecc_error(g, gr_fecs_intr); | ||
1799 | |||
1683 | clean_up: | 1800 | clean_up: |
1684 | /* handle any remaining interrupts */ | 1801 | /* handle any remaining interrupts */ |
1685 | return gk20a_gr_handle_fecs_error(g, __ch, isr_data); | 1802 | return gk20a_gr_handle_fecs_error(g, __ch, isr_data); |
@@ -2214,5 +2331,6 @@ void gv11b_init_gr(struct gpu_ops *gops) | |||
2214 | gops->gr.write_pm_ptr = gr_gv11b_write_pm_ptr; | 2331 | gops->gr.write_pm_ptr = gr_gv11b_write_pm_ptr; |
2215 | gops->gr.init_elcg_mode = gr_gv11b_init_elcg_mode; | 2332 | gops->gr.init_elcg_mode = gr_gv11b_init_elcg_mode; |
2216 | gops->gr.load_tpc_mask = gr_gv11b_load_tpc_mask; | 2333 | gops->gr.load_tpc_mask = gr_gv11b_load_tpc_mask; |
2217 | 2334 | gops->gr.handle_gpc_gpccs_exception = | |
2335 | gr_gv11b_handle_gpc_gpccs_exception; | ||
2218 | } | 2336 | } |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 6f38cf5b..9917f86d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | |||
@@ -1398,6 +1398,22 @@ static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) | |||
1398 | { | 1398 | { |
1399 | return (v & 0xffff) << 0; | 1399 | return (v & 0xffff) << 0; |
1400 | } | 1400 | } |
1401 | static inline u32 gr_fecs_host_int_status_ecc_corrected_f(u32 v) | ||
1402 | { | ||
1403 | return (v & 0x1) << 21; | ||
1404 | } | ||
1405 | static inline u32 gr_fecs_host_int_status_ecc_corrected_m(void) | ||
1406 | { | ||
1407 | return 0x1 << 21; | ||
1408 | } | ||
1409 | static inline u32 gr_fecs_host_int_status_ecc_uncorrected_f(u32 v) | ||
1410 | { | ||
1411 | return (v & 0x1) << 22; | ||
1412 | } | ||
1413 | static inline u32 gr_fecs_host_int_status_ecc_uncorrected_m(void) | ||
1414 | { | ||
1415 | return 0x1 << 22; | ||
1416 | } | ||
1401 | static inline u32 gr_fecs_host_int_clear_r(void) | 1417 | static inline u32 gr_fecs_host_int_clear_r(void) |
1402 | { | 1418 | { |
1403 | return 0x00409c20; | 1419 | return 0x00409c20; |
@@ -3378,6 +3394,10 @@ static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) | |||
3378 | { | 3394 | { |
3379 | return (v & 0xff) << 16; | 3395 | return (v & 0xff) << 16; |
3380 | } | 3396 | } |
3397 | static inline u32 gr_gpcs_gpccs_gpc_exception_en_gpccs_f(u32 v) | ||
3398 | { | ||
3399 | return (v & 0x1) << 14; | ||
3400 | } | ||
3381 | static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) | 3401 | static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) |
3382 | { | 3402 | { |
3383 | return 0x00502c90; | 3403 | return 0x00502c90; |
@@ -3450,6 +3470,18 @@ static inline u32 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_v(u32 r) | |||
3450 | { | 3470 | { |
3451 | return (r >> 0) & 0xffff; | 3471 | return (r >> 0) & 0xffff; |
3452 | } | 3472 | } |
3473 | static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_f(u32 v) | ||
3474 | { | ||
3475 | return (v & 0x1) << 14; | ||
3476 | } | ||
3477 | static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_m(void) | ||
3478 | { | ||
3479 | return 0x1 << 14; | ||
3480 | } | ||
3481 | static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_pending_f(void) | ||
3482 | { | ||
3483 | return 0x4000; | ||
3484 | } | ||
3453 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) | 3485 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) |
3454 | { | 3486 | { |
3455 | return 0x00504508; | 3487 | return 0x00504508; |
@@ -3954,4 +3986,432 @@ static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) | |||
3954 | { | 3986 | { |
3955 | return 0x1ff << 0; | 3987 | return 0x1ff << 0; |
3956 | } | 3988 | } |
3989 | static inline u32 gr_gpc0_gpccs_hww_esr_r(void) | ||
3990 | { | ||
3991 | return 0x00502c98; | ||
3992 | } | ||
3993 | static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_f(u32 v) | ||
3994 | { | ||
3995 | return (v & 0x1) << 0; | ||
3996 | } | ||
3997 | static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_m(void) | ||
3998 | { | ||
3999 | return 0x1 << 0; | ||
4000 | } | ||
4001 | static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_pending_f(void) | ||
4002 | { | ||
4003 | return 0x1; | ||
4004 | } | ||
4005 | static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_f(u32 v) | ||
4006 | { | ||
4007 | return (v & 0x1) << 1; | ||
4008 | } | ||
4009 | static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_m(void) | ||
4010 | { | ||
4011 | return 0x1 << 1; | ||
4012 | } | ||
4013 | static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_pending_f(void) | ||
4014 | { | ||
4015 | return 0x2; | ||
4016 | } | ||
4017 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_r(void) | ||
4018 | { | ||
4019 | return 0x00502678; | ||
4020 | } | ||
4021 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_f(u32 v) | ||
4022 | { | ||
4023 | return (v & 0x1) << 0; | ||
4024 | } | ||
4025 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_m(void) | ||
4026 | { | ||
4027 | return 0x1 << 0; | ||
4028 | } | ||
4029 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_pending_f(void) | ||
4030 | { | ||
4031 | return 0x1; | ||
4032 | } | ||
4033 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_f(u32 v) | ||
4034 | { | ||
4035 | return (v & 0x1) << 1; | ||
4036 | } | ||
4037 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_m(void) | ||
4038 | { | ||
4039 | return 0x1 << 1; | ||
4040 | } | ||
4041 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_pending_f(void) | ||
4042 | { | ||
4043 | return 0x2; | ||
4044 | } | ||
4045 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_f(u32 v) | ||
4046 | { | ||
4047 | return (v & 0x1) << 4; | ||
4048 | } | ||
4049 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_m(void) | ||
4050 | { | ||
4051 | return 0x1 << 4; | ||
4052 | } | ||
4053 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_pending_f(void) | ||
4054 | { | ||
4055 | return 0x10; | ||
4056 | } | ||
4057 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_f(u32 v) | ||
4058 | { | ||
4059 | return (v & 0x1) << 5; | ||
4060 | } | ||
4061 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_m(void) | ||
4062 | { | ||
4063 | return 0x1 << 5; | ||
4064 | } | ||
4065 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_pending_f(void) | ||
4066 | { | ||
4067 | return 0x20; | ||
4068 | } | ||
4069 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) | ||
4070 | { | ||
4071 | return (v & 0x1) << 10; | ||
4072 | } | ||
4073 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m(void) | ||
4074 | { | ||
4075 | return 0x1 << 10; | ||
4076 | } | ||
4077 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_pending_f(void) | ||
4078 | { | ||
4079 | return 0x400; | ||
4080 | } | ||
4081 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_f(u32 v) | ||
4082 | { | ||
4083 | return (v & 0x1) << 8; | ||
4084 | } | ||
4085 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_m(void) | ||
4086 | { | ||
4087 | return 0x1 << 8; | ||
4088 | } | ||
4089 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_pending_f(void) | ||
4090 | { | ||
4091 | return 0x100; | ||
4092 | } | ||
4093 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) | ||
4094 | { | ||
4095 | return (v & 0x1) << 11; | ||
4096 | } | ||
4097 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_m(void) | ||
4098 | { | ||
4099 | return 0x1 << 11; | ||
4100 | } | ||
4101 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_pending_f(void) | ||
4102 | { | ||
4103 | return 0x800; | ||
4104 | } | ||
4105 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) | ||
4106 | { | ||
4107 | return (v & 0x1) << 9; | ||
4108 | } | ||
4109 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_m(void) | ||
4110 | { | ||
4111 | return 0x1 << 9; | ||
4112 | } | ||
4113 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_pending_f(void) | ||
4114 | { | ||
4115 | return 0x200; | ||
4116 | } | ||
4117 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_reset_f(u32 v) | ||
4118 | { | ||
4119 | return (v & 0x1) << 31; | ||
4120 | } | ||
4121 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_reset_task_f(void) | ||
4122 | { | ||
4123 | return 0x80000000; | ||
4124 | } | ||
4125 | static inline u32 gr_gpc0_gpccs_falcon_ecc_address_r(void) | ||
4126 | { | ||
4127 | return 0x00502684; | ||
4128 | } | ||
4129 | static inline u32 gr_gpc0_gpccs_falcon_ecc_address_index_f(u32 v) | ||
4130 | { | ||
4131 | return (v & 0x7fffff) << 0; | ||
4132 | } | ||
4133 | static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_s(void) | ||
4134 | { | ||
4135 | return 20; | ||
4136 | } | ||
4137 | static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_f(u32 v) | ||
4138 | { | ||
4139 | return (v & 0xfffff) << 0; | ||
4140 | } | ||
4141 | static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_m(void) | ||
4142 | { | ||
4143 | return 0xfffff << 0; | ||
4144 | } | ||
4145 | static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_v(u32 r) | ||
4146 | { | ||
4147 | return (r >> 0) & 0xfffff; | ||
4148 | } | ||
4149 | static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_r(void) | ||
4150 | { | ||
4151 | return 0x0050267c; | ||
4152 | } | ||
4153 | static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_s(void) | ||
4154 | { | ||
4155 | return 16; | ||
4156 | } | ||
4157 | static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_f(u32 v) | ||
4158 | { | ||
4159 | return (v & 0xffff) << 0; | ||
4160 | } | ||
4161 | static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_m(void) | ||
4162 | { | ||
4163 | return 0xffff << 0; | ||
4164 | } | ||
4165 | static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_v(u32 r) | ||
4166 | { | ||
4167 | return (r >> 0) & 0xffff; | ||
4168 | } | ||
4169 | static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_s(void) | ||
4170 | { | ||
4171 | return 16; | ||
4172 | } | ||
4173 | static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_f(u32 v) | ||
4174 | { | ||
4175 | return (v & 0xffff) << 16; | ||
4176 | } | ||
4177 | static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_m(void) | ||
4178 | { | ||
4179 | return 0xffff << 16; | ||
4180 | } | ||
4181 | static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_v(u32 r) | ||
4182 | { | ||
4183 | return (r >> 16) & 0xffff; | ||
4184 | } | ||
4185 | static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_r(void) | ||
4186 | { | ||
4187 | return 0x00502680; | ||
4188 | } | ||
4189 | static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_f(u32 v) | ||
4190 | { | ||
4191 | return (v & 0xffff) << 0; | ||
4192 | } | ||
4193 | static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_m(void) | ||
4194 | { | ||
4195 | return 0xffff << 0; | ||
4196 | } | ||
4197 | static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_v(u32 r) | ||
4198 | { | ||
4199 | return (r >> 0) & 0xffff; | ||
4200 | } | ||
4201 | static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_s(void) | ||
4202 | { | ||
4203 | return 16; | ||
4204 | } | ||
4205 | static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_f(u32 v) | ||
4206 | { | ||
4207 | return (v & 0xffff) << 16; | ||
4208 | } | ||
4209 | static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_m(void) | ||
4210 | { | ||
4211 | return 0xffff << 16; | ||
4212 | } | ||
4213 | static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r) | ||
4214 | { | ||
4215 | return (r >> 16) & 0xffff; | ||
4216 | } | ||
4217 | static inline u32 gr_fecs_falcon_ecc_status_r(void) | ||
4218 | { | ||
4219 | return 0x00409678; | ||
4220 | } | ||
4221 | static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_f(u32 v) | ||
4222 | { | ||
4223 | return (v & 0x1) << 0; | ||
4224 | } | ||
4225 | static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_m(void) | ||
4226 | { | ||
4227 | return 0x1 << 0; | ||
4228 | } | ||
4229 | static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_pending_f(void) | ||
4230 | { | ||
4231 | return 0x1; | ||
4232 | } | ||
4233 | static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_f(u32 v) | ||
4234 | { | ||
4235 | return (v & 0x1) << 1; | ||
4236 | } | ||
4237 | static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_m(void) | ||
4238 | { | ||
4239 | return 0x1 << 1; | ||
4240 | } | ||
4241 | static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_pending_f(void) | ||
4242 | { | ||
4243 | return 0x2; | ||
4244 | } | ||
4245 | static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_f(u32 v) | ||
4246 | { | ||
4247 | return (v & 0x1) << 4; | ||
4248 | } | ||
4249 | static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_m(void) | ||
4250 | { | ||
4251 | return 0x1 << 4; | ||
4252 | } | ||
4253 | static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_pending_f(void) | ||
4254 | { | ||
4255 | return 0x10; | ||
4256 | } | ||
4257 | static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_f(u32 v) | ||
4258 | { | ||
4259 | return (v & 0x1) << 5; | ||
4260 | } | ||
4261 | static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_m(void) | ||
4262 | { | ||
4263 | return 0x1 << 5; | ||
4264 | } | ||
4265 | static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_pending_f(void) | ||
4266 | { | ||
4267 | return 0x20; | ||
4268 | } | ||
4269 | static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) | ||
4270 | { | ||
4271 | return (v & 0x1) << 10; | ||
4272 | } | ||
4273 | static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m(void) | ||
4274 | { | ||
4275 | return 0x1 << 10; | ||
4276 | } | ||
4277 | static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_pending_f(void) | ||
4278 | { | ||
4279 | return 0x400; | ||
4280 | } | ||
4281 | static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_f(u32 v) | ||
4282 | { | ||
4283 | return (v & 0x1) << 8; | ||
4284 | } | ||
4285 | static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_m(void) | ||
4286 | { | ||
4287 | return 0x1 << 8; | ||
4288 | } | ||
4289 | static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_pending_f(void) | ||
4290 | { | ||
4291 | return 0x100; | ||
4292 | } | ||
4293 | static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) | ||
4294 | { | ||
4295 | return (v & 0x1) << 11; | ||
4296 | } | ||
4297 | static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_m(void) | ||
4298 | { | ||
4299 | return 0x1 << 11; | ||
4300 | } | ||
4301 | static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_pending_f(void) | ||
4302 | { | ||
4303 | return 0x800; | ||
4304 | } | ||
4305 | static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) | ||
4306 | { | ||
4307 | return (v & 0x1) << 9; | ||
4308 | } | ||
4309 | static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_m(void) | ||
4310 | { | ||
4311 | return 0x1 << 9; | ||
4312 | } | ||
4313 | static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_pending_f(void) | ||
4314 | { | ||
4315 | return 0x200; | ||
4316 | } | ||
4317 | static inline u32 gr_fecs_falcon_ecc_status_reset_f(u32 v) | ||
4318 | { | ||
4319 | return (v & 0x1) << 31; | ||
4320 | } | ||
4321 | static inline u32 gr_fecs_falcon_ecc_status_reset_task_f(void) | ||
4322 | { | ||
4323 | return 0x80000000; | ||
4324 | } | ||
4325 | static inline u32 gr_fecs_falcon_ecc_address_r(void) | ||
4326 | { | ||
4327 | return 0x00409684; | ||
4328 | } | ||
4329 | static inline u32 gr_fecs_falcon_ecc_address_index_f(u32 v) | ||
4330 | { | ||
4331 | return (v & 0x7fffff) << 0; | ||
4332 | } | ||
4333 | static inline u32 gr_fecs_falcon_ecc_address_row_address_s(void) | ||
4334 | { | ||
4335 | return 20; | ||
4336 | } | ||
4337 | static inline u32 gr_fecs_falcon_ecc_address_row_address_f(u32 v) | ||
4338 | { | ||
4339 | return (v & 0xfffff) << 0; | ||
4340 | } | ||
4341 | static inline u32 gr_fecs_falcon_ecc_address_row_address_m(void) | ||
4342 | { | ||
4343 | return 0xfffff << 0; | ||
4344 | } | ||
4345 | static inline u32 gr_fecs_falcon_ecc_address_row_address_v(u32 r) | ||
4346 | { | ||
4347 | return (r >> 0) & 0xfffff; | ||
4348 | } | ||
4349 | static inline u32 gr_fecs_falcon_ecc_corrected_err_count_r(void) | ||
4350 | { | ||
4351 | return 0x0040967c; | ||
4352 | } | ||
4353 | static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_s(void) | ||
4354 | { | ||
4355 | return 16; | ||
4356 | } | ||
4357 | static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_f(u32 v) | ||
4358 | { | ||
4359 | return (v & 0xffff) << 0; | ||
4360 | } | ||
4361 | static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_m(void) | ||
4362 | { | ||
4363 | return 0xffff << 0; | ||
4364 | } | ||
4365 | static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_v(u32 r) | ||
4366 | { | ||
4367 | return (r >> 0) & 0xffff; | ||
4368 | } | ||
4369 | static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_s(void) | ||
4370 | { | ||
4371 | return 16; | ||
4372 | } | ||
4373 | static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_f(u32 v) | ||
4374 | { | ||
4375 | return (v & 0xffff) << 16; | ||
4376 | } | ||
4377 | static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_m(void) | ||
4378 | { | ||
4379 | return 0xffff << 16; | ||
4380 | } | ||
4381 | static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_v(u32 r) | ||
4382 | { | ||
4383 | return (r >> 16) & 0xffff; | ||
4384 | } | ||
4385 | static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_r(void) | ||
4386 | { | ||
4387 | return 0x00409680; | ||
4388 | } | ||
4389 | static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_f(u32 v) | ||
4390 | { | ||
4391 | return (v & 0xffff) << 0; | ||
4392 | } | ||
4393 | static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_m(void) | ||
4394 | { | ||
4395 | return 0xffff << 0; | ||
4396 | } | ||
4397 | static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_v(u32 r) | ||
4398 | { | ||
4399 | return (r >> 0) & 0xffff; | ||
4400 | } | ||
4401 | static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_s(void) | ||
4402 | { | ||
4403 | return 16; | ||
4404 | } | ||
4405 | static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_f(u32 v) | ||
4406 | { | ||
4407 | return (v & 0xffff) << 16; | ||
4408 | } | ||
4409 | static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_m(void) | ||
4410 | { | ||
4411 | return 0xffff << 16; | ||
4412 | } | ||
4413 | static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r) | ||
4414 | { | ||
4415 | return (r >> 16) & 0xffff; | ||
4416 | } | ||
3957 | #endif | 4417 | #endif |