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authorPeter Daifuku <pdaifuku@nvidia.com>2016-06-09 19:09:52 -0400
committerVladislav Buzov <vbuzov@nvidia.com>2016-07-06 18:26:22 -0400
commit1b04326f400489f25399167ef9f1c931a576656e (patch)
tree0dca7cf0982773647ca7bee54b2e190e02a97f97
parentda4d5130e81b68d9773c8d64c7a6d944acfac0c8 (diff)
gpu: nvgpu: vgpu: dbg_set_powergate support
Add support for dbg_set_powergate when virtualized Jira VFND-1905 Change-Id: I0d81c8863b3eda4ae4fee42e5a95d2fc9d78b174 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1162048 (cherry picked from commit 0dfc55f390a10e21ae13e14dd2f16e89a3bddfa7) Reviewed-on: http://git-master/r/1167182 (cherry picked from commit 4e34a1844558d93da5ad208532ec28aeda228f95) Reviewed-on: http://git-master/r/1174701 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
-rw-r--r--drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c28
-rw-r--r--drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.h1
-rw-r--r--drivers/gpu/nvgpu/vgpu/dbg_vgpu.c36
-rw-r--r--include/linux/tegra_vgpu.h6
4 files changed, 55 insertions, 16 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
index 5e57502e..a23758ab 100644
--- a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
@@ -31,8 +31,11 @@
31#include "hw_gr_gk20a.h" 31#include "hw_gr_gk20a.h"
32#include "hw_perf_gk20a.h" 32#include "hw_perf_gk20a.h"
33 33
34static int dbg_set_powergate(struct dbg_session_gk20a *dbg_s, u32 powermode);
35
34struct dbg_gpu_session_ops dbg_gpu_session_ops_gk20a = { 36struct dbg_gpu_session_ops dbg_gpu_session_ops_gk20a = {
35 .exec_reg_ops = exec_regops_gk20a, 37 .exec_reg_ops = exec_regops_gk20a,
38 .dbg_set_powergate = dbg_set_powergate,
36}; 39};
37 40
38/* 41/*
@@ -116,11 +119,6 @@ static int gk20a_dbg_gpu_do_dev_open(struct inode *inode,
116 dbg_session->is_profiler = is_profiler; 119 dbg_session->is_profiler = is_profiler;
117 dbg_session->is_pg_disabled = false; 120 dbg_session->is_pg_disabled = false;
118 dbg_session->is_timeout_disabled = false; 121 dbg_session->is_timeout_disabled = false;
119 /* For vgpu, all power-gating features are currently disabled
120 * in the server. Set is_pg_disable to true to reflect this
121 * on the client side. */
122 if (gk20a_gpu_is_virtual(dev))
123 dbg_session->is_pg_disabled = true;
124 122
125 init_waitqueue_head(&dbg_session->dbg_events.wait_queue); 123 init_waitqueue_head(&dbg_session->dbg_events.wait_queue);
126 INIT_LIST_HEAD(&dbg_session->ch_list); 124 INIT_LIST_HEAD(&dbg_session->ch_list);
@@ -344,9 +342,6 @@ int gk20a_dbg_gpu_clear_broadcast_stop_trigger(struct channel_gk20a *ch)
344 return 0; 342 return 0;
345} 343}
346 344
347static int dbg_set_powergate(struct dbg_session_gk20a *dbg_s,
348 __u32 powermode);
349
350static int nvgpu_dbg_timeout_enable(struct dbg_session_gk20a *dbg_s, 345static int nvgpu_dbg_timeout_enable(struct dbg_session_gk20a *dbg_s,
351 int timeout_mode) 346 int timeout_mode)
352{ 347{
@@ -483,7 +478,8 @@ int gk20a_dbg_gpu_dev_release(struct inode *inode, struct file *filp)
483 * calling powergate/timeout enable ioctl 478 * calling powergate/timeout enable ioctl
484 */ 479 */
485 mutex_lock(&g->dbg_sessions_lock); 480 mutex_lock(&g->dbg_sessions_lock);
486 dbg_set_powergate(dbg_s, NVGPU_DBG_GPU_POWERGATE_MODE_ENABLE); 481 dbg_s->ops->dbg_set_powergate(dbg_s,
482 NVGPU_DBG_GPU_POWERGATE_MODE_ENABLE);
487 nvgpu_dbg_timeout_enable(dbg_s, NVGPU_DBG_GPU_IOCTL_TIMEOUT_ENABLE); 483 nvgpu_dbg_timeout_enable(dbg_s, NVGPU_DBG_GPU_IOCTL_TIMEOUT_ENABLE);
488 mutex_unlock(&g->dbg_sessions_lock); 484 mutex_unlock(&g->dbg_sessions_lock);
489 485
@@ -1018,8 +1014,11 @@ static int nvgpu_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s,
1018 * on other channels */ 1014 * on other channels */
1019 mutex_lock(&g->dbg_sessions_lock); 1015 mutex_lock(&g->dbg_sessions_lock);
1020 1016
1021 if (!dbg_s->is_pg_disabled) { 1017 if (!dbg_s->is_pg_disabled && !gk20a_gpu_is_virtual(dbg_s->dev)) {
1022 powergate_err = dbg_set_powergate(dbg_s, 1018 /* In the virtual case, the server will handle
1019 * disabling/enabling powergating when processing reg ops
1020 */
1021 powergate_err = dbg_s->ops->dbg_set_powergate(dbg_s,
1023 NVGPU_DBG_GPU_POWERGATE_MODE_DISABLE); 1022 NVGPU_DBG_GPU_POWERGATE_MODE_DISABLE);
1024 is_pg_disabled = true; 1023 is_pg_disabled = true;
1025 } 1024 }
@@ -1028,7 +1027,7 @@ static int nvgpu_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s,
1028 err = dbg_s->ops->exec_reg_ops(dbg_s, ops, args->num_ops); 1027 err = dbg_s->ops->exec_reg_ops(dbg_s, ops, args->num_ops);
1029 /* enable powergate, if previously disabled */ 1028 /* enable powergate, if previously disabled */
1030 if (is_pg_disabled) { 1029 if (is_pg_disabled) {
1031 powergate_err = dbg_set_powergate(dbg_s, 1030 powergate_err = dbg_s->ops->dbg_set_powergate(dbg_s,
1032 NVGPU_DBG_GPU_POWERGATE_MODE_ENABLE); 1031 NVGPU_DBG_GPU_POWERGATE_MODE_ENABLE);
1033 } 1032 }
1034 } 1033 }
@@ -1056,8 +1055,7 @@ static int nvgpu_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s,
1056 return err; 1055 return err;
1057} 1056}
1058 1057
1059static int dbg_set_powergate(struct dbg_session_gk20a *dbg_s, 1058static int dbg_set_powergate(struct dbg_session_gk20a *dbg_s, u32 powermode)
1060 __u32 powermode)
1061{ 1059{
1062 int err = 0; 1060 int err = 0;
1063 struct gk20a *g = get_gk20a(dbg_s->dev); 1061 struct gk20a *g = get_gk20a(dbg_s->dev);
@@ -1168,7 +1166,7 @@ static int nvgpu_ioctl_powergate_gk20a(struct dbg_session_gk20a *dbg_s,
1168 dev_name(dbg_s->dev), args->mode); 1166 dev_name(dbg_s->dev), args->mode);
1169 1167
1170 mutex_lock(&g->dbg_sessions_lock); 1168 mutex_lock(&g->dbg_sessions_lock);
1171 err = dbg_set_powergate(dbg_s, args->mode); 1169 err = dbg_s->ops->dbg_set_powergate(dbg_s, args->mode);
1172 mutex_unlock(&g->dbg_sessions_lock); 1170 mutex_unlock(&g->dbg_sessions_lock);
1173 return err; 1171 return err;
1174} 1172}
diff --git a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.h b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.h
index d569a6cd..55ff54b9 100644
--- a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.h
@@ -38,6 +38,7 @@ struct dbg_gpu_session_ops {
38 int (*exec_reg_ops)(struct dbg_session_gk20a *dbg_s, 38 int (*exec_reg_ops)(struct dbg_session_gk20a *dbg_s,
39 struct nvgpu_dbg_gpu_reg_op *ops, 39 struct nvgpu_dbg_gpu_reg_op *ops,
40 u64 num_ops); 40 u64 num_ops);
41 int (*dbg_set_powergate)(struct dbg_session_gk20a *dbg_s, u32 mode);
41}; 42};
42 43
43struct dbg_gpu_session_events { 44struct dbg_gpu_session_events {
diff --git a/drivers/gpu/nvgpu/vgpu/dbg_vgpu.c b/drivers/gpu/nvgpu/vgpu/dbg_vgpu.c
index a9533e03..38f072de 100644
--- a/drivers/gpu/nvgpu/vgpu/dbg_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/dbg_vgpu.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -69,7 +69,41 @@ fail:
69 return err; 69 return err;
70} 70}
71 71
72static int vgpu_dbg_set_powergate(struct dbg_session_gk20a *dbg_s, __u32 mode)
73{
74 struct gk20a_platform *platform = gk20a_get_platform(dbg_s->g->dev);
75 struct tegra_vgpu_cmd_msg msg;
76 struct tegra_vgpu_set_powergate_params *p = &msg.params.set_powergate;
77 int err = 0;
78
79 gk20a_dbg_fn("");
80
81 /* Just return if requested mode is the same as the session's mode */
82 switch (mode) {
83 case NVGPU_DBG_GPU_POWERGATE_MODE_DISABLE:
84 if (dbg_s->is_pg_disabled)
85 return 0;
86 dbg_s->is_pg_disabled = true;
87 break;
88 case NVGPU_DBG_GPU_POWERGATE_MODE_ENABLE:
89 if (!dbg_s->is_pg_disabled)
90 return 0;
91 dbg_s->is_pg_disabled = false;
92 break;
93 default:
94 return -EINVAL;
95 }
96
97 msg.cmd = TEGRA_VGPU_CMD_SET_POWERGATE;
98 msg.handle = platform->virt_handle;
99 p->mode = mode;
100 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
101 err = err ? err : msg.ret;
102 return err;
103}
104
72void vgpu_dbg_init(void) 105void vgpu_dbg_init(void)
73{ 106{
74 dbg_gpu_session_ops_gk20a.exec_reg_ops = vgpu_exec_regops; 107 dbg_gpu_session_ops_gk20a.exec_reg_ops = vgpu_exec_regops;
108 dbg_gpu_session_ops_gk20a.dbg_set_powergate = vgpu_dbg_set_powergate;
75} 109}
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h
index 196b08ca..6e8f5d53 100644
--- a/include/linux/tegra_vgpu.h
+++ b/include/linux/tegra_vgpu.h
@@ -96,6 +96,7 @@ enum {
96 TEGRA_VGPU_CMD_CHANNEL_FORCE_RESET = 57, 96 TEGRA_VGPU_CMD_CHANNEL_FORCE_RESET = 57,
97 TEGRA_VGPU_CMD_CHANNEL_ENABLE = 58, 97 TEGRA_VGPU_CMD_CHANNEL_ENABLE = 58,
98 TEGRA_VGPU_CMD_READ_PTIMER = 59, 98 TEGRA_VGPU_CMD_READ_PTIMER = 59,
99 TEGRA_VGPU_CMD_SET_POWERGATE = 60,
99}; 100};
100 101
101struct tegra_vgpu_connect_params { 102struct tegra_vgpu_connect_params {
@@ -394,6 +395,10 @@ struct tegra_vgpu_read_ptimer_params {
394 u64 time; 395 u64 time;
395}; 396};
396 397
398struct tegra_vgpu_set_powergate_params {
399 u32 mode;
400};
401
397struct tegra_vgpu_cmd_msg { 402struct tegra_vgpu_cmd_msg {
398 u32 cmd; 403 u32 cmd;
399 int ret; 404 int ret;
@@ -435,6 +440,7 @@ struct tegra_vgpu_cmd_msg {
435 struct tegra_vgpu_tsg_timeslice_params tsg_timeslice; 440 struct tegra_vgpu_tsg_timeslice_params tsg_timeslice;
436 struct tegra_vgpu_tsg_runlist_interleave_params tsg_interleave; 441 struct tegra_vgpu_tsg_runlist_interleave_params tsg_interleave;
437 struct tegra_vgpu_read_ptimer_params read_ptimer; 442 struct tegra_vgpu_read_ptimer_params read_ptimer;
443 struct tegra_vgpu_set_powergate_params set_powergate;
438 char padding[192]; 444 char padding[192];
439 } params; 445 } params;
440}; 446};