diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2017-04-06 15:17:26 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-04-07 16:48:24 -0400 |
commit | 1add126551309a323ae422be41c9db2203bbe112 (patch) | |
tree | d9a620ca88a3c73c0f3dc0f7079ea4d3c24eb075 | |
parent | 86ecddf68734e4a938eda351f4dde11ab507de3f (diff) |
gpu: nvgpu: clk: Use new error macros
gk20a_err() and gk20a_warn() require a struct device pointer,
which is not portable across operating systems. The new nvgpu_err()
and nvgpu_warn() macros take struct gk20a pointer. Convert code
to use the more portable macros.
JIRA NVGPU-16
Change-Id: I58bb9e2fb7e5b18f74fbb92b70150cce97968fc3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1457347
Reviewed-by: Alex Waterman <alexw@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk.c | 21 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_arb.c | 60 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_common.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_domain.c | 14 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_fll.c | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_freq_controller.c | 13 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_mclk.c | 21 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_prog.c | 25 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_vf_point.c | 18 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_vin.c | 8 |
10 files changed, 79 insertions, 115 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk.c b/drivers/gpu/nvgpu/clk/clk.c index e809b5e9..8b36394d 100644 --- a/drivers/gpu/nvgpu/clk/clk.c +++ b/drivers/gpu/nvgpu/clk/clk.c | |||
@@ -36,8 +36,7 @@ static void clkrpc_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg, | |||
36 | gk20a_dbg_info(""); | 36 | gk20a_dbg_info(""); |
37 | 37 | ||
38 | if (msg->msg.clk.msg_type != NV_PMU_CLK_MSG_ID_RPC) { | 38 | if (msg->msg.clk.msg_type != NV_PMU_CLK_MSG_ID_RPC) { |
39 | gk20a_err(dev_from_gk20a(g), | 39 | nvgpu_err(g, "unsupported msg for VFE LOAD RPC %x", |
40 | "unsupported msg for VFE LOAD RPC %x", | ||
41 | msg->msg.clk.msg_type); | 40 | msg->msg.clk.msg_type); |
42 | return; | 41 | return; |
43 | } | 42 | } |
@@ -99,8 +98,7 @@ int clk_pmu_freq_controller_load(struct gk20a *g, bool bload) | |||
99 | &seqdesc, ~0); | 98 | &seqdesc, ~0); |
100 | 99 | ||
101 | if (status) { | 100 | if (status) { |
102 | gk20a_err(dev_from_gk20a(g), | 101 | nvgpu_err(g, "unable to post clk RPC cmd %x", |
103 | "unable to post clk RPC cmd %x", | ||
104 | cmd.cmd.clk.cmd_type); | 102 | cmd.cmd.clk.cmd_type); |
105 | goto done; | 103 | goto done; |
106 | } | 104 | } |
@@ -110,7 +108,7 @@ int clk_pmu_freq_controller_load(struct gk20a *g, bool bload) | |||
110 | &handler.success, 1); | 108 | &handler.success, 1); |
111 | 109 | ||
112 | if (handler.success == 0) { | 110 | if (handler.success == 0) { |
113 | gk20a_err(dev_from_gk20a(g), "rpc call to load freq cntlr cal failed"); | 111 | nvgpu_err(g, "rpc call to load freq cntlr cal failed"); |
114 | status = -EINVAL; | 112 | status = -EINVAL; |
115 | } | 113 | } |
116 | 114 | ||
@@ -159,8 +157,7 @@ u32 clk_pmu_vin_load(struct gk20a *g) | |||
159 | &seqdesc, ~0); | 157 | &seqdesc, ~0); |
160 | 158 | ||
161 | if (status) { | 159 | if (status) { |
162 | gk20a_err(dev_from_gk20a(g), | 160 | nvgpu_err(g, "unable to post clk RPC cmd %x", |
163 | "unable to post clk RPC cmd %x", | ||
164 | cmd.cmd.clk.cmd_type); | 161 | cmd.cmd.clk.cmd_type); |
165 | goto done; | 162 | goto done; |
166 | } | 163 | } |
@@ -170,7 +167,7 @@ u32 clk_pmu_vin_load(struct gk20a *g) | |||
170 | &handler.success, 1); | 167 | &handler.success, 1); |
171 | 168 | ||
172 | if (handler.success == 0) { | 169 | if (handler.success == 0) { |
173 | gk20a_err(dev_from_gk20a(g), "rpc call to load vin cal failed"); | 170 | nvgpu_err(g, "rpc call to load vin cal failed"); |
174 | status = -EINVAL; | 171 | status = -EINVAL; |
175 | } | 172 | } |
176 | 173 | ||
@@ -258,8 +255,7 @@ static u32 clk_pmu_vf_inject(struct gk20a *g, struct set_fll_clk *setfllclk) | |||
258 | &seqdesc, ~0); | 255 | &seqdesc, ~0); |
259 | 256 | ||
260 | if (status) { | 257 | if (status) { |
261 | gk20a_err(dev_from_gk20a(g), | 258 | nvgpu_err(g, "unable to post clk RPC cmd %x", |
262 | "unable to post clk RPC cmd %x", | ||
263 | cmd.cmd.clk.cmd_type); | 259 | cmd.cmd.clk.cmd_type); |
264 | goto done; | 260 | goto done; |
265 | } | 261 | } |
@@ -269,7 +265,7 @@ static u32 clk_pmu_vf_inject(struct gk20a *g, struct set_fll_clk *setfllclk) | |||
269 | &handler.success, 1); | 265 | &handler.success, 1); |
270 | 266 | ||
271 | if (handler.success == 0) { | 267 | if (handler.success == 0) { |
272 | gk20a_err(dev_from_gk20a(g), "rpc call to inject clock failed"); | 268 | nvgpu_err(g, "rpc call to inject clock failed"); |
273 | status = -EINVAL; | 269 | status = -EINVAL; |
274 | } | 270 | } |
275 | done: | 271 | done: |
@@ -359,8 +355,7 @@ int clk_set_fll_clks(struct gk20a *g, struct set_fll_clk *setfllclk) | |||
359 | status = clk_pmu_vf_inject(g, setfllclk); | 355 | status = clk_pmu_vf_inject(g, setfllclk); |
360 | 356 | ||
361 | if (status) | 357 | if (status) |
362 | gk20a_err(dev_from_gk20a(g), | 358 | nvgpu_err(g, "vf inject to change clk failed"); |
363 | "vf inject to change clk failed"); | ||
364 | 359 | ||
365 | /* save regime ids */ | 360 | /* save regime ids */ |
366 | status = set_regime_id(g, CTRL_CLK_DOMAIN_XBAR2CLK, | 361 | status = set_regime_id(g, CTRL_CLK_DOMAIN_XBAR2CLK, |
diff --git a/drivers/gpu/nvgpu/clk/clk_arb.c b/drivers/gpu/nvgpu/clk/clk_arb.c index b8be3334..85a5018d 100644 --- a/drivers/gpu/nvgpu/clk/clk_arb.c +++ b/drivers/gpu/nvgpu/clk/clk_arb.c | |||
@@ -706,14 +706,12 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) | |||
706 | /* Get allowed memory ranges */ | 706 | /* Get allowed memory ranges */ |
707 | if (g->ops.clk_arb.get_arbiter_clk_range(g, CTRL_CLK_DOMAIN_GPC2CLK, | 707 | if (g->ops.clk_arb.get_arbiter_clk_range(g, CTRL_CLK_DOMAIN_GPC2CLK, |
708 | &gpc2clk_min, &gpc2clk_max) < 0) { | 708 | &gpc2clk_min, &gpc2clk_max) < 0) { |
709 | gk20a_err(dev_from_gk20a(g), | 709 | nvgpu_err(g, "failed to fetch GPC2CLK range"); |
710 | "failed to fetch GPC2CLK range"); | ||
711 | goto exit_vf_table; | 710 | goto exit_vf_table; |
712 | } | 711 | } |
713 | if (g->ops.clk_arb.get_arbiter_clk_range(g, CTRL_CLK_DOMAIN_MCLK, | 712 | if (g->ops.clk_arb.get_arbiter_clk_range(g, CTRL_CLK_DOMAIN_MCLK, |
714 | &mclk_min, &mclk_max) < 0) { | 713 | &mclk_min, &mclk_max) < 0) { |
715 | gk20a_err(dev_from_gk20a(g), | 714 | nvgpu_err(g, "failed to fetch MCLK range"); |
716 | "failed to fetch MCLK range"); | ||
717 | goto exit_vf_table; | 715 | goto exit_vf_table; |
718 | } | 716 | } |
719 | 717 | ||
@@ -722,20 +720,17 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) | |||
722 | 720 | ||
723 | if (clk_domain_get_f_points(arb->g, CTRL_CLK_DOMAIN_GPC2CLK, | 721 | if (clk_domain_get_f_points(arb->g, CTRL_CLK_DOMAIN_GPC2CLK, |
724 | &table->gpc2clk_num_points, arb->gpc2clk_f_points)) { | 722 | &table->gpc2clk_num_points, arb->gpc2clk_f_points)) { |
725 | gk20a_err(dev_from_gk20a(g), | 723 | nvgpu_err(g, "failed to fetch GPC2CLK frequency points"); |
726 | "failed to fetch GPC2CLK frequency points"); | ||
727 | goto exit_vf_table; | 724 | goto exit_vf_table; |
728 | } | 725 | } |
729 | 726 | ||
730 | if (clk_domain_get_f_points(arb->g, CTRL_CLK_DOMAIN_MCLK, | 727 | if (clk_domain_get_f_points(arb->g, CTRL_CLK_DOMAIN_MCLK, |
731 | &table->mclk_num_points, arb->mclk_f_points)) { | 728 | &table->mclk_num_points, arb->mclk_f_points)) { |
732 | gk20a_err(dev_from_gk20a(g), | 729 | nvgpu_err(g, "failed to fetch MCLK frequency points"); |
733 | "failed to fetch MCLK frequency points"); | ||
734 | goto exit_vf_table; | 730 | goto exit_vf_table; |
735 | } | 731 | } |
736 | if (!table->mclk_num_points || !table->gpc2clk_num_points) { | 732 | if (!table->mclk_num_points || !table->gpc2clk_num_points) { |
737 | gk20a_err(dev_from_gk20a(g), | 733 | nvgpu_err(g, "empty queries to f points mclk %d gpc2clk %d", |
738 | "empty queries to f points mclk %d gpc2clk %d", | ||
739 | table->mclk_num_points, table->gpc2clk_num_points); | 734 | table->mclk_num_points, table->gpc2clk_num_points); |
740 | status = -EINVAL; | 735 | status = -EINVAL; |
741 | goto exit_vf_table; | 736 | goto exit_vf_table; |
@@ -749,15 +744,13 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) | |||
749 | p5_info = pstate_get_clk_set_info(g, | 744 | p5_info = pstate_get_clk_set_info(g, |
750 | CTRL_PERF_PSTATE_P5, clkwhich_mclk); | 745 | CTRL_PERF_PSTATE_P5, clkwhich_mclk); |
751 | if (!p5_info) { | 746 | if (!p5_info) { |
752 | gk20a_err(dev_from_gk20a(g), | 747 | nvgpu_err(g, "failed to get MCLK P5 info"); |
753 | "failed to get MCLK P5 info"); | ||
754 | goto exit_vf_table; | 748 | goto exit_vf_table; |
755 | } | 749 | } |
756 | p0_info = pstate_get_clk_set_info(g, | 750 | p0_info = pstate_get_clk_set_info(g, |
757 | CTRL_PERF_PSTATE_P0, clkwhich_mclk); | 751 | CTRL_PERF_PSTATE_P0, clkwhich_mclk); |
758 | if (!p0_info) { | 752 | if (!p0_info) { |
759 | gk20a_err(dev_from_gk20a(g), | 753 | nvgpu_err(g, "failed to get MCLK P0 info"); |
760 | "failed to get MCLK P0 info"); | ||
761 | goto exit_vf_table; | 754 | goto exit_vf_table; |
762 | } | 755 | } |
763 | 756 | ||
@@ -775,7 +768,7 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) | |||
775 | &table->mclk_points[j].mem_mhz, &mclk_voltuv, | 768 | &table->mclk_points[j].mem_mhz, &mclk_voltuv, |
776 | CTRL_VOLT_DOMAIN_LOGIC); | 769 | CTRL_VOLT_DOMAIN_LOGIC); |
777 | if (status < 0) { | 770 | if (status < 0) { |
778 | gk20a_err(dev_from_gk20a(g), | 771 | nvgpu_err(g, |
779 | "failed to get MCLK LOGIC voltage"); | 772 | "failed to get MCLK LOGIC voltage"); |
780 | goto exit_vf_table; | 773 | goto exit_vf_table; |
781 | } | 774 | } |
@@ -784,8 +777,7 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) | |||
784 | &mclk_voltuv_sram, | 777 | &mclk_voltuv_sram, |
785 | CTRL_VOLT_DOMAIN_SRAM); | 778 | CTRL_VOLT_DOMAIN_SRAM); |
786 | if (status < 0) { | 779 | if (status < 0) { |
787 | gk20a_err(dev_from_gk20a(g), | 780 | nvgpu_err(g, "failed to get MCLK SRAM voltage"); |
788 | "failed to get MCLK SRAM voltage"); | ||
789 | goto exit_vf_table; | 781 | goto exit_vf_table; |
790 | } | 782 | } |
791 | 783 | ||
@@ -815,8 +807,7 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) | |||
815 | CTRL_PERF_PSTATE_P5, clkwhich_gpc2clk); | 807 | CTRL_PERF_PSTATE_P5, clkwhich_gpc2clk); |
816 | if (!p5_info) { | 808 | if (!p5_info) { |
817 | status = -EINVAL; | 809 | status = -EINVAL; |
818 | gk20a_err(dev_from_gk20a(g), | 810 | nvgpu_err(g, "failed to get GPC2CLK P5 info"); |
819 | "failed to get GPC2CLK P5 info"); | ||
820 | goto exit_vf_table; | 811 | goto exit_vf_table; |
821 | } | 812 | } |
822 | 813 | ||
@@ -824,8 +815,7 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) | |||
824 | CTRL_PERF_PSTATE_P0, clkwhich_gpc2clk); | 815 | CTRL_PERF_PSTATE_P0, clkwhich_gpc2clk); |
825 | if (!p0_info) { | 816 | if (!p0_info) { |
826 | status = -EINVAL; | 817 | status = -EINVAL; |
827 | gk20a_err(dev_from_gk20a(g), | 818 | nvgpu_err(g, "failed to get GPC2CLK P0 info"); |
828 | "failed to get GPC2CLK P0 info"); | ||
829 | goto exit_vf_table; | 819 | goto exit_vf_table; |
830 | } | 820 | } |
831 | 821 | ||
@@ -847,7 +837,7 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) | |||
847 | setfllclk.gpc2clkmhz = arb->gpc2clk_f_points[i]; | 837 | setfllclk.gpc2clkmhz = arb->gpc2clk_f_points[i]; |
848 | status = clk_get_fll_clks(g, &setfllclk); | 838 | status = clk_get_fll_clks(g, &setfllclk); |
849 | if (status < 0) { | 839 | if (status < 0) { |
850 | gk20a_err(dev_from_gk20a(g), | 840 | nvgpu_err(g, |
851 | "failed to get GPC2CLK slave clocks"); | 841 | "failed to get GPC2CLK slave clocks"); |
852 | goto exit_vf_table; | 842 | goto exit_vf_table; |
853 | } | 843 | } |
@@ -888,8 +878,7 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) | |||
888 | clkwhich_sys2clk); | 878 | clkwhich_sys2clk); |
889 | if (!p5_info) { | 879 | if (!p5_info) { |
890 | status = -EINVAL; | 880 | status = -EINVAL; |
891 | gk20a_err(dev_from_gk20a(g), | 881 | nvgpu_err(g, "failed to get SYS2CLK P5 info"); |
892 | "failed to get SYS2CLK P5 info"); | ||
893 | goto exit_vf_table; | 882 | goto exit_vf_table; |
894 | } | 883 | } |
895 | 884 | ||
@@ -915,8 +904,7 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) | |||
915 | } | 904 | } |
916 | /* no VF exists that satisfies condition */ | 905 | /* no VF exists that satisfies condition */ |
917 | if (j == table->gpc2clk_num_points) { | 906 | if (j == table->gpc2clk_num_points) { |
918 | gk20a_err(dev_from_gk20a(g), | 907 | nvgpu_err(g, "NO SYS2CLK VF point possible"); |
919 | "NO SYS2CLK VF point possible"); | ||
920 | status = -EINVAL; | 908 | status = -EINVAL; |
921 | goto exit_vf_table; | 909 | goto exit_vf_table; |
922 | } | 910 | } |
@@ -928,8 +916,7 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) | |||
928 | clkwhich_xbar2clk); | 916 | clkwhich_xbar2clk); |
929 | if (!p5_info) { | 917 | if (!p5_info) { |
930 | status = -EINVAL; | 918 | status = -EINVAL; |
931 | gk20a_err(dev_from_gk20a(g), | 919 | nvgpu_err(g, "failed to get SYS2CLK P5 info"); |
932 | "failed to get SYS2CLK P5 info"); | ||
933 | goto exit_vf_table; | 920 | goto exit_vf_table; |
934 | } | 921 | } |
935 | 922 | ||
@@ -954,8 +941,7 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) | |||
954 | /* no VF exists that satisfies condition */ | 941 | /* no VF exists that satisfies condition */ |
955 | if (j == table->gpc2clk_num_points) { | 942 | if (j == table->gpc2clk_num_points) { |
956 | status = -EINVAL; | 943 | status = -EINVAL; |
957 | gk20a_err(dev_from_gk20a(g), | 944 | nvgpu_err(g, "NO XBAR2CLK VF point possible"); |
958 | "NO XBAR2CLK VF point possible"); | ||
959 | 945 | ||
960 | goto exit_vf_table; | 946 | goto exit_vf_table; |
961 | } | 947 | } |
@@ -966,8 +952,7 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) | |||
966 | &alt_gpc2clk, &gpc2clk_voltuv, | 952 | &alt_gpc2clk, &gpc2clk_voltuv, |
967 | CTRL_VOLT_DOMAIN_LOGIC); | 953 | CTRL_VOLT_DOMAIN_LOGIC); |
968 | if (status < 0) { | 954 | if (status < 0) { |
969 | gk20a_err(dev_from_gk20a(g), | 955 | nvgpu_err(g, "failed to get GPC2CLK LOGIC voltage"); |
970 | "failed to get GPC2CLK LOGIC voltage"); | ||
971 | goto exit_vf_table; | 956 | goto exit_vf_table; |
972 | } | 957 | } |
973 | 958 | ||
@@ -976,8 +961,7 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) | |||
976 | &gpc2clk_voltuv_sram, | 961 | &gpc2clk_voltuv_sram, |
977 | CTRL_VOLT_DOMAIN_SRAM); | 962 | CTRL_VOLT_DOMAIN_SRAM); |
978 | if (status < 0) { | 963 | if (status < 0) { |
979 | gk20a_err(dev_from_gk20a(g), | 964 | nvgpu_err(g, "failed to get GPC2CLK SRAM voltage"); |
980 | "failed to get GPC2CLK SRAM voltage"); | ||
981 | goto exit_vf_table; | 965 | goto exit_vf_table; |
982 | } | 966 | } |
983 | 967 | ||
@@ -1017,8 +1001,7 @@ static void nvgpu_clk_arb_run_vf_table_cb(struct work_struct *work) | |||
1017 | /* get latest vf curve from pmu */ | 1001 | /* get latest vf curve from pmu */ |
1018 | err = clk_vf_point_cache(g); | 1002 | err = clk_vf_point_cache(g); |
1019 | if (err) { | 1003 | if (err) { |
1020 | gk20a_err(dev_from_gk20a(g), | 1004 | nvgpu_err(g, "failed to cache VF table"); |
1021 | "failed to cache VF table"); | ||
1022 | nvgpu_clk_arb_set_global_alarm(g, | 1005 | nvgpu_clk_arb_set_global_alarm(g, |
1023 | EVENT(ALARM_VF_TABLE_UPDATE_FAILED)); | 1006 | EVENT(ALARM_VF_TABLE_UPDATE_FAILED)); |
1024 | if (arb->update_work_queue) | 1007 | if (arb->update_work_queue) |
@@ -1288,8 +1271,7 @@ static void nvgpu_clk_arb_run_arbiter_cb(struct work_struct *work) | |||
1288 | 1271 | ||
1289 | exit_arb: | 1272 | exit_arb: |
1290 | if (status < 0) { | 1273 | if (status < 0) { |
1291 | gk20a_err(dev_from_gk20a(g), | 1274 | nvgpu_err(g, "Error in arbiter update"); |
1292 | "Error in arbiter update"); | ||
1293 | nvgpu_clk_arb_set_global_alarm(g, | 1275 | nvgpu_clk_arb_set_global_alarm(g, |
1294 | EVENT(ALARM_CLOCK_ARBITER_FAILED)); | 1276 | EVENT(ALARM_CLOCK_ARBITER_FAILED)); |
1295 | } | 1277 | } |
@@ -1856,7 +1838,7 @@ static u8 nvgpu_clk_arb_find_vf_point(struct nvgpu_clk_arb *arb, | |||
1856 | if (!table) | 1838 | if (!table) |
1857 | continue; | 1839 | continue; |
1858 | if ((!table->gpc2clk_num_points) || (!table->mclk_num_points)) { | 1840 | if ((!table->gpc2clk_num_points) || (!table->mclk_num_points)) { |
1859 | gk20a_err(dev_from_gk20a(arb->g), "found empty table"); | 1841 | nvgpu_err(arb->g, "found empty table"); |
1860 | goto find_exit; | 1842 | goto find_exit; |
1861 | } | 1843 | } |
1862 | /* First we check MCLK to find out which PSTATE we are | 1844 | /* First we check MCLK to find out which PSTATE we are |
diff --git a/drivers/gpu/nvgpu/clk/clk_common.c b/drivers/gpu/nvgpu/clk/clk_common.c index 346ad12b..3230ded0 100644 --- a/drivers/gpu/nvgpu/clk/clk_common.c +++ b/drivers/gpu/nvgpu/clk/clk_common.c | |||
@@ -29,7 +29,7 @@ struct clk *gk20a_clk_get(struct gk20a *g) | |||
29 | 29 | ||
30 | clk = clk_get_sys(clk_dev_id, "gpu"); | 30 | clk = clk_get_sys(clk_dev_id, "gpu"); |
31 | if (IS_ERR(clk)) { | 31 | if (IS_ERR(clk)) { |
32 | gk20a_err(dev, "fail to get tegra gpu clk %s/gpu\n", | 32 | nvgpu_err(g, "fail to get tegra gpu clk %s/gpu\n", |
33 | clk_dev_id); | 33 | clk_dev_id); |
34 | return NULL; | 34 | return NULL; |
35 | } | 35 | } |
diff --git a/drivers/gpu/nvgpu/clk/clk_domain.c b/drivers/gpu/nvgpu/clk/clk_domain.c index 2a614f55..c784bdb4 100644 --- a/drivers/gpu/nvgpu/clk/clk_domain.c +++ b/drivers/gpu/nvgpu/clk/clk_domain.c | |||
@@ -81,7 +81,7 @@ static u32 _clk_domains_pmudatainit_3x(struct gk20a *g, | |||
81 | 81 | ||
82 | status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu); | 82 | status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu); |
83 | if (status) { | 83 | if (status) { |
84 | gk20a_err(dev_from_gk20a(g), | 84 | nvgpu_err(g, |
85 | "error updating pmu boardobjgrp for clk domain 0x%x", | 85 | "error updating pmu boardobjgrp for clk domain 0x%x", |
86 | status); | 86 | status); |
87 | goto done; | 87 | goto done; |
@@ -142,7 +142,7 @@ u32 clk_domain_sw_setup(struct gk20a *g) | |||
142 | 142 | ||
143 | status = boardobjgrpconstruct_e32(&g->clk_pmu.clk_domainobjs.super); | 143 | status = boardobjgrpconstruct_e32(&g->clk_pmu.clk_domainobjs.super); |
144 | if (status) { | 144 | if (status) { |
145 | gk20a_err(dev_from_gk20a(g), | 145 | nvgpu_err(g, |
146 | "error creating boardobjgrp for clk domain, status - 0x%x", | 146 | "error creating boardobjgrp for clk domain, status - 0x%x", |
147 | status); | 147 | status); |
148 | goto done; | 148 | goto done; |
@@ -156,7 +156,7 @@ u32 clk_domain_sw_setup(struct gk20a *g) | |||
156 | status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, | 156 | status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, |
157 | clk, CLK, clk_domain, CLK_DOMAIN); | 157 | clk, CLK, clk_domain, CLK_DOMAIN); |
158 | if (status) { | 158 | if (status) { |
159 | gk20a_err(dev_from_gk20a(g), | 159 | nvgpu_err(g, |
160 | "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", | 160 | "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", |
161 | status); | 161 | status); |
162 | goto done; | 162 | goto done; |
@@ -379,7 +379,7 @@ static u32 devinit_get_clocks_table(struct gk20a *g, | |||
379 | break; | 379 | break; |
380 | 380 | ||
381 | default: | 381 | default: |
382 | gk20a_err(dev_from_gk20a(g), | 382 | nvgpu_err(g, |
383 | "error reading clock domain entry %d", index); | 383 | "error reading clock domain entry %d", index); |
384 | status = -EINVAL; | 384 | status = -EINVAL; |
385 | goto done; | 385 | goto done; |
@@ -388,7 +388,7 @@ static u32 devinit_get_clocks_table(struct gk20a *g, | |||
388 | pclkdomain_dev = construct_clk_domain(g, | 388 | pclkdomain_dev = construct_clk_domain(g, |
389 | (void *)&clk_domain_data); | 389 | (void *)&clk_domain_data); |
390 | if (pclkdomain_dev == NULL) { | 390 | if (pclkdomain_dev == NULL) { |
391 | gk20a_err(dev_from_gk20a(g), | 391 | nvgpu_err(g, |
392 | "unable to construct clock domain boardobj for %d", | 392 | "unable to construct clock domain boardobj for %d", |
393 | index); | 393 | index); |
394 | status = -EINVAL; | 394 | status = -EINVAL; |
@@ -397,7 +397,7 @@ static u32 devinit_get_clocks_table(struct gk20a *g, | |||
397 | status = boardobjgrp_objinsert(&pclkdomainobjs->super.super, | 397 | status = boardobjgrp_objinsert(&pclkdomainobjs->super.super, |
398 | (struct boardobj *)pclkdomain_dev, index); | 398 | (struct boardobj *)pclkdomain_dev, index); |
399 | if (status) { | 399 | if (status) { |
400 | gk20a_err(dev_from_gk20a(g), | 400 | nvgpu_err(g, |
401 | "unable to insert clock domain boardobj for %d", index); | 401 | "unable to insert clock domain boardobj for %d", index); |
402 | status = -EINVAL; | 402 | status = -EINVAL; |
403 | goto done; | 403 | goto done; |
@@ -1097,7 +1097,7 @@ u32 clk_domain_clk_prog_link(struct gk20a *g, struct clk_pmupstate *pclk) | |||
1097 | struct clk_domain *, pdomain, i) { | 1097 | struct clk_domain *, pdomain, i) { |
1098 | status = pdomain->clkdomainclkproglink(g, pclk, pdomain); | 1098 | status = pdomain->clkdomainclkproglink(g, pclk, pdomain); |
1099 | if (status) { | 1099 | if (status) { |
1100 | gk20a_err(dev_from_gk20a(g), | 1100 | nvgpu_err(g, |
1101 | "error flattening VF for CLK DOMAIN - 0x%x", | 1101 | "error flattening VF for CLK DOMAIN - 0x%x", |
1102 | pdomain->domain); | 1102 | pdomain->domain); |
1103 | goto done; | 1103 | goto done; |
diff --git a/drivers/gpu/nvgpu/clk/clk_fll.c b/drivers/gpu/nvgpu/clk/clk_fll.c index 7694e720..e097e593 100644 --- a/drivers/gpu/nvgpu/clk/clk_fll.c +++ b/drivers/gpu/nvgpu/clk/clk_fll.c | |||
@@ -45,7 +45,7 @@ static u32 _clk_fll_devgrp_pmudatainit_super(struct gk20a *g, | |||
45 | 45 | ||
46 | status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu); | 46 | status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu); |
47 | if (status) { | 47 | if (status) { |
48 | gk20a_err(dev_from_gk20a(g), "failed to init fll pmuobjgrp"); | 48 | nvgpu_err(g, "failed to init fll pmuobjgrp"); |
49 | return status; | 49 | return status; |
50 | } | 50 | } |
51 | pset->lut_num_entries = pfll_objs->lut_num_entries; | 51 | pset->lut_num_entries = pfll_objs->lut_num_entries; |
@@ -118,7 +118,7 @@ u32 clk_fll_sw_setup(struct gk20a *g) | |||
118 | 118 | ||
119 | status = boardobjgrpconstruct_e32(&g->clk_pmu.avfs_fllobjs.super); | 119 | status = boardobjgrpconstruct_e32(&g->clk_pmu.avfs_fllobjs.super); |
120 | if (status) { | 120 | if (status) { |
121 | gk20a_err(dev_from_gk20a(g), | 121 | nvgpu_err(g, |
122 | "error creating boardobjgrp for fll, status - 0x%x", status); | 122 | "error creating boardobjgrp for fll, status - 0x%x", status); |
123 | goto done; | 123 | goto done; |
124 | } | 124 | } |
@@ -130,7 +130,7 @@ u32 clk_fll_sw_setup(struct gk20a *g) | |||
130 | status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, | 130 | status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, |
131 | clk, CLK, clk_fll_device, CLK_FLL_DEVICE); | 131 | clk, CLK, clk_fll_device, CLK_FLL_DEVICE); |
132 | if (status) { | 132 | if (status) { |
133 | gk20a_err(dev_from_gk20a(g), | 133 | nvgpu_err(g, |
134 | "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", | 134 | "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", |
135 | status); | 135 | status); |
136 | goto done; | 136 | goto done; |
@@ -155,7 +155,7 @@ u32 clk_fll_sw_setup(struct gk20a *g) | |||
155 | &g->clk_pmu.avfs_fllobjs.super.super, | 155 | &g->clk_pmu.avfs_fllobjs.super.super, |
156 | clk, CLK, clk_fll_device, CLK_FLL_DEVICE); | 156 | clk, CLK, clk_fll_device, CLK_FLL_DEVICE); |
157 | if (status) { | 157 | if (status) { |
158 | gk20a_err(dev_from_gk20a(g), | 158 | nvgpu_err(g, |
159 | "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", | 159 | "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", |
160 | status); | 160 | status); |
161 | goto done; | 161 | goto done; |
@@ -179,7 +179,7 @@ u32 clk_fll_sw_setup(struct gk20a *g) | |||
179 | &pfllobjs->lut_prog_master_mask.super, | 179 | &pfllobjs->lut_prog_master_mask.super, |
180 | BOARDOBJ_GET_IDX(pfll)); | 180 | BOARDOBJ_GET_IDX(pfll)); |
181 | if (status) { | 181 | if (status) { |
182 | gk20a_err(dev_from_gk20a(g), "err setting lutprogmask"); | 182 | nvgpu_err(g, "err setting lutprogmask"); |
183 | goto done; | 183 | goto done; |
184 | } | 184 | } |
185 | pfll_master = pfll; | 185 | pfll_master = pfll; |
@@ -188,7 +188,7 @@ u32 clk_fll_sw_setup(struct gk20a *g) | |||
188 | g, pfllobjs, pfll_master, pfll); | 188 | g, pfllobjs, pfll_master, pfll); |
189 | 189 | ||
190 | if (status) { | 190 | if (status) { |
191 | gk20a_err(dev_from_gk20a(g), "err setting lutslavemask"); | 191 | nvgpu_err(g, "err setting lutslavemask"); |
192 | goto done; | 192 | goto done; |
193 | } | 193 | } |
194 | } | 194 | } |
diff --git a/drivers/gpu/nvgpu/clk/clk_freq_controller.c b/drivers/gpu/nvgpu/clk/clk_freq_controller.c index 4b47d978..61c8b81b 100644 --- a/drivers/gpu/nvgpu/clk/clk_freq_controller.c +++ b/drivers/gpu/nvgpu/clk/clk_freq_controller.c | |||
@@ -287,7 +287,7 @@ static u32 clk_get_freq_controller_table(struct gk20a *g, | |||
287 | (void *)&freq_controller_data); | 287 | (void *)&freq_controller_data); |
288 | 288 | ||
289 | if (pclk_freq_cntr == NULL) { | 289 | if (pclk_freq_cntr == NULL) { |
290 | gk20a_err(dev_from_gk20a(g), | 290 | nvgpu_err(g, |
291 | "unable to construct clock freq cntlr boardobj for %d", | 291 | "unable to construct clock freq cntlr boardobj for %d", |
292 | entry_idx); | 292 | entry_idx); |
293 | status = -EINVAL; | 293 | status = -EINVAL; |
@@ -298,7 +298,7 @@ static u32 clk_get_freq_controller_table(struct gk20a *g, | |||
298 | &pclk_freq_controllers->super.super, | 298 | &pclk_freq_controllers->super.super, |
299 | (struct boardobj *)pclk_freq_cntr, entry_idx); | 299 | (struct boardobj *)pclk_freq_cntr, entry_idx); |
300 | if (status) { | 300 | if (status) { |
301 | gk20a_err(dev_from_gk20a(g), | 301 | nvgpu_err(g, |
302 | "unable to insert clock freq cntlr boardobj for"); | 302 | "unable to insert clock freq cntlr boardobj for"); |
303 | status = -EINVAL; | 303 | status = -EINVAL; |
304 | goto done; | 304 | goto done; |
@@ -363,7 +363,7 @@ static u32 _clk_freq_controllers_pmudatainit(struct gk20a *g, | |||
363 | 363 | ||
364 | status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu); | 364 | status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu); |
365 | if (status) { | 365 | if (status) { |
366 | gk20a_err(dev_from_gk20a(g), | 366 | nvgpu_err(g, |
367 | "error updating pmu boardobjgrp for clk freq ctrs 0x%x", | 367 | "error updating pmu boardobjgrp for clk freq ctrs 0x%x", |
368 | status); | 368 | status); |
369 | goto done; | 369 | goto done; |
@@ -391,7 +391,7 @@ u32 clk_freq_controller_sw_setup(struct gk20a *g) | |||
391 | pclk_freq_controllers = &g->clk_pmu.clk_freq_controllers; | 391 | pclk_freq_controllers = &g->clk_pmu.clk_freq_controllers; |
392 | status = boardobjgrpconstruct_e32(&pclk_freq_controllers->super); | 392 | status = boardobjgrpconstruct_e32(&pclk_freq_controllers->super); |
393 | if (status) { | 393 | if (status) { |
394 | gk20a_err(dev_from_gk20a(g), | 394 | nvgpu_err(g, |
395 | "error creating boardobjgrp for clk FCT, status - 0x%x", | 395 | "error creating boardobjgrp for clk FCT, status - 0x%x", |
396 | status); | 396 | status); |
397 | goto done; | 397 | goto done; |
@@ -413,7 +413,7 @@ u32 clk_freq_controller_sw_setup(struct gk20a *g) | |||
413 | status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, | 413 | status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, |
414 | clk, CLK, clk_freq_controller, CLK_FREQ_CONTROLLER); | 414 | clk, CLK, clk_freq_controller, CLK_FREQ_CONTROLLER); |
415 | if (status) { | 415 | if (status) { |
416 | gk20a_err(dev_from_gk20a(g), | 416 | nvgpu_err(g, |
417 | "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", | 417 | "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", |
418 | status); | 418 | status); |
419 | goto done; | 419 | goto done; |
@@ -421,8 +421,7 @@ u32 clk_freq_controller_sw_setup(struct gk20a *g) | |||
421 | 421 | ||
422 | status = clk_get_freq_controller_table(g, pclk_freq_controllers); | 422 | status = clk_get_freq_controller_table(g, pclk_freq_controllers); |
423 | if (status) { | 423 | if (status) { |
424 | gk20a_err(dev_from_gk20a(g), | 424 | nvgpu_err(g, "error reading freq controller table - 0x%x", |
425 | "error reading freq controller table - 0x%x", | ||
426 | status); | 425 | status); |
427 | goto done; | 426 | goto done; |
428 | } | 427 | } |
diff --git a/drivers/gpu/nvgpu/clk/clk_mclk.c b/drivers/gpu/nvgpu/clk/clk_mclk.c index f973a696..690f8681 100644 --- a/drivers/gpu/nvgpu/clk/clk_mclk.c +++ b/drivers/gpu/nvgpu/clk/clk_mclk.c | |||
@@ -1979,7 +1979,7 @@ static void mclk_seq_pmucmdhandler(struct gk20a *g, struct pmu_msg *_msg, | |||
1979 | gk20a_dbg_info(""); | 1979 | gk20a_dbg_info(""); |
1980 | 1980 | ||
1981 | if (status != 0) { | 1981 | if (status != 0) { |
1982 | gk20a_err(dev_from_gk20a(g), "mclk seq_script cmd aborted"); | 1982 | nvgpu_err(g, "mclk seq_script cmd aborted"); |
1983 | msg_status = -ENOENT; | 1983 | msg_status = -ENOENT; |
1984 | goto status_update; | 1984 | goto status_update; |
1985 | } | 1985 | } |
@@ -2088,8 +2088,7 @@ static int mclk_get_memclk_table(struct gk20a *g) | |||
2088 | } | 2088 | } |
2089 | 2089 | ||
2090 | if (shadow_idx > fb_fbpa_fbio_delay_priv_max_v()) { | 2090 | if (shadow_idx > fb_fbpa_fbio_delay_priv_max_v()) { |
2091 | gk20a_err(dev_from_gk20a(g), | 2091 | nvgpu_err(g, "invalid shadow reg script index"); |
2092 | "invalid shadow reg script index"); | ||
2093 | status = -EINVAL; | 2092 | status = -EINVAL; |
2094 | goto done; | 2093 | goto done; |
2095 | } | 2094 | } |
@@ -2140,8 +2139,8 @@ static int mclk_get_memclk_table(struct gk20a *g) | |||
2140 | } | 2139 | } |
2141 | 2140 | ||
2142 | if (cmd_idx > fb_fbpa_fbio_cmd_delay_cmd_priv_max_v()) { | 2141 | if (cmd_idx > fb_fbpa_fbio_cmd_delay_cmd_priv_max_v()) { |
2143 | gk20a_err(dev_from_gk20a(g), | 2142 | nvgpu_err(g, |
2144 | "invalid shadow reg cmd script index"); | 2143 | "invalid shadow reg cmd script index"); |
2145 | status = -EINVAL; | 2144 | status = -EINVAL; |
2146 | goto done; | 2145 | goto done; |
2147 | } | 2146 | } |
@@ -2236,8 +2235,7 @@ int clk_mclkseq_init_mclk_gddr5(struct gk20a *g) | |||
2236 | 2235 | ||
2237 | mclk->vreg_buf = nvgpu_kcalloc(g, VREG_COUNT, sizeof(u32)); | 2236 | mclk->vreg_buf = nvgpu_kcalloc(g, VREG_COUNT, sizeof(u32)); |
2238 | if (!mclk->vreg_buf) { | 2237 | if (!mclk->vreg_buf) { |
2239 | gk20a_err(dev_from_gk20a(g), | 2238 | nvgpu_err(g, "unable to allocate memory for VREG"); |
2240 | "unable to allocate memory for VREG"); | ||
2241 | err = -ENOMEM; | 2239 | err = -ENOMEM; |
2242 | goto fail_data_mutex; | 2240 | goto fail_data_mutex; |
2243 | } | 2241 | } |
@@ -2318,8 +2316,7 @@ int clk_mclkseq_change_mclk_gddr5(struct gk20a *g, u16 val) | |||
2318 | } | 2316 | } |
2319 | break; | 2317 | break; |
2320 | default: | 2318 | default: |
2321 | gk20a_err(dev_from_gk20a(g), | 2319 | nvgpu_err(g, "Illegal MCLK clock change"); |
2322 | "Illegal MCLK clock change"); | ||
2323 | status = -EINVAL; | 2320 | status = -EINVAL; |
2324 | goto exit_status; | 2321 | goto exit_status; |
2325 | } | 2322 | } |
@@ -2368,8 +2365,7 @@ int clk_mclkseq_change_mclk_gddr5(struct gk20a *g, u16 val) | |||
2368 | mclk_seq_pmucmdhandler, | 2365 | mclk_seq_pmucmdhandler, |
2369 | &seq_completion_status, &seqdesc, ~0); | 2366 | &seq_completion_status, &seqdesc, ~0); |
2370 | if (status) { | 2367 | if (status) { |
2371 | gk20a_err(dev_from_gk20a(g), | 2368 | nvgpu_err(g, "unable to post seq script exec cmd for unit %x", |
2372 | "unable to post seq script exec cmd for unit %x ", | ||
2373 | cmd.hdr.unit_id); | 2369 | cmd.hdr.unit_id); |
2374 | goto exit_status; | 2370 | goto exit_status; |
2375 | } | 2371 | } |
@@ -2377,8 +2373,7 @@ int clk_mclkseq_change_mclk_gddr5(struct gk20a *g, u16 val) | |||
2377 | pmu_wait_message_cond(&g->pmu, (gk20a_get_gr_idle_timeout(g)), | 2373 | pmu_wait_message_cond(&g->pmu, (gk20a_get_gr_idle_timeout(g)), |
2378 | &seq_completion_status, 0); | 2374 | &seq_completion_status, 0); |
2379 | if (seq_completion_status != 0) { | 2375 | if (seq_completion_status != 0) { |
2380 | gk20a_err(dev_from_gk20a(g), | 2376 | nvgpu_err(g, "seq_script update failed"); |
2381 | "seq_script update failed"); | ||
2382 | status = -EBUSY; | 2377 | status = -EBUSY; |
2383 | goto exit_status; | 2378 | goto exit_status; |
2384 | } | 2379 | } |
diff --git a/drivers/gpu/nvgpu/clk/clk_prog.c b/drivers/gpu/nvgpu/clk/clk_prog.c index dc9c58a6..5697c255 100644 --- a/drivers/gpu/nvgpu/clk/clk_prog.c +++ b/drivers/gpu/nvgpu/clk/clk_prog.c | |||
@@ -46,8 +46,7 @@ static u32 _clk_progs_pmudatainit(struct gk20a *g, | |||
46 | 46 | ||
47 | status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu); | 47 | status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu); |
48 | if (status) { | 48 | if (status) { |
49 | gk20a_err(dev_from_gk20a(g), | 49 | nvgpu_err(g, "error updating pmu boardobjgrp for clk prog 0x%x", |
50 | "error updating pmu boardobjgrp for clk prog 0x%x", | ||
51 | status); | 50 | status); |
52 | goto done; | 51 | goto done; |
53 | } | 52 | } |
@@ -89,7 +88,7 @@ u32 clk_prog_sw_setup(struct gk20a *g) | |||
89 | 88 | ||
90 | status = boardobjgrpconstruct_e255(&g->clk_pmu.clk_progobjs.super); | 89 | status = boardobjgrpconstruct_e255(&g->clk_pmu.clk_progobjs.super); |
91 | if (status) { | 90 | if (status) { |
92 | gk20a_err(dev_from_gk20a(g), | 91 | nvgpu_err(g, |
93 | "error creating boardobjgrp for clk prog, status - 0x%x", | 92 | "error creating boardobjgrp for clk prog, status - 0x%x", |
94 | status); | 93 | status); |
95 | goto done; | 94 | goto done; |
@@ -103,7 +102,7 @@ u32 clk_prog_sw_setup(struct gk20a *g) | |||
103 | status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, | 102 | status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, |
104 | clk, CLK, clk_prog, CLK_PROG); | 103 | clk, CLK, clk_prog, CLK_PROG); |
105 | if (status) { | 104 | if (status) { |
106 | gk20a_err(dev_from_gk20a(g), | 105 | nvgpu_err(g, |
107 | "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", | 106 | "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", |
108 | status); | 107 | status); |
109 | goto done; | 108 | goto done; |
@@ -118,8 +117,7 @@ u32 clk_prog_sw_setup(struct gk20a *g) | |||
118 | 117 | ||
119 | status = clk_domain_clk_prog_link(g, &g->clk_pmu); | 118 | status = clk_domain_clk_prog_link(g, &g->clk_pmu); |
120 | if (status) { | 119 | if (status) { |
121 | gk20a_err(dev_from_gk20a(g), | 120 | nvgpu_err(g, "error constructing VF point board objects"); |
122 | "error constructing VF point board objects"); | ||
123 | goto done; | 121 | goto done; |
124 | } | 122 | } |
125 | 123 | ||
@@ -265,8 +263,7 @@ static u32 devinit_get_clk_prog_table(struct gk20a *g, | |||
265 | break; | 263 | break; |
266 | 264 | ||
267 | default: | 265 | default: |
268 | gk20a_err(dev_from_gk20a(g), | 266 | nvgpu_err(g, "invalid source %d", prog_type); |
269 | "invalid source %d", prog_type); | ||
270 | status = -EINVAL; | 267 | status = -EINVAL; |
271 | goto done; | 268 | goto done; |
272 | } | 269 | } |
@@ -346,16 +343,15 @@ static u32 devinit_get_clk_prog_table(struct gk20a *g, | |||
346 | 343 | ||
347 | 344 | ||
348 | default: | 345 | default: |
349 | gk20a_err(dev_from_gk20a(g), | 346 | nvgpu_err(g, "source issue %d", prog_type); |
350 | "source issue %d", prog_type); | ||
351 | status = -EINVAL; | 347 | status = -EINVAL; |
352 | goto done; | 348 | goto done; |
353 | } | 349 | } |
354 | 350 | ||
355 | pprog = construct_clk_prog(g, (void *)&prog_data); | 351 | pprog = construct_clk_prog(g, (void *)&prog_data); |
356 | if (pprog == NULL) { | 352 | if (pprog == NULL) { |
357 | gk20a_err(dev_from_gk20a(g), | 353 | nvgpu_err(g, |
358 | "error constructing clk_prog boardobj %d", i); | 354 | "error constructing clk_prog boardobj %d", i); |
359 | status = -EINVAL; | 355 | status = -EINVAL; |
360 | goto done; | 356 | goto done; |
361 | } | 357 | } |
@@ -363,8 +359,7 @@ static u32 devinit_get_clk_prog_table(struct gk20a *g, | |||
363 | status = boardobjgrp_objinsert(&pclkprogobjs->super.super, | 359 | status = boardobjgrp_objinsert(&pclkprogobjs->super.super, |
364 | (struct boardobj *)pprog, i); | 360 | (struct boardobj *)pprog, i); |
365 | if (status) { | 361 | if (status) { |
366 | gk20a_err(dev_from_gk20a(g), | 362 | nvgpu_err(g, "error adding clk_prog boardobj %d", i); |
367 | "error adding clk_prog boardobj %d", i); | ||
368 | status = -EINVAL; | 363 | status = -EINVAL; |
369 | goto done; | 364 | goto done; |
370 | } | 365 | } |
@@ -930,7 +925,7 @@ static u32 vflookup_prog_1x_master | |||
930 | for (j = pvfentry->vf_point_idx_first; | 925 | for (j = pvfentry->vf_point_idx_first; |
931 | j <= pvfentry->vf_point_idx_last; j++) { | 926 | j <= pvfentry->vf_point_idx_last; j++) { |
932 | pvfpoint = CLK_CLK_VF_POINT_GET(pclk, j); | 927 | pvfpoint = CLK_CLK_VF_POINT_GET(pclk, j); |
933 | gk20a_err(dev_from_gk20a(g), "v %x c %x", | 928 | nvgpu_err(g, "v %x c %x", |
934 | clkvfpointvoltageuvget(g, pvfpoint), | 929 | clkvfpointvoltageuvget(g, pvfpoint), |
935 | clkvfpointfreqmhzget(g, pvfpoint)); | 930 | clkvfpointfreqmhzget(g, pvfpoint)); |
936 | } | 931 | } |
diff --git a/drivers/gpu/nvgpu/clk/clk_vf_point.c b/drivers/gpu/nvgpu/clk/clk_vf_point.c index f4019f9d..3ec111f0 100644 --- a/drivers/gpu/nvgpu/clk/clk_vf_point.c +++ b/drivers/gpu/nvgpu/clk/clk_vf_point.c | |||
@@ -31,7 +31,7 @@ static u32 _clk_vf_points_pmudatainit(struct gk20a *g, | |||
31 | 31 | ||
32 | status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu); | 32 | status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu); |
33 | if (status) { | 33 | if (status) { |
34 | gk20a_err(dev_from_gk20a(g), | 34 | nvgpu_err(g, |
35 | "error updating pmu boardobjgrp for clk vfpoint 0x%x", | 35 | "error updating pmu boardobjgrp for clk vfpoint 0x%x", |
36 | status); | 36 | status); |
37 | goto done; | 37 | goto done; |
@@ -90,7 +90,7 @@ u32 clk_vf_point_sw_setup(struct gk20a *g) | |||
90 | 90 | ||
91 | status = boardobjgrpconstruct_e255(&g->clk_pmu.clk_vf_pointobjs.super); | 91 | status = boardobjgrpconstruct_e255(&g->clk_pmu.clk_vf_pointobjs.super); |
92 | if (status) { | 92 | if (status) { |
93 | gk20a_err(dev_from_gk20a(g), | 93 | nvgpu_err(g, |
94 | "error creating boardobjgrp for clk vfpoint, status - 0x%x", | 94 | "error creating boardobjgrp for clk vfpoint, status - 0x%x", |
95 | status); | 95 | status); |
96 | goto done; | 96 | goto done; |
@@ -104,7 +104,7 @@ u32 clk_vf_point_sw_setup(struct gk20a *g) | |||
104 | status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, | 104 | status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, |
105 | clk, CLK, clk_vf_point, CLK_VF_POINT); | 105 | clk, CLK, clk_vf_point, CLK_VF_POINT); |
106 | if (status) { | 106 | if (status) { |
107 | gk20a_err(dev_from_gk20a(g), | 107 | nvgpu_err(g, |
108 | "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", | 108 | "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", |
109 | status); | 109 | status); |
110 | goto done; | 110 | goto done; |
@@ -114,7 +114,7 @@ u32 clk_vf_point_sw_setup(struct gk20a *g) | |||
114 | &g->clk_pmu.clk_vf_pointobjs.super.super, | 114 | &g->clk_pmu.clk_vf_pointobjs.super.super, |
115 | clk, CLK, clk_vf_point, CLK_VF_POINT); | 115 | clk, CLK, clk_vf_point, CLK_VF_POINT); |
116 | if (status) { | 116 | if (status) { |
117 | gk20a_err(dev_from_gk20a(g), | 117 | nvgpu_err(g, |
118 | "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", | 118 | "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", |
119 | status); | 119 | status); |
120 | goto done; | 120 | goto done; |
@@ -356,7 +356,7 @@ static u32 clk_vf_point_update(struct gk20a *g, | |||
356 | ppmudata; | 356 | ppmudata; |
357 | 357 | ||
358 | if (pstatus->super.type != pclk_vf_point->super.type) { | 358 | if (pstatus->super.type != pclk_vf_point->super.type) { |
359 | gk20a_err(dev_from_gk20a(g), | 359 | nvgpu_err(g, |
360 | "pmu data and boardobj type not matching"); | 360 | "pmu data and boardobj type not matching"); |
361 | return -EINVAL; | 361 | return -EINVAL; |
362 | } | 362 | } |
@@ -386,7 +386,7 @@ u32 clk_vf_point_cache(struct gk20a *g) | |||
386 | 386 | ||
387 | status = pboardobjgrp->pmugetstatus(g, pboardobjgrp, pboardobjgrpmask); | 387 | status = pboardobjgrp->pmugetstatus(g, pboardobjgrp, pboardobjgrpmask); |
388 | if (status) { | 388 | if (status) { |
389 | gk20a_err(dev_from_gk20a(g), "err getting boardobjs from pmu"); | 389 | nvgpu_err(g, "err getting boardobjs from pmu"); |
390 | return status; | 390 | return status; |
391 | } | 391 | } |
392 | pboardobjgrppmu = pboardobjgrp->pmu.getstatus.buf; | 392 | pboardobjgrppmu = pboardobjgrp->pmu.getstatus.buf; |
@@ -396,16 +396,14 @@ u32 clk_vf_point_cache(struct gk20a *g) | |||
396 | (struct nv_pmu_boardobjgrp *)pboardobjgrppmu, | 396 | (struct nv_pmu_boardobjgrp *)pboardobjgrppmu, |
397 | &pboardobjpmustatus, index); | 397 | &pboardobjpmustatus, index); |
398 | if (status) { | 398 | if (status) { |
399 | gk20a_err(dev_from_gk20a(g), | 399 | nvgpu_err(g, "could not get status object instance"); |
400 | "could not get status object instance"); | ||
401 | return status; | 400 | return status; |
402 | } | 401 | } |
403 | 402 | ||
404 | status = clk_vf_point_update(g, pboardobj, | 403 | status = clk_vf_point_update(g, pboardobj, |
405 | (struct nv_pmu_boardobj *)pboardobjpmustatus); | 404 | (struct nv_pmu_boardobj *)pboardobjpmustatus); |
406 | if (status) { | 405 | if (status) { |
407 | gk20a_err(dev_from_gk20a(g), | 406 | nvgpu_err(g, "invalid data from pmu at %d", index); |
408 | "invalid data from pmu at %d", index); | ||
409 | return status; | 407 | return status; |
410 | } | 408 | } |
411 | } | 409 | } |
diff --git a/drivers/gpu/nvgpu/clk/clk_vin.c b/drivers/gpu/nvgpu/clk/clk_vin.c index af388671..0fceb89d 100644 --- a/drivers/gpu/nvgpu/clk/clk_vin.c +++ b/drivers/gpu/nvgpu/clk/clk_vin.c | |||
@@ -252,7 +252,7 @@ u32 clk_vin_sw_setup(struct gk20a *g) | |||
252 | 252 | ||
253 | status = boardobjgrpconstruct_e32(&g->clk_pmu.avfs_vinobjs.super); | 253 | status = boardobjgrpconstruct_e32(&g->clk_pmu.avfs_vinobjs.super); |
254 | if (status) { | 254 | if (status) { |
255 | gk20a_err(dev_from_gk20a(g), | 255 | nvgpu_err(g, |
256 | "error creating boardobjgrp for clk vin, statu - 0x%x", | 256 | "error creating boardobjgrp for clk vin, statu - 0x%x", |
257 | status); | 257 | status); |
258 | goto done; | 258 | goto done; |
@@ -266,7 +266,7 @@ u32 clk_vin_sw_setup(struct gk20a *g) | |||
266 | status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, | 266 | status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, |
267 | clk, CLK, clk_vin_device, CLK_VIN_DEVICE); | 267 | clk, CLK, clk_vin_device, CLK_VIN_DEVICE); |
268 | if (status) { | 268 | if (status) { |
269 | gk20a_err(dev_from_gk20a(g), | 269 | nvgpu_err(g, |
270 | "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", | 270 | "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", |
271 | status); | 271 | status); |
272 | goto done; | 272 | goto done; |
@@ -290,7 +290,7 @@ u32 clk_vin_sw_setup(struct gk20a *g) | |||
290 | status = read_vin_cal_slope_intercept_fuse(g, | 290 | status = read_vin_cal_slope_intercept_fuse(g, |
291 | pvindev->id, &slope, &intercept); | 291 | pvindev->id, &slope, &intercept); |
292 | if (status) { | 292 | if (status) { |
293 | gk20a_err(dev_from_gk20a(g), | 293 | nvgpu_err(g, |
294 | "err reading vin cal for id %x", pvindev->id); | 294 | "err reading vin cal for id %x", pvindev->id); |
295 | goto done; | 295 | goto done; |
296 | } | 296 | } |
@@ -304,7 +304,7 @@ u32 clk_vin_sw_setup(struct gk20a *g) | |||
304 | &g->clk_pmu.avfs_vinobjs.super.super, | 304 | &g->clk_pmu.avfs_vinobjs.super.super, |
305 | clk, CLK, clk_vin_device, CLK_VIN_DEVICE); | 305 | clk, CLK, clk_vin_device, CLK_VIN_DEVICE); |
306 | if (status) { | 306 | if (status) { |
307 | gk20a_err(dev_from_gk20a(g), | 307 | nvgpu_err(g, |
308 | "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", | 308 | "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", |
309 | status); | 309 | status); |
310 | goto done; | 310 | goto done; |