gpu: nvgpu: use force_reset_ch in ch wdt handler

- let force_reset_ch pass down err code
- force_reset_ch callback can cover vgpu too.

Bug 1776876
JIRA VFND-2151

Change-Id: I48f7890294c6455247198e0cab5f21f83f61f0e1
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1202255
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 files changed, 17 insertions, 59 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
index a8a39302..41fced99 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
@@ -1721,10 +1721,6 @@ static void gk20a_channel_timeout_handler(struct work_struct *work)
         struct channel_gk20a_job *job;
         struct gk20a *g;
         struct channel_gk20a *ch;
-        struct channel_gk20a *failing_ch;
-        u32 engine_id;
-        int id = -1;
-        bool is_tsg = false;
 
         ch = container_of(to_delayed_work(work), struct channel_gk20a,
                         timeout.wq);
@@ -1746,16 +1742,11 @@ static void gk20a_channel_timeout_handler(struct work_struct *work)
         ch->timeout.initialized = false;
         mutex_unlock(&ch->timeout.lock);
 
-        if (gr_gk20a_disable_ctxsw(g)) {
-                gk20a_err(dev_from_gk20a(g), "Unable to disable ctxsw!");
-                goto fail_unlock;
-        }
-
         if (gk20a_fence_is_expired(job->post_fence)) {
                 gk20a_err(dev_from_gk20a(g),
                           "Timed out fence is expired on c=%d!",
                           ch->hw_chid);
-                goto fail_enable_ctxsw;
+                goto fail_unlock;
         }
 
         gk20a_err(dev_from_gk20a(g), "Confirmed: job on channel %d timed out",
@@ -1764,43 +1755,9 @@ static void gk20a_channel_timeout_handler(struct work_struct *work)
         gk20a_debug_dump(g->dev);
         gk20a_gr_debug_dump(g->dev);
 
-        /* Get failing engine data */
-        engine_id = gk20a_fifo_get_failing_engine_data(g, &id, &is_tsg);
-
-        if (!gk20a_fifo_is_valid_engine_id(g, engine_id)) {
-                /* If no failing engine, abort the channels */
-                if (gk20a_is_channel_marked_as_tsg(ch)) {
-                        struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid];
-
-                        gk20a_fifo_set_ctx_mmu_error_tsg(g, tsg);
-                        gk20a_fifo_abort_tsg(g, ch->tsgid, false);
-                } else {
-                        gk20a_fifo_set_ctx_mmu_error_ch(g, ch);
-                        gk20a_channel_abort(ch, false);
-                }
-        } else {
-                /* If failing engine, trigger recovery */
-                failing_ch = gk20a_channel_get(&g->fifo.channel[id]);
-                if (!failing_ch)
-                        goto fail_enable_ctxsw;
-
-                if (failing_ch->hw_chid != ch->hw_chid) {
-                        gk20a_channel_timeout_start(ch, job);
-
-                        mutex_lock(&failing_ch->timeout.lock);
-                        failing_ch->timeout.initialized = false;
-                        mutex_unlock(&failing_ch->timeout.lock);
-                }
-
-                gk20a_fifo_recover(g, BIT(engine_id),
-                        failing_ch->hw_chid, is_tsg,
-                        true, failing_ch->timeout_debug_dump);
-
-                gk20a_channel_put(failing_ch);
-        }
+        g->ops.fifo.force_reset_ch(ch,
+                NVGPU_CHANNEL_FIFO_ERROR_IDLE_TIMEOUT, true);
 
-fail_enable_ctxsw:
-        gr_gk20a_enable_ctxsw(g);
 fail_unlock:
         mutex_unlock(&g->ch_wdt_lock);
         gk20a_channel_put(ch);
@@ -3231,7 +3188,8 @@ long gk20a_channel_ioctl(struct file *filp,
                                 __func__, cmd);
                         break;
                 }
-                err = ch->g->ops.fifo.force_reset_ch(ch, true);
+                err = ch->g->ops.fifo.force_reset_ch(ch,
+                                NVGPU_CHANNEL_RESETCHANNEL_VERIF_ERROR, true);
                 gk20a_idle(dev);
                 break;
         case NVGPU_IOCTL_CHANNEL_EVENT_ID_CTRL:
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index b025f4d6..bd31656f 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -1746,7 +1746,8 @@ void gk20a_fifo_recover(struct gk20a *g, u32 __engine_ids,
 }
 
 /* force reset channel and tsg (if it's part of one) */
-int gk20a_fifo_force_reset_ch(struct channel_gk20a *ch, bool verbose)
+int gk20a_fifo_force_reset_ch(struct channel_gk20a *ch,
+                                u32 err_code, bool verbose)
 {
         struct tsg_gk20a *tsg = NULL;
         struct channel_gk20a *ch_tsg = NULL;
@@ -1759,8 +1760,7 @@ int gk20a_fifo_force_reset_ch(struct channel_gk20a *ch, bool verbose)
 
                 list_for_each_entry(ch_tsg, &tsg->ch_list, ch_entry) {
                         if (gk20a_channel_get(ch_tsg)) {
-                                gk20a_set_error_notifier(ch_tsg,
-                                       NVGPU_CHANNEL_RESETCHANNEL_VERIF_ERROR);
+                                gk20a_set_error_notifier(ch_tsg, err_code);
                                 gk20a_channel_put(ch_tsg);
                         }
                 }
@@ -1768,8 +1768,7 @@ int gk20a_fifo_force_reset_ch(struct channel_gk20a *ch, bool verbose)
                 mutex_unlock(&tsg->ch_list_lock);
                 gk20a_fifo_recover_tsg(g, ch->tsgid, verbose);
         } else {
-                gk20a_set_error_notifier(ch,
-                        NVGPU_CHANNEL_RESETCHANNEL_VERIF_ERROR);
+                gk20a_set_error_notifier(ch, err_code);
                 gk20a_fifo_recover_ch(g, ch->hw_chid, verbose);
         }
 
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
index f5a73a12..17c6dbf6 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
@@ -197,7 +197,8 @@ void gk20a_fifo_recover(struct gk20a *g,
                         bool id_is_known, bool verbose);
 void gk20a_fifo_recover_ch(struct gk20a *g, u32 hw_chid, bool verbose);
 void gk20a_fifo_recover_tsg(struct gk20a *g, u32 tsgid, bool verbose);
-int gk20a_fifo_force_reset_ch(struct channel_gk20a *ch, bool verbose);
+int gk20a_fifo_force_reset_ch(struct channel_gk20a *ch,
+                                u32 err_code, bool verbose);
 void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id);
 int gk20a_init_fifo_reset_enable_hw(struct gk20a *g);
 void gk20a_init_fifo(struct gpu_ops *gops);
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 6f735af9..463317e3 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -363,7 +363,8 @@ struct gpu_ops {
                 int (*channel_set_timeslice)(struct channel_gk20a *ch,
                                         u32 timeslice);
                 int (*tsg_set_timeslice)(struct tsg_gk20a *tsg, u32 timeslice);
-                int (*force_reset_ch)(struct channel_gk20a *ch, bool verbose);
+                int (*force_reset_ch)(struct channel_gk20a *ch,
+                                        u32 err_code, bool verbose);
                 int (*engine_enum_from_type)(struct gk20a *g, u32 engine_type,
                                         u32 *inst_id);
                 void (*device_info_data_parse)(struct gk20a *g,
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
index 9a8c319b..90e44e8c 100644
--- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
@@ -634,7 +634,8 @@ static int vgpu_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice)
         return err ? err : msg.ret;
 }
 
-static int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch, bool verbose)
+static int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch,
+                                        u32 err_code, bool verbose)
 {
         struct tsg_gk20a *tsg = NULL;
         struct channel_gk20a *ch_tsg = NULL;
@@ -653,16 +654,14 @@ static int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch, bool verbose)
 
                 list_for_each_entry(ch_tsg, &tsg->ch_list, ch_entry) {
                         if (gk20a_channel_get(ch_tsg)) {
-                                gk20a_set_error_notifier(ch_tsg,
-                                       NVGPU_CHANNEL_RESETCHANNEL_VERIF_ERROR);
+                                gk20a_set_error_notifier(ch_tsg, err_code);
                                 gk20a_channel_put(ch_tsg);
                         }
                 }
 
                 mutex_unlock(&tsg->ch_list_lock);
         } else {
-                gk20a_set_error_notifier(ch,
-                        NVGPU_CHANNEL_RESETCHANNEL_VERIF_ERROR);
+                gk20a_set_error_notifier(ch, err_code);
         }
 
         msg.cmd = TEGRA_VGPU_CMD_CHANNEL_FORCE_RESET;