gpu: nvgpu: support for dumping vpr/wpr info

Added support for dumping vpr/wpr info for gm20b.
This dump info called when ever gk20a_mm_fb_flush
is timed-out.

Bug 200082817

Change-Id: I21b0372d0e3f976a189c9c428c015165b715bf88
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/711439
(cherry picked from commit b69897d71c8f6119b49ceb8d3273cdb354178cc5)
Reviewed-on: http://git-master/r/712675
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

4 files changed, 95 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 441ea7cc..4fac3cc5 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -176,6 +176,7 @@ struct gpu_ops {
                 void (*init_kind_attr)(struct gk20a *g);
                 void (*set_mmu_page_size)(struct gk20a *g);
                 int (*compression_page_size)(struct gk20a *g);
+                void (*dump_vpr_wpr_info)(struct gk20a *g);
         } fb;
         struct {
                 void (*slcg_bus_load_gating_prod)(struct gk20a *g, bool prod);
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
index 67680c4c..b53d53a3 100644
--- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
@@ -2805,6 +2805,8 @@ int gk20a_mm_fb_flush(struct gk20a *g)
         if (tegra_platform_is_silicon() && retry < 0) {
                 gk20a_warn(dev_from_gk20a(g),
                         "fb_flush too many retries");
+                if (g->ops.fb.dump_vpr_wpr_info)
+                        g->ops.fb.dump_vpr_wpr_info(g);
                 ret = -EBUSY;
         }
 
diff --git a/drivers/gpu/nvgpu/gm20b/fb_gm20b.c b/drivers/gpu/nvgpu/gm20b/fb_gm20b.c
index deef7896..666d27e9 100644
--- a/drivers/gpu/nvgpu/gm20b/fb_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/fb_gm20b.c
@@ -1,7 +1,7 @@
 /*
  * GM20B GPC MMU
  *
- * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
 *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -95,11 +95,41 @@ static int gm20b_fb_compression_page_size(struct gk20a *g)
         return SZ_128K;
 }
 
+static void gm20b_fb_dump_vpr_wpr_info(struct gk20a *g)
+{
+        u32 val;
+
+        /* print vpr and wpr info */
+        val = gk20a_readl(g, fb_mmu_vpr_info_r());
+        val &= ~0x3;
+        val |= fb_mmu_vpr_info_index_addr_lo_v();
+        gk20a_writel(g, fb_mmu_vpr_info_r(), val);
+        gk20a_err(dev_from_gk20a(g), "VPR: %08x %08x %08x %08x",
+                gk20a_readl(g, fb_mmu_vpr_info_r()),
+                gk20a_readl(g, fb_mmu_vpr_info_r()),
+                gk20a_readl(g, fb_mmu_vpr_info_r()),
+                gk20a_readl(g, fb_mmu_vpr_info_r()));
+
+        val = gk20a_readl(g, fb_mmu_wpr_info_r());
+        val &= ~0xf;
+        val |= (fb_mmu_wpr_info_index_allow_read_v());
+        gk20a_writel(g, fb_mmu_wpr_info_r(), val);
+        gk20a_err(dev_from_gk20a(g), "WPR: %08x %08x %08x %08x %08x %08x",
+                gk20a_readl(g, fb_mmu_wpr_info_r()),
+                gk20a_readl(g, fb_mmu_wpr_info_r()),
+                gk20a_readl(g, fb_mmu_wpr_info_r()),
+                gk20a_readl(g, fb_mmu_wpr_info_r()),
+                gk20a_readl(g, fb_mmu_wpr_info_r()),
+                gk20a_readl(g, fb_mmu_wpr_info_r()));
+
+}
+
 void gm20b_init_fb(struct gpu_ops *gops)
 {
         gops->fb.init_fs_state = fb_gm20b_init_fs_state;
         gops->fb.set_mmu_page_size = gm20b_fb_set_mmu_page_size;
         gops->fb.compression_page_size = gm20b_fb_compression_page_size;
+        gops->fb.dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info;
         gm20b_init_uncompressed_kind_map();
         gm20b_init_kind_attr();
 }
diff --git a/drivers/gpu/nvgpu/gm20b/hw_fb_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_fb_gm20b.h
index 91b998ca..a753074e 100644
--- a/drivers/gpu/nvgpu/gm20b/hw_fb_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/hw_fb_gm20b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -222,6 +222,34 @@ static inline u32 fb_mmu_vpr_info_r(void)
 {
         return 0x00100cd0;
 }
+static inline u32 fb_mmu_vpr_info_index_f(u32 v)
+{
+        return (v & 0x3) << 0;
+}
+static inline u32 fb_mmu_vpr_info_index_v(u32 r)
+{
+        return (r >> 0) & 0x3;
+}
+static inline u32 fb_mmu_vpr_info_index_addr_lo_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 fb_mmu_vpr_info_index_addr_hi_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 fb_mmu_vpr_info_index_cya_lo_v(void)
+{
+        return 0x00000002;
+}
+static inline u32 fb_mmu_vpr_info_index_cya_hi_v(void)
+{
+        return 0x00000003;
+}
+static inline u32 fb_mmu_vpr_info_fetch_f(u32 v)
+{
+        return (v & 0x1) << 2;
+}
 static inline u32 fb_mmu_vpr_info_fetch_v(u32 r)
 {
         return (r >> 2) & 0x1;
@@ -234,4 +262,36 @@ static inline u32 fb_mmu_vpr_info_fetch_true_v(void)
 {
         return 0x00000001;
 }
+static inline u32 fb_mmu_wpr_info_r(void)
+{
+        return 0x00100cd4;
+}
+static inline u32 fb_mmu_wpr_info_index_f(u32 v)
+{
+        return (v & 0xf) << 0;
+}
+static inline u32 fb_mmu_wpr_info_index_allow_read_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 fb_mmu_wpr_info_index_allow_write_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 fb_mmu_wpr_info_index_wpr1_addr_lo_v(void)
+{
+        return 0x00000002;
+}
+static inline u32 fb_mmu_wpr_info_index_wpr1_addr_hi_v(void)
+{
+        return 0x00000003;
+}
+static inline u32 fb_mmu_wpr_info_index_wpr2_addr_lo_v(void)
+{
+        return 0x00000004;
+}
+static inline u32 fb_mmu_wpr_info_index_wpr2_addr_hi_v(void)
+{
+        return 0x00000005;
+}
 #endif