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authorThomas Fleury <tfleury@nvidia.com>2018-01-26 20:56:55 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2018-02-26 00:48:28 -0500
commit180604fec0bde1710923e78a3877d49892cbf883 (patch)
treec5d5942600d9310da86fc12df12a75dda314e153
parent0601fd25a5e01d0da638efef13c58b64f198bafb (diff)
gpu: nvgpu: gv100: fb hal to init and enable nvlink
Add the following hals: (1) init_nvlink to configure nvlink(s) for sysmem in HSHUB (2) enable_nvlink to switch from PCIe sysmem to nvlink sysmem, and setup atomics. Change-Id: I73d2370aaf8e0530158a1091d9efef4a8cf2aac5 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1648044 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h2
-rw-r--r--drivers/gpu/nvgpu/gv100/fb_gv100.c52
-rw-r--r--drivers/gpu/nvgpu/gv100/fb_gv100.h2
-rw-r--r--drivers/gpu/nvgpu/gv100/hal_gv100.c2
-rw-r--r--drivers/gpu/nvgpu/gv100/nvlink_gv100.c14
5 files changed, 71 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 40656edd..ac3364b0 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -481,6 +481,8 @@ struct gpu_ops {
481 void (*tlb_invalidate)(struct gk20a *g, struct nvgpu_mem *pdb); 481 void (*tlb_invalidate)(struct gk20a *g, struct nvgpu_mem *pdb);
482 void (*hub_isr)(struct gk20a *g); 482 void (*hub_isr)(struct gk20a *g);
483 int (*mem_unlock)(struct gk20a *g); 483 int (*mem_unlock)(struct gk20a *g);
484 int (*init_nvlink)(struct gk20a *g);
485 int (*enable_nvlink)(struct gk20a *g);
484 } fb; 486 } fb;
485 struct { 487 struct {
486 void (*slcg_bus_load_gating_prod)(struct gk20a *g, bool prod); 488 void (*slcg_bus_load_gating_prod)(struct gk20a *g, bool prod);
diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.c b/drivers/gpu/nvgpu/gv100/fb_gv100.c
index 0a2939bf..84a8d64a 100644
--- a/drivers/gpu/nvgpu/gv100/fb_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/fb_gv100.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GV100 FB 2 * GV100 FB
3 * 3 *
4 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -182,3 +182,53 @@ exit:
182 182
183 return err; 183 return err;
184} 184}
185
186int gv100_fb_init_nvlink(struct gk20a *g)
187{
188 u32 data;
189 u32 mask = g->nvlink.enabled_links;
190
191 /* Map enabled link to SYSMEM */
192 data = nvgpu_readl(g, fb_hshub_config0_r());
193 data = set_field(data, fb_hshub_config0_sysmem_nvlink_mask_m(),
194 fb_hshub_config0_sysmem_nvlink_mask_f(mask));
195 nvgpu_writel(g, fb_hshub_config0_r(), data);
196
197 return 0;
198}
199
200int gv100_fb_enable_nvlink(struct gk20a *g)
201{
202 u32 data;
203
204 nvgpu_log(g, gpu_dbg_nvlink|gpu_dbg_info, "enabling nvlink");
205
206 /* Enable nvlink for NISO FBHUB */
207 data = nvgpu_readl(g, fb_niso_cfg1_r());
208 data = set_field(data, fb_niso_cfg1_sysmem_nvlink_m(),
209 fb_niso_cfg1_sysmem_nvlink_enabled_f());
210 nvgpu_writel(g, fb_niso_cfg1_r(), data);
211
212 /* Setup atomics */
213 data = nvgpu_readl(g, fb_mmu_ctrl_r());
214 data = set_field(data, fb_mmu_ctrl_atomic_capability_mode_m(),
215 fb_mmu_ctrl_atomic_capability_mode_rmw_f());
216 nvgpu_writel(g, fb_mmu_ctrl_r(), data);
217
218 data = nvgpu_readl(g, fb_hsmmu_pri_mmu_ctrl_r());
219 data = set_field(data, fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_m(),
220 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_rmw_f());
221 nvgpu_writel(g, fb_hsmmu_pri_mmu_ctrl_r(), data);
222
223 data = nvgpu_readl(g, fb_fbhub_num_active_ltcs_r());
224 data = set_field(data, fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_m(),
225 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f());
226 nvgpu_writel(g, fb_fbhub_num_active_ltcs_r(), data);
227
228 data = nvgpu_readl(g, fb_hshub_num_active_ltcs_r());
229 data = set_field(data, fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m(),
230 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f());
231 nvgpu_writel(g, fb_hshub_num_active_ltcs_r(), data);
232
233 return 0;
234}
diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.h b/drivers/gpu/nvgpu/gv100/fb_gv100.h
index b6db262a..5b99fe5e 100644
--- a/drivers/gpu/nvgpu/gv100/fb_gv100.h
+++ b/drivers/gpu/nvgpu/gv100/fb_gv100.h
@@ -29,4 +29,6 @@ struct gk20a;
29 29
30void gv100_fb_reset(struct gk20a *g); 30void gv100_fb_reset(struct gk20a *g);
31int gv100_fb_memory_unlock(struct gk20a *g); 31int gv100_fb_memory_unlock(struct gk20a *g);
32int gv100_fb_init_nvlink(struct gk20a *g);
33int gv100_fb_enable_nvlink(struct gk20a *g);
32#endif 34#endif
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index 53d61bfb..c380df8d 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -445,6 +445,8 @@ static const struct gpu_ops gv100_ops = {
445 .tlb_invalidate = gk20a_fb_tlb_invalidate, 445 .tlb_invalidate = gk20a_fb_tlb_invalidate,
446 .hub_isr = gv11b_fb_hub_isr, 446 .hub_isr = gv11b_fb_hub_isr,
447 .mem_unlock = gv100_fb_memory_unlock, 447 .mem_unlock = gv100_fb_memory_unlock,
448 .init_nvlink = gv100_fb_init_nvlink,
449 .enable_nvlink = gv100_fb_enable_nvlink,
448 }, 450 },
449 .fifo = { 451 .fifo = {
450 .get_preempt_timeout = gv100_fifo_get_preempt_timeout, 452 .get_preempt_timeout = gv100_fifo_get_preempt_timeout,
diff --git a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c
index e5e65c51..ba649382 100644
--- a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c
@@ -1638,6 +1638,13 @@ int gv100_nvlink_init(struct gk20a *g)
1638 1638
1639 /* Set HSHUB and SG_PHY */ 1639 /* Set HSHUB and SG_PHY */
1640 __nvgpu_set_enabled(g, NVGPU_MM_USE_PHYSICAL_SG, true); 1640 __nvgpu_set_enabled(g, NVGPU_MM_USE_PHYSICAL_SG, true);
1641
1642 err = g->ops.fb.enable_nvlink(g);
1643 if (err) {
1644 nvgpu_err(g, "failed switch to nvlink sysmem");
1645 return err;
1646 }
1647
1641 return err; 1648 return err;
1642} 1649}
1643 1650
@@ -2142,12 +2149,19 @@ int gv100_nvlink_interface_init(struct gk20a *g)
2142{ 2149{
2143 unsigned long mask = g->nvlink.enabled_links; 2150 unsigned long mask = g->nvlink.enabled_links;
2144 u32 link_id; 2151 u32 link_id;
2152 int err;
2145 2153
2146 for_each_set_bit(link_id, &mask, 32) { 2154 for_each_set_bit(link_id, &mask, 32) {
2147 gv100_nvlink_initialize_mif(g, link_id); 2155 gv100_nvlink_initialize_mif(g, link_id);
2148 gv100_nvlink_mif_intr_enable(g, link_id, true); 2156 gv100_nvlink_mif_intr_enable(g, link_id, true);
2149 } 2157 }
2150 2158
2159 err = g->ops.fb.init_nvlink(g);
2160 if (err) {
2161 nvgpu_err(g, "failed to setup nvlinks for sysmem");
2162 return err;
2163 }
2164
2151 return 0; 2165 return 0;
2152} 2166}
2153 2167