diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2014-09-19 06:39:36 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:11:21 -0400 |
commit | 17aeb7e87ecfc103d90c93902414e59509a51497 (patch) | |
tree | faab6b9f5d9a2aee79825768fcec31731097a81a | |
parent | bc10e7e47af667c1afa7499e01070a595b006ef6 (diff) |
gpu: nvgpu: Fix calculation of MMU debug address
Fix calculation of the debug buffer address.
Bug 1551221
Change-Id: I8d7921070549a1689dba0675d83bfdbf76ba5193
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/500705
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Riku Salminen <rsalminen@nvidia.com>
Tested-by: Riku Salminen <rsalminen@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 21 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hw_fb_gk20a.h | 8 |
2 files changed, 11 insertions, 18 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 0c71ece3..90838c64 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -4239,7 +4239,6 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g) | |||
4239 | struct aiv_list_gk20a *sw_ctx_load = &g->gr.ctx_vars.sw_ctx_load; | 4239 | struct aiv_list_gk20a *sw_ctx_load = &g->gr.ctx_vars.sw_ctx_load; |
4240 | struct av_list_gk20a *sw_method_init = &g->gr.ctx_vars.sw_method_init; | 4240 | struct av_list_gk20a *sw_method_init = &g->gr.ctx_vars.sw_method_init; |
4241 | u32 data; | 4241 | u32 data; |
4242 | u32 addr_lo, addr_hi; | ||
4243 | u64 addr; | 4242 | u64 addr; |
4244 | unsigned long end_jiffies = jiffies + | 4243 | unsigned long end_jiffies = jiffies + |
4245 | msecs_to_jiffies(gk20a_get_gr_idle_timeout(g)); | 4244 | msecs_to_jiffies(gk20a_get_gr_idle_timeout(g)); |
@@ -4249,31 +4248,25 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g) | |||
4249 | 4248 | ||
4250 | gk20a_dbg_fn(""); | 4249 | gk20a_dbg_fn(""); |
4251 | 4250 | ||
4252 | if (g->ops.gr.init_gpc_mmu) | ||
4253 | g->ops.gr.init_gpc_mmu(g); | ||
4254 | |||
4255 | /* init mmu debug buffer */ | 4251 | /* init mmu debug buffer */ |
4256 | addr = NV_MC_SMMU_VADDR_TRANSLATE(gr->mmu_wr_mem.iova); | 4252 | addr = NV_MC_SMMU_VADDR_TRANSLATE(gr->mmu_wr_mem.iova); |
4257 | addr_lo = u64_lo32(addr); | 4253 | addr >>= fb_mmu_debug_wr_addr_alignment_v(); |
4258 | addr_hi = u64_hi32(addr); | ||
4259 | addr = (addr_lo >> fb_mmu_debug_wr_addr_alignment_v()) | | ||
4260 | (addr_hi << (32 - fb_mmu_debug_wr_addr_alignment_v())); | ||
4261 | 4254 | ||
4262 | gk20a_writel(g, fb_mmu_debug_wr_r(), | 4255 | gk20a_writel(g, fb_mmu_debug_wr_r(), |
4263 | fb_mmu_debug_wr_aperture_vid_mem_f() | | 4256 | fb_mmu_debug_wr_aperture_vid_mem_f() | |
4264 | fb_mmu_debug_wr_vol_false_f() | | 4257 | fb_mmu_debug_wr_vol_false_f() | |
4265 | fb_mmu_debug_wr_addr_v(addr)); | 4258 | fb_mmu_debug_wr_addr_f(addr)); |
4266 | 4259 | ||
4267 | addr = NV_MC_SMMU_VADDR_TRANSLATE(gr->mmu_rd_mem.iova); | 4260 | addr = NV_MC_SMMU_VADDR_TRANSLATE(gr->mmu_rd_mem.iova); |
4268 | addr_lo = u64_lo32(addr); | 4261 | addr >>= fb_mmu_debug_rd_addr_alignment_v(); |
4269 | addr_hi = u64_hi32(addr); | ||
4270 | addr = (addr_lo >> fb_mmu_debug_rd_addr_alignment_v()) | | ||
4271 | (addr_hi << (32 - fb_mmu_debug_rd_addr_alignment_v())); | ||
4272 | 4262 | ||
4273 | gk20a_writel(g, fb_mmu_debug_rd_r(), | 4263 | gk20a_writel(g, fb_mmu_debug_rd_r(), |
4274 | fb_mmu_debug_rd_aperture_vid_mem_f() | | 4264 | fb_mmu_debug_rd_aperture_vid_mem_f() | |
4275 | fb_mmu_debug_rd_vol_false_f() | | 4265 | fb_mmu_debug_rd_vol_false_f() | |
4276 | fb_mmu_debug_rd_addr_v(addr)); | 4266 | fb_mmu_debug_rd_addr_f(addr)); |
4267 | |||
4268 | if (g->ops.gr.init_gpc_mmu) | ||
4269 | g->ops.gr.init_gpc_mmu(g); | ||
4277 | 4270 | ||
4278 | /* load gr floorsweeping registers */ | 4271 | /* load gr floorsweeping registers */ |
4279 | data = gk20a_readl(g, gr_gpc0_ppc0_pes_vsc_strem_r()); | 4272 | data = gk20a_readl(g, gr_gpc0_ppc0_pes_vsc_strem_r()); |
diff --git a/drivers/gpu/nvgpu/gk20a/hw_fb_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_fb_gk20a.h index b7edc29d..1c50d0d5 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_fb_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_fb_gk20a.h | |||
@@ -154,9 +154,9 @@ static inline u32 fb_mmu_debug_wr_vol_true_f(void) | |||
154 | { | 154 | { |
155 | return 0x4; | 155 | return 0x4; |
156 | } | 156 | } |
157 | static inline u32 fb_mmu_debug_wr_addr_v(u32 r) | 157 | static inline u32 fb_mmu_debug_wr_addr_f(u32 v) |
158 | { | 158 | { |
159 | return (r >> 4) & 0xfffffff; | 159 | return (v & 0xfffffff) << 4; |
160 | } | 160 | } |
161 | static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) | 161 | static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) |
162 | { | 162 | { |
@@ -174,9 +174,9 @@ static inline u32 fb_mmu_debug_rd_vol_false_f(void) | |||
174 | { | 174 | { |
175 | return 0x0; | 175 | return 0x0; |
176 | } | 176 | } |
177 | static inline u32 fb_mmu_debug_rd_addr_v(u32 r) | 177 | static inline u32 fb_mmu_debug_rd_addr_f(u32 v) |
178 | { | 178 | { |
179 | return (r >> 4) & 0xfffffff; | 179 | return (v & 0xfffffff) << 4; |
180 | } | 180 | } |
181 | static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) | 181 | static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) |
182 | { | 182 | { |