summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorThomas Fleury <tfleury@nvidia.com>2017-03-22 10:28:09 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-03-27 07:45:30 -0400
commit0f2eb5430d19cc49661d69571dde042650766691 (patch)
tree76263ebafdf1b375e2c1bcc6a62667d55fdd8e25
parent4f5996e23d7ea3d576c33f9b0ec5c7b590d6adca (diff)
gpu: nvgpu: add INA3221 I2C info in platform data
Add I2C device index and address for INA3221 in platform data. Jira EVLR-1048 Change-Id: I3791f24bd6d8ab99483ea0103313b2b671dfb445 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1327047 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r--drivers/gpu/nvgpu/gk20a/platform_gk20a.h4
-rw-r--r--drivers/gpu/nvgpu/pci.c8
-rw-r--r--drivers/gpu/nvgpu/pmgr/pmgrpmu.c14
3 files changed, 20 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/platform_gk20a.h b/drivers/gpu/nvgpu/gk20a/platform_gk20a.h
index 2d8c2bd7..4bdbda43 100644
--- a/drivers/gpu/nvgpu/gk20a/platform_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/platform_gk20a.h
@@ -252,6 +252,10 @@ struct gk20a_platform {
252 * power limits 252 * power limits
253 */ 253 */
254 bool hardcode_sw_threshold; 254 bool hardcode_sw_threshold;
255
256 /* i2c device index and address for INA3221 */
257 u32 ina3221_dcb_index;
258 u32 ina3221_i2c_address;
255}; 259};
256 260
257static inline struct gk20a_platform *gk20a_get_platform( 261static inline struct gk20a_platform *gk20a_get_platform(
diff --git a/drivers/gpu/nvgpu/pci.c b/drivers/gpu/nvgpu/pci.c
index a7899f7e..93c0a5cc 100644
--- a/drivers/gpu/nvgpu/pci.c
+++ b/drivers/gpu/nvgpu/pci.c
@@ -86,6 +86,8 @@ static struct gk20a_platform nvgpu_pci_device[] = {
86 .vidmem_is_vidmem = true, 86 .vidmem_is_vidmem = true,
87 .vbios_min_version = 0x86063000, 87 .vbios_min_version = 0x86063000,
88 .hardcode_sw_threshold = true, 88 .hardcode_sw_threshold = true,
89 .ina3221_dcb_index = 0,
90 .ina3221_i2c_address = 0x84,
89 }, 91 },
90 { /* DEVICE=0x1c36 */ 92 { /* DEVICE=0x1c36 */
91 /* ptimer src frequency in hz */ 93 /* ptimer src frequency in hz */
@@ -118,6 +120,8 @@ static struct gk20a_platform nvgpu_pci_device[] = {
118 .vidmem_is_vidmem = true, 120 .vidmem_is_vidmem = true,
119 .vbios_min_version = 0x86062d00, 121 .vbios_min_version = 0x86062d00,
120 .hardcode_sw_threshold = true, 122 .hardcode_sw_threshold = true,
123 .ina3221_dcb_index = 0,
124 .ina3221_i2c_address = 0x84,
121 }, 125 },
122 { /* DEVICE=0x1c37 */ 126 { /* DEVICE=0x1c37 */
123 /* ptimer src frequency in hz */ 127 /* ptimer src frequency in hz */
@@ -150,6 +154,8 @@ static struct gk20a_platform nvgpu_pci_device[] = {
150 .vidmem_is_vidmem = true, 154 .vidmem_is_vidmem = true,
151 .vbios_min_version = 0x86063000, 155 .vbios_min_version = 0x86063000,
152 .hardcode_sw_threshold = true, 156 .hardcode_sw_threshold = true,
157 .ina3221_dcb_index = 0,
158 .ina3221_i2c_address = 0x84,
153 }, 159 },
154 { /* DEVICE=0x1c75 */ 160 { /* DEVICE=0x1c75 */
155 /* ptimer src frequency in hz */ 161 /* ptimer src frequency in hz */
@@ -182,6 +188,8 @@ static struct gk20a_platform nvgpu_pci_device[] = {
182 .vidmem_is_vidmem = true, 188 .vidmem_is_vidmem = true,
183 .vbios_min_version = 0x86064700, 189 .vbios_min_version = 0x86064700,
184 .hardcode_sw_threshold = false, 190 .hardcode_sw_threshold = false,
191 .ina3221_dcb_index = 1,
192 .ina3221_i2c_address = 0x80,
185 } 193 }
186}; 194};
187 195
diff --git a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c
index 9873bd17..9201de2b 100644
--- a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c
+++ b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c
@@ -138,18 +138,20 @@ exit:
138static u32 pmgr_send_i2c_device_topology_to_pmu(struct gk20a *g) 138static u32 pmgr_send_i2c_device_topology_to_pmu(struct gk20a *g)
139{ 139{
140 struct nv_pmu_pmgr_i2c_device_desc_table i2c_desc_table; 140 struct nv_pmu_pmgr_i2c_device_desc_table i2c_desc_table;
141 struct gk20a_platform *platform = gk20a_get_platform(g->dev);
142 u32 idx = platform->ina3221_dcb_index;
141 u32 status = 0; 143 u32 status = 0;
142 144
143 /* INA3221 I2C device info */ 145 /* INA3221 I2C device info */
144 i2c_desc_table.dev_mask = 0x01; 146 i2c_desc_table.dev_mask = (1UL << idx);
145 147
146 /* INA3221 */ 148 /* INA3221 */
147 i2c_desc_table.devices[0].super.type = 0x4E; 149 i2c_desc_table.devices[idx].super.type = 0x4E;
148 150
149 i2c_desc_table.devices[0].dcb_index = 0; 151 i2c_desc_table.devices[idx].dcb_index = idx;
150 i2c_desc_table.devices[0].i2c_address = 0x84; 152 i2c_desc_table.devices[idx].i2c_address = platform->ina3221_i2c_address;
151 i2c_desc_table.devices[0].i2c_flags = 0xC2F; 153 i2c_desc_table.devices[idx].i2c_flags = 0xC2F;
152 i2c_desc_table.devices[0].i2c_port = 0x2; 154 i2c_desc_table.devices[idx].i2c_port = 0x2;
153 155
154 /* Pass the table down the PMU as an object */ 156 /* Pass the table down the PMU as an object */
155 status = pmgr_pmu_set_object( 157 status = pmgr_pmu_set_object(