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authorAlex Waterman <alexw@nvidia.com>2018-01-18 17:05:07 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2018-01-24 17:41:28 -0500
commit0f291f0d5854b35e802fc0cd102fe2d669103edd (patch)
treefb795cabf3ab77f3bc993eacfec9310927131d71
parent6a5bd72856ce8cef4a29d1c26c47432195b93826 (diff)
gpu: nvgpu: Remove fault_buf_status array
Now that we have a consistent way to check if a mem allocation is valid this array is not necessary. The code can simply check the validity of the nvgpu_mem. Change-Id: I6aaf563ddc314cf86a2c2b98f7eb75fa7a9a1ad9 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1641637 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r--drivers/gpu/nvgpu/gv11b/mm_gv11b.c33
-rw-r--r--drivers/gpu/nvgpu/gv11b/mm_gv11b.h5
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/mm.h1
3 files changed, 8 insertions, 31 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c
index bb3e5694..439bf9ed 100644
--- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c
@@ -126,8 +126,6 @@ static void gv11b_mm_mmu_hw_fault_buf_init(struct gk20a *g,
126 return; 126 return;
127 } 127 }
128 128
129 g->mm.hw_fault_buf_status[NONREPLAY_REG_INDEX] =
130 HW_FAULT_BUF_STATUS_ALLOC_TRUE;
131 *hub_intr_types |= HUB_INTR_TYPE_NONREPLAY; 129 *hub_intr_types |= HUB_INTR_TYPE_NONREPLAY;
132 130
133 err = nvgpu_dma_alloc_map_sys(vm, fb_size, 131 err = nvgpu_dma_alloc_map_sys(vm, fb_size,
@@ -138,8 +136,7 @@ static void gv11b_mm_mmu_hw_fault_buf_init(struct gk20a *g,
138 /* Fault will be snapped in pri reg but not in buffer */ 136 /* Fault will be snapped in pri reg but not in buffer */
139 return; 137 return;
140 } 138 }
141 g->mm.hw_fault_buf_status[REPLAY_REG_INDEX] = 139
142 HW_FAULT_BUF_STATUS_ALLOC_TRUE;
143 *hub_intr_types |= HUB_INTR_TYPE_REPLAY; 140 *hub_intr_types |= HUB_INTR_TYPE_REPLAY;
144} 141}
145 142
@@ -165,21 +162,13 @@ static void gv11b_mm_mmu_hw_fault_buf_deinit(struct gk20a *g)
165 FAULT_BUF_DISABLED); 162 FAULT_BUF_DISABLED);
166 } 163 }
167 164
168 if (g->mm.hw_fault_buf_status[NONREPLAY_REG_INDEX] == 165 if (nvgpu_mem_is_valid(
169 HW_FAULT_BUF_STATUS_ALLOC_TRUE) { 166 &g->mm.hw_fault_buf[FAULT_TYPE_OTHER_AND_NONREPLAY]))
170 nvgpu_dma_unmap_free(vm, 167 nvgpu_dma_unmap_free(vm,
171 &g->mm.hw_fault_buf[FAULT_TYPE_OTHER_AND_NONREPLAY]); 168 &g->mm.hw_fault_buf[FAULT_TYPE_OTHER_AND_NONREPLAY]);
172 g->mm.hw_fault_buf_status[NONREPLAY_REG_INDEX] = 169 if (nvgpu_mem_is_valid(&g->mm.hw_fault_buf[FAULT_TYPE_REPLAY]))
173 HW_FAULT_BUF_STATUS_ALLOC_FALSE;
174 }
175
176 if (g->mm.hw_fault_buf_status[REPLAY_REG_INDEX] ==
177 HW_FAULT_BUF_STATUS_ALLOC_TRUE) {
178 nvgpu_dma_unmap_free(vm, 170 nvgpu_dma_unmap_free(vm,
179 &g->mm.hw_fault_buf[FAULT_TYPE_REPLAY]); 171 &g->mm.hw_fault_buf[FAULT_TYPE_REPLAY]);
180 g->mm.hw_fault_buf_status[REPLAY_REG_INDEX] =
181 HW_FAULT_BUF_STATUS_ALLOC_FALSE;
182 }
183} 172}
184 173
185void gv11b_mm_remove_bar2_vm(struct gk20a *g) 174void gv11b_mm_remove_bar2_vm(struct gk20a *g)
@@ -196,14 +185,11 @@ void gv11b_mm_remove_bar2_vm(struct gk20a *g)
196 185
197static void gv11b_mm_mmu_fault_setup_hw(struct gk20a *g) 186static void gv11b_mm_mmu_fault_setup_hw(struct gk20a *g)
198{ 187{
199 if (g->mm.hw_fault_buf_status[NONREPLAY_REG_INDEX] == 188 if (nvgpu_mem_is_valid(
200 HW_FAULT_BUF_STATUS_ALLOC_TRUE) { 189 &g->mm.hw_fault_buf[FAULT_TYPE_OTHER_AND_NONREPLAY]))
201 gv11b_fb_fault_buf_configure_hw(g, NONREPLAY_REG_INDEX); 190 gv11b_fb_fault_buf_configure_hw(g, NONREPLAY_REG_INDEX);
202 } 191 if (nvgpu_mem_is_valid(&g->mm.hw_fault_buf[FAULT_TYPE_REPLAY]))
203 if (g->mm.hw_fault_buf_status[REPLAY_REG_INDEX] ==
204 HW_FAULT_BUF_STATUS_ALLOC_TRUE) {
205 gv11b_fb_fault_buf_configure_hw(g, REPLAY_REG_INDEX); 192 gv11b_fb_fault_buf_configure_hw(g, REPLAY_REG_INDEX);
206 }
207} 193}
208 194
209static int gv11b_mm_mmu_fault_setup_sw(struct gk20a *g) 195static int gv11b_mm_mmu_fault_setup_sw(struct gk20a *g)
@@ -214,11 +200,6 @@ static int gv11b_mm_mmu_fault_setup_sw(struct gk20a *g)
214 200
215 nvgpu_mutex_init(&g->mm.hub_isr_mutex); 201 nvgpu_mutex_init(&g->mm.hub_isr_mutex);
216 202
217 g->mm.hw_fault_buf_status[NONREPLAY_REG_INDEX] =
218 HW_FAULT_BUF_STATUS_ALLOC_FALSE;
219 g->mm.hw_fault_buf_status[REPLAY_REG_INDEX] =
220 HW_FAULT_BUF_STATUS_ALLOC_FALSE;
221
222 g->mm.hub_intr_types = HUB_INTR_TYPE_ECC_UNCORRECTED; 203 g->mm.hub_intr_types = HUB_INTR_TYPE_ECC_UNCORRECTED;
223 204
224 err = gv11b_mm_mmu_fault_info_buf_init(g, &g->mm.hub_intr_types); 205 err = gv11b_mm_mmu_fault_info_buf_init(g, &g->mm.hub_intr_types);
diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.h b/drivers/gpu/nvgpu/gv11b/mm_gv11b.h
index d830b7cc..2b3ebf4e 100644
--- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.h
@@ -1,6 +1,6 @@
1/* 1/*
2 * GV11B MM 2 * GV11B MM
3 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. 3 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
4 * 4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a 5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"), 6 * copy of this software and associated documentation files (the "Software"),
@@ -24,9 +24,6 @@
24#ifndef MM_GV11B_H 24#ifndef MM_GV11B_H
25#define MM_GV11B_H 25#define MM_GV11B_H
26 26
27#define HW_FAULT_BUF_STATUS_ALLOC_TRUE 1
28#define HW_FAULT_BUF_STATUS_ALLOC_FALSE 0
29
30struct gk20a; 27struct gk20a;
31struct nvgpu_mem; 28struct nvgpu_mem;
32struct vm_gk20a; 29struct vm_gk20a;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/mm.h b/drivers/gpu/nvgpu/include/nvgpu/mm.h
index e7b3e52c..90c6946a 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/mm.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/mm.h
@@ -129,7 +129,6 @@ struct mm_gk20a {
129 struct nvgpu_mem bar2_desc; 129 struct nvgpu_mem bar2_desc;
130 130
131 struct nvgpu_mem hw_fault_buf[FAULT_TYPE_NUM]; 131 struct nvgpu_mem hw_fault_buf[FAULT_TYPE_NUM];
132 unsigned int hw_fault_buf_status[FAULT_TYPE_NUM];
133 struct mmu_fault_info *fault_info[FAULT_TYPE_NUM]; 132 struct mmu_fault_info *fault_info[FAULT_TYPE_NUM];
134 struct nvgpu_mutex hub_isr_mutex; 133 struct nvgpu_mutex hub_isr_mutex;
135 u32 hub_intr_types; 134 u32 hub_intr_types;