diff options
author | seshendra Gadagottu <sgadagottu@nvidia.com> | 2017-09-27 14:18:13 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-10-03 16:33:00 -0400 |
commit | 0d63e22a9920eb1e3d8653665cda650eca2311cd (patch) | |
tree | 8342c14bb0fe168c698f3d4b0dc734fcf6217a8f | |
parent | 1f6755b287cd5382a6e16baf0342bf6a7ab97f6c (diff) |
gpu: nvgpu: gv11b: check for memory aperture type
Check for memory aperture type before setting relevant
sysmem non-coherent or vidmem flags in ram entry.
Modified following functions to correct memory aperture type:
gv11b_get_ch_runlist_entry
gv11b_subctx_commit_pdb
Added following hw constants for chan_inst_target:
ram_rl_entry_chan_inst_target_sys_mem_coh_v
ram_rl_entry_chan_inst_target_vid_mem_v
Change-Id: I85698044b9fe4c8baed71121845e4fb69dc33922
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1569521
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h | 8 |
4 files changed, 26 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 26e444cc..5fe40663 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |||
@@ -107,9 +107,13 @@ void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist) | |||
107 | ram_rl_entry_chan_runqueue_selector_f( | 107 | ram_rl_entry_chan_runqueue_selector_f( |
108 | c->t19x.runqueue_sel) | | 108 | c->t19x.runqueue_sel) | |
109 | ram_rl_entry_chan_userd_target_f( | 109 | ram_rl_entry_chan_userd_target_f( |
110 | ram_rl_entry_chan_userd_target_sys_mem_ncoh_v()) | | 110 | nvgpu_aperture_mask(g, &g->fifo.userd, |
111 | ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(), | ||
112 | ram_rl_entry_chan_userd_target_vid_mem_v())) | | ||
111 | ram_rl_entry_chan_inst_target_f( | 113 | ram_rl_entry_chan_inst_target_f( |
112 | ram_rl_entry_chan_userd_target_sys_mem_ncoh_v()); | 114 | nvgpu_aperture_mask(g, &c->inst_block, |
115 | ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(), | ||
116 | ram_rl_entry_chan_inst_target_vid_mem_v())); | ||
113 | 117 | ||
114 | addr_lo = u64_lo32(c->userd_iova) >> | 118 | addr_lo = u64_lo32(c->userd_iova) >> |
115 | ram_rl_entry_chan_userd_ptr_align_shift_v(); | 119 | ram_rl_entry_chan_userd_ptr_align_shift_v(); |
diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 84d21a9a..4951d3a4 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | |||
@@ -158,12 +158,15 @@ void gv11b_subctx_commit_pdb(struct channel_gk20a *c, | |||
158 | u32 format_word; | 158 | u32 format_word; |
159 | u32 pdb_addr_lo, pdb_addr_hi; | 159 | u32 pdb_addr_lo, pdb_addr_hi; |
160 | u64 pdb_addr; | 160 | u64 pdb_addr; |
161 | u32 aperture = nvgpu_aperture_mask(g, vm->pdb.mem, | ||
162 | ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(), | ||
163 | ram_in_sc_page_dir_base_target_vid_mem_v()); | ||
161 | 164 | ||
162 | pdb_addr = nvgpu_mem_get_addr(g, vm->pdb.mem); | 165 | pdb_addr = nvgpu_mem_get_addr(g, vm->pdb.mem); |
163 | pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); | 166 | pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); |
164 | pdb_addr_hi = u64_hi32(pdb_addr); | 167 | pdb_addr_hi = u64_hi32(pdb_addr); |
165 | format_word = ram_in_sc_page_dir_base_target_f( | 168 | format_word = ram_in_sc_page_dir_base_target_f( |
166 | ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(), 0) | | 169 | aperture, 0) | |
167 | ram_in_sc_page_dir_base_vol_f( | 170 | ram_in_sc_page_dir_base_vol_f( |
168 | ram_in_sc_page_dir_base_vol_true_v(), 0) | | 171 | ram_in_sc_page_dir_base_vol_true_v(), 0) | |
169 | ram_in_sc_page_dir_base_fault_replay_tex_f(1, 0) | | 172 | ram_in_sc_page_dir_base_fault_replay_tex_f(1, 0) | |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h index fa42ebbe..3a5bf6cb 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h | |||
@@ -672,6 +672,14 @@ static inline u32 ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(void) | |||
672 | { | 672 | { |
673 | return 0x00000003; | 673 | return 0x00000003; |
674 | } | 674 | } |
675 | static inline u32 ram_rl_entry_chan_inst_target_sys_mem_coh_v(void) | ||
676 | { | ||
677 | return 0x00000002U; | ||
678 | } | ||
679 | static inline u32 ram_rl_entry_chan_inst_target_vid_mem_v(void) | ||
680 | { | ||
681 | return 0x00000000U; | ||
682 | } | ||
675 | static inline u32 ram_rl_entry_chan_userd_target_f(u32 v) | 683 | static inline u32 ram_rl_entry_chan_userd_target_f(u32 v) |
676 | { | 684 | { |
677 | return (v & 0x3) << 6; | 685 | return (v & 0x3) << 6; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h index c7f15f57..fe8bcd6b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h | |||
@@ -672,6 +672,14 @@ static inline u32 ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(void) | |||
672 | { | 672 | { |
673 | return 0x00000003; | 673 | return 0x00000003; |
674 | } | 674 | } |
675 | static inline u32 ram_rl_entry_chan_inst_target_sys_mem_coh_v(void) | ||
676 | { | ||
677 | return 0x00000002U; | ||
678 | } | ||
679 | static inline u32 ram_rl_entry_chan_inst_target_vid_mem_v(void) | ||
680 | { | ||
681 | return 0x00000000U; | ||
682 | } | ||
675 | static inline u32 ram_rl_entry_chan_userd_target_f(u32 v) | 683 | static inline u32 ram_rl_entry_chan_userd_target_f(u32 v) |
676 | { | 684 | { |
677 | return (v & 0x3) << 6; | 685 | return (v & 0x3) << 6; |