diff options
author | Vinod G <vinodg@nvidia.com> | 2018-06-11 23:11:43 -0400 |
---|---|---|
committer | Tejal Kudav <tkudav@nvidia.com> | 2018-06-14 09:44:08 -0400 |
commit | 0aa8d6e27394ec15c1816943996daf8f8ffab438 (patch) | |
tree | f4cc5406bfe6a2f39a3871bb680286ee66925130 | |
parent | 12637d9c23227647e5e62a907974afc987c773a4 (diff) |
gpu: nvgpu: Mask an unused HCE_ILLEGAL_OP Interrupt
HCE interrupt is not being used in nvgpu platform now,
masking the bit from the interrupt register.
bug 2082123
Change-Id: I1d53584afebe57b9621c8f4ec395cd1dcd6c7611
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1746850
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
8 files changed, 59 insertions, 11 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 997856aa..00119300 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -834,11 +834,14 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g) | |||
834 | gk20a_writel(g, pbdma_intr_stall_r(i), intr_stall); | 834 | gk20a_writel(g, pbdma_intr_stall_r(i), intr_stall); |
835 | nvgpu_log_info(g, "pbdma id:%u, intr_en_0 0x%08x", i, intr_stall); | 835 | nvgpu_log_info(g, "pbdma id:%u, intr_en_0 0x%08x", i, intr_stall); |
836 | gk20a_writel(g, pbdma_intr_en_0_r(i), intr_stall); | 836 | gk20a_writel(g, pbdma_intr_en_0_r(i), intr_stall); |
837 | 837 | intr_stall = gk20a_readl(g, pbdma_intr_stall_1_r(i)); | |
838 | nvgpu_log_info(g, "pbdma id:%u, intr_en_1 0x%08x", i, | 838 | /* |
839 | ~pbdma_intr_en_0_lbreq_enabled_f()); | 839 | * For bug 2082123 |
840 | gk20a_writel(g, pbdma_intr_en_1_r(i), | 840 | * Mask the unused HCE_RE_ILLEGAL_OP bit from the interrupt. |
841 | ~pbdma_intr_en_0_lbreq_enabled_f()); | 841 | */ |
842 | intr_stall &= ~pbdma_intr_stall_1_hce_illegal_op_enabled_f(); | ||
843 | nvgpu_log_info(g, "pbdma id:%u, intr_en_1 0x%08x", i, intr_stall); | ||
844 | gk20a_writel(g, pbdma_intr_en_1_r(i), intr_stall); | ||
842 | } | 845 | } |
843 | 846 | ||
844 | /* reset runlist interrupts */ | 847 | /* reset runlist interrupts */ |
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index fdd9ecf0..a7c6360b 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |||
@@ -1222,6 +1222,11 @@ int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) | |||
1222 | gk20a_writel(g, pbdma_intr_en_0_r(i), intr_stall); | 1222 | gk20a_writel(g, pbdma_intr_en_0_r(i), intr_stall); |
1223 | 1223 | ||
1224 | intr_stall = gk20a_readl(g, pbdma_intr_stall_1_r(i)); | 1224 | intr_stall = gk20a_readl(g, pbdma_intr_stall_1_r(i)); |
1225 | /* | ||
1226 | * For bug 2082123 | ||
1227 | * Mask the unused HCE_RE_ILLEGAL_OP bit from the interrupt. | ||
1228 | */ | ||
1229 | intr_stall &= ~pbdma_intr_stall_1_hce_illegal_op_enabled_f(); | ||
1225 | nvgpu_log_info(g, "pbdma id:%u, intr_en_1 0x%08x", i, intr_stall); | 1230 | nvgpu_log_info(g, "pbdma id:%u, intr_en_1 0x%08x", i, intr_stall); |
1226 | gk20a_writel(g, pbdma_intr_en_1_r(i), intr_stall); | 1231 | gk20a_writel(g, pbdma_intr_en_1_r(i), intr_stall); |
1227 | } | 1232 | } |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pbdma_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pbdma_gk20a.h index 338edef2..2c8f48d6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pbdma_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pbdma_gk20a.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2012-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -528,6 +528,14 @@ static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) | |||
528 | { | 528 | { |
529 | return 0x100U; | 529 | return 0x100U; |
530 | } | 530 | } |
531 | static inline u32 pbdma_intr_stall_1_r(u32 i) | ||
532 | { | ||
533 | return 0x00040140U + i*8192U; | ||
534 | } | ||
535 | static inline u32 pbdma_intr_stall_1_hce_illegal_op_enabled_f(void) | ||
536 | { | ||
537 | return 0x1U; | ||
538 | } | ||
531 | static inline u32 pbdma_udma_nop_r(void) | 539 | static inline u32 pbdma_udma_nop_r(void) |
532 | { | 540 | { |
533 | return 0x00000008U; | 541 | return 0x00000008U; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pbdma_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pbdma_gm20b.h index b8d7bbe4..10ed9eca 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pbdma_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pbdma_gm20b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -516,6 +516,14 @@ static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) | |||
516 | { | 516 | { |
517 | return 0x100U; | 517 | return 0x100U; |
518 | } | 518 | } |
519 | static inline u32 pbdma_intr_stall_1_r(u32 i) | ||
520 | { | ||
521 | return 0x00040140U + i*8192U; | ||
522 | } | ||
523 | static inline u32 pbdma_intr_stall_1_hce_illegal_op_enabled_f(void) | ||
524 | { | ||
525 | return 0x1U; | ||
526 | } | ||
519 | static inline u32 pbdma_udma_nop_r(void) | 527 | static inline u32 pbdma_udma_nop_r(void) |
520 | { | 528 | { |
521 | return 0x00000008U; | 529 | return 0x00000008U; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pbdma_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pbdma_gp106.h index dad6317d..1005c5ab 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pbdma_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pbdma_gp106.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -504,6 +504,14 @@ static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) | |||
504 | { | 504 | { |
505 | return 0x100U; | 505 | return 0x100U; |
506 | } | 506 | } |
507 | static inline u32 pbdma_intr_stall_1_r(u32 i) | ||
508 | { | ||
509 | return 0x00040140U + i*8192U; | ||
510 | } | ||
511 | static inline u32 pbdma_intr_stall_1_hce_illegal_op_enabled_f(void) | ||
512 | { | ||
513 | return 0x1U; | ||
514 | } | ||
507 | static inline u32 pbdma_udma_nop_r(void) | 515 | static inline u32 pbdma_udma_nop_r(void) |
508 | { | 516 | { |
509 | return 0x00000008U; | 517 | return 0x00000008U; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pbdma_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pbdma_gp10b.h index 4f45f824..66e8ddbf 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pbdma_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pbdma_gp10b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -528,6 +528,14 @@ static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) | |||
528 | { | 528 | { |
529 | return 0x100U; | 529 | return 0x100U; |
530 | } | 530 | } |
531 | static inline u32 pbdma_intr_stall_1_r(u32 i) | ||
532 | { | ||
533 | return 0x00040140U + i*8192U; | ||
534 | } | ||
535 | static inline u32 pbdma_intr_stall_1_hce_illegal_op_enabled_f(void) | ||
536 | { | ||
537 | return 0x1U; | ||
538 | } | ||
531 | static inline u32 pbdma_udma_nop_r(void) | 539 | static inline u32 pbdma_udma_nop_r(void) |
532 | { | 540 | { |
533 | return 0x00000008U; | 541 | return 0x00000008U; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h index 4b7eb25c..a5c8dad3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -548,6 +548,10 @@ static inline u32 pbdma_intr_stall_1_r(u32 i) | |||
548 | { | 548 | { |
549 | return 0x00040140U + i*8192U; | 549 | return 0x00040140U + i*8192U; |
550 | } | 550 | } |
551 | static inline u32 pbdma_intr_stall_1_hce_illegal_op_enabled_f(void) | ||
552 | { | ||
553 | return 0x1U; | ||
554 | } | ||
551 | static inline u32 pbdma_udma_nop_r(void) | 555 | static inline u32 pbdma_udma_nop_r(void) |
552 | { | 556 | { |
553 | return 0x00000008U; | 557 | return 0x00000008U; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h index f05bee84..75bdae1c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -548,6 +548,10 @@ static inline u32 pbdma_intr_stall_1_r(u32 i) | |||
548 | { | 548 | { |
549 | return 0x00040140U + i*8192U; | 549 | return 0x00040140U + i*8192U; |
550 | } | 550 | } |
551 | static inline u32 pbdma_intr_stall_1_hce_illegal_op_enabled_f(void) | ||
552 | { | ||
553 | return 0x1U; | ||
554 | } | ||
551 | static inline u32 pbdma_udma_nop_r(void) | 555 | static inline u32 pbdma_udma_nop_r(void) |
552 | { | 556 | { |
553 | return 0x00000008U; | 557 | return 0x00000008U; |