diff options
author | Scott Long <scottl@nvidia.com> | 2018-08-08 21:30:09 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-08-22 20:31:42 -0400 |
commit | 07f6739285140d7c5335ddcb8996450966bfc175 (patch) | |
tree | c7f1b3a73d519e44e4fe0d29516e6516740edb26 | |
parent | 1c13da1d29c344cb60953eabeca56b601446c64a (diff) |
gpu: nvgpu: switch gk20a nonstall ops to #defines
Fix MISRA rule 10.1 violations involving gk20a_nonstall_ops
enums by replacing them with with corresponding #defines.
Because these values can be used in expressions that require
unsigned values (e.g. bitwise OR) we cannot use enums.
The g->ce2.isr_nonstall() function was previously returning an
int that was a combination of gk20a_nonstall_ops enum bits which
led to the violations.
JIRA NVGPU-650
Change-Id: I6210aacec8829b3c8d339c5fe3db2f3069c67406
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1796242
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ce2_gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mc_gk20a.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/ce_gp10b.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/ce_gp10b.h | 4 |
9 files changed, 23 insertions, 25 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c index 5aae0613..0248b0ca 100644 --- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | |||
@@ -88,9 +88,9 @@ void gk20a_ce2_isr(struct gk20a *g, u32 inst_id, u32 pri_base) | |||
88 | return; | 88 | return; |
89 | } | 89 | } |
90 | 90 | ||
91 | int gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) | 91 | u32 gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) |
92 | { | 92 | { |
93 | int ops = 0; | 93 | u32 ops = 0; |
94 | u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r()); | 94 | u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r()); |
95 | 95 | ||
96 | nvgpu_log(g, gpu_dbg_intr, "ce2 nonstall isr %08x\n", ce2_intr); | 96 | nvgpu_log(g, gpu_dbg_intr, "ce2 nonstall isr %08x\n", ce2_intr); |
@@ -98,8 +98,8 @@ int gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) | |||
98 | if (ce2_intr & ce2_intr_status_nonblockpipe_pending_f()) { | 98 | if (ce2_intr & ce2_intr_status_nonblockpipe_pending_f()) { |
99 | gk20a_writel(g, ce2_intr_status_r(), | 99 | gk20a_writel(g, ce2_intr_status_r(), |
100 | ce2_nonblockpipe_isr(g, ce2_intr)); | 100 | ce2_nonblockpipe_isr(g, ce2_intr)); |
101 | ops |= (gk20a_nonstall_ops_wakeup_semaphore | | 101 | ops |= (GK20A_NONSTALL_OPS_WAKEUP_SEMAPHORE | |
102 | gk20a_nonstall_ops_post_events); | 102 | GK20A_NONSTALL_OPS_POST_EVENTS); |
103 | } | 103 | } |
104 | return ops; | 104 | return ops; |
105 | } | 105 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h index 1a102070..19a169da 100644 --- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h | |||
@@ -3,7 +3,7 @@ | |||
3 | * | 3 | * |
4 | * GK20A graphics copy engine (gr host) | 4 | * GK20A graphics copy engine (gr host) |
5 | * | 5 | * |
6 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. | 6 | * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. |
7 | * | 7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | 8 | * Permission is hereby granted, free of charge, to any person obtaining a |
9 | * copy of this software and associated documentation files (the "Software"), | 9 | * copy of this software and associated documentation files (the "Software"), |
@@ -30,7 +30,7 @@ | |||
30 | #include "tsg_gk20a.h" | 30 | #include "tsg_gk20a.h" |
31 | 31 | ||
32 | void gk20a_ce2_isr(struct gk20a *g, u32 inst_id, u32 pri_base); | 32 | void gk20a_ce2_isr(struct gk20a *g, u32 inst_id, u32 pri_base); |
33 | int gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base); | 33 | u32 gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base); |
34 | 34 | ||
35 | /* CE command utility macros */ | 35 | /* CE command utility macros */ |
36 | #define NVGPU_CE_LOWER_ADDRESS_OFFSET_MASK 0xffffffff | 36 | #define NVGPU_CE_LOWER_ADDRESS_OFFSET_MASK 0xffffffff |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 4628de4f..20fb51e7 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -2720,7 +2720,7 @@ void gk20a_fifo_isr(struct gk20a *g) | |||
2720 | return; | 2720 | return; |
2721 | } | 2721 | } |
2722 | 2722 | ||
2723 | enum gk20a_nonstall_ops gk20a_fifo_nonstall_isr(struct gk20a *g) | 2723 | u32 gk20a_fifo_nonstall_isr(struct gk20a *g) |
2724 | { | 2724 | { |
2725 | u32 fifo_intr = gk20a_readl(g, fifo_intr_0_r()); | 2725 | u32 fifo_intr = gk20a_readl(g, fifo_intr_0_r()); |
2726 | u32 clear_intr = 0; | 2726 | u32 clear_intr = 0; |
@@ -2732,7 +2732,7 @@ enum gk20a_nonstall_ops gk20a_fifo_nonstall_isr(struct gk20a *g) | |||
2732 | 2732 | ||
2733 | gk20a_writel(g, fifo_intr_0_r(), clear_intr); | 2733 | gk20a_writel(g, fifo_intr_0_r(), clear_intr); |
2734 | 2734 | ||
2735 | return gk20a_nonstall_ops_wakeup_semaphore; | 2735 | return GK20A_NONSTALL_OPS_WAKEUP_SEMAPHORE; |
2736 | } | 2736 | } |
2737 | 2737 | ||
2738 | void gk20a_fifo_issue_preempt(struct gk20a *g, u32 id, bool is_tsg) | 2738 | void gk20a_fifo_issue_preempt(struct gk20a *g, u32 id, bool is_tsg) |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index 120950c1..77030c94 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | |||
@@ -31,7 +31,6 @@ | |||
31 | 31 | ||
32 | struct gk20a_debug_output; | 32 | struct gk20a_debug_output; |
33 | struct mmu_fault_info; | 33 | struct mmu_fault_info; |
34 | enum gk20a_nonstall_ops; | ||
35 | 34 | ||
36 | enum { | 35 | enum { |
37 | NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW = 0, | 36 | NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW = 0, |
@@ -229,7 +228,7 @@ int gk20a_init_fifo_support(struct gk20a *g); | |||
229 | int gk20a_init_fifo_setup_hw(struct gk20a *g); | 228 | int gk20a_init_fifo_setup_hw(struct gk20a *g); |
230 | 229 | ||
231 | void gk20a_fifo_isr(struct gk20a *g); | 230 | void gk20a_fifo_isr(struct gk20a *g); |
232 | enum gk20a_nonstall_ops gk20a_fifo_nonstall_isr(struct gk20a *g); | 231 | u32 gk20a_fifo_nonstall_isr(struct gk20a *g); |
233 | 232 | ||
234 | int gk20a_fifo_preempt_channel(struct gk20a *g, u32 chid); | 233 | int gk20a_fifo_preempt_channel(struct gk20a *g, u32 chid); |
235 | int gk20a_fifo_preempt_tsg(struct gk20a *g, u32 tsgid); | 234 | int gk20a_fifo_preempt_tsg(struct gk20a *g, u32 tsgid); |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 5300f7dd..cf202f14 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -207,7 +207,7 @@ struct gpu_ops { | |||
207 | } ltc; | 207 | } ltc; |
208 | struct { | 208 | struct { |
209 | void (*isr_stall)(struct gk20a *g, u32 inst_id, u32 pri_base); | 209 | void (*isr_stall)(struct gk20a *g, u32 inst_id, u32 pri_base); |
210 | int (*isr_nonstall)(struct gk20a *g, u32 inst_id, u32 pri_base); | 210 | u32 (*isr_nonstall)(struct gk20a *g, u32 inst_id, u32 pri_base); |
211 | u32 (*get_num_pce)(struct gk20a *g); | 211 | u32 (*get_num_pce)(struct gk20a *g); |
212 | } ce2; | 212 | } ce2; |
213 | struct { | 213 | struct { |
@@ -1668,10 +1668,8 @@ struct gk20a_cyclestate_buffer_elem { | |||
1668 | }; | 1668 | }; |
1669 | 1669 | ||
1670 | /* operations that will need to be executed on non stall workqueue */ | 1670 | /* operations that will need to be executed on non stall workqueue */ |
1671 | enum gk20a_nonstall_ops { | 1671 | #define GK20A_NONSTALL_OPS_WAKEUP_SEMAPHORE BIT32(0) |
1672 | gk20a_nonstall_ops_wakeup_semaphore = BIT(0), /* wake up semaphore */ | 1672 | #define GK20A_NONSTALL_OPS_POST_EVENTS BIT32(1) |
1673 | gk20a_nonstall_ops_post_events = BIT(1), | ||
1674 | }; | ||
1675 | 1673 | ||
1676 | /* register accessors */ | 1674 | /* register accessors */ |
1677 | void __nvgpu_check_gpu_state(struct gk20a *g); | 1675 | void __nvgpu_check_gpu_state(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 90643971..f2b083d7 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -6101,8 +6101,8 @@ u32 gk20a_gr_nonstall_isr(struct gk20a *g) | |||
6101 | /* Clear the interrupt */ | 6101 | /* Clear the interrupt */ |
6102 | gk20a_writel(g, gr_intr_nonstall_r(), | 6102 | gk20a_writel(g, gr_intr_nonstall_r(), |
6103 | gr_intr_nonstall_trap_pending_f()); | 6103 | gr_intr_nonstall_trap_pending_f()); |
6104 | ops |= (u32)(gk20a_nonstall_ops_wakeup_semaphore | | 6104 | ops |= (GK20A_NONSTALL_OPS_WAKEUP_SEMAPHORE | |
6105 | gk20a_nonstall_ops_post_events); | 6105 | GK20A_NONSTALL_OPS_POST_EVENTS); |
6106 | } | 6106 | } |
6107 | return ops; | 6107 | return ops; |
6108 | } | 6108 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c index 26084bd6..a0eae127 100644 --- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c | |||
@@ -319,9 +319,10 @@ void mc_gk20a_handle_intr_nonstall(struct gk20a *g, u32 ops) | |||
319 | { | 319 | { |
320 | bool semaphore_wakeup, post_events; | 320 | bool semaphore_wakeup, post_events; |
321 | 321 | ||
322 | semaphore_wakeup = (((ops & (u32)gk20a_nonstall_ops_wakeup_semaphore) != 0U) ? | 322 | semaphore_wakeup = |
323 | (((ops & GK20A_NONSTALL_OPS_WAKEUP_SEMAPHORE) != 0U) ? | ||
323 | true : false); | 324 | true : false); |
324 | post_events = (((ops & (u32)gk20a_nonstall_ops_post_events) != 0U) ? | 325 | post_events = (((ops & GK20A_NONSTALL_OPS_POST_EVENTS) != 0U) ? |
325 | true: false); | 326 | true: false); |
326 | 327 | ||
327 | if (semaphore_wakeup) { | 328 | if (semaphore_wakeup) { |
diff --git a/drivers/gpu/nvgpu/gp10b/ce_gp10b.c b/drivers/gpu/nvgpu/gp10b/ce_gp10b.c index 048a9ba0..76179b78 100644 --- a/drivers/gpu/nvgpu/gp10b/ce_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ce_gp10b.c | |||
@@ -61,9 +61,9 @@ void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base) | |||
61 | return; | 61 | return; |
62 | } | 62 | } |
63 | 63 | ||
64 | int gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) | 64 | u32 gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) |
65 | { | 65 | { |
66 | int ops = 0; | 66 | u32 ops = 0; |
67 | u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id)); | 67 | u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id)); |
68 | 68 | ||
69 | nvgpu_log(g, gpu_dbg_intr, "ce nonstall isr %08x %08x\n", ce_intr, inst_id); | 69 | nvgpu_log(g, gpu_dbg_intr, "ce nonstall isr %08x %08x\n", ce_intr, inst_id); |
@@ -71,8 +71,8 @@ int gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) | |||
71 | if (ce_intr & ce_intr_status_nonblockpipe_pending_f()) { | 71 | if (ce_intr & ce_intr_status_nonblockpipe_pending_f()) { |
72 | gk20a_writel(g, ce_intr_status_r(inst_id), | 72 | gk20a_writel(g, ce_intr_status_r(inst_id), |
73 | ce_intr_status_nonblockpipe_pending_f()); | 73 | ce_intr_status_nonblockpipe_pending_f()); |
74 | ops |= (gk20a_nonstall_ops_wakeup_semaphore | | 74 | ops |= (GK20A_NONSTALL_OPS_WAKEUP_SEMAPHORE | |
75 | gk20a_nonstall_ops_post_events); | 75 | GK20A_NONSTALL_OPS_POST_EVENTS); |
76 | } | 76 | } |
77 | 77 | ||
78 | return ops; | 78 | return ops; |
diff --git a/drivers/gpu/nvgpu/gp10b/ce_gp10b.h b/drivers/gpu/nvgpu/gp10b/ce_gp10b.h index 7b747751..fbf5e6f8 100644 --- a/drivers/gpu/nvgpu/gp10b/ce_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/ce_gp10b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Pascal GPU series Copy Engine. | 2 | * Pascal GPU series Copy Engine. |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -28,6 +28,6 @@ | |||
28 | #include "gk20a/tsg_gk20a.h" | 28 | #include "gk20a/tsg_gk20a.h" |
29 | 29 | ||
30 | void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base); | 30 | void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base); |
31 | int gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base); | 31 | u32 gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base); |
32 | 32 | ||
33 | #endif /*__CE2_GP10B_H__*/ | 33 | #endif /*__CE2_GP10B_H__*/ |