gpu: nvgpu: Enabling/disabling FECS trace support

- To enable FECS trace support, nvgpu should set the MSB
of the read pointer (MAILBOX1).
- The ucode will check if the feature is enabled/disabled
before writing a record into the circular buffer. If the
feature is disabled, it will not write the record.
- If the feature is enabled and the buffer is not allocated,
HW will throw a page fault error.

Bug 2459186
Bug 200542611

Change-Id: I6f181643737d1cf1bda02077eaa714a3f4ef3d8c
Signed-off-by: seshendra <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2189250
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

7 files changed, 74 insertions, 7 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c
index 6b384c89..11f1169b 100644
--- a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -362,6 +362,11 @@ int gk20a_fecs_trace_poll(struct gk20a *g)
         /* Ensure all FECS writes have made it to SYSMEM */
         g->ops.mm.fb_flush(g);
 
+        if (nvgpu_is_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL)) {
+                /* Bits 30:0 of MAILBOX1 represents actual read pointer value */
+                read = read & (~(BIT32(NVGPU_FECS_TRACE_FEATURE_CONTROL_BIT)));
+        }
+
         while (read != write) {
                 cnt = gk20a_fecs_trace_ring_read(g, read);
                 if (cnt <= 0)
@@ -371,6 +376,15 @@ int gk20a_fecs_trace_poll(struct gk20a *g)
                 read = (read + 1) & (GK20A_FECS_TRACE_NUM_RECORDS - 1);
         }
 
+        if (nvgpu_is_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL)) {
+                /*
+                 * In the next step, read pointer is going to be updated.
+                 * So, MSB of read pointer should be set back to 1. This will
+                 * keep FECS trace enabled.
+                 */
+                read = read | (BIT32(NVGPU_FECS_TRACE_FEATURE_CONTROL_BIT));
+        }
+
         /* ensure FECS records has been updated before incrementing read index */
         nvgpu_wmb();
         gk20a_fecs_trace_set_read_index(g, read);
@@ -606,8 +620,30 @@ int gk20a_fecs_trace_enable(struct gk20a *g)
         if (g->ops.fecs_trace.flush)
                 g->ops.fecs_trace.flush(g);
         write = gk20a_fecs_trace_get_write_index(g);
+
+        if (nvgpu_is_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL)) {
+                /*
+                 * For enabling FECS trace support, MAILBOX1's MSB
+                 * (Bit 31:31) should be set to 1. Bits 30:0 represents
+                 * actual pointer value.
+                 */
+                write = write |
+                        (BIT32(NVGPU_FECS_TRACE_FEATURE_CONTROL_BIT));
+        }
         gk20a_fecs_trace_set_read_index(g, write);
 
+        /*
+         * FECS ucode does a priv holdoff around the assertion of
+         * context reset. So, pri transactions (e.g. mailbox1 register
+         * write) might fail due to this. Hence, do write with ack
+         * i.e. write and read it back to make sure write happened for
+         * mailbox1.
+         */
+        while (gk20a_fecs_trace_get_read_index(g) != write) {
+                nvgpu_log(g, gpu_dbg_ctxsw, "mailbox1 update failed");
+                gk20a_fecs_trace_set_read_index(g, write);
+        }
+
         err = nvgpu_thread_create(&trace->poll_task, g,
                         gk20a_fecs_trace_periodic_polling, __func__);
         if (err) {
@@ -622,10 +658,35 @@ int gk20a_fecs_trace_enable(struct gk20a *g)
 int gk20a_fecs_trace_disable(struct gk20a *g)
 {
         struct gk20a_fecs_trace *trace = g->fecs_trace;
+        int read = 0;
 
         if (nvgpu_thread_is_running(&trace->poll_task))
                 nvgpu_thread_stop(&trace->poll_task);
 
+        if (nvgpu_is_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL)) {
+                /*
+                 * For disabling FECS trace support, MAILBOX1's MSB
+                 * (Bit 31:31) should be set to 0.
+                 */
+                read = gk20a_fecs_trace_get_read_index(g) &
+                        (~(BIT32(NVGPU_FECS_TRACE_FEATURE_CONTROL_BIT)));
+
+                gk20a_fecs_trace_set_read_index(g, read);
+
+                /*
+                 * FECS ucode does a priv holdoff around the assertion
+                 * of context reset. So, pri transactions (e.g.
+                 * mailbox1 register write) might fail due to this.
+                 * Hence, do write with ack i.e. write and read it back
+                 * to make sure write happened for mailbox1.
+                 */
+                while (gk20a_fecs_trace_get_read_index(g) != read) {
+                        nvgpu_log(g, gpu_dbg_ctxsw,
+                                        "mailbox1 update failed");
+                        gk20a_fecs_trace_set_read_index(g, read);
+                }
+        }
+
         return -EPERM;
 }
 
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 113f6520..c978f9aa 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -1,7 +1,7 @@
 /*
  * GM20B Graphics
  *
- * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -752,6 +752,7 @@ int gm20b_init_hal(struct gk20a *g)
 
         __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
         __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
+        __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, false);
 
         /* Read fuses to check if gpu needs to boot in secure/non-secure mode */
         if (gops->fuse.check_priv_security(g)) {
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 0723fa0e..561d24d8 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -1,7 +1,7 @@
 /*
  * GP10B Tegra HAL interface
  *
- * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -782,6 +782,7 @@ int gp10b_init_hal(struct gk20a *g)
         __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
         __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
         __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, false);
+        __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, false);
 
         /* Read fuses to check if gpu needs to boot in secure/non-secure mode */
         if (gops->fuse.check_priv_security(g)) {
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index 31ca997f..9a3d2241 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -1,7 +1,7 @@
 /*
  * GV100 Tegra HAL interface
  *
- * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -1039,6 +1039,7 @@ int gv100_init_hal(struct gk20a *g)
         __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
         __nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false);
         __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true);
+        __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, false);
 
         /* for now */
         __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true);
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index ea9b41d8..84469fa0 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -1,7 +1,7 @@
 /*
  * GV11B Tegra HAL interface
  *
- * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -949,6 +949,7 @@ int gv11b_init_hal(struct gk20a *g)
 
         __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
         __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true);
+        __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, true);
 
         __nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false);
 
diff --git a/drivers/gpu/nvgpu/include/nvgpu/ctxsw_trace.h b/drivers/gpu/nvgpu/include/nvgpu/ctxsw_trace.h
index 2da6b837..033e020a 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/ctxsw_trace.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/ctxsw_trace.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -48,6 +48,7 @@ struct channel_gk20a;
         ((p)->tag_bits[(n) / 64] &   (1 << ((n) & 63)))
 
 #define NVGPU_GPU_CTXSW_FILTER_SIZE (NVGPU_GPU_CTXSW_TAG_LAST + 1)
+#define NVGPU_FECS_TRACE_FEATURE_CONTROL_BIT 31
 
 struct nvgpu_gpu_ctxsw_trace_filter {
         u64 tag_bits[(NVGPU_GPU_CTXSW_FILTER_SIZE + 63) / 64];
diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h
index 79bffcac..76f0f2bd 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -37,6 +37,7 @@ struct gk20a;
 #define NVGPU_FECS_TRACE_VA                     4
 #define NVGPU_CAN_RAILGATE                      5
 #define NVGPU_KERNEL_IS_DYING                   6
+#define NVGPU_FECS_TRACE_FEATURE_CONTROL        7
 
 /*
  * ECC flags