diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2018-01-03 15:57:14 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-01-04 14:04:39 -0500 |
commit | 031eb0ec834c31e0f03b563877b996788f9d9f9f (patch) | |
tree | 192b8014c147273bab978d2fbc0ed3478d71ca85 | |
parent | e0aca109b1d98ca4ddb42ac42a60b0f267f1ecf5 (diff) |
gpu: nvgpu: Remove gk20a specific optimization
Remove compute optimization specific to gk20a. We do not support
gk20a anymore.
Change-Id: Ibd548eee8d891a667f28a451d586fcfaac7f026a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1631144
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 59 |
2 files changed, 0 insertions, 62 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 6a669d88..9d51be59 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -1439,12 +1439,9 @@ static inline void gk20a_gr_flush_channel_tlb(struct gr_gk20a *gr) | |||
1439 | /* classes that the device supports */ | 1439 | /* classes that the device supports */ |
1440 | /* TBD: get these from an open-sourced SDK? */ | 1440 | /* TBD: get these from an open-sourced SDK? */ |
1441 | enum { | 1441 | enum { |
1442 | KEPLER_C = 0xA297, | ||
1443 | FERMI_TWOD_A = 0x902D, | 1442 | FERMI_TWOD_A = 0x902D, |
1444 | KEPLER_COMPUTE_A = 0xA0C0, | ||
1445 | KEPLER_INLINE_TO_MEMORY_A = 0xA040, | 1443 | KEPLER_INLINE_TO_MEMORY_A = 0xA040, |
1446 | KEPLER_DMA_COPY_A = 0xA0B5, | 1444 | KEPLER_DMA_COPY_A = 0xA0B5, |
1447 | KEPLER_CHANNEL_GPFIFO_C = 0xA26F, | ||
1448 | }; | 1445 | }; |
1449 | 1446 | ||
1450 | #define GK20A_BAR0_IORESOURCE_MEM 0 | 1447 | #define GK20A_BAR0_IORESOURCE_MEM 0 |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index f07a54b1..c7104941 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -2979,65 +2979,6 @@ int gk20a_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags) | |||
2979 | gr_gk20a_commit_global_ctx_buffers(g, c, true)); | 2979 | gr_gk20a_commit_global_ctx_buffers(g, c, true)); |
2980 | } | 2980 | } |
2981 | 2981 | ||
2982 | /* tweak any perf parameters per-context here */ | ||
2983 | if (class_num == KEPLER_COMPUTE_A) { | ||
2984 | u32 tex_lock_disable_mask; | ||
2985 | u32 texlock; | ||
2986 | u32 lockboost_mask; | ||
2987 | u32 lockboost; | ||
2988 | |||
2989 | if (g->support_pmu && g->can_elpg) { | ||
2990 | err = nvgpu_pmu_disable_elpg(g); | ||
2991 | if (err) { | ||
2992 | nvgpu_err(g, | ||
2993 | "failed to set disable elpg"); | ||
2994 | } | ||
2995 | } | ||
2996 | |||
2997 | tex_lock_disable_mask = | ||
2998 | gr_gpcs_tpcs_sm_sch_texlock_tex_hash_m() | | ||
2999 | gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tile_m() | | ||
3000 | gr_gpcs_tpcs_sm_sch_texlock_tex_hash_phase_m() | | ||
3001 | gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tex_m() | | ||
3002 | gr_gpcs_tpcs_sm_sch_texlock_tex_hash_timeout_m() | | ||
3003 | gr_gpcs_tpcs_sm_sch_texlock_dot_t_unlock_m(); | ||
3004 | |||
3005 | texlock = gk20a_readl(g, gr_gpcs_tpcs_sm_sch_texlock_r()); | ||
3006 | |||
3007 | texlock = (texlock & ~tex_lock_disable_mask) | | ||
3008 | (gr_gpcs_tpcs_sm_sch_texlock_tex_hash_disable_f() | | ||
3009 | gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tile_disable_f() | | ||
3010 | gr_gpcs_tpcs_sm_sch_texlock_tex_hash_phase_disable_f() | | ||
3011 | gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tex_disable_f() | | ||
3012 | gr_gpcs_tpcs_sm_sch_texlock_tex_hash_timeout_disable_f() | | ||
3013 | gr_gpcs_tpcs_sm_sch_texlock_dot_t_unlock_disable_f()); | ||
3014 | |||
3015 | lockboost_mask = | ||
3016 | gr_gpcs_tpcs_sm_sch_macro_sched_lockboost_size_m(); | ||
3017 | |||
3018 | lockboost = gk20a_readl(g, gr_gpcs_tpcs_sm_sch_macro_sched_r()); | ||
3019 | lockboost = (lockboost & ~lockboost_mask) | | ||
3020 | gr_gpcs_tpcs_sm_sch_macro_sched_lockboost_size_f(0); | ||
3021 | |||
3022 | err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx, false); | ||
3023 | |||
3024 | if (!err) { | ||
3025 | gr_gk20a_ctx_patch_write(g, ch_ctx, | ||
3026 | gr_gpcs_tpcs_sm_sch_texlock_r(), | ||
3027 | texlock, true); | ||
3028 | gr_gk20a_ctx_patch_write(g, ch_ctx, | ||
3029 | gr_gpcs_tpcs_sm_sch_macro_sched_r(), | ||
3030 | lockboost, true); | ||
3031 | gr_gk20a_ctx_patch_write_end(g, ch_ctx, false); | ||
3032 | } else { | ||
3033 | nvgpu_err(g, | ||
3034 | "failed to set texlock for compute class"); | ||
3035 | } | ||
3036 | |||
3037 | if (g->support_pmu && g->can_elpg) | ||
3038 | nvgpu_pmu_enable_elpg(g); | ||
3039 | } | ||
3040 | |||
3041 | /* init golden image, ELPG enabled after this is done */ | 2982 | /* init golden image, ELPG enabled after this is done */ |
3042 | err = gr_gk20a_init_golden_ctx_image(g, c); | 2983 | err = gr_gk20a_init_golden_ctx_image(g, c); |
3043 | if (err) { | 2984 | if (err) { |