/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <linux/io.h>
#include <linux/highmem.h>
#include <linux/platform_device.h>
#include "gk20a.h"
#include "platform_gk20a.h"
#include <nvgpu/log.h>
#include <nvgpu/hw/gk20a/hw_sim_gk20a.h>
static inline void sim_writel(struct gk20a *g, u32 r, u32 v)
{
writel(v, g->sim.regs + r);
}
static inline u32 sim_readl(struct gk20a *g, u32 r)
{
return readl(g->sim.regs + r);
}
static void kunmap_and_free_iopage(void **kvaddr, struct page **page)
{
if (*kvaddr) {
kunmap(*kvaddr);
*kvaddr = NULL;
}
if (*page) {
__free_page(*page);
*page = NULL;
}
}
static void gk20a_free_sim_support(struct gk20a *g)
{
/* free sim mappings, bfrs */
kunmap_and_free_iopage(&g->sim.send_bfr.kvaddr,
&g->sim.send_bfr.page);
kunmap_and_free_iopage(&g->sim.recv_bfr.kvaddr,
&g->sim.recv_bfr.page);
kunmap_and_free_iopage(&g->sim.msg_bfr.kvaddr,
&g->sim.msg_bfr.page);
}
static void gk20a_remove_sim_support(struct sim_gk20a *s)
{
struct gk20a *g = s->g;
if (g->sim.regs)
sim_writel(g, sim_config_r(), sim_config_mode_disabled_v());
gk20a_free_sim_support(g);
}
static int alloc_and_kmap_iopage(struct gk20a *g,
void **kvaddr,
u64 *phys,
struct page **page)
{
int err = 0;
*page = alloc_page(GFP_KERNEL);
if (!*page) {
err = -ENOMEM;
nvgpu_err(g, "couldn't allocate io page");
goto fail;
}
*kvaddr = kmap(*page);
if (!*kvaddr) {
err = -ENOMEM;
nvgpu_err(g, "couldn't kmap io page");
goto fail;
}
*phys = page_to_phys(*page);
return 0;
fail:
kunmap_and_free_iopage(kvaddr, page);
return err;
}
int gk20a_init_sim_support(struct platform_device *pdev)
{
int err = 0;
struct device *dev = &pdev->dev;
struct gk20a *g = get_gk20a(dev);
u64 phys;
/* allocate sim event/msg buffers */
err = alloc_and_kmap_iopage(g, &g->sim.send_bfr.kvaddr,
&g->sim.send_bfr.phys,
&g->sim.send_bfr.page);
err = err || alloc_and_kmap_iopage(g, &g->sim.recv_bfr.kvaddr,
&g->sim.recv_bfr.phys,
&g->sim.recv_bfr.page);
err = err || alloc_and_kmap_iopage(g, &g->sim.msg_bfr.kvaddr,
&g->sim.msg_bfr.phys,
&g->sim.msg_bfr.page);
if (!(g->sim.send_bfr.kvaddr && g->sim.recv_bfr.kvaddr &&
g->sim.msg_bfr.kvaddr)) {
nvgpu_err(g, "couldn't allocate all sim buffers");
goto fail;
}
/*mark send ring invalid*/
sim_writel(g, sim_send_ring_r(), sim_send_ring_status_invalid_f());
/*read get pointer and make equal to put*/
g->sim.send_ring_put = sim_readl(g, sim_send_get_r());
sim_writel(g, sim_send_put_r(), g->sim.send_ring_put);
/*write send ring address and make it valid*/
phys = g->sim.send_bfr.phys;
sim_writel(g, sim_send_ring_hi_r(),
sim_send_ring_hi_addr_f(u64_hi32(phys)));
sim_writel(g, sim_send_ring_r(),
sim_send_ring_status_valid_f() |
sim_send_ring_target_phys_pci_coherent_f() |
sim_send_ring_size_4kb_f() |
sim_send_ring_addr_lo_f(phys >> PAGE_SHIFT));
/*repeat for recv ring (but swap put,get as roles are opposite) */
sim_writel(g, sim_recv_ring_r(), sim_recv_ring_status_invalid_f());
/*read put pointer and make equal to get*/
g->sim.recv_ring_get = sim_readl(g, sim_recv_put_r());
sim_writel(g, sim_recv_get_r(), g->sim.recv_ring_get);
/*write send ring address and make it valid*/
phys = g->sim.recv_bfr.phys;
sim_writel(g, sim_recv_ring_hi_r(),
sim_recv_ring_hi_addr_f(u64_hi32(phys)));
sim_writel(g, sim_recv_ring_r(),
sim_recv_ring_status_valid_f() |
sim_recv_ring_target_phys_pci_coherent_f() |
sim_recv_ring_size_4kb_f() |
sim_recv_ring_addr_lo_f(phys >> PAGE_SHIFT));
g->sim.remove_support = gk20a_remove_sim_support;
return 0;
fail:
gk20a_free_sim_support(g);
return err;
}
static inline u32 sim_msg_header_size(void)
{
return 24;/*TBD: fix the header to gt this from NV_VGPU_MSG_HEADER*/
}
static inline u32 *sim_msg_bfr(struct gk20a *g, u32 byte_offset)
{
return (u32 *)(g->sim.msg_bfr.kvaddr + byte_offset);
}
static inline u32 *sim_msg_hdr(struct gk20a *g, u32 byte_offset)
{
return sim_msg_bfr(g, byte_offset); /*starts at 0*/
}
static inline u32 *sim_msg_param(struct gk20a *g, u32 byte_offset)
{
/*starts after msg header/cmn*/
return sim_msg_bfr(g, byte_offset + sim_msg_header_size());
}
static inline void sim_write_hdr(struct gk20a *g, u32 func, u32 size)
{
/*memset(g->sim.msg_bfr.kvaddr,0,min(PAGE_SIZE,size));*/
*sim_msg_hdr(g, sim_msg_signature_r()) = sim_msg_signature_valid_v();
*sim_msg_hdr(g, sim_msg_result_r()) = sim_msg_result_rpc_pending_v();
*sim_msg_hdr(g, sim_msg_spare_r()) = sim_msg_spare__init_v();
*sim_msg_hdr(g, sim_msg_function_r()) = func;
*sim_msg_hdr(g, sim_msg_length_r()) = size + sim_msg_header_size();
}
static inline u32 sim_escape_read_hdr_size(void)
{
return 12; /*TBD: fix NV_VGPU_SIM_ESCAPE_READ_HEADER*/
}
static u32 *sim_send_ring_bfr(struct gk20a *g, u32 byte_offset)
{
return (u32 *)(g->sim.send_bfr.kvaddr + byte_offset);
}
static int rpc_send_message(struct gk20a *g)
{
/* calculations done in units of u32s */
u32 send_base = sim_send_put_pointer_v(g->sim.send_ring_put) * 2;
u32 dma_offset = send_base + sim_dma_r()/sizeof(u32);
u32 dma_hi_offset = send_base + sim_dma_hi_r()/sizeof(u32);
*sim_send_ring_bfr(g, dma_offset*sizeof(u32)) =
sim_dma_target_phys_pci_coherent_f() |
sim_dma_status_valid_f() |
sim_dma_size_4kb_f() |
sim_dma_addr_lo_f(g->sim.msg_bfr.phys >> PAGE_SHIFT);
*sim_send_ring_bfr(g, dma_hi_offset*sizeof(u32)) =
u64_hi32(g->sim.msg_bfr.phys);
*sim_msg_hdr(g, sim_msg_sequence_r()) = g->sim.sequence_base++;
g->sim.send_ring_put = (g->sim.send_ring_put + 2 * sizeof(u32)) %
PAGE_SIZE;
__cpuc_flush_dcache_area(g->sim.msg_bfr.kvaddr, PAGE_SIZE);
__cpuc_flush_dcache_area(g->sim.send_bfr.kvaddr, PAGE_SIZE);
__cpuc_flush_dcache_area(g->sim.recv_bfr.kvaddr, PAGE_SIZE);
/* Update the put pointer. This will trap into the host. */
sim_writel(g, sim_send_put_r(), g->sim.send_ring_put);
return 0;
}
static inline u32 *sim_recv_ring_bfr(struct gk20a *g, u32 byte_offset)
{
return (u32 *)(g->sim.recv_bfr.kvaddr + byte_offset);
}
static int rpc_recv_poll(struct gk20a *g)
{
u64 recv_phys_addr;
/* XXX This read is not required (?) */
/*pVGpu->recv_ring_get = VGPU_REG_RD32(pGpu, NV_VGPU_RECV_GET);*/
/* Poll the recv ring get pointer in an infinite loop*/
do {
g->sim.recv_ring_put = sim_readl(g, sim_recv_put_r());
} while (g->sim.recv_ring_put == g->sim.recv_ring_get);
/* process all replies */
while (g->sim.recv_ring_put != g->sim.recv_ring_get) {
/* these are in u32 offsets*/
u32 dma_lo_offset =
sim_recv_put_pointer_v(g->sim.recv_ring_get)*2 + 0;
u32 dma_hi_offset = dma_lo_offset + 1;
u32 recv_phys_addr_lo = sim_dma_addr_lo_v(
*sim_recv_ring_bfr(g, dma_lo_offset*4));
u32 recv_phys_addr_hi = sim_dma_hi_addr_v(
*sim_recv_ring_bfr(g, dma_hi_offset*4));
recv_phys_addr = (u64)recv_phys_addr_hi << 32 |
(u64)recv_phys_addr_lo << PAGE_SHIFT;
if (recv_phys_addr != g->sim.msg_bfr.phys) {
nvgpu_err(g, "%s Error in RPC reply",
__func__);
return -1;
}
/* Update GET pointer */
g->sim.recv_ring_get = (g->sim.recv_ring_get + 2*sizeof(u32)) %
PAGE_SIZE;
__cpuc_flush_dcache_area(g->sim.msg_bfr.kvaddr, PAGE_SIZE);
__cpuc_flush_dcache_area(g->sim.send_bfr.kvaddr, PAGE_SIZE);
__cpuc_flush_dcache_area(g->sim.recv_bfr.kvaddr, PAGE_SIZE);
sim_writel(g, sim_recv_get_r(), g->sim.recv_ring_get);
g->sim.recv_ring_put = sim_readl(g, sim_recv_put_r());
}
return 0;
}
static int issue_rpc_and_wait(struct gk20a *g)
{
int err;
err = rpc_send_message(g);
if (err) {
nvgpu_err(g, "%s failed rpc_send_message",
__func__);
return err;
}
err = rpc_recv_poll(g);
if (err) {
nvgpu_err(g, "%s failed rpc_recv_poll",
__func__);
return err;
}
/* Now check if RPC really succeeded */
if (*sim_msg_hdr(g, sim_msg_result_r()) != sim_msg_result_success_v()) {
nvgpu_err(g, "%s received failed status!",
__func__);
return -(*sim_msg_hdr(g, sim_msg_result_r()));
}
return 0;
}
int gk20a_sim_esc_readl(struct gk20a *g, char *path, u32 index, u32 *data)
{
int err;
size_t pathlen = strlen(path);
u32 data_offset;
sim_write_hdr(g, sim_msg_function_sim_escape_read_v(),
sim_escape_read_hdr_size());
*sim_msg_param(g, 0) = index;
*sim_msg_param(g, 4) = sizeof(u32);
data_offset = roundup(0xc + pathlen + 1, sizeof(u32));
*sim_msg_param(g, 8) = data_offset;
strcpy((char *)sim_msg_param(g, 0xc), path);
err = issue_rpc_and_wait(g);
if (!err)
memcpy(data, sim_msg_param(g, data_offset), sizeof(u32));
return err;
}
