nvgpu.git/drivers/gpu/nvgpu/include, branch gpu-paging

gpu-paging: Allow for more than one buffer to be swapped at a time

2022-06-03T19:41:42+00:00

This uses a very primitive linear disk sector allocation scheme.
Sectors are only reused when userspace resets assignment to 0 with
an NVGPU_AS_IOCTL_SWAP_RESET ioctl (which invalidates all current
swap buffers).

This sector assignment scheme is sufficient for use in a TimeWall-
like system, where all allocations are assumed to be static after
after task system release. This is not suitable for a system with
dynamic allocations, unless userspace manually resets swap state
regularly (benchmarks run a reset at start for example).

Support for dynamic allocations is on the backlog.

No significant speed impact.

Benchmarks, 100 iters, after:
gpu_paging_speed, write: 186.0ms +/- 3.51
gpu_paging_speed, read: 162.7ms +/- 2.58
gpu_paging_overhead_speed, write start: 35.4ms +/- 4.47
gpu_paging_overhead_speed, write finish: 3.3ms +/- 0.18
gpu_paging_overhead_speed, read start: 69.8ms +/- 6.42
gpu_paging_overhead_speed, read finish: 43.2ms +/- 0.91

gpu-paging: Support asynchronous paging

2022-05-31T15:32:12+00:00

- Fully enables *_ASYNC API
- Allows page mapping to be overlapped with I/O, resulting in an 11% speedup
  to synchronous reads

Benchmarks, 1,000 iters, before:
gpu_paging_speed, write: 185.5ms +/- 3.58
gpu_paging_speed, read: 180.5ms +/- 1.42
gpu_paging_overhead_speed, write start: 183.3ms +/- 3.89
gpu_paging_overhead_speed, write finish: 3.4ms +/- 2.61
gpu_paging_overhead_speed, read start: 181.6ms +/- 3.34
gpu_paging_overhead_speed, read finish: 41.1ms +/- 2.69

Benchmarks, 1,000 iters, after:
gpu_paging_speed, write: 185.8ms +/- 3.70
gpu_paging_speed, read: 161.3ms +/- 0.97
gpu_paging_overhead_speed, write start: 38.9ms +/- 5.47
gpu_paging_overhead_speed, write finish: 3.1ms +/- 2.42
gpu_paging_overhead_speed, read start: 79.4 +/- 6.42
gpu_paging_overhead_speed, read finish: 44.3 +/- 1.53

gpu-paging: Initial working implementation

2022-05-25T01:11:59+00:00

Supports synchronous page out or in of a specific buffer.

Includes fast reverse struct mapped_buf lookup.

Requires initial set of changes to nvmap as well.

gpu: nvgpu: add support for disabling l3 via DT

2022-02-02T20:10:51+00:00

On volta the GPU determines whether to do L3 allocation for a mapping by
checking bit 36 of the physical address. So if a mapping should allocate lines
in the L3 this bit must be set.

However, when the physical addresses for 64GB of RAM uses the 36th bit
resulting in a conflict. Thus, add support for disabling l3 support
for SKUs having 64GB of physical memory.

Bug 3486025

Signed-off-by: Debarshi Dutta 
Change-Id: Ic540e754274cf1d9e6625493962699d21509e540
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2661548
Reviewed-by: Brad Griffis 
Reviewed-by: Bibek Basu 
Tested-by: Brad Griffis 
GVS: Gerrit_Virtual_Submit

nvgpu: gpu: adds support for ACR dbg/prod.

2021-10-11T19:56:53+00:00

ACR ucode is encrypted using different keys for prod/dbg boards.
This change adds a check to select ACR ucode based on board type.

ACR ucode binaries are also renamed with "nv_" prefix to conform
to release naming conventions.

Bug 2672836

Change-Id: I48818f018f903c0d03642c12485d60e392121eb6
Signed-off-by: smadhavan 
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2492587
(cherry picked from commit 5dacead521aaee1bd8a3b2e9db3e281c085038f7)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2597878
Reviewed-by: Mayur Poojary 
Reviewed-by: Deepak Nibade 
Reviewed-by: mobile promotions 
Tested-by: Mayur Poojary 
Tested-by: mobile promotions 
GVS: Gerrit_Virtual_Submit

nvgpu: gpu: adds support for ACR dbg/prod.

2021-10-06T02:10:26+00:00

ACR ucode is encrypted using different keys for prod/dbg boards.
This change adds a check to select ACR ucode based on board type.
Note: This support is added only for t19x.

Bug 2350733
Bug 2672832
Bug 2672836
Bug 2674821
JIRA NVGPU-4001

(cherry picked from commit c19a0f0c26ab94f6bbf4380ab93e458b88589c82)

Change-Id: I2febc2cbe869c06bca0adebd7723b0d6fc1d4b23
Signed-off-by: smadhavan 
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2483968
Tested-by: Amulya Yarlagadda 
Tested-by: mobile promotions 
Reviewed-by: Amulya Yarlagadda 
Reviewed-by: mobile promotions 
GVS: Gerrit_Virtual_Submit

gpu: nvgpu: Add ECC Support for GV11B in Linux

2021-05-28T19:10:24+00:00

Implement nvgpu plumbing to allow reporting ECC errors(corrected
and uncorrected) to a L1SS service(if one exists).

This patch includes the following

1) Added code that submits ECC error reports via the Interrupt context
directly to a L1SS service in linux OS.

2) Added support for enabling/disabling the error reports via L1SS's
registration/deregistration API. Nvgpu simply invokes an empty function
until the registration is successful.

3) Added Spinlock to correctly handle concurrency for accessing the
correct Ops for submitting requests.

4) Adds error reporting for a subset of interrupts that can be verified
via external ECC injection logic. A subsequent patch will add the
API for rest of the interrupts.

5) In case of critical(uncorrected errors), change nvgpu's state to
quiesce state.

Jira L4T-1187
Bug 200700400

Change-Id: Id31f70531fba355e94e72c4f9762593e7667a11c
Signed-off-by: Debarshi Dutta 
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2530411
Tested-by: Bibek Basu 
Tested-by: mobile promotions 
Reviewed-by: Bibek Basu 
Reviewed-by: svc-mobile-coverity 
Reviewed-by: mobile promotions 
GVS: Gerrit_Virtual_Submit

gpu: nvgpu: wait for stalling interrupts to complete during TSG unbind preempt

2021-05-04T21:40:45+00:00

Some of the engine stalling interrupts can block the context save off
the engine if not handled during fifo.preempt_tsg. They need to be
handled while polling for engine ctxsw status.

Bug 200711183
Bug 200726848

Change-Id: Ie45d76d9d1d8be3ffb842670843507f2d9aea6d0
Signed-off-by: Sagar Kamble 
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2521971
(cherry picked from commit I7418a9e0354013b81fbefd8c0cab5068404fc44e)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2523938
Reviewed-by: svc-mobile-coverity 
Reviewed-by: Deepak Nibade 
Reviewed-by: Bibek Basu 
Reviewed-by: mobile promotions 
Tested-by: mobile promotions 
GVS: Gerrit_Virtual_Submit

gpu: nvgpu: create timed wait functions for stall and nonstall interrupts completion

2021-05-04T21:40:40+00:00

In order to process stalling interrupts during TSG unbind, we need a API
to wait for the stalling interrupts to complete within certain duration.

Prepare these APIs for stalling and non-stalling interrupts.

Bug 200711183
Bug 200726848

Change-Id: I634738249ade64224326b356d6244ad4299f1baf
Signed-off-by: Sagar Kamble 
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2521970
(cherry picked from commit I0b7a64c0f3761bbd0ca0843aea28a591ed23739f)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2523937
Reviewed-by: svc-mobile-coverity 
Reviewed-by: Deepak Nibade 
Reviewed-by: Bibek Basu 
Reviewed-by: mobile promotions 
Tested-by: mobile promotions 
GVS: Gerrit_Virtual_Submit

gpu: nvgpu: retry tsg unbind if NEXT is set

2021-03-19T21:39:39+00:00

The NEXT bit can remain set for the channel if timeslice expires before
scheduler clears it. Due to this nvgpu fails TSG unbind and in turn
nvrm_gpu fails channel close. In this case, checking the channel hw
state after some time can help see NEXT bit cleared by scheduler.

Reenable the tsg and return -EAGAIN to nvrm_gpu for it to retry again.

Bug 3144960
Bug 200520811

Change-Id: I35f417f02270e371a4e632986b73a00f8a4f921a
Signed-off-by: Sagar Kamble 
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2468391
(cherry picked from commit cf287a4ef592e7329f813c076ec8bdad18dc5933)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2479106
Tested-by: mobile promotions 
Reviewed-by: Deepak Nibade 
Reviewed-by: svc-mobile-coverity 
Reviewed-by: mobile promotions 
GVS: Gerrit_Virtual_Submit