nvgpu.git/drivers/gpu/nvgpu/boardobj, branch gpu-paging

gpu: nvgpu: pmgr: fix MISRA Rule 10.4 Violations

2018-09-27T06:35:37+00:00

MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.

Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.

This fixes violation where an arithmetic operation is performed on
signed and unsigned int types.

JIRA NVGPU-992

Change-Id: Id3b2c8ea1af1807087468c6978abfbfc85bee2ec
Signed-off-by: Sai Nikhil 
Reviewed-on: https://git-master.nvidia.com/r/1809757
Reviewed-by: svc-misra-checker 
GVS: Gerrit_Virtual_Submit
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Adeel Raza 
Reviewed-by: mobile promotions 
Tested-by: mobile promotions

gpu: nvgpu: MISRA Rule 21.2 header guard fixes

2018-09-25T04:17:42+00:00

MISRA rule 21.2 doesn't allow the use of macro names which start with
an underscore. These leading underscores are to be removed from the
macro names. This patch will fix such violations in nvgpu by
renaming them to follow the convention,'NVGPU_PARENT-DIR_HEADER-NAME'
when there is no keyword repetition between file name and directory
or 'NVGPU_HEADER-NAME' when there is repetition.

JIRA NVGPU-1028

Change-Id: I8a473c6c1a864f3893920d8e06e305095e523d2a
Signed-off-by: smadhavan 
Reviewed-on: https://git-master.nvidia.com/r/1809082
Reviewed-by: svc-misra-checker 
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Tested-by: Debarshi Dutta 
Reviewed-by: Adeel Raza 
Reviewed-by: mobile promotions 
Tested-by: mobile promotions

gpu:nvgpu: Update number of LUT entries

2018-09-20T17:51:03+00:00

CTRL_CLK_LUT_NUM_ENTRIES to 128
And fix build issues that appeared with 128 entries.

Bug 2331655

Change-Id: If116bff14be9a1923e075f783fdb9a2e992208b8
Signed-off-by: Vaikundanathan S 
Reviewed-on: https://git-master.nvidia.com/r/1810493
Reviewed-on: https://git-master.nvidia.com/r/1813861
Reviewed-by: mobile promotions 
Tested-by: mobile promotions

gpu: nvgpu: add igpu support for clk_arbiter.

2018-09-20T17:50:12+00:00

This patch constructs clk_arbiter specific code for gp10b as well as
gv11b and does the necessary plumbing in the clk_arbiter code. The
changes made are as follows.

1) Constructed clk_arb_gp10b.* files which add support for clk_arb
related HALS including the nvgpu_clk_arb_init and nvgpu_clk_arb_cb.
This doesn't have support for debugfs nor the VFUpdateEvent yet and
consequently no support for arb->notifications.

2) Added gpcclk specific variables corresponding to every gpc2clk in
a given clk_arb related struct.

3) Linux specific support_clk_freq_controller is assigned true in
platform_gp10b.c and platform_gv11b.c files.

4) Incremented the clk_arb_worker.put atomic variable during
worker_deinit so as to allow the worker thread to be stopped.

5) Added the flag clk_arb_events_supported as part of struct
nvgpu_clk_arb. This flag is used to selectively account for the extra
refcounting present in OS specific code i.e.
nvgpu_clk_arb_commit_request_fd. For igpus, the extra refcount is
reduced during nvgpu_clk_arb_release_completion_dev.

Bug 2061372

Change-Id: Id00acb106db2b46e55aa0324034a16a73723c078
Signed-off-by: Debarshi Dutta 
Reviewed-on: https://git-master.nvidia.com/r/1774281
Reviewed-by: mobile promotions 
Tested-by: mobile promotions

gpu: nvgpu: change location of gk20a.h

2018-09-14T22:34:58+00:00

Update the location of gk20a.h to include/nvgpu/gk20a.h in the
following directories.

nvgpu/boardobj/
nvgpu/clk/
nvgpu/lpwr/
nvgpu/perf/
nvgpu/pmgr/
nvgpu/pstate/
nvgpu/therm/
nvgpu/volt/

Jira NVGPU-597

Change-Id: I5d9e74ae2f1a646087f15a5872daf9017c1580a9
Signed-off-by: Debarshi Dutta 
Reviewed-on: https://git-master.nvidia.com/r/1822741
Reviewed-by: svc-misra-checker 
Reviewed-by: Konsta Holtta 
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom 
Reviewed-by: mobile promotions 
Tested-by: mobile promotions

gpu: nvgpu: cleanup return types for MISRA 10.3

2018-09-07T04:33:50+00:00

This is a big cleanup of return types across a number of modules in the
nvgpu driver. Many functions were returning u32 but using negative
return codes. This is a MISRA 10.3 violation by assigning signed values
to a u32.

JIRA NVGPU-647

Change-Id: I59ee66706321f5b5b1a07ed8c24b81583e9ba28c
Signed-off-by: Philip Elcan 
Reviewed-on: https://git-master.nvidia.com/r/1810743
Reviewed-by: mobile promotions 
Tested-by: mobile promotions

gpu: nvgpu: move gp106 specific clk_arbiter code into HAL

2018-09-04T14:25:41+00:00

Currently, clock arbiter code is extensively using dgpu specific
implementation. This patch restructures the clk_arbiter code and moves
gp106 specific code into HAL. Following changes are made in this patch

1) clk_domain_get_f_points is now invoked via HAL for gp106 i.e.
g->ops.clk.clk_domain_get_f_points.

2) moved nvgpu_clk_arb_change_vf_point and other related static
functions to clk_arb_gp106.c.

3) Instead of only checking if get_arbiter_clk_domain is empty, a
check for support_clk_freq_controller is also added. This is to enable
the clk_arbiter based on support from both the OS and the chips.

Bug 2061372

Change-Id: I65b0a4e02145a86fbbfb420ed591b1fa3c86f6dc
Signed-off-by: Debarshi Dutta 
Reviewed-on: https://git-master.nvidia.com/r/1774279
Reviewed-by: svc-misra-checker 
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade 
Reviewed-by: Vijayakumar Subbu 
Reviewed-by: mobile promotions 
Tested-by: mobile promotions

gpu: nvgpu: boardobj: Fix MISRA 15.6 violations

2018-08-28T13:47:36+00:00

MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces, introducing the braces.

JIRA NVGPU-671

Change-Id: I604d85367cd4b99c39df2b9fa2d7a7219ef941d5
Signed-off-by: Srirangan 
Reviewed-on: https://git-master.nvidia.com/r/1807153
Reviewed-by: svc-misra-checker 
Reviewed-by: Konsta Holtta 
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu 
Reviewed-by: mobile promotions 
Tested-by: mobile promotions

gpu: nvgpu: Fix MISRA 15.6 violations

2018-08-10T05:28:15+00:00

MISRA Rule-15.6 requires that all loop bodies must be enclosed in braces
including single statement loop bodies. This patch fix the MISRA
violations due to single statement loop bodies without braces by adding
them.

JIRA NVGPU-989

Change-Id: If79f56f92b94d0114477b66a6f654ac16ee8ea27
Signed-off-by: Srirangan 
Reviewed-on: https://git-master.nvidia.com/r/1791194
Reviewed-by: Adeel Raza 
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman 
Reviewed-by: mobile promotions 
Tested-by: mobile promotions

gpu: nvgpu: remove clk_arb.h to gk20a.h circular dependency

2018-08-09T03:14:16+00:00

clk_arb.h and gk20a.h has circular dependencies to each other. This is
removed by forward declaring struct gk20a in clk_arb.h and removing the
header gk20a.h from clk_arb.h and similarly forward declaring struct
nvgpu_clk_arb in gk20a.h and removing the header clk_arb.h from gk20a.h
alongwith putting headers in every execution unit which calls clk_arb.h
related methods.

JIRA NVGPU-597

Change-Id: I7cedca17206c148b21d93e5d7f0d88c2f98b979a
Signed-off-by: Debarshi Dutta 
Reviewed-on: https://git-master.nvidia.com/r/1790915
Reviewed-by: mobile promotions 
Tested-by: mobile promotions