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.*
*.ko
*.mod.c
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/*
 * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */
/*
 * Function naming determines intended use:
 *
 *     <x>_r(void) : Returns the offset for register <x>.
 *
 *     <x>_o(void) : Returns the offset for element <x>.
 *
 *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
 *
 *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
 *
 *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
 *         and masked to place it at field <y> of register <x>.  This value
 *         can be |'d with others to produce a full register value for
 *         register <x>.
 *
 *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
 *         value can be ~'d and then &'d to clear the value of field <y> for
 *         register <x>.
 *
 *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
 *         to place it at field <y> of register <x>.  This value can be |'d
 *         with others to produce a full register value for <x>.
 *
 *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
 *         <x> value 'r' after being shifted to place its LSB at bit 0.
 *         This value is suitable for direct comparison with other unshifted
 *         values appropriate for use in field <y> of register <x>.
 *
 *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
 *         field <y> of register <x>.  This value is suitable for direct
 *         comparison with unshifted values appropriate for use in field <y>
 *         of register <x>.
 */
#ifndef _hw_minion_gv100_h_
#define _hw_minion_gv100_h_

static inline u32 minion_minion_status_r(void)
{
	return 0x00000830U;
}
static inline u32 minion_minion_status_status_f(u32 v)
{
	return (v & 0xffU) << 0U;
}
static inline u32 minion_minion_status_status_m(void)
{
	return 0xffU << 0U;
}
static inline u32 minion_minion_status_status_v(u32 r)
{
	return (r >> 0U) & 0xffU;
}
static inline u32 minion_minion_status_status_boot_v(void)
{
	return 0x00000001U;
}
static inline u32 minion_minion_status_status_boot_f(void)
{
	return 0x1U;
}
static inline u32 minion_minion_status_intr_code_f(u32 v)
{
	return (v & 0xffffffU) << 8U;
}
static inline u32 minion_minion_status_intr_code_m(void)
{
	return 0xffffffU << 8U;
}
static inline u32 minion_minion_status_intr_code_v(u32 r)
{
	return (r >> 8U) & 0xffffffU;
}
static inline u32 minion_falcon_irqstat_r(void)
{
	return 0x00000008U;
}
static inline u32 minion_falcon_irqstat_halt_f(u32 v)
{
	return (v & 0x1U) << 4U;
}
static inline u32 minion_falcon_irqstat_halt_v(u32 r)
{
	return (r >> 4U) & 0x1U;
}
static inline u32 minion_falcon_irqstat_exterr_f(u32 v)
{
	return (v & 0x1U) << 5U;
}
static inline u32 minion_falcon_irqstat_exterr_v(u32 r)
{
	return (r >> 5U) & 0x1U;
}
static inline u32 minion_falcon_irqstat_exterr_true_v(void)
{
	return 0x00000001U;
}
static inline u32 minion_falcon_irqstat_exterr_true_f(void)
{
	return 0x20U;
}
static inline u32 minion_falcon_irqmask_r(void)
{
	return 0x00000018U;
}
static inline u32 minion_falcon_irqsclr_r(void)
{
	return 0x00000004U;
}
static inline u32 minion_falcon_irqsset_r(void)
{
	return 0x00000000U;
}
static inline u32 minion_falcon_irqmset_r(void)
{
	return 0x00000010U;
}
static inline u32 minion_falcon_irqmset_wdtmr_f(u32 v)
{
	return (v & 0x1U) << 1U;
}
static inline u32 minion_falcon_irqmset_wdtmr_m(void)
{
	return 0x1U << 1U;
}
static inline u32 minion_falcon_irqmset_wdtmr_v(u32 r)
{
	return (r >> 1U) & 0x1U;
}
static inline u32 minion_falcon_irqmset_wdtmr_set_v(void)
{
	return 0x00000001U;
}
static inline u32 minion_falcon_irqmset_wdtmr_set_f(void)
{
	return 0x2U;
}
static inline u32 minion_falcon_irqmset_halt_f(u32 v)
{
	return (v & 0x1U) << 4U;
}
static inline u32 minion_falcon_irqmset_halt_m(void)
{
	return 0x1U << 4U;
}
static inline u32 minion_falcon_irqmset_halt_v(u32 r)
{
	return (r >> 4U) & 0x1U;
}
static inline u32 minion_falcon_irqmset_halt_set_v(void)
{
	return 0x00000001U;
}
static inline u32 minion_falcon_irqmset_halt_set_f(void)
{
	return 0x10U;
}
static inline u32 minion_falcon_irqmset_exterr_f(u32 v)
{
	return (v & 0x1U) << 5U;
}
static inline u32 minion_falcon_irqmset_exterr_m(void)
{
	return 0x1U << 5U;
}
static inline u32 minion_falcon_irqmset_exterr_v(u32 r)
{
	return (r >> 5U) & 0x1U;
}
static inline u32 minion_falcon_irqmset_exterr_set_v(void)
{
	return 0x00000001U;
}
static inline u32 minion_falcon_irqmset_exterr_set_f(void)
{
	return 0x20U;
}
static inline u32 minion_falcon_irqmset_swgen0_f(u32 v)
{
	return (v & 0x1U) << 6U;
}
static inline u32 minion_falcon_irqmset_swgen0_m(void)
{
	return 0x1U << 6U;
}
static inline u32 minion_falcon_irqmset_swgen0_v(u32 r)
{
	return (r >> 6U) & 0x1U;
}
static inline u32 minion_falcon_irqmset_swgen0_set_v(void)
{
	return 0x00000001U;
}
static inline u32 minion_falcon_irqmset_swgen0_set_f(void)
{
	return 0x40U;
}
static inline u32 minion_falcon_irqmset_swgen1_f(u32 v)
{
	return (v & 0x1U) << 7U;
}
static inline u32 minion_falcon_irqmset_swgen1_m(void)
{
	return 0x1U << 7U;
}
static inline u32 minion_falcon_irqmset_swgen1_v(u32 r)
{
	return (r >> 7U) & 0x1U;
}
static inline u32 minion_falcon_irqmset_swgen1_set_v(void)
{
	return 0x00000001U;
}
static inline u32 minion_falcon_irqmset_swgen1_set_f(void)
{
	return 0x80U;
}
static inline u32 minion_falcon_irqdest_r(void)
{
	return 0x0000001cU;
}
static inline u32 minion_falcon_irqdest_host_wdtmr_f(u32 v)
{
	return (v & 0x1U) << 1U;
}
static inline u32 minion_falcon_irqdest_host_wdtmr_m(void)
{
	return 0x1U << 1U;
}
static inline u32 minion_falcon_irqdest_host_wdtmr_v(u32 r)
{
	return (r >> 1U) & 0x1U;
}
static inline u32 minion_falcon_irqdest_host_wdtmr_host_v(void)
{
	return 0x00000001U;
}
static inline u32 minion_falcon_irqdest_host_wdtmr_host_f(void)
{
	return 0x2U;
}
static inline u32 minion_falcon_irqdest_host_halt_f(u32 v)
{
	return (v & 0x1U) << 4U;
}
static inline u32 minion_falcon_irqdest_host_halt_m(void)
{
	return 0x1U << 4U;
}
static inline u32 minion_falcon_irqdest_host_halt_v(u32 r)
{
	return (r >> 4U) & 0x1U;
}
static inline u32 minion_falcon_irqdest_host_halt_host_v(void)
{
	return 0x00000001U;
}
static inline u32 minion_falcon_irqdest_host_halt_host_f(void)
{
	return 0x10U;
}
static inline u32 minion_falcon_irqdest_host_exterr_f(u32 v