/* * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #include #include #include #include "thrmdev.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" #include "gp106/bios_gp106.h" #include "ctrl/ctrltherm.h" static int _therm_device_pmudata_instget(struct gk20a *g, struct nv_pmu_boardobjgrp *pmuboardobjgrp, struct nv_pmu_boardobj **ppboardobjpmudata, u8 idx) { struct nv_pmu_therm_therm_device_boardobj_grp_set *pgrp_set = (struct nv_pmu_therm_therm_device_boardobj_grp_set *) pmuboardobjgrp; nvgpu_log_info(g, " "); /*check whether pmuboardobjgrp has a valid boardobj in index*/ if (((u32)BIT(idx) & pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) { return -EINVAL; } *ppboardobjpmudata = (struct nv_pmu_boardobj *) &pgrp_set->objects[idx].data; nvgpu_log_info(g, " Done"); return 0; } static int construct_therm_device(struct gk20a *g, struct boardobj **ppboardobj, u16 size, void *pargs) { return boardobj_construct_super(g, ppboardobj, size, pargs); } static int construct_therm_device_gpu(struct gk20a *g, struct boardobj **ppboardobj, u16 size, void *pargs) { return construct_therm_device(g, ppboardobj, size, pargs); } static int construct_therm_device_gpu_sci(struct gk20a *g, struct boardobj **ppboardobj, u16 size, void *pargs) { return construct_therm_device(g, ppboardobj, size, pargs); } static int therm_device_pmu_data_init_gpu_gpc_tsosc(struct gk20a *g, struct boardobj *pboard_obj, struct nv_pmu_boardobj *ppmudata) { int status = 0; struct therm_device_gpu_gpc_tsosc *pdev = NULL; struct nv_pmu_therm_therm_device_gpu_gpc_tsosc_boardobj_set *pset; status = boardobj_pmudatainit_super(g, pboard_obj, ppmudata); if (status != 0) { goto exit; } pdev = (struct therm_device_gpu_gpc_tsosc *)(void *)pboard_obj; pset = (struct nv_pmu_therm_therm_device_gpu_gpc_tsosc_boardobj_set *) (void*) ppmudata; pset->gpc_tsosc_idx = pdev->gpc_tsosc_idx; exit: return status; } static int construct_therm_device_gpu_tsosc(struct gk20a *g, struct boardobj **ppboardobj, u16 size, void *pargs) { struct therm_device_gpu_gpc_tsosc *pdev = NULL; struct therm_device_gpu_gpc_tsosc *ptmp_dev = (struct therm_device_gpu_gpc_tsosc *)pargs; int status = 0; status = construct_therm_device(g, ppboardobj, size, pargs); if (status != 0) { return status; } pdev = (struct therm_device_gpu_gpc_tsosc *)(void *)*ppboardobj; pdev->super.super.pmudatainit = therm_device_pmu_data_init_gpu_gpc_tsosc; pdev->gpc_tsosc_idx = ptmp_dev->gpc_tsosc_idx; return status; } static int therm_device_pmu_data_init_hbm2_site(struct gk20a *g, struct boardobj *pboard_obj, struct nv_pmu_boardobj *ppmudata) { int status = 0; struct therm_device_hbm2_site *pdev = NULL; struct nv_pmu_therm_therm_device_hbm2_site_boardobj_set *pset; status = boardobj_pmudatainit_super(g, pboard_obj, ppmudata); if (status != 0) { goto exit; } pdev = (struct therm_device_hbm2_site *)(void *)pboard_obj; pset = (struct nv_pmu_therm_therm_device_hbm2_site_boardobj_set *) (void *)ppmudata; pset->site_idx = pdev->site_idx; exit: return status; } static int construct_therm_device_hbm2_site(struct gk20a *g, struct boardobj **ppboardobj, u16 size, void *pargs) { struct therm_device_hbm2_site *pdev = NULL; struct therm_device_hbm2_site *ptmp_dev = (struct therm_device_hbm2_site *)pargs; int status = 0; status = construct_therm_device(g, ppboardobj, size, pargs); if (status != 0) { return status; } pdev = (struct therm_device_hbm2_site *)(void *)*ppboardobj; pdev->super.super.pmudatainit = therm_device_pmu_data_init_hbm2_site; pdev->site_idx = ptmp_dev->site_idx; return status; } static int construct_therm_device_hbm2_combined(struct gk20a *g, struct boardobj **ppboardobj, u16 size, void *pargs) { return construct_therm_device(g, ppboardobj, size, pargs); } static struct boardobj *therm_device_construct(struct gk20a *g, void *pargs) { struct boardobj *board_obj_ptr = NULL; int status = 0; switch (BOARDOBJ_GET_TYPE(pargs)) { case NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU: status = construct_therm_device_gpu(g, &board_obj_ptr, sizeof(struct therm_device), pargs); break; case NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU_GPC_SCI: status = construct_therm_device_gpu_sci(g, &board_obj_ptr, sizeof(struct therm_device_gpu_sci), pargs); break; case NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU_GPC_TSOSC: status = construct_therm_device_gpu_tsosc(g, &board_obj_ptr, sizeof(struct therm_device_gpu_gpc_tsosc), pargs); break; case NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_HBM2_SITE: status = construct_therm_device_hbm2_site(g, &board_obj_ptr, sizeof(struct therm_device_hbm2_site), pargs); break; case NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_HBM2_COMBINED: status = construct_therm_device_hbm2_combined(g, &board_obj_ptr, sizeof(struct therm_device_hbm2_combined), pargs); break; default: nvgpu_err(g, "unsupported therm_device class - 0x%x", BOARDOBJ_GET_TYPE(pargs)); break; } if(status) { board_obj_ptr = NULL; nvgpu_err(g, "could not allocate memory for therm_device"); if (board_obj_ptr != NULL) { nvgpu_kfree(g, board_obj_ptr); } } return board_obj_ptr; } static int devinit_get_therm_device_table(struct gk20a *g, struct therm_devices *pthermdeviceobjs) { int status = 0; u8 *therm_device_table_ptr = NULL; u8 *curr_therm_device_table_ptr = NULL; struct boardobj *boardobj; struct therm_device_1x_header therm_device_table_header = { 0 }; struct therm_device_1x_entry *therm_device_table_entry = NULL; u32 index; u32 obj_index = 0; u8 class_id = 0; union { struct boardobj boardobj; struct therm_device therm_device; struct therm_device_gpu_sci gpu_sci; struct therm_device_gpu_gpc_tsosc gpu_gpc_tsosc; struct therm_device_hbm2_site hbm2_site; struct therm_device_hbm2_combined hbm2_combined; } therm_device_data; nvgpu_log_info(g, " "); therm_device_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, g->bios.perf_token, THERMAL_DEVICE_TABLE); if (therm_device_table_ptr == NULL) { status = -EINVAL; goto done; } memcpy(&therm_device_table_header, therm_device_table_ptr, VBIOS_THERM_DEVICE_1X_HEADER_SIZE_04); if (therm_device_table_header.version != VBIOS_THERM_DEVICE_VERSION_1X) { status = -EINVAL; goto done; } if (therm_device_table_header.header_size < VBIOS_THERM_DEVICE_1X_HEADER_SIZE_04) { status = -EINVAL; goto done; } curr_therm_device_table_ptr = /* * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #ifndef NVGPU_FLCNIF_CMN_H #define NVGPU_FLCNIF_CMN_H #define PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED 0 struct falc_u64 { u32 lo; u32 hi; }; struct falc_dma_addr { u32 dma_base; /* * dma_base1 is 9-bit MSB for FB Base * address for the transfer in FB after * address using 49b FB address */ u16 dma_base1; u8 dma_offset; }; struct pmu_mem_v1 { u32 dma_base;