From 2c5337a24f7f2d02989dfb733c55d6d8c7e90493 Mon Sep 17 00:00:00 2001 From: Joshua Bakita Date: Sun, 29 Oct 2023 13:07:40 -0400 Subject: Update includes to L4T r32.7.4 and drop nvgpu/gk20a.h dependency Also add instructions for updating `include/`. These files are now only needed to build on Linux 4.9-based Tegra platforms. --- include/HOW_TO_REBUILD_THIS.md | 22 + include/clk/clk_arb.c | 4 +- include/gk20a/fifo_gk20a.c | 54 +- include/gk20a/fifo_gk20a.h | 7 +- include/gk20a/gk20a.c | 7 +- include/gk20a/gr_gk20a.c | 108 +- include/gk20a/gr_gk20a.h | 5 +- include/gk20a/hw_bus_gk20a.h | 171 -- include/gk20a/hw_ccsr_gk20a.h | 163 -- include/gk20a/hw_ce2_gk20a.h | 87 - include/gk20a/hw_ctxsw_prog_gk20a.h | 447 --- include/gk20a/hw_falcon_gk20a.h | 559 ---- include/gk20a/hw_fb_gk20a.h | 263 -- include/gk20a/hw_fifo_gk20a.h | 619 ----- include/gk20a/hw_flush_gk20a.h | 187 -- include/gk20a/hw_gmmu_gk20a.h | 283 -- include/gk20a/hw_gr_gk20a.h | 3807 -------------------------- include/gk20a/hw_ltc_gk20a.h | 455 --- include/gk20a/hw_mc_gk20a.h | 291 -- include/gk20a/hw_pbdma_gk20a.h | 575 ---- include/gk20a/hw_perf_gk20a.h | 211 -- include/gk20a/hw_pram_gk20a.h | 63 - include/gk20a/hw_pri_ringmaster_gk20a.h | 159 -- include/gk20a/hw_pri_ringstation_fbp_gk20a.h | 231 -- include/gk20a/hw_pri_ringstation_gpc_gk20a.h | 79 - include/gk20a/hw_pri_ringstation_sys_gk20a.h | 91 - include/gk20a/hw_proj_gk20a.h | 167 -- include/gk20a/hw_pwr_gk20a.h | 823 ------ include/gk20a/hw_ram_gk20a.h | 443 --- include/gk20a/hw_therm_gk20a.h | 367 --- include/gk20a/hw_timer_gk20a.h | 127 - include/gk20a/hw_top_gk20a.h | 211 -- include/gk20a/hw_trim_gk20a.h | 315 --- include/nvgpu/acr/nvgpu_acr.h | 6 +- include/nvgpu/bug.h | 20 +- include/nvgpu/enabled.h | 9 +- include/nvgpu/gk20a.h | 8 +- include/nvgpu/hw/gk20a/hw_gr_gk20a.h | 61 + include/nvgpu/hw/gm20b/hw_gr_gm20b.h | 14 +- include/nvgpu/hw/gp106/hw_gr_gp106.h | 4 + include/nvgpu/hw/gp10b/hw_gr_gp10b.h | 4 + include/nvgpu/hw/gv100/hw_gr_gv100.h | 4 + include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 4 + include/nvgpu/log.h | 3 +- include/nvgpu/nvgpu_err.h | 359 +++ include/nvgpu/nvlink.h | 2 +- include/nvgpu/pmu.h | 20 +- include/nvgpu/pmuif/gpmuif_pg.h | 14 +- include/nvgpu/tsg.h | 4 +- include/os/linux/debug.c | 4 +- include/os/linux/driver_common.c | 69 +- include/os/linux/ecc_linux.h | 49 + include/os/linux/ioctl_clk_arb.c | 17 +- include/os/linux/ioctl_ctrl.c | 122 +- include/os/linux/ioctl_tsg.c | 26 +- include/os/linux/module.c | 22 +- include/os/linux/os_linux.h | 7 +- include/os/linux/platform_gv11b_tegra.c | 4 +- include/os/linux/scale.c | 29 +- include/os/linux/sdl.c | 341 +++ include/os/linux/vm.c | 8 +- include/os/posix/nvgpu.c | 18 +- 62 files changed, 1301 insertions(+), 11352 deletions(-) create mode 100644 include/HOW_TO_REBUILD_THIS.md delete mode 100644 include/gk20a/hw_bus_gk20a.h delete mode 100644 include/gk20a/hw_ccsr_gk20a.h delete mode 100644 include/gk20a/hw_ce2_gk20a.h delete mode 100644 include/gk20a/hw_ctxsw_prog_gk20a.h delete mode 100644 include/gk20a/hw_falcon_gk20a.h delete mode 100644 include/gk20a/hw_fb_gk20a.h delete mode 100644 include/gk20a/hw_fifo_gk20a.h delete mode 100644 include/gk20a/hw_flush_gk20a.h delete mode 100644 include/gk20a/hw_gmmu_gk20a.h delete mode 100644 include/gk20a/hw_gr_gk20a.h delete mode 100644 include/gk20a/hw_ltc_gk20a.h delete mode 100644 include/gk20a/hw_mc_gk20a.h delete mode 100644 include/gk20a/hw_pbdma_gk20a.h delete mode 100644 include/gk20a/hw_perf_gk20a.h delete mode 100644 include/gk20a/hw_pram_gk20a.h delete mode 100644 include/gk20a/hw_pri_ringmaster_gk20a.h delete mode 100644 include/gk20a/hw_pri_ringstation_fbp_gk20a.h delete mode 100644 include/gk20a/hw_pri_ringstation_gpc_gk20a.h delete mode 100644 include/gk20a/hw_pri_ringstation_sys_gk20a.h delete mode 100644 include/gk20a/hw_proj_gk20a.h delete mode 100644 include/gk20a/hw_pwr_gk20a.h delete mode 100644 include/gk20a/hw_ram_gk20a.h delete mode 100644 include/gk20a/hw_therm_gk20a.h delete mode 100644 include/gk20a/hw_timer_gk20a.h delete mode 100644 include/gk20a/hw_top_gk20a.h delete mode 100644 include/gk20a/hw_trim_gk20a.h create mode 100644 include/nvgpu/nvgpu_err.h create mode 100644 include/os/linux/ecc_linux.h create mode 100644 include/os/linux/sdl.c (limited to 'include') diff --git a/include/HOW_TO_REBUILD_THIS.md b/include/HOW_TO_REBUILD_THIS.md new file mode 100644 index 0000000..dcb1084 --- /dev/null +++ b/include/HOW_TO_REBUILD_THIS.md @@ -0,0 +1,22 @@ +First the internal `include` and `os` directories: +``` +cp -r /playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/include/nvgpu/ +cp -r /playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/os include/ +``` + +Then every directory needed by either of those includes: +``` +cp -r /playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/os include/ +/playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/gk20a include/ +/playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/ctrl include/ +/playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/clk include/ +/playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/boardobj include/ +/playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/pmu_perf include/ +/playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/pstate include/ +/playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/volt include/ +/playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/lpwr include/ +/playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/pmgr include/ +/playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/therm include/ +``` + +Make sure to pull the same version of L4T that you're building on! The structure layout is highly dependant on the version. diff --git a/include/clk/clk_arb.c b/include/clk/clk_arb.c index 6cf005c..8e9fb41 100644 --- a/include/clk/clk_arb.c +++ b/include/clk/clk_arb.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -886,8 +886,8 @@ void nvgpu_clk_arb_free_session(struct nvgpu_ref *refcount) nvgpu_spinlock_acquire(&session->session_lock); nvgpu_list_for_each_entry_safe(dev, tmp, &session->targets, nvgpu_clk_dev, node) { - nvgpu_ref_put(&dev->refcount, nvgpu_clk_arb_free_fd); nvgpu_list_del(&dev->node); + nvgpu_ref_put(&dev->refcount, nvgpu_clk_arb_free_fd); } nvgpu_spinlock_release(&session->session_lock); diff --git a/include/gk20a/fifo_gk20a.c b/include/gk20a/fifo_gk20a.c index 4477f7c..77babc7 100644 --- a/include/gk20a/fifo_gk20a.c +++ b/include/gk20a/fifo_gk20a.c @@ -1,7 +1,7 @@ /* * GK20A Graphics FIFO (gr host) * - * Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -58,8 +58,6 @@ #include #include -#include - #define FECS_METHOD_WFI_RESTORE 0x80000 #define FECS_MAILBOX_0_ACK_RESTORE 0x4 @@ -1409,6 +1407,7 @@ static void gk20a_fifo_handle_chsw_fault(struct gk20a *g) intr = gk20a_readl(g, fifo_intr_chsw_error_r()); nvgpu_err(g, "chsw: %08x", intr); gk20a_fecs_dump_falcon_stats(g); + gk20a_gpccs_dump_falcon_stats(g); gk20a_writel(g, fifo_intr_chsw_error_r(), intr); } @@ -1604,6 +1603,7 @@ int gk20a_fifo_deferred_reset(struct gk20a *g, struct channel_gk20a *ch) engines = gk20a_fifo_engines_on_id(g, tsg->tsgid, true); } else { nvgpu_err(g, "chid: %d is not bound to tsg", ch->chid); + engines = g->fifo.deferred_fault_engines; } if (engines == 0U) { @@ -1724,6 +1724,7 @@ static bool gk20a_fifo_handle_mmu_fault_locked( if (ctxsw) { gk20a_fecs_dump_falcon_stats(g); + gk20a_gpccs_dump_falcon_stats(g); nvgpu_err(g, "gr_status_r : 0x%x", gk20a_readl(g, gr_status_r())); } @@ -2198,9 +2199,9 @@ int gk20a_fifo_tsg_unbind_channel_verify_status(struct channel_gk20a *ch) struct gk20a *g = ch->g; if (gk20a_fifo_channel_status_is_next(g, ch->chid)) { - nvgpu_err(g, "Channel %d to be removed from TSG %d has NEXT set!", + nvgpu_log_info(g, "Channel %d to be removed from TSG %d has NEXT set!", ch->chid, ch->tsgid); - return -EINVAL; + return -EAGAIN; } if (g->ops.fifo.tsg_verify_status_ctx_reload) { @@ -2983,7 +2984,7 @@ static u32 gk20a_fifo_get_preempt_timeout(struct gk20a *g) } int gk20a_fifo_is_preempt_pending(struct gk20a *g, u32 id, - unsigned int id_type) + unsigned int id_type, bool preempt_retries_left) { struct nvgpu_timeout timeout; u32 delay = GR_IDLE_CHECK_DEFAULT; @@ -3039,7 +3040,8 @@ void gk20a_fifo_preempt_timeout_rc(struct gk20a *g, struct channel_gk20a *ch) RC_TYPE_PREEMPT_TIMEOUT); } -int __locked_fifo_preempt(struct gk20a *g, u32 id, bool is_tsg) +int __locked_fifo_preempt(struct gk20a *g, u32 id, bool is_tsg, + bool preempt_retries_left) { int ret; unsigned int id_type; @@ -3051,8 +3053,17 @@ int __locked_fifo_preempt(struct gk20a *g, u32 id, bool is_tsg) id_type = is_tsg ? ID_TYPE_TSG : ID_TYPE_CHANNEL; - /* wait for preempt */ - ret = g->ops.fifo.is_preempt_pending(g, id, id_type); + /* + * Poll for preempt done. if stalling interrupts are pending + * while preempt is in progress we poll for stalling interrupts + * to finish based on return value from this function and + * retry preempt again. + * If HW is hung, on the last retry instance we try to identify + * the engines hung and set the runlist reset_eng_bitmask + * and mark preemption completion. + */ + ret = g->ops.fifo.is_preempt_pending(g, id, id_type, + preempt_retries_left); return ret; } @@ -3074,7 +3085,7 @@ int gk20a_fifo_preempt_channel(struct gk20a *g, struct channel_gk20a *ch) mutex_ret = nvgpu_pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); - ret = __locked_fifo_preempt(g, ch->chid, false); + ret = __locked_fifo_preempt(g, ch->chid, false, false); if (!mutex_ret) { nvgpu_pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); @@ -3114,7 +3125,7 @@ int gk20a_fifo_preempt_tsg(struct gk20a *g, struct tsg_gk20a *tsg) mutex_ret = nvgpu_pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); - ret = __locked_fifo_preempt(g, tsg->tsgid, true); + ret = __locked_fifo_preempt(g, tsg->tsgid, true, false); if (!mutex_ret) { nvgpu_pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); @@ -3584,36 +3595,17 @@ void gk20a_fifo_runlist_hw_submit(struct gk20a *g, u32 runlist_id, { struct fifo_runlist_info_gk20a *runlist = NULL; u64 runlist_iova; - u32 val_wrote; - struct nvgpu_os_linux *l; runlist = &g->fifo.runlist_info[runlist_id]; runlist_iova = nvgpu_mem_get_addr(g, &runlist->mem[buffer_index]); - if (count != 0) { - printk(KERN_INFO "Runlist base register: %0x\n", fifo_runlist_base_r()); - printk(KERN_INFO "Runlist KVA: %px\n", (void*)(runlist->mem[buffer_index].cpu_va)); - printk(KERN_INFO "Runlist PA: %px\n", (void*)virt_to_phys((runlist->mem[buffer_index].cpu_va))); - printk(KERN_INFO "Runlist dma_address: %px\n", (void*)(runlist->mem[buffer_index].priv.sgt->sgl->dma_address)); - printk(KERN_INFO "Runlist pages KVA: %px\n", (void*)(runlist->mem[buffer_index].priv.pages)); - printk(KERN_INFO "Runlist pages PA: %px\n", (void*)virt_to_phys(runlist->mem[buffer_index].priv.pages)); - printk(KERN_INFO "Runlist dma_address: %px\n", (void*)(runlist->mem[buffer_index].priv.sgt->sgl->dma_address)); - printk(KERN_INFO "Runlist page_to_phys %px + offset %px\n", (void*)(page_to_phys(sg_page(runlist->mem[buffer_index].priv.sgt->sgl))), (void*)(runlist->mem[buffer_index].priv.sgt->sgl->offset)); - printk(KERN_INFO "Runlist IOVA: %px\n", (void*)runlist_iova); - printk(KERN_INFO "Using struct gk20* %px\n", g); - printk(KERN_INFO "g->name: %s, g->power_on: %d, g->sw_ready: %d, g->is_virtual %d\n", g->name, g->power_on, g->sw_ready, g->is_virtual); - printk(KERN_INFO "COHERENT_SYSMEM? %d, iommuable? %d\n", nvgpu_is_enabled(g, NVGPU_USE_COHERENT_SYSMEM), nvgpu_iommuable(g)); - l = container_of(g, struct nvgpu_os_linux, g); - printk(KERN_INFO "l->regs %px\n", l->regs); gk20a_writel(g, fifo_runlist_base_r(), fifo_runlist_base_ptr_f(u64_lo32(runlist_iova >> 12)) | nvgpu_aperture_mask(g, &runlist->mem[buffer_index], fifo_runlist_base_target_sys_mem_ncoh_f(), fifo_runlist_base_target_sys_mem_coh_f(), fifo_runlist_base_target_vid_mem_f())); - val_wrote = nvgpu_readl(g, 0x2270); - printk(KERN_INFO "Wrote runlist base as %0llx\n", (u64)(val_wrote & 0x0fffffff) << 12); } gk20a_writel(g, fifo_runlist_r(), @@ -3806,7 +3798,7 @@ static int __locked_fifo_reschedule_preempt_next(struct channel_gk20a *ch, gk20a_readl(g, fifo_preempt_r())); #endif if (wait_preempt) { - g->ops.fifo.is_preempt_pending(g, preempt_id, preempt_type); + g->ops.fifo.is_preempt_pending(g, preempt_id, preempt_type, false); } #ifdef TRACEPOINTS_ENABLED trace_gk20a_reschedule_preempted_next(ch->chid); diff --git a/include/gk20a/fifo_gk20a.h b/include/gk20a/fifo_gk20a.h index 26365ca..078236d 100644 --- a/include/gk20a/fifo_gk20a.h +++ b/include/gk20a/fifo_gk20a.h @@ -1,7 +1,7 @@ /* * GK20A graphics fifo (gr host) * - * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -388,8 +388,9 @@ void gk20a_fifo_channel_unbind(struct channel_gk20a *ch_gk20a); u32 gk20a_fifo_intr_0_error_mask(struct gk20a *g); int gk20a_fifo_is_preempt_pending(struct gk20a *g, u32 id, - unsigned int id_type); -int __locked_fifo_preempt(struct gk20a *g, u32 id, bool is_tsg); + unsigned int id_type, bool preempt_retries_left); +int __locked_fifo_preempt(struct gk20a *g, u32 id, bool is_tsg, + bool preempt_retries_left); void gk20a_fifo_preempt_timeout_rc_tsg(struct gk20a *g, struct tsg_gk20a *tsg); void gk20a_fifo_preempt_timeout_rc(struct gk20a *g, struct channel_gk20a *ch); int gk20a_fifo_setup_ramfc(struct channel_gk20a *c, diff --git a/include/gk20a/gk20a.c b/include/gk20a/gk20a.c index c3068b7..1a11716 100644 --- a/include/gk20a/gk20a.c +++ b/include/gk20a/gk20a.c @@ -1,7 +1,7 @@ /* * GK20A Graphics * - * Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -39,6 +39,7 @@ #include #include #include +#include #include @@ -525,6 +526,10 @@ static void gk20a_free_cb(struct nvgpu_ref *refcount) struct gk20a *g = container_of(refcount, struct gk20a, refcount); +#ifdef CONFIG_NVGPU_SUPPORT_LINUX_ECC_ERROR_REPORTING + nvgpu_deinit_ecc_reporting(g); +#endif + nvgpu_log(g, gpu_dbg_shutdown, "Freeing GK20A struct!"); gk20a_ce_destroy(g); diff --git a/include/gk20a/gr_gk20a.c b/include/gk20a/gr_gk20a.c index 7bcf528..1eda853 100644 --- a/include/gk20a/gr_gk20a.c +++ b/include/gk20a/gr_gk20a.c @@ -1,7 +1,7 @@ /* * GK20A Graphics * - * Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -121,6 +121,83 @@ int gr_gk20a_get_ctx_id(struct gk20a *g, return 0; } +void gk20a_gpccs_dump_falcon_stats(struct gk20a *g) +{ + unsigned int i; + + nvgpu_err(g, "gr_gpc0_gpccs_falcon_irqstat : %d", + gk20a_readl(g, gr_gpc0_gpccs_falcon_irqstat_r())); + nvgpu_err(g, "gr_gpc0_gpccs_falcon_irqmode : %d", + gk20a_readl(g, gr_gpc0_gpccs_falcon_irqmode_r())); + nvgpu_err(g, "gr_gpc0_gpccs_falcon_irqmask : %d", + gk20a_readl(g, gr_gpc0_gpccs_falcon_irqmask_r())); + nvgpu_err(g, "gr_gpc0_gpccs_falcon_irqdest : %d", + gk20a_readl(g, gr_gpc0_gpccs_falcon_irqdest_r())); + nvgpu_err(g, "gr_gpc0_gpccs_falcon_debug1 : %d", + gk20a_readl(g, gr_gpc0_gpccs_falcon_debug1_r())); + nvgpu_err(g, "gr_gpc0_gpccs_falcon_debuginfo : %d", + gk20a_readl(g, gr_gpc0_gpccs_falcon_debuginfo_r())); + nvgpu_err(g, "gr_gpc0_gpccs_falcon_engctl : %d", + gk20a_readl(g, gr_gpc0_gpccs_falcon_engctl_r())); + nvgpu_err(g, "gr_gpc0_gpccs_falcon_curctx : %d", + gk20a_readl(g, gr_gpc0_gpccs_falcon_curctx_r())); + nvgpu_err(g, "gr_gpc0_gpccs_falcon_nxtctx : %d", + gk20a_readl(g, gr_gpc0_gpccs_falcon_nxtctx_r())); + nvgpu_err(g, "gr_gpc0_gpccs_ctxsw_status_1 : %d", + gk20a_readl(g, gr_gpc0_gpccs_ctxsw_status_1_r())); + + for (i = 0; i < g->ops.gr.gpc0_gpccs_ctxsw_mailbox_size(); i++) { + nvgpu_err(g, "gr_gpc0_gpccs_ctxsw_mailbox_r(%d) : 0x%x", + i, gk20a_readl(g, gr_gpc0_gpccs_ctxsw_mailbox_r(i))); + } + + + gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(), + gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() | + gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_IMB)); + nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_IMB : 0x%x", + gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r())); + + gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(), + gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() | + gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_DMB)); + nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_DMB : 0x%x", + gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r())); + + gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(), + gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() | + gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_CSW)); + nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_CSW : 0x%x", + gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r())); + + gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(), + gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() | + gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_CTX)); + nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_CTX : 0x%x", + gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r())); + + gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(), + gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() | + gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_EXCI)); + nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_EXCI : 0x%x", + gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r())); + + + for (i = 0; i < 4U; i++) { + gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(), + gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() | + gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_PC)); + nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_PC : 0x%x", + gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r())); + + gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(), + gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() | + gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_SP)); + nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_SP : 0x%x", + gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r())); + } +} + void gk20a_fecs_dump_falcon_stats(struct gk20a *g) { unsigned int i; @@ -527,6 +604,7 @@ int gr_gk20a_ctx_wait_ucode(struct gk20a *g, u32 mailbox_id, "timeout waiting on mailbox=%d value=0x%08x", mailbox_id, reg); gk20a_fecs_dump_falcon_stats(g); + gk20a_gpccs_dump_falcon_stats(g); gk20a_gr_debug_dump(g); return -1; } else if (check == WAIT_UCODE_ERROR) { @@ -534,6 +612,7 @@ int gr_gk20a_ctx_wait_ucode(struct gk20a *g, u32 mailbox_id, "ucode method failed on mailbox=%d value=0x%08x", mailbox_id, reg); gk20a_fecs_dump_falcon_stats(g); + gk20a_gpccs_dump_falcon_stats(g); return -1; } @@ -1583,6 +1662,10 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g, sw_ctx_load->l[i].value); } + if (g->ops.gr.disable_rd_coalesce) { + g->ops.gr.disable_rd_coalesce(g); + } + if (g->ops.gr.init_preemption_state) { g->ops.gr.init_preemption_state(g); } @@ -4625,16 +4708,16 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g) g->ops.fb.init_cbc(g, gr); } - if (g->ops.gr.disable_rd_coalesce) { - g->ops.gr.disable_rd_coalesce(g); - } - /* load ctx init */ for (i = 0; i < sw_ctx_load->count; i++) { gk20a_writel(g, sw_ctx_load->l[i].addr, sw_ctx_load->l[i].value); } + if (g->ops.gr.disable_rd_coalesce) { + g->ops.gr.disable_rd_coalesce(g); + } + err = gr_gk20a_wait_idle(g, gk20a_get_gr_idle_timeout(g), GR_IDLE_CHECK_DEFAULT); if (err != 0U) { @@ -5297,9 +5380,10 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch, } else if ((gr_fecs_intr & gr_fecs_host_int_status_watchdog_active_f()) != 0U) { /* currently, recovery is not initiated */ - nvgpu_err(g, "fecs watchdog triggered for channel %u, " - "cannot ctxsw anymore !!", chid); + nvgpu_err(g, "fecs watchdog triggered for channel %u", chid); gk20a_fecs_dump_falcon_stats(g); + gk20a_gpccs_dump_falcon_stats(g); + gk20a_gr_debug_dump(g); } else if ((gr_fecs_intr & gr_fecs_host_int_status_ctxsw_intr_f(CTXSW_INTR0)) != 0U) { u32 mailbox_value = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(6)); @@ -5321,8 +5405,9 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch, } else { nvgpu_err(g, "unhandled fecs error interrupt 0x%08x for channel %u", - gr_fecs_intr, ch->chid); + gr_fecs_intr, chid); gk20a_fecs_dump_falcon_stats(g); + gk20a_gpccs_dump_falcon_stats(g); } gk20a_writel(g, gr_fecs_host_int_clear_r(), gr_fecs_intr); @@ -8851,6 +8936,10 @@ int gr_gk20a_wait_for_pause(struct gk20a *g, struct nvgpu_warpstate *w_state) u32 gpc, tpc, sm, sm_id; u32 global_mask; + if (!g->ops.gr.get_sm_no_lock_down_hww_global_esr_mask || + !g->ops.gr.lock_down_sm || !g->ops.gr.bpt_reg_info) + return -EINVAL; + /* Wait for the SMs to reach full stop. This condition is: * 1) All SMs with valid warps must be in the trap handler (SM_IN_TRAP_MODE) * 2) All SMs in the trap handler must have equivalent VALID and PAUSED warp @@ -8908,6 +8997,9 @@ int gr_gk20a_clear_sm_errors(struct gk20a *g) u32 global_esr; u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC); + if (!g->ops.gr.get_sm_hww_global_esr || !g->ops.gr.clear_sm_hww) + return -EINVAL; + for (gpc = 0; gpc < gr->gpc_count; gpc++) { /* check if any tpc has an exception */ diff --git a/include/gk20a/gr_gk20a.h b/include/gk20a/gr_gk20a.h index 08b81e8..2cd6a4f 100644 --- a/include/gk20a/gr_gk20a.h +++ b/include/gk20a/gr_gk20a.h @@ -1,7 +1,7 @@ /* * GK20A Graphics Engine * - * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -438,6 +438,7 @@ struct gr_gk20a { }; void gk20a_fecs_dump_falcon_stats(struct gk20a *g); +void gk20a_gpccs_dump_falcon_stats(struct gk20a *g); /* contexts associated with a TSG */ struct nvgpu_gr_ctx { @@ -602,7 +603,7 @@ u32 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g); if (g->support_pmu) {\ err = nvgpu_pg_elpg_disable(g);\ if (err != 0) {\ - err = nvgpu_pg_elpg_enable(g); \ + (void)nvgpu_pg_elpg_enable(g); \ } \ } \ if (err == 0) { \ diff --git a/include/gk20a/hw_bus_gk20a.h b/include/gk20a/hw_bus_gk20a.h deleted file mode 100644 index d3bb9e9..0000000 --- a/include/gk20a/hw_bus_gk20a.h +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_bus_gk20a_h_ -#define _hw_bus_gk20a_h_ - -static inline u32 bus_bar0_window_r(void) -{ - return 0x00001700U; -} -static inline u32 bus_bar0_window_base_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 bus_bar0_window_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) -{ - return 0x2000000U; -} -static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) -{ - return 0x3000000U; -} -static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) -{ - return 0x00000010U; -} -static inline u32 bus_bar1_block_r(void) -{ - return 0x00001704U; -} -static inline u32 bus_bar1_block_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 bus_bar1_block_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar1_block_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 bus_bar1_block_mode_virtual_f(void) -{ - return 0x80000000U; -} -static inline u32 bus_bar2_block_r(void) -{ - return 0x00001714U; -} -static inline u32 bus_bar2_block_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 bus_bar2_block_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar2_block_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 bus_bar2_block_mode_virtual_f(void) -{ - return 0x80000000U; -} -static inline u32 bus_bar1_block_ptr_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 bus_bar2_block_ptr_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 bus_intr_0_r(void) -{ - return 0x00001100U; -} -static inline u32 bus_intr_0_pri_squash_m(void) -{ - return 0x1U << 1U; -} -static inline u32 bus_intr_0_pri_fecserr_m(void) -{ - return 0x1U << 2U; -} -static inline u32 bus_intr_0_pri_timeout_m(void) -{ - return 0x1U << 3U; -} -static inline u32 bus_intr_en_0_r(void) -{ - return 0x00001140U; -} -static inline u32 bus_intr_en_0_pri_squash_m(void) -{ - return 0x1U << 1U; -} -static inline u32 bus_intr_en_0_pri_fecserr_m(void) -{ - return 0x1U << 2U; -} -static inline u32 bus_intr_en_0_pri_timeout_m(void) -{ - return 0x1U << 3U; -} -#endif diff --git a/include/gk20a/hw_ccsr_gk20a.h b/include/gk20a/hw_ccsr_gk20a.h deleted file mode 100644 index 95151f6..0000000 --- a/include/gk20a/hw_ccsr_gk20a.h +++ /dev/null @@ -1,163 +0,0 @@ -/* - * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ccsr_gk20a_h_ -#define _hw_ccsr_gk20a_h_ - -static inline u32 ccsr_channel_inst_r(u32 i) -{ - return 0x00800000U + i*8U; -} -static inline u32 ccsr_channel_inst__size_1_v(void) -{ - return 0x00000080U; -} -static inline u32 ccsr_channel_inst_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 ccsr_channel_inst_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 ccsr_channel_inst_bind_false_f(void) -{ - return 0x0U; -} -static inline u32 ccsr_channel_inst_bind_true_f(void) -{ - return 0x80000000U; -} -static inline u32 ccsr_channel_r(u32 i) -{ - return 0x00800004U + i*8U; -} -static inline u32 ccsr_channel__size_1_v(void) -{ - return 0x00000080U; -} -static inline u32 ccsr_channel_enable_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ccsr_channel_enable_set_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 ccsr_channel_enable_set_true_f(void) -{ - return 0x400U; -} -static inline u32 ccsr_channel_enable_clr_true_f(void) -{ - return 0x800U; -} -static inline u32 ccsr_channel_runlist_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 ccsr_channel_status_v(u32 r) -{ - return (r >> 24U) & 0xfU; -} -static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) -{ - return 0x00000002U; -} -static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) -{ - return 0x00000004U; -} -static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) -{ - return 0x0000000aU; -} -static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) -{ - return 0x0000000bU; -} -static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) -{ - return 0x0000000cU; -} -static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) -{ - return 0x0000000dU; -} -static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) -{ - return 0x0000000eU; -} -static inline u32 ccsr_channel_next_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ccsr_channel_next_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_busy_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -#endif diff --git a/include/gk20a/hw_ce2_gk20a.h b/include/gk20a/hw_ce2_gk20a.h deleted file mode 100644 index 87481cd..0000000 --- a/include/gk20a/hw_ce2_gk20a.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ce2_gk20a_h_ -#define _hw_ce2_gk20a_h_ - -static inline u32 ce2_intr_status_r(void) -{ - return 0x00106908U; -} -static inline u32 ce2_intr_status_blockpipe_pending_f(void) -{ - return 0x1U; -} -static inline u32 ce2_intr_status_blockpipe_reset_f(void) -{ - return 0x1U; -} -static inline u32 ce2_intr_status_nonblockpipe_pending_f(void) -{ - return 0x2U; -} -static inline u32 ce2_intr_status_nonblockpipe_reset_f(void) -{ - return 0x2U; -} -static inline u32 ce2_intr_status_launcherr_pending_f(void) -{ - return 0x4U; -} -static inline u32 ce2_intr_status_launcherr_reset_f(void) -{ - return 0x4U; -} -#endif diff --git a/include/gk20a/hw_ctxsw_prog_gk20a.h b/include/gk20a/hw_ctxsw_prog_gk20a.h deleted file mode 100644 index 131fd12..0000000 --- a/include/gk20a/hw_ctxsw_prog_gk20a.h +++ /dev/null @@ -1,447 +0,0 @@ -/* - * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ctxsw_prog_gk20a_h_ -#define _hw_ctxsw_prog_gk20a_h_ - -static inline u32 ctxsw_prog_fecs_header_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) -{ - return 0x00000008U; -} -static inline u32 ctxsw_prog_main_image_patch_count_o(void) -{ - return 0x00000010U; -} -static inline u32 ctxsw_prog_main_image_context_id_o(void) -{ - return 0x000000f0U; -} -static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) -{ - return 0x00000014U; -} -static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) -{ - return 0x00000018U; -} -static inline u32 ctxsw_prog_main_image_zcull_o(void) -{ - return 0x0000001cU; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) -{ - return 0x00000001U; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) -{ - return 0x00000020U; -} -static inline u32 ctxsw_prog_main_image_pm_o(void) -{ - return 0x00000028U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_m(void) -{ - return 0x7U << 0U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_ctxsw_f(void) -{ - return 0x1U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) -{ - return 0x7U << 3U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) -{ - return 0x8U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) -{ - return 0x0000002cU; -} -static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) -{ - return 0x000000f4U; -} -static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) -{ - return 0x000000f8U; -} -static inline u32 ctxsw_prog_main_image_magic_value_o(void) -{ - return 0x000000fcU; -} -static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) -{ - return 0x600dc0deU; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_ppc_info_o(void) -{ - return 0x000000f4U; -} -static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) -{ - return 0x000000f8U; -} -static inline u32 ctxsw_prog_local_magic_value_o(void) -{ - return 0x000000fcU; -} -static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) -{ - return 0xad0becabU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) -{ - return 0x000000ecU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) -{ - return 0x00000005U; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_extended_num_smpc_quadrants_v(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) -{ - return 0x000000a0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) -{ - return 2U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) -{ - return 0x3U << 0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) -{ - return 0x2U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) -{ - return 0x000000a4U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) -{ - return 0x000000a8U; -} -static inline u32 ctxsw_prog_main_image_misc_options_o(void) -{ - return 0x0000003cU; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) -{ - return 0x1U << 3U; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_o(void) -{ - return 0x000000acU; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(void) -{ - return 0x000000b0U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m(void) -{ - return 0xfffffffU << 0U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_m(void) -{ - return 0x3U << 28U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_coherent_f(void) -{ - return 0x20000000U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_noncoherent_f(void) -{ - return 0x30000000U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(void) -{ - return 0x000000b4U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_record_timestamp_record_size_in_bytes_v(void) -{ - return 0x00000080U; -} -static inline u32 ctxsw_prog_record_timestamp_record_size_in_words_v(void) -{ - return 0x00000020U; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_o(void) -{ - return 0x00000000U; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_v_value_v(void) -{ - return 0x00000000U; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_o(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_v_value_v(void) -{ - return 0x600dbeefU; -} -static inline u32 ctxsw_prog_record_timestamp_context_id_o(void) -{ - return 0x00000008U; -} -static inline u32 ctxsw_prog_record_timestamp_context_ptr_o(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_record_timestamp_new_context_id_o(void) -{ - return 0x00000010U; -} -static inline u32 ctxsw_prog_record_timestamp_new_context_ptr_o(void) -{ - return 0x00000014U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_lo_o(void) -{ - return 0x00000018U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_o(void) -{ - return 0x0000001cU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_m(void) -{ - return 0xffU << 24U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_v(u32 r) -{ - return (r >> 24U) & 0xffU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v(void) -{ - return 0x00000001U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_f(void) -{ - return 0x1000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_f(void) -{ - return 0x2000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_v(void) -{ - return 0x0000000aU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_f(void) -{ - return 0xa000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_v(void) -{ - return 0x0000000bU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_f(void) -{ - return 0xb000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_v(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_f(void) -{ - return 0xc000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_v(void) -{ - return 0x0000000dU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_f(void) -{ - return 0xd000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_v(void) -{ - return 0x00000003U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_f(void) -{ - return 0x3000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_v(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_f(void) -{ - return 0x4000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_v(void) -{ - return 0x00000005U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_f(void) -{ - return 0x5000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v(void) -{ - return 0x000000ffU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f(void) -{ - return 0xff000000U; -} -#endif diff --git a/include/gk20a/hw_falcon_gk20a.h b/include/gk20a/hw_falcon_gk20a.h deleted file mode 100644 index 7b4d87b..0000000 --- a/include/gk20a/hw_falcon_gk20a.h +++ /dev/null @@ -1,559 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_falcon_gk20a_h_ -#define _hw_falcon_gk20a_h_ - -static inline u32 falcon_falcon_irqsset_r(void) -{ - return 0x00000000U; -} -static inline u32 falcon_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 falcon_falcon_irqsclr_r(void) -{ - return 0x00000004U; -} -static inline u32 falcon_falcon_irqstat_r(void) -{ - return 0x00000008U; -} -static inline u32 falcon_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 falcon_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 falcon_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 falcon_falcon_irqmode_r(void) -{ - return 0x0000000cU; -} -static inline u32 falcon_falcon_irqmset_r(void) -{ - return 0x00000010U; -} -static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqmclr_r(void) -{ - return 0x00000014U; -} -static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_irqmask_r(void) -{ - return 0x00000018U; -} -static inline u32 falcon_falcon_irqdest_r(void) -{ - return 0x0000001cU; -} -static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 falcon_falcon_curctx_r(void) -{ - return 0x00000050U; -} -static inline u32 falcon_falcon_nxtctx_r(void) -{ - return 0x00000054U; -} -static inline u32 falcon_falcon_mailbox0_r(void) -{ - return 0x00000040U; -} -static inline u32 falcon_falcon_mailbox1_r(void) -{ - return 0x00000044U; -} -static inline u32 falcon_falcon_itfen_r(void) -{ - return 0x00000048U; -} -static inline u32 falcon_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 falcon_falcon_idlestate_r(void) -{ - return 0x0000004cU; -} -static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 falcon_falcon_os_r(void) -{ - return 0x00000080U; -} -static inline u32 falcon_falcon_engctl_r(void) -{ - return 0x000000a4U; -} -static inline u32 falcon_falcon_cpuctl_r(void) -{ - return 0x00000100U; -} -static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_m(void) -{ - return 0x1U << 4U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 falcon_falcon_cpuctl_stopped_m(void) -{ - return 0x1U << 5U; -} -static inline u32 falcon_falcon_imemc_r(u32 i) -{ - return 0x00000180U + i*16U; -} -static inline u32 falcon_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 falcon_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 falcon_falcon_imemc_secure_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 falcon_falcon_imemd_r(u32 i) -{ - return 0x00000184U + i*16U; -} -static inline u32 falcon_falcon_imemt_r(u32 i) -{ - return 0x00000188U + i*16U; -} -static inline u32 falcon_falcon_bootvec_r(void) -{ - return 0x00000104U; -} -static inline u32 falcon_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 falcon_falcon_dmactl_r(void) -{ - return 0x0000010cU; -} -static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void) -{ - return 0x1U << 1U; -} -static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void) -{ - return 0x1U << 2U; -} -static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_hwcfg_r(void) -{ - return 0x00000108U; -} -static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 falcon_falcon_dmatrfbase_r(void) -{ - return 0x00000110U; -} -static inline u32 falcon_falcon_dmatrfmoffs_r(void) -{ - return 0x00000114U; -} -static inline u32 falcon_falcon_dmatrfcmd_r(void) -{ - return 0x00000118U; -} -static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 falcon_falcon_dmatrffboffs_r(void) -{ - return 0x0000011cU; -} -static inline u32 falcon_falcon_imstat_r(void) -{ - return 0x00000144U; -} -static inline u32 falcon_falcon_traceidx_r(void) -{ - return 0x00000148U; -} -static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 falcon_falcon_traceidx_idx_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 falcon_falcon_tracepc_r(void) -{ - return 0x0000014cU; -} -static inline u32 falcon_falcon_tracepc_pc_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 falcon_falcon_exterraddr_r(void) -{ - return 0x00000168U; -} -static inline u32 falcon_falcon_exterrstat_r(void) -{ - return 0x0000016cU; -} -static inline u32 falcon_falcon_exterrstat_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 falcon_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 falcon_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 falcon_falcon_icd_cmd_r(void) -{ - return 0x00000200U; -} -static inline u32 falcon_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 falcon_falcon_icd_cmd_opc_m(void) -{ - return 0xfU << 0U; -} -static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 falcon_falcon_icd_rdata_r(void) -{ - return 0x0000020cU; -} -static inline u32 falcon_falcon_dmemc_r(u32 i) -{ - return 0x000001c0U + i*8U; -} -static inline u32 falcon_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 falcon_falcon_dmemc_offs_m(void) -{ - return 0x3fU << 2U; -} -static inline u32 falcon_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_dmemc_blk_m(void) -{ - return 0xffU << 8U; -} -static inline u32 falcon_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 falcon_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 falcon_falcon_dmemd_