From 01e6fac4d61fdd7fff5433942ec93fc2ea1e4df1 Mon Sep 17 00:00:00 2001 From: Joshua Bakita Date: Wed, 28 Jun 2023 18:24:25 -0400 Subject: Include nvgpu headers These are needed to build on NVIDIA's Jetson boards for the time being. Only a couple structs are required, so it should be fairly easy to remove this dependency at some point in the future. --- include/therm/thrm.c | 55 +++++++ include/therm/thrm.h | 38 +++++ include/therm/thrmchannel.c | 256 ++++++++++++++++++++++++++++++ include/therm/thrmchannel.h | 51 ++++++ include/therm/thrmdev.c | 370 ++++++++++++++++++++++++++++++++++++++++++++ include/therm/thrmdev.h | 58 +++++++ include/therm/thrmpmu.c | 271 ++++++++++++++++++++++++++++++++ include/therm/thrmpmu.h | 31 ++++ 8 files changed, 1130 insertions(+) create mode 100644 include/therm/thrm.c create mode 100644 include/therm/thrm.h create mode 100644 include/therm/thrmchannel.c create mode 100644 include/therm/thrmchannel.h create mode 100644 include/therm/thrmdev.c create mode 100644 include/therm/thrmdev.h create mode 100644 include/therm/thrmpmu.c create mode 100644 include/therm/thrmpmu.h (limited to 'include/therm') diff --git a/include/therm/thrm.c b/include/therm/thrm.c new file mode 100644 index 0000000..c4e2731 --- /dev/null +++ b/include/therm/thrm.c @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include + +#include "thrm.h" +#include "thrmpmu.h" + +u32 therm_domain_sw_setup(struct gk20a *g) +{ + u32 status; + + status = therm_device_sw_setup(g); + if (status) { + nvgpu_err(g, + "error creating boardobjgrp for therm devices, status - 0x%x", + status); + goto exit; + } + + status = therm_channel_sw_setup(g); + if (status) { + nvgpu_err(g, + "error creating boardobjgrp for therm channel, status - 0x%x", + status); + goto exit; + } + +exit: + return status; +} + +u32 therm_domain_pmu_setup(struct gk20a *g) +{ + return therm_send_pmgr_tables_to_pmu(g); +} diff --git a/include/therm/thrm.h b/include/therm/thrm.h new file mode 100644 index 0000000..d9d73b7 --- /dev/null +++ b/include/therm/thrm.h @@ -0,0 +1,38 @@ +/* + * general thermal table structures & definitions + * + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_THERM_THRM_H +#define NVGPU_THERM_THRM_H + +#include "thrmdev.h" +#include "thrmchannel.h" + +struct therm_pmupstate { + struct therm_devices therm_deviceobjs; + struct therm_channels therm_channelobjs; +}; + +u32 therm_domain_sw_setup(struct gk20a *g); +u32 therm_domain_pmu_setup(struct gk20a *g); + +#endif /* NVGPU_THERM_THRM_H */ diff --git a/include/therm/thrmchannel.c b/include/therm/thrmchannel.c new file mode 100644 index 0000000..419ce0b --- /dev/null +++ b/include/therm/thrmchannel.c @@ -0,0 +1,256 @@ +/* + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include "thrmchannel.h" +#include "boardobj/boardobjgrp.h" +#include "boardobj/boardobjgrp_e32.h" +#include "gp106/bios_gp106.h" + +static int _therm_channel_pmudatainit_device(struct gk20a *g, + struct boardobj *board_obj_ptr, + struct nv_pmu_boardobj *ppmudata) +{ + int status = 0; + struct therm_channel *pchannel; + struct therm_channel_device *ptherm_channel; + struct nv_pmu_therm_therm_channel_device_boardobj_set *pset; + + status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); + if (status) { + nvgpu_err(g, + "error updating pmu boardobjgrp for therm channel 0x%x", + status); + status = -ENOMEM; + goto done; + } + + pchannel = (struct therm_channel *)board_obj_ptr; + pset = (struct nv_pmu_therm_therm_channel_device_boardobj_set *)ppmudata; + ptherm_channel = (struct therm_channel_device *)board_obj_ptr; + + pset->super.scaling = pchannel->scaling; + pset->super.offset = pchannel->offset; + pset->super.temp_min = pchannel->temp_min; + pset->super.temp_max = pchannel->temp_max; + + pset->therm_dev_idx = ptherm_channel->therm_dev_idx; + pset->therm_dev_prov_idx = ptherm_channel->therm_dev_prov_idx; + +done: + return status; +} +static struct boardobj *construct_channel_device(struct gk20a *g, + void *pargs, u16 pargs_size, u8 type) +{ + struct boardobj *board_obj_ptr = NULL; + struct therm_channel *pchannel; + struct therm_channel_device *pchannel_device; + int status; + struct therm_channel_device *therm_device = (struct therm_channel_device*)pargs; + + status = boardobj_construct_super(g, &board_obj_ptr, + pargs_size, pargs); + if (status) { + return NULL; + } + + /* Set Super class interfaces */ + board_obj_ptr->pmudatainit = _therm_channel_pmudatainit_device; + + pchannel = (struct therm_channel *)board_obj_ptr; + pchannel_device = (struct therm_channel_device *)board_obj_ptr; + + g->ops.therm.get_internal_sensor_limits(&pchannel->temp_max, + &pchannel->temp_min); + pchannel->scaling = (1 << 8); + pchannel->offset = 0; + + pchannel_device->therm_dev_idx = therm_device->therm_dev_idx; + pchannel_device->therm_dev_prov_idx = therm_device->therm_dev_prov_idx; + + nvgpu_log_info(g, " Done"); + + return board_obj_ptr; +} + +static int _therm_channel_pmudata_instget(struct gk20a *g, + struct nv_pmu_boardobjgrp *pmuboardobjgrp, + struct nv_pmu_boardobj **ppboardobjpmudata, + u8 idx) +{ + struct nv_pmu_therm_therm_channel_boardobj_grp_set *pgrp_set = + (struct nv_pmu_therm_therm_channel_boardobj_grp_set *) + pmuboardobjgrp; + + nvgpu_log_info(g, " "); + + /*check whether pmuboardobjgrp has a valid boardobj in index*/ + if (((u32)BIT(idx) & + pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) { + return -EINVAL; + } + + *ppboardobjpmudata = (struct nv_pmu_boardobj *) + &pgrp_set->objects[idx].data.board_obj; + + nvgpu_log_info(g, " Done"); + + return 0; +} + +static int devinit_get_therm_channel_table(struct gk20a *g, + struct therm_channels *pthermchannelobjs) +{ + int status = 0; + u8 *therm_channel_table_ptr = NULL; + u8 *curr_therm_channel_table_ptr = NULL; + struct boardobj *boardobj; + struct therm_channel_1x_header therm_channel_table_header = { 0 }; + struct therm_channel_1x_entry *therm_channel_table_entry = NULL; + u32 index; + u32 obj_index = 0; + u16 therm_channel_size = 0; + union { + struct boardobj boardobj; + struct therm_channel therm_channel; + struct therm_channel_device device; + } therm_channel_data; + + nvgpu_log_info(g, " "); + + therm_channel_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, + g->bios.perf_token, THERMAL_CHANNEL_TABLE); + if (therm_channel_table_ptr == NULL) { + status = -EINVAL; + goto done; + } + + memcpy(&therm_channel_table_header, therm_channel_table_ptr, + VBIOS_THERM_CHANNEL_1X_HEADER_SIZE_09); + + if (therm_channel_table_header.version != + VBIOS_THERM_CHANNEL_VERSION_1X) { + status = -EINVAL; + goto done; + } + + if (therm_channel_table_header.header_size < + VBIOS_THERM_CHANNEL_1X_HEADER_SIZE_09) { + status = -EINVAL; + goto done; + } + + curr_therm_channel_table_ptr = (therm_channel_table_ptr + + VBIOS_THERM_CHANNEL_1X_HEADER_SIZE_09); + + for (index = 0; index < therm_channel_table_header.num_table_entries; + index++) { + therm_channel_table_entry = (struct therm_channel_1x_entry *) + (curr_therm_channel_table_ptr + + (therm_channel_table_header.table_entry_size * index)); + + if (therm_channel_table_entry->class_id != + NV_VBIOS_THERM_CHANNEL_1X_ENTRY_CLASS_DEVICE) { + continue; + } + + therm_channel_data.device.therm_dev_idx = therm_channel_table_entry->param0; + therm_channel_data.device.therm_dev_prov_idx = therm_channel_table_entry->param1; + + therm_channel_size = sizeof(struct therm_channel_device); + therm_channel_data.boardobj.type = CTRL_THERMAL_THERM_CHANNEL_CLASS_DEVICE; + + boardobj = construct_channel_device(g, &therm_channel_data, + therm_channel_size, therm_channel_data.boardobj.type); + + if (!boardobj) { + nvgpu_err(g, + "unable to create thermal device for %d type %d", + index, therm_channel_data.boardobj.type); + status = -EINVAL; + goto done; + } + + status = boardobjgrp_objinsert(&pthermchannelobjs->super.super, + boardobj, obj_index); + + if (status) { + nvgpu_err(g, + "unable to insert thermal device boardobj for %d", index); + status = -EINVAL; + goto done; + } + + ++obj_index; + } + +done: + nvgpu_log_info(g, " done status %x", status); + return status; +} + +int therm_channel_sw_setup(struct gk20a *g) +{ + int status; + struct boardobjgrp *pboardobjgrp = NULL; + struct therm_channels *pthermchannelobjs; + + /* Construct the Super Class and override the Interfaces */ + status = boardobjgrpconstruct_e32(g, + &g->therm_pmu.therm_channelobjs.super); + if (status) { + nvgpu_err(g, + "error creating boardobjgrp for therm devices, status - 0x%x", + status); + goto done; + } + + pboardobjgrp = &g->therm_pmu.therm_channelobjs.super.super; + pthermchannelobjs = &(g->therm_pmu.therm_channelobjs); + + /* Override the Interfaces */ + pboardobjgrp->pmudatainstget = _therm_channel_pmudata_instget; + + status = devinit_get_therm_channel_table(g, pthermchannelobjs); + if (status) { + goto done; + } + + BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, THERM, THERM_CHANNEL); + + status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, + therm, THERM, therm_channel, THERM_CHANNEL); + if (status) { + nvgpu_err(g, + "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", + status); + goto done; + } + +done: + nvgpu_log_info(g, " done status %x", status); + return status; +} diff --git a/include/therm/thrmchannel.h b/include/therm/thrmchannel.h new file mode 100644 index 0000000..89be673 --- /dev/null +++ b/include/therm/thrmchannel.h @@ -0,0 +1,51 @@ +/* + * general thermal device structures & definitions + * + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_THERM_THRMCHANNEL_H +#define NVGPU_THERM_THRMCHANNEL_H + +#include "boardobj/boardobj.h" +#include "boardobj/boardobjgrp.h" +#include "ctrl/ctrltherm.h" + +struct therm_channel { + struct boardobj super; + s16 scaling; + s16 offset; + s32 temp_min; + s32 temp_max; +}; + +struct therm_channels { + struct boardobjgrp_e32 super; +}; + +struct therm_channel_device { + struct therm_channel super; + u8 therm_dev_idx; + u8 therm_dev_prov_idx; +}; + +int therm_channel_sw_setup(struct gk20a *g); + +#endif /* NVGPU_THERM_THRMCHANNEL_H */ diff --git a/include/therm/thrmdev.c b/include/therm/thrmdev.c new file mode 100644 index 0000000..63e1033 --- /dev/null +++ b/include/therm/thrmdev.c @@ -0,0 +1,370 @@ +/* + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include "thrmdev.h" +#include "boardobj/boardobjgrp.h" +#include "boardobj/boardobjgrp_e32.h" +#include "gp106/bios_gp106.h" +#include "ctrl/ctrltherm.h" + +static int _therm_device_pmudata_instget(struct gk20a *g, + struct nv_pmu_boardobjgrp *pmuboardobjgrp, + struct nv_pmu_boardobj **ppboardobjpmudata, + u8 idx) +{ + struct nv_pmu_therm_therm_device_boardobj_grp_set *pgrp_set = + (struct nv_pmu_therm_therm_device_boardobj_grp_set *) + pmuboardobjgrp; + + nvgpu_log_info(g, " "); + + /*check whether pmuboardobjgrp has a valid boardobj in index*/ + if (((u32)BIT(idx) & + pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) { + return -EINVAL; + } + + *ppboardobjpmudata = (struct nv_pmu_boardobj *) + &pgrp_set->objects[idx].data; + + nvgpu_log_info(g, " Done"); + + return 0; +} + +static int construct_therm_device(struct gk20a *g, + struct boardobj **ppboardobj, u16 size, void *pargs) +{ + return boardobj_construct_super(g, ppboardobj, size, pargs); +} + +static int construct_therm_device_gpu(struct gk20a *g, + struct boardobj **ppboardobj, u16 size, void *pargs) +{ + return construct_therm_device(g, ppboardobj, size, pargs); +} + +static int construct_therm_device_gpu_sci(struct gk20a *g, + struct boardobj **ppboardobj, u16 size, void *pargs) +{ + return construct_therm_device(g, ppboardobj, size, pargs); +} + + +static int therm_device_pmu_data_init_gpu_gpc_tsosc(struct gk20a *g, + struct boardobj *pboard_obj, struct nv_pmu_boardobj *ppmudata) +{ + int status = 0; + struct therm_device_gpu_gpc_tsosc *pdev = NULL; + struct nv_pmu_therm_therm_device_gpu_gpc_tsosc_boardobj_set *pset; + + status = boardobj_pmudatainit_super(g, pboard_obj, ppmudata); + if (status != 0) { + goto exit; + } + + pdev = (struct therm_device_gpu_gpc_tsosc *)(void *)pboard_obj; + pset = (struct nv_pmu_therm_therm_device_gpu_gpc_tsosc_boardobj_set *) + (void*) ppmudata; + + pset->gpc_tsosc_idx = pdev->gpc_tsosc_idx; + +exit: + return status; +} + +static int construct_therm_device_gpu_tsosc(struct gk20a *g, + struct boardobj **ppboardobj, u16 size, void *pargs) +{ + struct therm_device_gpu_gpc_tsosc *pdev = NULL; + struct therm_device_gpu_gpc_tsosc *ptmp_dev = + (struct therm_device_gpu_gpc_tsosc *)pargs; + int status = 0; + + status = construct_therm_device(g, ppboardobj, size, pargs); + if (status != 0) { + return status; + } + + pdev = (struct therm_device_gpu_gpc_tsosc *)(void *)*ppboardobj; + + pdev->super.super.pmudatainit = + therm_device_pmu_data_init_gpu_gpc_tsosc; + + pdev->gpc_tsosc_idx = ptmp_dev->gpc_tsosc_idx; + + return status; +} + +static int therm_device_pmu_data_init_hbm2_site(struct gk20a *g, + struct boardobj *pboard_obj, struct nv_pmu_boardobj *ppmudata) +{ + int status = 0; + struct therm_device_hbm2_site *pdev = NULL; + struct nv_pmu_therm_therm_device_hbm2_site_boardobj_set *pset; + + status = boardobj_pmudatainit_super(g, pboard_obj, ppmudata); + if (status != 0) { + goto exit; + } + + pdev = (struct therm_device_hbm2_site *)(void *)pboard_obj; + pset = (struct nv_pmu_therm_therm_device_hbm2_site_boardobj_set *) + (void *)ppmudata; + + pset->site_idx = pdev->site_idx; + +exit: + return status; +} + +static int construct_therm_device_hbm2_site(struct gk20a *g, + struct boardobj **ppboardobj, u16 size, void *pargs) +{ + struct therm_device_hbm2_site *pdev = NULL; + struct therm_device_hbm2_site *ptmp_dev = + (struct therm_device_hbm2_site *)pargs; + int status = 0; + + status = construct_therm_device(g, ppboardobj, size, pargs); + if (status != 0) { + return status; + } + + pdev = (struct therm_device_hbm2_site *)(void *)*ppboardobj; + + pdev->super.super.pmudatainit = + therm_device_pmu_data_init_hbm2_site; + + pdev->site_idx = ptmp_dev->site_idx; + + return status; +} + +static int construct_therm_device_hbm2_combined(struct gk20a *g, + struct boardobj **ppboardobj, u16 size, void *pargs) +{ + return construct_therm_device(g, ppboardobj, size, pargs); +} + + +static struct boardobj *therm_device_construct(struct gk20a *g, + void *pargs) +{ + struct boardobj *board_obj_ptr = NULL; + int status = 0; + + switch (BOARDOBJ_GET_TYPE(pargs)) { + case NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU: + status = construct_therm_device_gpu(g, &board_obj_ptr, + sizeof(struct therm_device), pargs); + break; + case NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU_GPC_SCI: + status = construct_therm_device_gpu_sci(g, &board_obj_ptr, + sizeof(struct therm_device_gpu_sci), pargs); + break; + case NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU_GPC_TSOSC: + status = construct_therm_device_gpu_tsosc(g, &board_obj_ptr, + sizeof(struct therm_device_gpu_gpc_tsosc), pargs); + break; + case NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_HBM2_SITE: + status = construct_therm_device_hbm2_site(g, &board_obj_ptr, + sizeof(struct therm_device_hbm2_site), pargs); + break; + case NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_HBM2_COMBINED: + status = construct_therm_device_hbm2_combined(g, &board_obj_ptr, + sizeof(struct therm_device_hbm2_combined), pargs); + break; + default: + nvgpu_err(g, + "unsupported therm_device class - 0x%x", + BOARDOBJ_GET_TYPE(pargs)); + break; + } + + if(status) { + board_obj_ptr = NULL; + nvgpu_err(g, + "could not allocate memory for therm_device"); + if (board_obj_ptr != NULL) { + nvgpu_kfree(g, board_obj_ptr); + } + } + + + return board_obj_ptr; +} + +static int devinit_get_therm_device_table(struct gk20a *g, + struct therm_devices *pthermdeviceobjs) +{ + int status = 0; + u8 *therm_device_table_ptr = NULL; + u8 *curr_therm_device_table_ptr = NULL; + struct boardobj *boardobj; + struct therm_device_1x_header therm_device_table_header = { 0 }; + struct therm_device_1x_entry *therm_device_table_entry = NULL; + u32 index; + u32 obj_index = 0; + u8 class_id = 0; + union { + struct boardobj boardobj; + struct therm_device therm_device; + struct therm_device_gpu_sci gpu_sci; + struct therm_device_gpu_gpc_tsosc gpu_gpc_tsosc; + struct therm_device_hbm2_site hbm2_site; + struct therm_device_hbm2_combined hbm2_combined; + } therm_device_data; + + nvgpu_log_info(g, " "); + + therm_device_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, + g->bios.perf_token, THERMAL_DEVICE_TABLE); + if (therm_device_table_ptr == NULL) { + status = -EINVAL; + goto done; + } + + memcpy(&therm_device_table_header, therm_device_table_ptr, + VBIOS_THERM_DEVICE_1X_HEADER_SIZE_04); + + if (therm_device_table_header.version != + VBIOS_THERM_DEVICE_VERSION_1X) { + status = -EINVAL; + goto done; + } + + if (therm_device_table_header.header_size < + VBIOS_THERM_DEVICE_1X_HEADER_SIZE_04) { + status = -EINVAL; + goto done; + } + + curr_therm_device_table_ptr = (therm_device_table_ptr + + VBIOS_THERM_DEVICE_1X_HEADER_SIZE_04); + + for (index = 0; index < therm_device_table_header.num_table_entries; + index++) { + therm_device_table_entry = (struct therm_device_1x_entry *) + (curr_therm_device_table_ptr + + (therm_device_table_header.table_entry_size * index)); + + class_id = therm_device_table_entry->class_id; + + switch (class_id) { + case NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_INVALID: + continue; + break; + case NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU: + case NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU_GPC_SCI: + break; + case NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU_GPC_TSOSC: + therm_device_data.gpu_gpc_tsosc.gpc_tsosc_idx = + therm_device_table_entry->param0; + break; + case NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_HBM2_SITE: + therm_device_data.hbm2_site.site_idx = + therm_device_table_entry->param0; + break; + case NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_HBM2_COMBINED: + break; + default: + nvgpu_err(g, + "Unknown thermal device class i - %x, class - %x", + index, class_id); + goto done; + } + + therm_device_data.boardobj.type = class_id; + boardobj = therm_device_construct(g, &therm_device_data); + if (!boardobj) { + nvgpu_err(g, + "unable to create thermal device for %d type %d", + index, therm_device_data.boardobj.type); + status = -EINVAL; + goto done; + } + + status = boardobjgrp_objinsert(&pthermdeviceobjs->super.super, + boardobj, obj_index); + + if (status) { + nvgpu_err(g, + "unable to insert thermal device boardobj for %d", index); + status = -EINVAL; + goto done; + } + + ++obj_index; + } + +done: + nvgpu_log_info(g, " done status %x", status); + return status; +} + +int therm_device_sw_setup(struct gk20a *g) +{ + int status; + struct boardobjgrp *pboardobjgrp = NULL; + struct therm_devices *pthermdeviceobjs; + + /* Construct the Super Class and override the Interfaces */ + status = boardobjgrpconstruct_e32(g, + &g->therm_pmu.therm_deviceobjs.super); + if (status) { + nvgpu_err(g, + "error creating boardobjgrp for therm devices, status - 0x%x", + status); + goto done; + } + + pboardobjgrp = &g->therm_pmu.therm_deviceobjs.super.super; + pthermdeviceobjs = &(g->therm_pmu.therm_deviceobjs); + + /* Override the Interfaces */ + pboardobjgrp->pmudatainstget = _therm_device_pmudata_instget; + + status = devinit_get_therm_device_table(g, pthermdeviceobjs); + if (status) { + goto done; + } + + BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, THERM, THERM_DEVICE); + + status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, + therm, THERM, therm_device, THERM_DEVICE); + if (status) { + nvgpu_err(g, + "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", + status); + goto done; + } + +done: + nvgpu_log_info(g, " done status %x", status); + return status; +} diff --git a/include/therm/thrmdev.h b/include/therm/thrmdev.h new file mode 100644 index 0000000..151e96f --- /dev/null +++ b/include/therm/thrmdev.h @@ -0,0 +1,58 @@ +/* + * general thermal device structures & definitions + * + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_THERM_THRMDEV_H +#define NVGPU_THERM_THRMDEV_H + +#include "boardobj/boardobj.h" +#include "boardobj/boardobjgrp.h" + +struct therm_devices { + struct boardobjgrp_e32 super; +}; + +struct therm_device { + struct boardobj super; +}; + +struct therm_device_gpu_sci { + struct therm_device super; +}; + +struct therm_device_gpu_gpc_tsosc { + struct therm_device super; + u8 gpc_tsosc_idx; +}; + +struct therm_device_hbm2_site { + struct therm_device super; + u8 site_idx; +}; + +struct therm_device_hbm2_combined { + struct therm_device super; +}; + +int therm_device_sw_setup(struct gk20a *g); + +#endif /* NVGPU_THERM_THRMDEV_H */ diff --git a/include/therm/thrmpmu.c b/include/therm/thrmpmu.c new file mode 100644 index 0000000..65587ab --- /dev/null +++ b/include/therm/thrmpmu.c @@ -0,0 +1,271 @@ +/* + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#include + +#include "boardobj/boardobjgrp.h" +#include "boardobj/boardobjgrp_e32.h" +#include "thrmpmu.h" +#include + +struct therm_pmucmdhandler_params { + struct nv_pmu_therm_rpc *prpccall; + u32 success; +}; + +static void therm_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg, + void *param, u32 handle, u32 status) +{ + struct therm_pmucmdhandler_params *phandlerparams = + (struct therm_pmucmdhandler_params *)param; + + if (msg->msg.therm.msg_type != NV_PMU_THERM_MSG_ID_RPC) { + nvgpu_err(g, "unknow msg %x", + msg->msg.pmgr.msg_type); + return; + } + + if (!phandlerparams->prpccall->b_supported) { + nvgpu_err(g, "RPC msg %x failed", + msg->msg.pmgr.msg_type); + } else { + phandlerparams->success = 1; + } +} + +int therm_send_pmgr_tables_to_pmu(struct gk20a *g) +{ + int status = 0; + struct boardobjgrp *pboardobjgrp = NULL; + + if (!BOARDOBJGRP_IS_EMPTY(&g->therm_pmu.therm_deviceobjs.super.super)) { + pboardobjgrp = &g->therm_pmu.therm_deviceobjs.super.super; + status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); + if (status) { + nvgpu_err(g, + "therm_send_pmgr_tables_to_pmu - therm_device failed %x", + status); + goto exit; + } + } + + if (!BOARDOBJGRP_IS_EMPTY( + &g->therm_pmu.therm_channelobjs.super.super)) { + pboardobjgrp = &g->therm_pmu.therm_channelobjs.super.super; + status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); + if (status) { + nvgpu_err(g, + "therm_send_pmgr_tables_to_pmu - therm_channel failed %x", + status); + goto exit; + } + } + +exit: + return status; +} + +static u32 therm_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd, + struct pmu_msg *msg, struct pmu_payload *payload, + u32 queue_id, pmu_callback callback, void* cb_param, + u32 *seq_desc, unsigned long timeout) +{ + u32 status; + struct therm_pmucmdhandler_params *handlerparams = NULL; + + status = nvgpu_pmu_cmd_post(g, cmd, msg, payload, + queue_id, + callback, + cb_param, + seq_desc, + timeout); + if (status) { + nvgpu_err(g, + "unable to post therm cmd for unit %x cmd id %x size %x", + cmd->hdr.unit_id, cmd->cmd.therm.cmd_type, cmd->hdr.size); + goto exit; + } + + if (cb_param) { + handlerparams = (struct therm_pmucmdhandler_params*)cb_param; + + pmu_wait_message_cond(&g->pmu, + gk20a_get_gr_idle_timeout(g), + &handlerparams->success, 1); + + if (handlerparams->success == 0) { + nvgpu_err(g, "could not process cmd"); + status = -ETIMEDOUT; + goto exit; + } + } + +exit: + return status; +} + +static u32 therm_set_warn_temp_limit(struct gk20a *g) +{ + u32 seqdesc = 0; + struct pmu_cmd cmd; + struct pmu_msg msg; + struct pmu_payload payload; + struct nv_pmu_therm_rpc rpccall; + struct therm_pmucmdhandler_params handlerparams; + + memset(&payload, 0, sizeof(struct pmu_payload)); + memset(&cmd, 0, sizeof(struct pmu_cmd)); + memset(&msg, 0, sizeof(struct pmu_msg)); + memset(&rpccall, 0, sizeof(struct nv_pmu_therm_rpc)); + memset(&handlerparams, 0, sizeof(struct therm_pmucmdhandler_params)); + + rpccall.function = NV_PMU_THERM_RPC_ID_SLCT_EVENT_TEMP_TH_SET; + rpccall.params.slct_event_temp_th_set.event_id = + NV_PMU_THERM_EVENT_THERMAL_1; + rpccall.params.slct_event_temp_th_set.temp_threshold = g->curr_warn_temp; + rpccall.b_supported = 0; + + cmd.hdr.unit_id = PMU_UNIT_THERM; + cmd.hdr.size = ((u32)sizeof(struct nv_pmu_therm_cmd_rpc) + + (u32)sizeof(struct pmu_hdr)); + cmd.cmd.therm.cmd_type = NV_PMU_THERM_CMD_ID_RPC; + + msg.hdr.size = sizeof(struct pmu_msg); + + payload.in.buf = (u8 *)&rpccall; + payload.in.size = (u32)sizeof(struct nv_pmu_therm_rpc); + payload.in.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED; + payload.in.offset = NV_PMU_THERM_CMD_RPC_ALLOC_OFFSET; + + payload.out.buf = (u8 *)&rpccall; + payload.out.size = (u32)sizeof(struct nv_pmu_therm_rpc); + payload.out.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED; + payload.out.offset = NV_PMU_CLK_MSG_RPC_ALLOC_OFFSET; + + /* Setup the handler params to communicate back results.*/ + handlerparams.success = 0; + handlerparams.prpccall = &rpccall; + + return therm_pmu_cmd_post(g, &cmd, NULL, &payload, + PMU_COMMAND_QUEUE_LPQ, + therm_pmucmdhandler, + (void *)&handlerparams, + &seqdesc, ~0); +} + +static u32 therm_enable_slct_notification_request(struct gk20a *g) +{ + u32 seqdesc = 0; + struct pmu_cmd cmd = { {0} }; + + cmd.hdr.unit_id = PMU_UNIT_THERM; + cmd.hdr.size = ((u32)sizeof(struct nv_pmu_therm_cmd_hw_slowdown_notification) + + (u32)sizeof(struct pmu_hdr)); + + cmd.cmd.therm.cmd_type = NV_PMU_THERM_CMD_ID_HW_SLOWDOWN_NOTIFICATION; + cmd.cmd.therm.hw_slct_notification.request = + NV_RM_PMU_THERM_HW_SLOWDOWN_NOTIFICATION_REQUEST_ENABLE; + + return therm_pmu_cmd_post(g, &cmd, NULL, NULL, + PMU_COMMAND_QUEUE_LPQ, + NULL, + NULL, + &seqdesc, ~0); +} + +static u32 therm_send_slct_configuration_to_pmu(struct gk20a *g) +{ + u32 seqdesc = 0; + struct pmu_cmd cmd; + struct pmu_msg msg; + struct pmu_payload payload; + struct nv_pmu_therm_rpc rpccall; + struct therm_pmucmdhandler_params handlerparams; + + memset(&payload, 0, sizeof(struct pmu_payload)); + memset(&cmd, 0, sizeof(struct pmu_cmd)); + memset(&msg, 0, sizeof(struct pmu_msg)); + memset(&rpccall, 0, sizeof(struct nv_pmu_therm_rpc)); + memset(&handlerparams, 0, sizeof(struct therm_pmucmdhandler_params)); + + rpccall.function = NV_PMU_THERM_RPC_ID_SLCT; + rpccall.params.slct.mask_enabled = + (1 << NV_PMU_THERM_EVENT_THERMAL_1); + rpccall.b_supported = 0; + + cmd.hdr.unit_id = PMU_UNIT_THERM; + cmd.hdr.size = ((u32)sizeof(struct nv_pmu_therm_cmd_rpc) + + (u32)sizeof(struct pmu_hdr)); + cmd.cmd.therm.cmd_type = NV_PMU_THERM_CMD_ID_RPC; + + msg.hdr.size = sizeof(struct pmu_msg); + + payload.in.buf = (u8 *)&rpccall; + payload.in.size = (u32)sizeof(struct nv_pmu_therm_rpc); + payload.in.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED; + payload.in.offset = NV_PMU_THERM_CMD_RPC_ALLOC_OFFSET; + + payload.out.buf = (u8 *)&rpccall; + payload.out.size = (u32)sizeof(struct nv_pmu_therm_rpc); + payload.out.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED; + payload.out.offset = NV_PMU_CLK_MSG_RPC_ALLOC_OFFSET; + + /* Setup the handler params to communicate back results.*/ + handlerparams.success = 0; + handlerparams.prpccall = &rpccall; + + return therm_pmu_cmd_post(g, &cmd, NULL, &payload, + PMU_COMMAND_QUEUE_LPQ, + therm_pmucmdhandler, + (void *)&handlerparams, + &seqdesc, ~0); +} + +u32 therm_configure_therm_alert(struct gk20a *g) +{ + u32 status; + + status = therm_enable_slct_notification_request(g); + if (status) { + nvgpu_err(g, + "therm_enable_slct_notification_request-failed %d", + status); + goto exit; + } + + status = therm_send_slct_configuration_to_pmu(g); + if (status) { + nvgpu_err(g, + "therm_send_slct_configuration_to_pmu-failed %d", + status); + goto exit; + } + + status = therm_set_warn_temp_limit(g); + if (status) { + nvgpu_err(g, + "therm_set_warn_temp_limit-failed %d", + status); + goto exit; + } +exit: + return status; +} diff --git a/include/therm/thrmpmu.h b/include/therm/thrmpmu.h new file mode 100644 index 0000000..42d5caa --- /dev/null +++ b/include/therm/thrmpmu.h @@ -0,0 +1,31 @@ +/* + * general thermal pmu control structures & definitions + * + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_THERM_THRMPMU_H +#define NVGPU_THERM_THRMPMU_H + +int therm_send_pmgr_tables_to_pmu(struct gk20a *g); + +u32 therm_configure_therm_alert(struct gk20a *g); + +#endif /* NVGPU_THERM_THRMPMU_H */ -- cgit v1.2.2