From 01e6fac4d61fdd7fff5433942ec93fc2ea1e4df1 Mon Sep 17 00:00:00 2001 From: Joshua Bakita Date: Wed, 28 Jun 2023 18:24:25 -0400 Subject: Include nvgpu headers These are needed to build on NVIDIA's Jetson boards for the time being. Only a couple structs are required, so it should be fairly easy to remove this dependency at some point in the future. --- include/os/linux/io.c | 130 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 130 insertions(+) create mode 100644 include/os/linux/io.c (limited to 'include/os/linux/io.c') diff --git a/include/os/linux/io.c b/include/os/linux/io.c new file mode 100644 index 0000000..3e84e88 --- /dev/null +++ b/include/os/linux/io.c @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include + +#include "os_linux.h" + +void nvgpu_writel(struct gk20a *g, u32 r, u32 v) +{ + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); + + if (unlikely(!l->regs)) { + __gk20a_warn_on_no_regs(); + nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v); + } else { + writel_relaxed(v, l->regs + r); + nvgpu_wmb(); + nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x", r, v); + } +} + +void nvgpu_writel_relaxed(struct gk20a *g, u32 r, u32 v) +{ + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); + + if (unlikely(!l->regs)) { + __gk20a_warn_on_no_regs(); + nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v); + } else { + writel_relaxed(v, l->regs + r); + } +} + +u32 nvgpu_readl(struct gk20a *g, u32 r) +{ + u32 v = __nvgpu_readl(g, r); + + if (v == 0xffffffff) + __nvgpu_check_gpu_state(g); + + return v; +} + +u32 __nvgpu_readl(struct gk20a *g, u32 r) +{ + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); + u32 v = 0xffffffff; + + if (unlikely(!l->regs)) { + __gk20a_warn_on_no_regs(); + nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v); + } else { + v = readl(l->regs + r); + nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x", r, v); + } + + return v; +} + +void nvgpu_writel_loop(struct gk20a *g, u32 r, u32 v) +{ + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); + + if (unlikely(!l->regs)) { + __gk20a_warn_on_no_regs(); + nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v); + } else { + nvgpu_wmb(); + do { + writel_relaxed(v, l->regs + r); + } while (readl(l->regs + r) != v); + nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x", r, v); + } +} + +void nvgpu_bar1_writel(struct gk20a *g, u32 b, u32 v) +{ + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); + + if (unlikely(!l->bar1)) { + __gk20a_warn_on_no_regs(); + nvgpu_log(g, gpu_dbg_reg, "b=0x%x v=0x%x (failed)", b, v); + } else { + nvgpu_wmb(); + writel_relaxed(v, l->bar1 + b); + nvgpu_log(g, gpu_dbg_reg, "b=0x%x v=0x%x", b, v); + } +} + +u32 nvgpu_bar1_readl(struct gk20a *g, u32 b) +{ + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); + u32 v = 0xffffffff; + + if (unlikely(!l->bar1)) { + __gk20a_warn_on_no_regs(); + nvgpu_log(g, gpu_dbg_reg, "b=0x%x v=0x%x (failed)", b, v); + } else { + v = readl(l->bar1 + b); + nvgpu_log(g, gpu_dbg_reg, "b=0x%x v=0x%x", b, v); + } + + return v; +} + +bool nvgpu_io_exists(struct gk20a *g) +{ + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); + + return l->regs != NULL; +} + +bool nvgpu_io_valid_reg(struct gk20a *g, u32 r) +{ + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); + + return r < resource_size(l->regs); +} -- cgit v1.2.2