From f347fde22f1297e4f022600d201780d5ead78114 Mon Sep 17 00:00:00 2001 From: Joshua Bakita Date: Wed, 25 Sep 2024 16:09:09 -0400 Subject: Delete no-longer-needed nvgpu headers The dependency on these was removed in commit 8340d234. --- include/nvgpu/acr/acr_flcnbl.h | 144 - include/nvgpu/acr/acr_lsfm.h | 328 -- include/nvgpu/acr/acr_objflcn.h | 91 - include/nvgpu/acr/acr_objlsfm.h | 97 - include/nvgpu/acr/nvgpu_acr.h | 192 - include/nvgpu/allocator.h | 331 -- include/nvgpu/as.h | 54 - include/nvgpu/atomic.h | 130 - include/nvgpu/barrier.h | 61 - include/nvgpu/bios.h | 1123 ---- include/nvgpu/bitops.h | 44 - include/nvgpu/bsearch.h | 31 - include/nvgpu/bug.h | 51 - include/nvgpu/channel.h | 478 -- include/nvgpu/channel_sync.h | 113 - include/nvgpu/circ_buf.h | 31 - include/nvgpu/clk.h | 42 - include/nvgpu/clk_arb.h | 378 -- include/nvgpu/comptags.h | 104 - include/nvgpu/cond.h | 106 - include/nvgpu/ctxsw_trace.h | 94 - include/nvgpu/debug.h | 63 - include/nvgpu/defaults.h | 33 - include/nvgpu/dma.h | 361 -- include/nvgpu/dt.h | 28 - include/nvgpu/ecc.h | 162 - include/nvgpu/enabled.h | 221 - include/nvgpu/errno.h | 41 - include/nvgpu/error_notifier.h | 49 - include/nvgpu/falcon.h | 335 -- include/nvgpu/fecs_trace.h | 60 - include/nvgpu/firmware.h | 74 - include/nvgpu/flcnif_cmn.h | 121 - include/nvgpu/fuse.h | 38 - include/nvgpu/gk20a.h | 1807 ------- include/nvgpu/gmmu.h | 369 -- include/nvgpu/hal_init.h | 33 - include/nvgpu/hashtable.h | 29 - include/nvgpu/hw/gk20a/hw_bus_gk20a.h | 171 - include/nvgpu/hw/gk20a/hw_ccsr_gk20a.h | 163 - include/nvgpu/hw/gk20a/hw_ce2_gk20a.h | 87 - include/nvgpu/hw/gk20a/hw_ctxsw_prog_gk20a.h | 447 -- include/nvgpu/hw/gk20a/hw_falcon_gk20a.h | 559 -- include/nvgpu/hw/gk20a/hw_fb_gk20a.h | 263 - include/nvgpu/hw/gk20a/hw_fifo_gk20a.h | 619 --- include/nvgpu/hw/gk20a/hw_flush_gk20a.h | 187 - include/nvgpu/hw/gk20a/hw_gmmu_gk20a.h | 283 - include/nvgpu/hw/gk20a/hw_gr_gk20a.h | 3868 ------------- include/nvgpu/hw/gk20a/hw_ltc_gk20a.h | 455 -- include/nvgpu/hw/gk20a/hw_mc_gk20a.h | 291 - include/nvgpu/hw/gk20a/hw_pbdma_gk20a.h | 575 -- include/nvgpu/hw/gk20a/hw_perf_gk20a.h | 211 - include/nvgpu/hw/gk20a/hw_pram_gk20a.h | 63 - include/nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h | 159 - .../nvgpu/hw/gk20a/hw_pri_ringstation_fbp_gk20a.h | 231 - .../nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h | 79 - .../nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h | 91 - include/nvgpu/hw/gk20a/hw_proj_gk20a.h | 167 - include/nvgpu/hw/gk20a/hw_pwr_gk20a.h | 827 --- include/nvgpu/hw/gk20a/hw_ram_gk20a.h | 443 -- include/nvgpu/hw/gk20a/hw_therm_gk20a.h | 367 -- include/nvgpu/hw/gk20a/hw_timer_gk20a.h | 127 - include/nvgpu/hw/gk20a/hw_top_gk20a.h | 211 - include/nvgpu/hw/gk20a/hw_trim_gk20a.h | 315 -- include/nvgpu/hw/gm20b/hw_bus_gm20b.h | 223 - include/nvgpu/hw/gm20b/hw_ccsr_gm20b.h | 163 - include/nvgpu/hw/gm20b/hw_ce2_gm20b.h | 87 - include/nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h | 475 -- include/nvgpu/hw/gm20b/hw_falcon_gm20b.h | 599 -- include/nvgpu/hw/gm20b/hw_fb_gm20b.h | 339 -- include/nvgpu/hw/gm20b/hw_fifo_gm20b.h | 571 -- include/nvgpu/hw/gm20b/hw_flush_gm20b.h | 187 - include/nvgpu/hw/gm20b/hw_fuse_gm20b.h | 147 - include/nvgpu/hw/gm20b/hw_gmmu_gm20b.h | 283 - include/nvgpu/hw/gm20b/hw_gr_gm20b.h | 3939 -------------- include/nvgpu/hw/gm20b/hw_ltc_gm20b.h | 527 -- include/nvgpu/hw/gm20b/hw_mc_gm20b.h | 287 - include/nvgpu/hw/gm20b/hw_pbdma_gm20b.h | 579 -- include/nvgpu/hw/gm20b/hw_perf_gm20b.h | 219 - include/nvgpu/hw/gm20b/hw_pram_gm20b.h | 63 - include/nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h | 167 - .../nvgpu/hw/gm20b/hw_pri_ringstation_gpc_gm20b.h | 79 - .../nvgpu/hw/gm20b/hw_pri_ringstation_sys_gm20b.h | 91 - include/nvgpu/hw/gm20b/hw_proj_gm20b.h | 171 - include/nvgpu/hw/gm20b/hw_pwr_gm20b.h | 879 --- include/nvgpu/hw/gm20b/hw_ram_gm20b.h | 459 -- include/nvgpu/hw/gm20b/hw_therm_gm20b.h | 355 -- include/nvgpu/hw/gm20b/hw_timer_gm20b.h | 127 - include/nvgpu/hw/gm20b/hw_top_gm20b.h | 235 - include/nvgpu/hw/gm20b/hw_trim_gm20b.h | 503 -- include/nvgpu/hw/gp106/hw_bus_gp106.h | 223 - include/nvgpu/hw/gp106/hw_ccsr_gp106.h | 163 - include/nvgpu/hw/gp106/hw_ce_gp106.h | 87 - include/nvgpu/hw/gp106/hw_ctxsw_prog_gp106.h | 295 - include/nvgpu/hw/gp106/hw_falcon_gp106.h | 603 --- include/nvgpu/hw/gp106/hw_fb_gp106.h | 563 -- include/nvgpu/hw/gp106/hw_fbpa_gp106.h | 67 - include/nvgpu/hw/gp106/hw_fifo_gp106.h | 695 --- include/nvgpu/hw/gp106/hw_flush_gp106.h | 187 - include/nvgpu/hw/gp106/hw_fuse_gp106.h | 275 - include/nvgpu/hw/gp106/hw_gc6_gp106.h | 62 - include/nvgpu/hw/gp106/hw_gmmu_gp106.h | 331 -- include/nvgpu/hw/gp106/hw_gr_gp106.h | 4167 -------------- include/nvgpu/hw/gp106/hw_ltc_gp106.h | 559 -- include/nvgpu/hw/gp106/hw_mc_gp106.h | 251 - include/nvgpu/hw/gp106/hw_pbdma_gp106.h | 535 -- include/nvgpu/hw/gp106/hw_perf_gp106.h | 219 - include/nvgpu/hw/gp106/hw_pram_gp106.h | 63 - include/nvgpu/hw/gp106/hw_pri_ringmaster_gp106.h | 151 - .../nvgpu/hw/gp106/hw_pri_ringstation_gpc_gp106.h | 79 - .../nvgpu/hw/gp106/hw_pri_ringstation_sys_gp106.h | 91 - include/nvgpu/hw/gp106/hw_proj_gp106.h | 179 - include/nvgpu/hw/gp106/hw_psec_gp106.h | 615 --- include/nvgpu/hw/gp106/hw_pwr_gp106.h | 895 --- include/nvgpu/hw/gp106/hw_ram_gp106.h | 507 -- include/nvgpu/hw/gp106/hw_therm_gp106.h | 183 - include/nvgpu/hw/gp106/hw_timer_gp106.h | 115 - include/nvgpu/hw/gp106/hw_top_gp106.h | 255 - include/nvgpu/hw/gp106/hw_trim_gp106.h | 195 - include/nvgpu/hw/gp106/hw_xp_gp106.h | 143 - include/nvgpu/hw/gp106/hw_xve_gp106.h | 207 - include/nvgpu/hw/gp10b/hw_bus_gp10b.h | 223 - include/nvgpu/hw/gp10b/hw_ccsr_gp10b.h | 163 - include/nvgpu/hw/gp10b/hw_ce_gp10b.h | 87 - include/nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h | 491 -- include/nvgpu/hw/gp10b/hw_falcon_gp10b.h | 603 --- include/nvgpu/hw/gp10b/hw_fb_gp10b.h | 463 -- include/nvgpu/hw/gp10b/hw_fifo_gp10b.h | 699 --- include/nvgpu/hw/gp10b/hw_flush_gp10b.h | 187 - include/nvgpu/hw/gp10b/hw_fuse_gp10b.h | 155 - include/nvgpu/hw/gp10b/hw_gmmu_gp10b.h | 331 -- include/nvgpu/hw/gp10b/hw_gr_gp10b.h | 4419 --------------- include/nvgpu/hw/gp10b/hw_ltc_gp10b.h | 587 -- include/nvgpu/hw/gp10b/hw_mc_gp10b.h | 255 - include/nvgpu/hw/gp10b/hw_pbdma_gp10b.h | 615 --- include/nvgpu/hw/gp10b/hw_perf_gp10b.h | 219 - include/nvgpu/hw/gp10b/hw_pram_gp10b.h | 63 - include/nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h | 167 - .../nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h | 87 - .../nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h | 99 - include/nvgpu/hw/gp10b/hw_proj_gp10b.h | 179 - include/nvgpu/hw/gp10b/hw_pwr_gp10b.h | 883 --- include/nvgpu/hw/gp10b/hw_ram_gp10b.h | 519 -- include/nvgpu/hw/gp10b/hw_therm_gp10b.h | 415 -- include/nvgpu/hw/gp10b/hw_timer_gp10b.h | 127 - include/nvgpu/hw/gp10b/hw_top_gp10b.h | 231 - include/nvgpu/hw/gv100/hw_bus_gv100.h | 227 - include/nvgpu/hw/gv100/hw_ccsr_gv100.h | 187 - include/nvgpu/hw/gv100/hw_ce_gv100.h | 107 - include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h | 459 -- include/nvgpu/hw/gv100/hw_falcon_gv100.h | 603 --- include/nvgpu/hw/gv100/hw_fb_gv100.h | 1923 ------- include/nvgpu/hw/gv100/hw_fifo_gv100.h | 531 -- include/nvgpu/hw/gv100/hw_flush_gv100.h | 187 - include/nvgpu/hw/gv100/hw_fuse_gv100.h | 147 - include/nvgpu/hw/gv100/hw_gmmu_gv100.h | 355 -- include/nvgpu/hw/gv100/hw_gr_gv100.h | 4123 -------------- include/nvgpu/hw/gv100/hw_ioctrl_gv100.h | 331 -- include/nvgpu/hw/gv100/hw_ioctrlmif_gv100.h | 331 -- include/nvgpu/hw/gv100/hw_ltc_gv100.h | 631 --- include/nvgpu/hw/gv100/hw_mc_gv100.h | 259 - include/nvgpu/hw/gv100/hw_minion_gv100.h | 943 ---- include/nvgpu/hw/gv100/hw_nvl_gv100.h | 1571 ------ .../nvgpu/hw/gv100/hw_nvlinkip_discovery_gv100.h | 311 -- include/nvgpu/hw/gv100/hw_nvlipt_gv100.h | 279 - include/nvgpu/hw/gv100/hw_nvtlc_gv100.h | 95 - include/nvgpu/hw/gv100/hw_pbdma_gv100.h | 651 --- include/nvgpu/hw/gv100/hw_perf_gv100.h | 263 - include/nvgpu/hw/gv100/hw_pgsp_gv100.h | 643 --- include/nvgpu/hw/gv100/hw_pram_gv100.h | 63 - include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h | 167 - .../nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h | 79 - .../nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h | 91 - include/nvgpu/hw/gv100/hw_proj_gv100.h | 199 - include/nvgpu/hw/gv100/hw_pwr_gv100.h | 983 ---- include/nvgpu/hw/gv100/hw_ram_gv100.h | 791 --- include/nvgpu/hw/gv100/hw_therm_gv100.h | 299 - include/nvgpu/hw/gv100/hw_timer_gv100.h | 115 - include/nvgpu/hw/gv100/hw_top_gv100.h | 343 -- include/nvgpu/hw/gv100/hw_trim_gv100.h | 247 - include/nvgpu/hw/gv100/hw_usermode_gv100.h | 95 - include/nvgpu/hw/gv100/hw_xp_gv100.h | 143 - include/nvgpu/hw/gv100/hw_xve_gv100.h | 207 - include/nvgpu/hw/gv11b/hw_bus_gv11b.h | 223 - include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h | 187 - include/nvgpu/hw/gv11b/hw_ce_gv11b.h | 115 - include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h | 463 -- include/nvgpu/hw/gv11b/hw_falcon_gv11b.h | 603 --- include/nvgpu/hw/gv11b/hw_fb_gv11b.h | 1867 ------- include/nvgpu/hw/gv11b/hw_fifo_gv11b.h | 667 --- include/nvgpu/hw/gv11b/hw_flush_gv11b.h | 187 - include/nvgpu/hw/gv11b/hw_fuse_gv11b.h | 155 - include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h | 571 -- include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 5703 -------------------- include/nvgpu/hw/gv11b/hw_ltc_gv11b.h | 815 --- include/nvgpu/hw/gv11b/hw_mc_gv11b.h | 231 - include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h | 651 --- include/nvgpu/hw/gv11b/hw_perf_gv11b.h | 263 - include/nvgpu/hw/gv11b/hw_pram_gv11b.h | 63 - include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h | 167 - .../nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h | 79 - .../nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h | 91 - include/nvgpu/hw/gv11b/hw_proj_gv11b.h | 191 - include/nvgpu/hw/gv11b/hw_pwr_gv11b.h | 1219 ----- include/nvgpu/hw/gv11b/hw_ram_gv11b.h | 791 --- include/nvgpu/hw/gv11b/hw_therm_gv11b.h | 487 -- include/nvgpu/hw/gv11b/hw_timer_gv11b.h | 127 - include/nvgpu/hw/gv11b/hw_top_gv11b.h | 235 - include/nvgpu/hw/gv11b/hw_usermode_gv11b.h | 95 - include/nvgpu/hw_sim.h | 2153 -------- include/nvgpu/hw_sim_pci.h | 2169 -------- include/nvgpu/io.h | 49 - include/nvgpu/io_usermode.h | 27 - include/nvgpu/kmem.h | 285 - include/nvgpu/kref.h | 87 - include/nvgpu/linux/atomic.h | 149 - include/nvgpu/linux/barrier.h | 37 - include/nvgpu/linux/cond.h | 81 - include/nvgpu/linux/dma.h | 38 - include/nvgpu/linux/kmem.h | 47 - include/nvgpu/linux/lock.h | 81 - include/nvgpu/linux/nvgpu_mem.h | 89 - include/nvgpu/linux/nvlink.h | 31 - include/nvgpu/linux/os_fence_android.h | 48 - include/nvgpu/linux/rwsem.h | 26 - include/nvgpu/linux/sim.h | 38 - include/nvgpu/linux/sim_pci.h | 26 - include/nvgpu/linux/thread.h | 29 - include/nvgpu/linux/vm.h | 92 - include/nvgpu/list.h | 104 - include/nvgpu/lock.h | 75 - include/nvgpu/log.h | 184 - include/nvgpu/log2.h | 31 - include/nvgpu/ltc.h | 35 - include/nvgpu/mc.h | 35 - include/nvgpu/mm.h | 223 - include/nvgpu/nvgpu_common.h | 36 - include/nvgpu/nvgpu_err.h | 359 -- include/nvgpu/nvgpu_mem.h | 359 -- include/nvgpu/nvhost.h | 112 - include/nvgpu/nvlink.h | 237 - include/nvgpu/os_fence.h | 138 - include/nvgpu/os_sched.h | 51 - include/nvgpu/page_allocator.h | 185 - include/nvgpu/pci.h | 39 - include/nvgpu/pmu.h | 545 -- include/nvgpu/pmuif/gpmu_super_surf_if.h | 77 - include/nvgpu/pmuif/gpmuif_acr.h | 159 - include/nvgpu/pmuif/gpmuif_ap.h | 256 - include/nvgpu/pmuif/gpmuif_cmn.h | 142 - include/nvgpu/pmuif/gpmuif_perfmon.h | 241 - include/nvgpu/pmuif/gpmuif_pg.h | 424 -- include/nvgpu/pmuif/gpmuif_pg_rppg.h | 110 - include/nvgpu/pmuif/gpmuif_pmu.h | 193 - include/nvgpu/pmuif/gpmuifbios.h | 50 - include/nvgpu/pmuif/gpmuifboardobj.h | 234 - include/nvgpu/pmuif/gpmuifclk.h | 573 -- include/nvgpu/pmuif/gpmuifperf.h | 154 - include/nvgpu/pmuif/gpmuifperfvfe.h | 206 - include/nvgpu/pmuif/gpmuifpmgr.h | 443 -- include/nvgpu/pmuif/gpmuifseq.h | 82 - include/nvgpu/pmuif/gpmuiftherm.h | 102 - include/nvgpu/pmuif/gpmuifthermsensor.h | 105 - include/nvgpu/pmuif/gpmuifvolt.h | 402 -- include/nvgpu/pmuif/nvgpu_gpmu_cmdif.h | 143 - include/nvgpu/posix/atomic.h | 191 - include/nvgpu/posix/barrier.h | 44 - include/nvgpu/posix/bitops.h | 95 - include/nvgpu/posix/bug.h | 56 - include/nvgpu/posix/circ_buf.h | 44 - include/nvgpu/posix/cond.h | 59 - include/nvgpu/posix/io.h | 114 - include/nvgpu/posix/kmem.h | 36 - include/nvgpu/posix/lock.h | 69 - include/nvgpu/posix/log2.h | 37 - include/nvgpu/posix/nvgpu_mem.h | 32 - include/nvgpu/posix/nvlink.h | 24 - include/nvgpu/posix/pci.h | 28 - include/nvgpu/posix/probe.h | 31 - include/nvgpu/posix/rwsem.h | 35 - include/nvgpu/posix/sizes.h | 38 - include/nvgpu/posix/sort.h | 35 - include/nvgpu/posix/thread.h | 51 - include/nvgpu/posix/types.h | 221 - include/nvgpu/posix/vm.h | 41 - include/nvgpu/power_features/cg.h | 57 - include/nvgpu/power_features/pg.h | 36 - include/nvgpu/power_features/power_features.h | 34 - include/nvgpu/pramin.h | 39 - include/nvgpu/ptimer.h | 55 - include/nvgpu/rbtree.h | 130 - include/nvgpu/rwsem.h | 48 - include/nvgpu/sched.h | 42 - include/nvgpu/sec2.h | 97 - include/nvgpu/sec2if/sec2_cmd_if.h | 50 - include/nvgpu/sec2if/sec2_if_acr.h | 96 - include/nvgpu/sec2if/sec2_if_cmn.h | 73 - include/nvgpu/sec2if/sec2_if_sec2.h | 75 - include/nvgpu/semaphore.h | 206 - include/nvgpu/sim.h | 58 - include/nvgpu/sizes.h | 33 - include/nvgpu/soc.h | 37 - include/nvgpu/sort.h | 33 - include/nvgpu/therm.h | 29 - include/nvgpu/thread.h | 92 - include/nvgpu/timers.h | 116 - include/nvgpu/tsg.h | 132 - include/nvgpu/types.h | 71 - include/nvgpu/unit.h | 41 - include/nvgpu/utils.h | 58 - include/nvgpu/vgpu/tegra_vgpu.h | 817 --- include/nvgpu/vgpu/vgpu.h | 110 - include/nvgpu/vgpu/vgpu_ivc.h | 45 - include/nvgpu/vgpu/vgpu_ivm.h | 37 - include/nvgpu/vgpu/vm.h | 31 - include/nvgpu/vidmem.h | 148 - include/nvgpu/vm.h | 330 -- include/nvgpu/vm_area.h | 75 - include/nvgpu/vpr.h | 30 - include/nvgpu/xve.h | 68 - 320 files changed, 108448 deletions(-) delete mode 100644 include/nvgpu/acr/acr_flcnbl.h delete mode 100644 include/nvgpu/acr/acr_lsfm.h delete mode 100644 include/nvgpu/acr/acr_objflcn.h delete mode 100644 include/nvgpu/acr/acr_objlsfm.h delete mode 100644 include/nvgpu/acr/nvgpu_acr.h delete mode 100644 include/nvgpu/allocator.h delete mode 100644 include/nvgpu/as.h delete mode 100644 include/nvgpu/atomic.h delete mode 100644 include/nvgpu/barrier.h delete mode 100644 include/nvgpu/bios.h delete mode 100644 include/nvgpu/bitops.h delete mode 100644 include/nvgpu/bsearch.h delete mode 100644 include/nvgpu/bug.h delete mode 100644 include/nvgpu/channel.h delete mode 100644 include/nvgpu/channel_sync.h delete mode 100644 include/nvgpu/circ_buf.h delete mode 100644 include/nvgpu/clk.h delete mode 100644 include/nvgpu/clk_arb.h delete mode 100644 include/nvgpu/comptags.h delete mode 100644 include/nvgpu/cond.h delete mode 100644 include/nvgpu/ctxsw_trace.h delete mode 100644 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All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_ACR_FLCNBL_H -#define NVGPU_ACR_FLCNBL_H - -#include - -#ifndef NVGPU_ACR_H -#warning "acr_flcnbl.h not included from nvgpu_acr.h!" \ - "Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces" -#endif - -/* - * Structure used by the boot-loader to load the rest of the code. This has - * to be filled by NVGPU and copied into DMEM at offset provided in the - * hsflcn_bl_desc.bl_desc_dmem_load_off. - */ -struct flcn_bl_dmem_desc { - u32 reserved[4]; /*Should be the first element..*/ - u32 signature[4]; /*Should be the first element..*/ - u32 ctx_dma; - u32 code_dma_base; - u32 non_sec_code_off; - u32 non_sec_code_size; - u32 sec_code_off; - u32 sec_code_size; - u32 code_entry_point; - u32 data_dma_base; - u32 data_size; - u32 code_dma_base1; - u32 data_dma_base1; -}; - -struct flcn_bl_dmem_desc_v1 { - u32 reserved[4]; /*Should be the first element..*/ - u32 signature[4]; /*Should be the first element..*/ - u32 ctx_dma; - struct falc_u64 code_dma_base; - u32 non_sec_code_off; - u32 non_sec_code_size; - u32 sec_code_off; - u32 sec_code_size; - u32 code_entry_point; - struct falc_u64 data_dma_base; - u32 data_size; - u32 argc; - u32 argv; -}; - -/* - * The header used by NVGPU to figure out code and data sections of bootloader - * - * bl_code_off - Offset of code section in the image - * bl_code_size - Size of code section in the image - * bl_data_off - Offset of data section in the image - * bl_data_size - Size of data section in the image - */ -struct flcn_bl_img_hdr { - u32 bl_code_off; - u32 bl_code_size; - u32 bl_data_off; - u32 bl_data_size; -}; - -/* - * The descriptor used by NVGPU to figure out the requirements of bootloader - * - * bl_start_tag - Starting tag of bootloader - * bl_desc_dmem_load_off - Dmem offset where _def_rm_flcn_bl_dmem_desc - * to be loaded - * bl_img_hdr - Description of the image - */ -struct hsflcn_bl_desc { - u32 bl_start_tag; - u32 bl_desc_dmem_load_off; - struct flcn_bl_img_hdr bl_img_hdr; -}; - -/* - * Legacy structure used by the current PMU/DPU bootloader. - */ -struct loader_config { - u32 dma_idx; - u32 code_dma_base; /* upper 32-bits of 40-bit dma address */ - u32 code_size_total; - u32 code_size_to_load; - u32 code_entry_point; - u32 data_dma_base; /* upper 32-bits of 40-bit dma address */ - u32 data_size; /* initialized data of the application */ - u32 overlay_dma_base; /* upper 32-bits of the 40-bit dma address */ - u32 argc; - u32 argv; - u16 code_dma_base1; /* upper 7 bits of 47-bit dma address */ - u16 data_dma_base1; /* upper 7 bits of 47-bit dma address */ - u16 overlay_dma_base1; /* upper 7 bits of the 47-bit dma address */ -}; - -struct loader_config_v1 { - u32 reserved; - u32 dma_idx; - struct falc_u64 code_dma_base; - u32 code_size_total; - u32 code_size_to_load; - u32 code_entry_point; - struct falc_u64 data_dma_base; - u32 data_size; - struct falc_u64 overlay_dma_base; - u32 argc; - u32 argv; -}; - -/* - * Union of all supported structures used by bootloaders. - */ -union flcn_bl_generic_desc { - struct flcn_bl_dmem_desc bl_dmem_desc; - struct loader_config loader_cfg; -}; - -union flcn_bl_generic_desc_v1 { - struct flcn_bl_dmem_desc_v1 bl_dmem_desc_v1; - struct loader_config_v1 loader_cfg_v1; -}; - -#endif /* NVGPU_ACR_FLCNBL_H */ diff --git a/include/nvgpu/acr/acr_lsfm.h b/include/nvgpu/acr/acr_lsfm.h deleted file mode 100644 index ed58552..0000000 --- a/include/nvgpu/acr/acr_lsfm.h +++ /dev/null @@ -1,328 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_ACR_LSFM_H -#define NVGPU_ACR_LSFM_H - -#ifndef NVGPU_ACR_H -#warning "acr_lsfm.h not included from nvgpu_acr.h!" \ - "Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces" -#endif - -/* - * READ/WRITE masks for WPR region - */ -/* Readable only from level 2 and 3 client */ -#define LSF_WPR_REGION_RMASK (0xC) -/* Writable only from level 2 and 3 client */ -#define LSF_WPR_REGION_WMASK (0xC) -/* Readable only from level 3 client */ -#define LSF_WPR_REGION_RMASK_SUB_WPR_ENABLED (0x8) -/* Writable only from level 3 client */ -#define LSF_WPR_REGION_WMASK_SUB_WPR_ENABLED (0x8) -/* Disallow read mis-match for all clients */ -#define LSF_WPR_REGION_ALLOW_READ_MISMATCH_NO (0x0) -/* Disallow write mis-match for all clients */ -#define LSF_WPR_REGION_ALLOW_WRITE_MISMATCH_NO (0x0) - -/* - * Falcon Id Defines - * Defines a common Light Secure Falcon identifier. - */ -#define LSF_FALCON_ID_PMU (0) -#define LSF_FALCON_ID_GSPLITE (1) -#define LSF_FALCON_ID_FECS (2) -#define LSF_FALCON_ID_GPCCS (3) -#define LSF_FALCON_ID_SEC2 (7) -#define LSF_FALCON_ID_END (11) -#define LSF_FALCON_ID_INVALID (0xFFFFFFFF) - -/* - * Light Secure Falcon Ucode Description Defines - * This structure is prelim and may change as the ucode signing flow evolves. - */ -struct lsf_ucode_desc { - u8 prd_keys[2][16]; - u8 dbg_keys[2][16]; - u32 b_prd_present; - u32 b_dbg_present; - u32 falcon_id; -}; - -struct lsf_ucode_desc_v1 { - u8 prd_keys[2][16]; - u8 dbg_keys[2][16]; - u32 b_prd_present; - u32 b_dbg_present; - u32 falcon_id; - u32 bsupports_versioning; - u32 version; - u32 dep_map_count; - u8 dep_map[LSF_FALCON_ID_END * 2 * 4]; - u8 kdf[16]; -}; - -/* - * Light Secure WPR Header - * Defines state allowing Light Secure Falcon bootstrapping. - */ -struct lsf_wpr_header { - u32 falcon_id; - u32 lsb_offset; - u32 bootstrap_owner; - u32 lazy_bootstrap; - u32 status; -}; - -struct lsf_wpr_header_v1 { - u32 falcon_id; - u32 lsb_offset; - u32 bootstrap_owner; - u32 lazy_bootstrap; - u32 bin_version; - u32 status; -}; - - -/* - * LSF shared SubWpr Header - * - * use_case_id - Shared SubWpr use case ID (updated by nvgpu) - * start_addr - start address of subWpr (updated by nvgpu) - * size_4K - size of subWpr in 4K (updated by nvgpu) - */ -struct lsf_shared_sub_wpr_header { - u32 use_case_id; - u32 start_addr; - u32 size_4K; -}; - -/* shared sub_wpr use case IDs */ -enum { - LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_FRTS_VBIOS_TABLES = 1, - LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_PLAYREADY_SHARED_DATA = 2 -}; - -#define LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX \ - LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_PLAYREADY_SHARED_DATA - -#define LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_INVALID (0xFFFFFFFF) - -#define MAX_SUPPORTED_SHARED_SUB_WPR_USE_CASES \ - LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX - -/* Static sizes of shared subWPRs */ -/* Minimum granularity supported is 4K */ -/* 1MB in 4K */ -#define LSF_SHARED_DATA_SUB_WPR_FRTS_VBIOS_TABLES_SIZE_IN_4K (0x100) -/* 4K */ -#define LSF_SHARED_DATA_SUB_WPR_PLAYREADY_SHARED_DATA_SIZE_IN_4K (0x1) - -/* - * Bootstrap Owner Defines - */ -#define LSF_BOOTSTRAP_OWNER_DEFAULT (LSF_FALCON_ID_PMU) - -/* - * Image Status Defines - */ -#define LSF_IMAGE_STATUS_NONE (0) -#define LSF_IMAGE_STATUS_COPY (1) -#define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED (2) -#define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED (3) -#define LSF_IMAGE_STATUS_VALIDATION_DONE (4) -#define LSF_IMAGE_STATUS_VALIDATION_SKIPPED (5) -#define LSF_IMAGE_STATUS_BOOTSTRAP_READY (6) - -/*Light Secure Bootstrap header related defines*/ -#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_FALSE 0 -#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_TRUE 1 -#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_FALSE 0 -#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_TRUE 4 -#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_TRUE 8 -#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_FALSE 0 - -/* - * Light Secure Bootstrap Header - * Defines state allowing Light Secure Falcon bootstrapping. - */ -struct lsf_lsb_header { - struct lsf_ucode_desc signature; - u32 ucode_off; - u32 ucode_size; - u32 data_size; - u32 bl_code_size; - u32 bl_imem_off; - u32 bl_data_off; - u32 bl_data_size; - u32 app_code_off; - u32 app_code_size; - u32 app_data_off; - u32 app_data_size; - u32 flags; -}; - -struct lsf_lsb_header_v1 { - struct lsf_ucode_desc_v1 signature; - u32 ucode_off; - u32 ucode_size; - u32 data_size; - u32 bl_code_size; - u32 bl_imem_off; - u32 bl_data_off; - u32 bl_data_size; - u32 app_code_off; - u32 app_code_size; - u32 app_data_off; - u32 app_data_size; - u32 flags; -}; - -/* - * Light Secure WPR Content Alignments - */ -#define LSF_WPR_HEADER_ALIGNMENT (256U) -#define LSF_SUB_WPR_HEADER_ALIGNMENT (256U) -#define LSF_LSB_HEADER_ALIGNMENT (256U) -#define LSF_BL_DATA_ALIGNMENT (256U) -#define LSF_BL_DATA_SIZE_ALIGNMENT (256U) -#define LSF_BL_CODE_SIZE_ALIGNMENT (256U) -#define LSF_DATA_SIZE_ALIGNMENT (256U) -#define LSF_CODE_SIZE_ALIGNMENT (256U) - -/* MMU excepts sub_wpr sizes in units of 4K */ -#define SUB_WPR_SIZE_ALIGNMENT (4096U) - -/* - * Maximum WPR Header size - */ -#define LSF_WPR_HEADERS_TOTAL_SIZE_MAX \ - (ALIGN_UP((sizeof(struct lsf_wpr_header_v1) * LSF_FALCON_ID_END), \ - LSF_WPR_HEADER_ALIGNMENT)) -#define LSF_LSB_HEADER_TOTAL_SIZE_MAX (\ - ALIGN_UP(sizeof(struct lsf_lsb_header_v1), LSF_LSB_HEADER_ALIGNMENT)) - -/* Maximum SUB WPR header size */ -#define LSF_SUB_WPR_HEADERS_TOTAL_SIZE_MAX (ALIGN_UP( \ - (sizeof(struct lsf_shared_sub_wpr_header) * \ - LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX), \ - LSF_SUB_WPR_HEADER_ALIGNMENT)) - - -#define LSF_UCODE_DATA_ALIGNMENT 4096 - -/* Defined for 1MB alignment */ -#define SHIFT_1MB (20) -#define SHIFT_4KB (12) - -/* - * Supporting maximum of 2 regions. - * This is needed to pre-allocate space in DMEM - */ -#define NVGPU_FLCN_ACR_MAX_REGIONS (2) -#define LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE (0x200) - -/* - * start_addr - Starting address of region - * end_addr - Ending address of region - * region_id - Region ID - * read_mask - Read Mask - * write_mask - WriteMask - * client_mask - Bit map of all clients currently using this region - */ -struct flcn_acr_region_prop { - u32 start_addr; - u32 end_addr; - u32 region_id; - u32 read_mask; - u32 write_mask; - u32 client_mask; -}; - -struct flcn_acr_region_prop_v1 { - u32 start_addr; - u32 end_addr; - u32 region_id; - u32 read_mask; - u32 write_mask; - u32 client_mask; - u32 shadowmMem_startaddress; -}; - -/* - * no_regions - Number of regions used. - * region_props - Region properties - */ -struct flcn_acr_regions { - u32 no_regions; - struct flcn_acr_region_prop region_props[NVGPU_FLCN_ACR_MAX_REGIONS]; -}; - -struct flcn_acr_regions_v1 { - u32 no_regions; - struct flcn_acr_region_prop_v1 region_props[NVGPU_FLCN_ACR_MAX_REGIONS]; -}; -/* - * reserved_dmem-When the bootstrap owner has done bootstrapping other falcons, - * and need to switch into LS mode, it needs to have its own - * actual DMEM image copied into DMEM as part of LS setup. If - * ACR desc is at location 0, it will definitely get overwritten - * causing data corruption. Hence we are reserving 0x200 bytes - * to give room for any loading data. NOTE: This has to be the - * first member always - * signature - Signature of ACR ucode. - * wpr_region_id - Region ID holding the WPR header and its details - * wpr_offset - Offset from the WPR region holding the wpr header - * regions - Region descriptors - * nonwpr_ucode_blob_start -stores non-WPR start where kernel stores ucode blob - * nonwpr_ucode_blob_end -stores non-WPR end where kernel stores ucode blob - */ -struct flcn_acr_desc { - union { - u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)]; - u32 signatures[4]; - } ucode_reserved_space; - /*Always 1st*/ - u32 wpr_region_id; - u32 wpr_offset; - u32 mmu_mem_range; - struct flcn_acr_regions regions; - u32 nonwpr_ucode_blob_size; - u64 nonwpr_ucode_blob_start; -}; - -struct flcn_acr_desc_v1 { - union { - u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)]; - } ucode_reserved_space; - u32 signatures[4]; - /*Always 1st*/ - u32 wpr_region_id; - u32 wpr_offset; - u32 mmu_mem_range; - struct flcn_acr_regions_v1 regions; - u32 nonwpr_ucode_blob_size; - u64 nonwpr_ucode_blob_start; - u32 dummy[4]; /* ACR_BSI_VPR_DESC */ -}; - - -#endif /* NVGPU_ACR_LSFM_H */ diff --git a/include/nvgpu/acr/acr_objflcn.h b/include/nvgpu/acr/acr_objflcn.h deleted file mode 100644 index 57b43c8..0000000 --- a/include/nvgpu/acr/acr_objflcn.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_ACR_OBJFLCN_H -#define NVGPU_ACR_OBJFLCN_H - -#ifndef NVGPU_ACR_H -#warning "acr_objflcn.h not included from nvgpu_acr.h!" \ - "Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces" -#endif - -struct flcn_ucode_img { - u32 *header; /* only some falcons have header */ - u32 *data; - struct pmu_ucode_desc *desc; /* only some falcons have descriptor */ - u32 data_size; - void *fw_ver; /* CTRL_GPU_GET_FIRMWARE_VERSION_PARAMS struct */ - u8 load_entire_os_data; /* load the whole osData section at boot time.*/ - /* NULL if not a light secure falcon.*/ - struct lsf_ucode_desc *lsf_desc; - /* True if there a resources to freed by the client. */ - u8 free_res_allocs; - u32 flcn_inst; -}; - -struct flcn_ucode_img_v1 { - u32 *header; - u32 *data; - struct pmu_ucode_desc_v1 *desc; - u32 data_size; - void *fw_ver; - u8 load_entire_os_data; - struct lsf_ucode_desc_v1 *lsf_desc; - u8 free_res_allocs; - u32 flcn_inst; -}; - -/* - * Falcon UCODE header index. - */ -#define FLCN_NL_UCODE_HDR_OS_CODE_OFF_IND (0) -#define FLCN_NL_UCODE_HDR_OS_CODE_SIZE_IND (1) -#define FLCN_NL_UCODE_HDR_OS_DATA_OFF_IND (2) -#define FLCN_NL_UCODE_HDR_OS_DATA_SIZE_IND (3) -#define FLCN_NL_UCODE_HDR_NUM_APPS_IND (4) - -/* - * There are total N number of Apps with code and offset defined in UCODE header - * This macro provides the CODE and DATA offset and size of Ath application. - */ -#define FLCN_NL_UCODE_HDR_APP_CODE_START_IND (5) -#define FLCN_NL_UCODE_HDR_APP_CODE_OFF_IND(N, A) \ - (FLCN_NL_UCODE_HDR_APP_CODE_START_IND + (A*2)) -#define FLCN_NL_UCODE_HDR_APP_CODE_SIZE_IND(N, A) \ - (FLCN_NL_UCODE_HDR_APP_CODE_START_IND + (A*2) + 1) -#define FLCN_NL_UCODE_HDR_APP_CODE_END_IND(N) \ - (FLCN_NL_UCODE_HDR_APP_CODE_START_IND + (N*2) - 1) - -#define FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) \ - (FLCN_NL_UCODE_HDR_APP_CODE_END_IND(N) + 1) -#define FLCN_NL_UCODE_HDR_APP_DATA_OFF_IND(N, A) \ - (FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + (A*2)) -#define FLCN_NL_UCODE_HDR_APP_DATA_SIZE_IND(N, A) \ - (FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + (A*2) + 1) -#define FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) \ - (FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + (N*2) - 1) - -#define FLCN_NL_UCODE_HDR_OS_OVL_OFF_IND(N) \ - (FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) + 1) -#define FLCN_NL_UCODE_HDR_OS_OVL_SIZE_IND(N) \ - (FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) + 2) - -#endif /* NVGPU_ACR_OBJFLCN_H */ diff --git a/include/nvgpu/acr/acr_objlsfm.h b/include/nvgpu/acr/acr_objlsfm.h deleted file mode 100644 index e3769bb..0000000 --- a/include/nvgpu/acr/acr_objlsfm.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_ACR_OBJLSFM_H -#define NVGPU_ACR_OBJLSFM_H - -#ifndef NVGPU_ACR_H -#warning "acr_objlsfm.h not included from nvgpu_acr.h!" \ - "Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces" -#endif - -#include "acr_flcnbl.h" -#include "acr_objflcn.h" - -/* - * LSFM Managed Ucode Image - * next : Next image the list, NULL if last. - * wpr_header : WPR header for this ucode image - * lsb_header : LSB header for this ucode image - * bl_gen_desc : Bootloader generic desc structure for this ucode image - * bl_gen_desc_size : Sizeof bootloader desc structure for this ucode image - * full_ucode_size : Surface size required for final ucode image - * ucode_img : Ucode image info - */ -struct lsfm_managed_ucode_img { - struct lsfm_managed_ucode_img *next; - struct lsf_wpr_header wpr_header; - struct lsf_lsb_header lsb_header; - union flcn_bl_generic_desc bl_gen_desc; - u32 bl_gen_desc_size; - u32 full_ucode_size; - struct flcn_ucode_img ucode_img; -}; - -struct lsfm_managed_ucode_img_v2 { - struct lsfm_managed_ucode_img_v2 *next; - struct lsf_wpr_header_v1 wpr_header; - struct lsf_lsb_header_v1 lsb_header; - union flcn_bl_generic_desc_v1 bl_gen_desc; - u32 bl_gen_desc_size; - u32 full_ucode_size; - struct flcn_ucode_img_v1 ucode_img; -}; - -/* - * Defines the structure used to contain all generic information related to - * the LSFM. - * Contains the Light Secure Falcon Manager (LSFM) feature related data. - */ -struct ls_flcn_mgr { - u16 managed_flcn_cnt; - u32 wpr_size; - u32 disable_mask; - struct lsfm_managed_ucode_img *ucode_img_list; - void *wpr_client_req_state;/*PACR_CLIENT_REQUEST_STATE originally*/ -}; - -/* - * LSFM SUB WPRs struct - * pnext : Next entry in the list, NULL if last - * sub_wpr_header : SubWpr Header struct - */ -struct lsfm_sub_wpr { - struct lsfm_sub_wpr *pnext; - struct lsf_shared_sub_wpr_header sub_wpr_header; -}; - -struct ls_flcn_mgr_v1 { - u16 managed_flcn_cnt; - u32 wpr_size; - u32 disable_mask; - struct lsfm_managed_ucode_img_v2 *ucode_img_list; - void *wpr_client_req_state;/*PACR_CLIENT_REQUEST_STATE originally*/ - u16 managed_sub_wpr_count; - struct lsfm_sub_wpr *psub_wpr_list; -}; - - -#endif /* NVGPU_ACR_OBJLSFM_H */ diff --git a/include/nvgpu/acr/nvgpu_acr.h b/include/nvgpu/acr/nvgpu_acr.h deleted file mode 100644 index cdb7bb8..0000000 --- a/include/nvgpu/acr/nvgpu_acr.h +++ /dev/null @@ -1,192 +0,0 @@ -/* - * Copyright (c) 2016-2021, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_ACR_H -#define NVGPU_ACR_H - -#include - -#include "gk20a/mm_gk20a.h" - -#include "acr_lsfm.h" -#include "acr_flcnbl.h" -#include "acr_objlsfm.h" -#include "acr_objflcn.h" - -struct nvgpu_firmware; -struct gk20a; -struct hs_acr_ops; -struct hs_acr; -struct nvgpu_acr; - -#define HSBIN_ACR_BL_UCODE_IMAGE "pmu_bl.bin" -#define GM20B_HSBIN_ACR_PROD_UCODE "nv_acr_ucode_prod.bin" -#define GM20B_HSBIN_ACR_DBG_UCODE "nv_acr_ucode_dbg.bin" -#define HSBIN_ACR_UCODE_IMAGE "acr_ucode.bin" -#define HSBIN_ACR_PROD_UCODE "acr_ucode_prod.bin" -#define HSBIN_ACR_DBG_UCODE "acr_ucode_dbg.bin" -#define HSBIN_ACR_AHESASC_PROD_UCODE "acr_ahesasc_prod_ucode.bin" -#define HSBIN_ACR_ASB_PROD_UCODE "acr_asb_prod_ucode.bin" -#define HSBIN_ACR_AHESASC_DBG_UCODE "acr_ahesasc_dbg_ucode.bin" -#define HSBIN_ACR_ASB_DBG_UCODE "acr_asb_dbg_ucode.bin" - -#define LSF_SEC2_UCODE_IMAGE_BIN "sec2_ucode_image.bin" -#define LSF_SEC2_UCODE_DESC_BIN "sec2_ucode_desc.bin" -#define LSF_SEC2_UCODE_SIG_BIN "sec2_sig.bin" - -#define MAX_SUPPORTED_LSFM 3 /*PMU, FECS, GPCCS*/ - -#define ACR_COMPLETION_TIMEOUT_MS 10000 /*in msec */ - -#define PMU_SECURE_MODE (0x1) -#define PMU_LSFM_MANAGED (0x2) - -struct bin_hdr { - /* 0x10de */ - u32 bin_magic; - /* versioning of bin format */ - u32 bin_ver; - /* Entire image size including this header */ - u32 bin_size; - /* - * Header offset of executable binary metadata, - * start @ offset- 0x100 * - */ - u32 header_offset; - /* - * Start of executable binary data, start @ - * offset- 0x200 - */ - u32 data_offset; - /* Size of executable binary */ - u32 data_size; -}; - -struct acr_fw_header { - u32 sig_dbg_offset; - u32 sig_dbg_size; - u32 sig_prod_offset; - u32 sig_prod_size; - u32 patch_loc; - u32 patch_sig; - u32 hdr_offset; /* This header points to acr_ucode_header_t210_load */ - u32 hdr_size; /* Size of above header */ -}; - -struct wpr_carveout_info { - u64 wpr_base; - u64 nonwpr_base; - u64 size; -}; - -/* ACR interfaces */ - -struct hs_flcn_bl { - char *bl_fw_name; - struct nvgpu_firmware *hs_bl_fw; - struct hsflcn_bl_desc *hs_bl_desc; - struct bin_hdr *hs_bl_bin_hdr; - struct nvgpu_mem hs_bl_ucode; -}; - -struct hs_acr { - u32 acr_type; - - /* HS bootloader to validate & load ACR ucode */ - struct hs_flcn_bl acr_hs_bl; - - /* ACR ucode */ - char *acr_fw_name; - struct nvgpu_firmware *acr_fw; - struct nvgpu_mem acr_ucode; - - union { - struct flcn_bl_dmem_desc bl_dmem_desc; - struct flcn_bl_dmem_desc_v1 bl_dmem_desc_v1; - }; - - void *ptr_bl_dmem_desc; - u32 bl_dmem_desc_size; - - union{ - struct flcn_acr_desc *acr_dmem_desc; - struct flcn_acr_desc_v1 *acr_dmem_desc_v1; - }; - - /* Falcon used to execute ACR ucode */ - struct nvgpu_falcon *acr_flcn; - - int (*acr_flcn_setup_hw_and_bl_bootstrap)(struct gk20a *g, - struct hs_acr *acr_desc, - struct nvgpu_falcon_bl_info *bl_info); -}; - -#define ACR_DEFAULT 0U -#define ACR_AHESASC 1U -#define ACR_ASB 2U - -struct nvgpu_acr { - struct gk20a *g; - - u32 bootstrap_owner; - u32 max_supported_lsfm; - u32 capabilities; - - /* - * non-wpr space to hold LSF ucodes, - * ACR does copy ucode from non-wpr to wpr - */ - struct nvgpu_mem ucode_blob; - /* - * Even though this mem_desc wouldn't be used, - * the wpr region needs to be reserved in the - * allocator in dGPU case. - */ - struct nvgpu_mem wpr_dummy; - - /* ACR member for different types of ucode */ - /* For older dgpu/tegra ACR cuode */ - struct hs_acr acr; - /* ACR load split feature support */ - struct hs_acr acr_ahesasc; - struct hs_acr acr_asb; - - u32 pmu_args; - struct nvgpu_firmware *pmu_fw; - struct nvgpu_firmware *pmu_desc; - - int (*prepare_ucode_blob)(struct gk20a *g, struct nvgpu_acr *acr); - void (*get_wpr_info)(struct gk20a *g, struct wpr_carveout_info *inf); - int (*alloc_blob_space)(struct gk20a *g, size_t size, - struct nvgpu_mem *mem); - int (*patch_wpr_info_to_ucode)(struct gk20a *g, struct nvgpu_acr *acr, - struct hs_acr *acr_desc, bool is_recovery); - int (*acr_fill_bl_dmem_desc)(struct gk20a *g, - struct nvgpu_acr *acr, struct hs_acr *acr_desc, - u32 *acr_ucode_header); - int (*bootstrap_hs_acr)(struct gk20a *g, struct nvgpu_acr *acr, - struct hs_acr *acr_desc); - - void (*remove_support)(struct nvgpu_acr *acr); -}; -#endif /* NVGPU_ACR_H */ - diff --git a/include/nvgpu/allocator.h b/include/nvgpu/allocator.h deleted file mode 100644 index c444543..0000000 --- a/include/nvgpu/allocator.h +++ /dev/null @@ -1,331 +0,0 @@ -/* - * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_ALLOCATOR_H -#define NVGPU_ALLOCATOR_H - -#ifdef __KERNEL__ -/* - * The Linux kernel has this notion of seq_files for printing info to userspace. - * One of the allocator function pointers takes advantage of this and allows the - * debug output to be directed either to nvgpu_log() or a seq_file. - */ -#include -#endif - -#include -#include -#include -#include - -/* #define ALLOCATOR_DEBUG_FINE */ - -struct nvgpu_allocator; -struct nvgpu_alloc_carveout; -struct vm_gk20a; -struct gk20a; - -/* - * Operations for an allocator to implement. - */ -struct nvgpu_allocator_ops { - u64 (*alloc)(struct nvgpu_allocator *allocator, u64 len); - u64 (*alloc_pte)(struct nvgpu_allocator *allocator, u64 len, - u32 page_size); - void (*free)(struct nvgpu_allocator *allocator, u64 addr); - - /* - * Special interface to allocate a memory region with a specific - * starting address. Yikes. Note: if free() works for freeing both - * regular and fixed allocations then free_fixed() does not need to - * be implemented. This behavior exists for legacy reasons and should - * not be propagated to new allocators. - * - * For allocators where the @page_size field is not applicable it can - * be left as 0. Otherwise a valid page size should be passed (4k or - * what the large page size is). - */ - u64 (*alloc_fixed)(struct nvgpu_allocator *allocator, - u64 base, u64 len, u32 page_size); - void (*free_fixed)(struct nvgpu_allocator *allocator, - u64 base, u64 len); - - /* - * Allow allocators to reserve space for carveouts. - */ - int (*reserve_carveout)(struct nvgpu_allocator *allocator, - struct nvgpu_alloc_carveout *co); - void (*release_carveout)(struct nvgpu_allocator *allocator, - struct nvgpu_alloc_carveout *co); - - /* - * Returns info about the allocator. - */ - u64 (*base)(struct nvgpu_allocator *allocator); - u64 (*length)(struct nvgpu_allocator *allocator); - u64 (*end)(struct nvgpu_allocator *allocator); - bool (*inited)(struct nvgpu_allocator *allocator); - u64 (*space)(struct nvgpu_allocator *allocator); - - /* Destructor. */ - void (*fini)(struct nvgpu_allocator *allocator); - -#ifdef __KERNEL__ - /* Debugging. */ - void (*print_stats)(struct nvgpu_allocator *allocator, - struct seq_file *s, int lock); -#endif -}; - -struct nvgpu_allocator { - struct gk20a *g; - - char name[32]; - struct nvgpu_mutex lock; - - void *priv; - const struct nvgpu_allocator_ops *ops; - - struct dentry *debugfs_entry; - bool debug; /* Control for debug msgs. */ -}; - -struct nvgpu_alloc_carveout { - const char *name; - u64 base; - u64 length; - - struct nvgpu_allocator *allocator; - - /* - * For usage by the allocator implementation. - */ - struct nvgpu_list_node co_entry; -}; - -static inline struct nvgpu_alloc_carveout * -nvgpu_alloc_carveout_from_co_entry(struct nvgpu_list_node *node) -{ - return (struct nvgpu_alloc_carveout *) - ((uintptr_t)node - offsetof(struct nvgpu_alloc_carveout, co_entry)); -}; - -#define NVGPU_CARVEOUT(local_name, local_base, local_length) \ - { \ - .name = (local_name), \ - .base = (local_base), \ - .length = (local_length) \ - } - -/* - * These are the available allocator flags. - * - * GPU_ALLOC_GVA_SPACE - * - * This flag makes sense for the buddy allocator only. It specifies that the - * allocator will be used for managing a GVA space. When managing GVA spaces - * special care has to be taken to ensure that allocations of similar PTE - * sizes are placed in the same PDE block. This allows the higher level - * code to skip defining both small and large PTE tables for every PDE. That - * can save considerable memory for address spaces that have a lot of - * allocations. - * - * GPU_ALLOC_NO_ALLOC_PAGE - * - * For any allocator that needs to manage a resource in a latency critical - * path this flag specifies that the allocator should not use any kmalloc() - * or similar functions during normal operation. Initialization routines - * may still use kmalloc(). This prevents the possibility of long waits for - * pages when using alloc_page(). Currently only the bitmap allocator - * implements this functionality. - * - * Also note that if you accept this flag then you must also define the - * free_fixed() function. Since no meta-data is allocated to help free - * allocations you need to keep track of the meta-data yourself (in this - * case the base and length of the allocation as opposed to just the base - * of the allocation). - * - * GPU_ALLOC_4K_VIDMEM_PAGES - * - * We manage vidmem pages at a large page granularity for performance - * reasons; however, this can lead to wasting memory. For page allocators - * setting this flag will tell the allocator to manage pools of 4K pages - * inside internally allocated large pages. - * - * Currently this flag is ignored since the only usage of the page allocator - * uses a 4K block size already. However, this flag has been reserved since - * it will be necessary in the future. - * - * GPU_ALLOC_FORCE_CONTIG - * - * Force allocations to be contiguous. Currently only relevant for page - * allocators since all other allocators are naturally contiguous. - * - * GPU_ALLOC_NO_SCATTER_GATHER - * - * The page allocator normally returns a scatter gather data structure for - * allocations (to handle discontiguous pages). However, at times that can - * be annoying so this flag forces the page allocator to return a u64 - * pointing to the allocation base (requires GPU_ALLOC_FORCE_CONTIG to be - * set as well). - */ -#define GPU_ALLOC_GVA_SPACE BIT64(0) -#define GPU_ALLOC_NO_ALLOC_PAGE BIT64(1) -#define GPU_ALLOC_4K_VIDMEM_PAGES BIT64(2) -#define GPU_ALLOC_FORCE_CONTIG BIT64(3) -#define GPU_ALLOC_NO_SCATTER_GATHER BIT64(4) - -static inline void alloc_lock(struct nvgpu_allocator *a) -{ - nvgpu_mutex_acquire(&a->lock); -} - -static inline void alloc_unlock(struct nvgpu_allocator *a) -{ - nvgpu_mutex_release(&a->lock); -} - -/* - * Buddy allocator specific initializers. - */ -int nvgpu_buddy_allocator_init(struct gk20a *g, struct nvgpu_allocator *na, - struct vm_gk20a *vm, const char *name, - u64 base, u64 size, u64 blk_size, - u64 max_order, u64 flags); - -/* - * Bitmap initializers. - */ -int nvgpu_bitmap_allocator_init(struct gk20a *g, struct nvgpu_allocator *na, - const char *name, u64 base, u64 length, - u64 blk_size, u64 flags); - -/* - * Page allocator initializers. - */ -int nvgpu_page_allocator_init(struct gk20a *g, struct nvgpu_allocator *na, - const char *name, u64 base, u64 length, - u64 blk_size, u64 flags); - -/* - * Lockless allocatior initializers. - * Note: This allocator can only allocate fixed-size structures of a - * pre-defined size. - */ -int nvgpu_lockless_allocator_init(struct gk20a *g, struct nvgpu_allocator *na, - const char *name, u64 base, u64 length, - u64 struct_size, u64 flags); - -#define GPU_BALLOC_MAX_ORDER 31U - -/* - * Allocator APIs. - */ -u64 nvgpu_alloc(struct nvgpu_allocator *allocator, u64 len); -u64 nvgpu_alloc_pte(struct nvgpu_allocator *a, u64 len, u32 page_size); -void nvgpu_free(struct nvgpu_allocator *allocator, u64 addr); - -u64 nvgpu_alloc_fixed(struct nvgpu_allocator *allocator, u64 base, u64 len, - u32 page_size); -void nvgpu_free_fixed(struct nvgpu_allocator *allocator, u64 base, u64 len); - -int nvgpu_alloc_reserve_carveout(struct nvgpu_allocator *a, - struct nvgpu_alloc_carveout *co); -void nvgpu_alloc_release_carveout(struct nvgpu_allocator *a, - struct nvgpu_alloc_carveout *co); - -u64 nvgpu_alloc_base(struct nvgpu_allocator *a); -u64 nvgpu_alloc_length(struct nvgpu_allocator *a); -u64 nvgpu_alloc_end(struct nvgpu_allocator *a); -bool nvgpu_alloc_initialized(struct nvgpu_allocator *a); -u64 nvgpu_alloc_space(struct nvgpu_allocator *a); - -void nvgpu_alloc_destroy(struct nvgpu_allocator *allocator); - -#ifdef __KERNEL__ -void nvgpu_alloc_print_stats(struct nvgpu_allocator *a, - struct seq_file *s, int lock); -#endif - -static inline struct gk20a *nvgpu_alloc_to_gpu(struct nvgpu_allocator *a) -{ - return a->g; -} - -#ifdef CONFIG_DEBUG_FS -/* - * Common functionality for the internals of the allocators. - */ -void nvgpu_init_alloc_debug(struct gk20a *g, struct nvgpu_allocator *a); -void nvgpu_fini_alloc_debug(struct nvgpu_allocator *a); -#endif - -int nvgpu_alloc_common_init(struct nvgpu_allocator *a, struct gk20a *g, - const char *name, void *priv, bool dbg, - const struct nvgpu_allocator_ops *ops); - -static inline void nvgpu_alloc_enable_dbg(struct nvgpu_allocator *a) -{ - a->debug = true; -} - -static inline void nvgpu_alloc_disable_dbg(struct nvgpu_allocator *a) -{ - a->debug = false; -} - -/* - * Debug stuff. - */ -#ifdef __KERNEL__ -#define __alloc_pstat(seq, allocator, fmt, arg...) \ - do { \ - if (seq) \ - seq_printf(seq, fmt "\n", ##arg); \ - else \ - alloc_dbg(allocator, fmt, ##arg); \ - } while (0) -#endif - -#define do_alloc_dbg(a, fmt, arg...) \ - nvgpu_log((a)->g, gpu_dbg_alloc, "%25s " fmt, (a)->name, ##arg) - -/* - * This gives finer control over debugging messages. By defining the - * ALLOCATOR_DEBUG_FINE macro prints for an allocator will only get made if - * that allocator's debug flag is set. - * - * Otherwise debugging is as normal: debug statements for all allocators - * if the GPU debugging mask bit is set. Note: even when ALLOCATOR_DEBUG_FINE - * is set gpu_dbg_alloc must still also be set to true. - */ -#if defined(ALLOCATOR_DEBUG_FINE) -#define alloc_dbg(a, fmt, arg...) \ - do { \ - if ((a)->debug) \ - do_alloc_dbg((a), fmt, ##arg); \ - } while (0) -#else -#define alloc_dbg(a, fmt, arg...) do_alloc_dbg(a, fmt, ##arg) -#endif - -#endif /* NVGPU_ALLOCATOR_H */ diff --git a/include/nvgpu/as.h b/include/nvgpu/as.h deleted file mode 100644 index f2249f9..0000000 --- a/include/nvgpu/as.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * GK20A Address Spaces - * - * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_AS_H -#define NVGPU_AS_H - -#include - -struct vm_gk20a; -struct gk20a; - -struct gk20a_as { - int last_share_id; /* dummy allocator for now */ -}; - -struct gk20a_as_share { - struct gk20a_as *as; - struct vm_gk20a *vm; - int id; -}; - -/* - * AS allocation flags. - */ -#define NVGPU_AS_ALLOC_USERSPACE_MANAGED (1 << 0) - -int gk20a_as_release_share(struct gk20a_as_share *as_share); - -/* if big_page_size == 0, the default big page size is used */ -int gk20a_as_alloc_share(struct gk20a *g, u32 big_page_size, - u32 flags, struct gk20a_as_share **out); - -struct gk20a *gk20a_from_as(struct gk20a_as *as); -#endif /* NVGPU_AS_H */ diff --git a/include/nvgpu/atomic.h b/include/nvgpu/atomic.h deleted file mode 100644 index 3edc1fc..0000000 --- a/include/nvgpu/atomic.h +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_ATOMIC_H -#define NVGPU_ATOMIC_H - -#ifdef __KERNEL__ -#include -#elif defined(__NVGPU_POSIX__) -#include -#else -#include -#endif - -#define NVGPU_ATOMIC_INIT(i) __nvgpu_atomic_init(i) -#define NVGPU_ATOMIC64_INIT(i) __nvgpu_atomic64_init(i) - -static inline void nvgpu_atomic_set(nvgpu_atomic_t *v, int i) -{ - __nvgpu_atomic_set(v, i); -} -static inline int nvgpu_atomic_read(nvgpu_atomic_t *v) -{ - return __nvgpu_atomic_read(v); -} -static inline void nvgpu_atomic_inc(nvgpu_atomic_t *v) -{ - __nvgpu_atomic_inc(v); -} -static inline int nvgpu_atomic_inc_return(nvgpu_atomic_t *v) -{ - return __nvgpu_atomic_inc_return(v); -} -static inline void nvgpu_atomic_dec(nvgpu_atomic_t *v) -{ - __nvgpu_atomic_dec(v); -} -static inline int nvgpu_atomic_dec_return(nvgpu_atomic_t *v) -{ - return __nvgpu_atomic_dec_return(v); -} -static inline int nvgpu_atomic_cmpxchg(nvgpu_atomic_t *v, int old, int new) -{ - return __nvgpu_atomic_cmpxchg(v, old, new); -} -static inline int nvgpu_atomic_xchg(nvgpu_atomic_t *v, int new) -{ - return __nvgpu_atomic_xchg(v, new); -} -static inline bool nvgpu_atomic_inc_and_test(nvgpu_atomic_t *v) -{ - return __nvgpu_atomic_inc_and_test(v); -} -static inline bool nvgpu_atomic_dec_and_test(nvgpu_atomic_t *v) -{ - return __nvgpu_atomic_dec_and_test(v); -} -static inline bool nvgpu_atomic_sub_and_test(int i, nvgpu_atomic_t *v) -{ - return __nvgpu_atomic_sub_and_test(i, v); -} -static inline int nvgpu_atomic_add_return(int i, nvgpu_atomic_t *v) -{ - return __nvgpu_atomic_add_return(i, v); -} -static inline int nvgpu_atomic_add_unless(nvgpu_atomic_t *v, int a, int u) -{ - return __nvgpu_atomic_add_unless(v, a, u); -} -static inline void nvgpu_atomic64_set(nvgpu_atomic64_t *v, long i) -{ - return __nvgpu_atomic64_set(v, i); -} -static inline long nvgpu_atomic64_read(nvgpu_atomic64_t *v) -{ - return __nvgpu_atomic64_read(v); -} -static inline void nvgpu_atomic64_add(long x, nvgpu_atomic64_t *v) -{ - __nvgpu_atomic64_add(x, v); -} -static inline void nvgpu_atomic64_inc(nvgpu_atomic64_t *v) -{ - __nvgpu_atomic64_inc(v); -} -static inline long nvgpu_atomic64_inc_return(nvgpu_atomic64_t *v) -{ - return __nvgpu_atomic64_inc_return(v); -} -static inline void nvgpu_atomic64_dec(nvgpu_atomic64_t *v) -{ - __nvgpu_atomic64_dec(v); -} -static inline void nvgpu_atomic64_dec_return(nvgpu_atomic64_t *v) -{ - __nvgpu_atomic64_dec_return(v); -} -static inline long nvgpu_atomic64_cmpxchg(nvgpu_atomic64_t *v, long old, - long new) -{ - return __nvgpu_atomic64_cmpxchg(v, old, new); -} -static inline void nvgpu_atomic64_sub(long x, nvgpu_atomic64_t *v) -{ - __nvgpu_atomic64_sub(x, v); -} -static inline long nvgpu_atomic64_sub_return(long x, nvgpu_atomic64_t *v) -{ - return __nvgpu_atomic64_sub_return(x, v); -} - -#endif /* NVGPU_ATOMIC_H */ diff --git a/include/nvgpu/barrier.h b/include/nvgpu/barrier.h deleted file mode 100644 index f0b6b2b..0000000 --- a/include/nvgpu/barrier.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -/* This file contains NVGPU_* high-level abstractions for various - * memor-barrier operations available in linux/kernel. Every OS - * should provide their own OS specific calls under this common API - */ - -#ifndef NVGPU_BARRIER_H -#define NVGPU_BARRIER_H - -#ifdef __KERNEL__ -#include -#elif defined(__NVGPU_POSIX__) -#include -#else -#include -#endif - -#define nvgpu_mb() __nvgpu_mb() -#define nvgpu_rmb() __nvgpu_rmb() -#define nvgpu_wmb() __nvgpu_wmb() - -#define nvgpu_smp_mb() __nvgpu_smp_mb() -#define nvgpu_smp_rmb() __nvgpu_smp_rmb() -#define nvgpu_smp_wmb() __nvgpu_smp_wmb() - -#define nvgpu_read_barrier_depends() __nvgpu_read_barrier_depends() -#define nvgpu_smp_read_barrier_depends() __nvgpu_smp_read_barrier_depends() - -#define NV_ACCESS_ONCE(x) __NV_ACCESS_ONCE(x) - -/* - * Sometimes we want to prevent speculation. - */ -#ifdef __NVGPU_PREVENT_UNTRUSTED_SPECULATION -#define nvgpu_speculation_barrier() __nvgpu_speculation_barrier() -#else -#define nvgpu_speculation_barrier() -#endif - -#endif /* NVGPU_BARRIER_H */ diff --git a/include/nvgpu/bios.h b/include/nvgpu/bios.h deleted file mode 100644 index 7d729b6..0000000 --- a/include/nvgpu/bios.h +++ /dev/null @@ -1,1123 +0,0 @@ -/* - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_BIOS_H -#define NVGPU_BIOS_H - -#include - -struct gk20a; - -#define PERF_PTRS_WIDTH 0x4 -#define PERF_PTRS_WIDTH_16 0x2 - -enum { - CLOCKS_TABLE = 2, - CLOCK_PROGRAMMING_TABLE, - FLL_TABLE, - VIN_TABLE, - FREQUENCY_CONTROLLER_TABLE -}; - -enum { - PERFORMANCE_TABLE = 0, - MEMORY_CLOCK_TABLE, - MEMORY_TWEAK_TABLE, - POWER_CONTROL_TABLE, - THERMAL_CONTROL_TABLE, - THERMAL_DEVICE_TABLE, - THERMAL_COOLERS_TABLE, - PERFORMANCE_SETTINGS_SCRIPT, - CONTINUOUS_VIRTUAL_BINNING_TABLE, - POWER_SENSORS_TABLE = 0xA, - POWER_CAPPING_TABLE = 0xB, - POWER_TOPOLOGY_TABLE = 0xF, - THERMAL_CHANNEL_TABLE = 0x12, - VOLTAGE_RAIL_TABLE = 26, - VOLTAGE_DEVICE_TABLE, - VOLTAGE_POLICY_TABLE, - LOWPOWER_TABLE, - LOWPOWER_GR_TABLE = 32, - LOWPOWER_MS_TABLE = 33, -}; - -enum { - VP_FIELD_TABLE = 0, - VP_FIELD_REGISTER, - VP_TRANSLATION_TABLE, -}; - -struct bit_token { - u8 token_id; - u8 data_version; - u16 data_size; - u16 data_ptr; -} __packed; - -#define BIOS_GET_FIELD(value, name) ((value & name##_MASK) >> name##_SHIFT) - -struct fll_descriptor_header { - u8 version; - u8 size; -} __packed; - -#define FLL_DESCRIPTOR_HEADER_10_SIZE_4 4U -#define FLL_DESCRIPTOR_HEADER_10_SIZE_6 6U - -struct fll_descriptor_header_10 { - u8 version; - u8 header_size; - u8 entry_size; - u8 entry_count; - u16 max_min_freq_mhz; -} __packed; - -#define FLL_DESCRIPTOR_ENTRY_10_SIZE 15U - -struct fll_descriptor_entry_10 { - u8 fll_device_type; - u8 clk_domain; - u8 fll_device_id; - u16 lut_params; - u8 vin_idx_logic; - u8 vin_idx_sram; - u16 fll_params; - u8 min_freq_vfe_idx; - u8 freq_ctrl_idx; - u16 ref_freq_mhz; - u16 ffr_cutoff_freq_mhz; -} __packed; - -#define NV_FLL_DESC_FLL_PARAMS_MDIV_MASK 0x1F -#define NV_FLL_DESC_FLL_PARAMS_MDIV_SHIFT 0 - -#define NV_FLL_DESC_FLL_PARAMS_SKIP_PLDIV_BELOW_DVCO_MIN_MASK 0x20 -#define NV_FLL_DESC_FLL_PARAMS_SKIP_PLDIV_BELOW_DVCO_MIN_SHIFT 5 - -#define NV_FLL_DESC_LUT_PARAMS_VSELECT_MASK 0x3 -#define NV_FLL_DESC_LUT_PARAMS_VSELECT_SHIFT 0 - -#define NV_FLL_DESC_LUT_PARAMS_HYSTERISIS_THRESHOLD_MASK 0x3C -#define NV_FLL_DESC_LUT_PARAMS_HYSTERISIS_THRESHOLD_SHIFT 2 - -struct vin_descriptor_header_10 { - u8 version; - u8 header_sizee; - u8 entry_size; - u8 entry_count; - u8 flags0; - u32 vin_cal; -} __packed; - -struct vin_descriptor_entry_10 { - u8 vin_device_type; - u8 volt_domain_vbios; - u8 vin_device_id; -} __packed; - -#define NV_VIN_DESC_FLAGS0_VIN_CAL_REVISION_MASK 0x7 -#define NV_VIN_DESC_FLAGS0_VIN_CAL_REVISION_SHIFT 0 - -#define NV_VIN_DESC_FLAGS0_VIN_CAL_TYPE_MASK 0xF0 -#define NV_VIN_DESC_FLAGS0_VIN_CAL_TYPE_SHIFT 4 - -#define NV_VIN_DESC_FLAGS0_DISABLE_CONTROL_MASK 0x8 -#define NV_VIN_DESC_FLAGS0_DISABLE_CONTROL_SHIFT 3 - -#define NV_VIN_DESC_VIN_CAL_SLOPE_FRACTION_MASK 0x1FF -#define NV_VIN_DESC_VIN_CAL_SLOPE_FRACTION_SHIFT 0 - -#define NV_VIN_DESC_VIN_CAL_SLOPE_INTEGER_MASK 0x3C00 -#define NV_VIN_DESC_VIN_CAL_SLOPE_INTEGER_SHIFT 10 - -#define NV_VIN_DESC_VIN_CAL_INTERCEPT_FRACTION_MASK 0x3C000 -#define NV_VIN_DESC_VIN_CAL_INTERCEPT_FRACTION_SHIFT 14 - -#define NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER_MASK 0xFFC0000 -#define NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER_SHIFT 18 - -#define NV_VIN_DESC_VIN_CAL_OFFSET_MASK 0x7F -#define NV_VIN_DESC_VIN_CAL_OFFSET_SHIFT 0 - -#define NV_VIN_DESC_VIN_CAL_GAIN_MASK 0xF80 -#define NV_VIN_DESC_VIN_CAL_GAIN_SHIFT 7 - -#define VBIOS_CLOCKS_TABLE_1X_HEADER_SIZE_07 0x07U -struct vbios_clocks_table_1x_header { - u8 version; - u8 header_size; - u8 entry_size; - u8 entry_count; - u8 clocks_hal; - u16 cntr_sampling_periodms; -} __packed; - -#define VBIOS_CLOCKS_TABLE_35_HEADER_SIZE_09 0x09U -struct vbios_clocks_table_35_header { - u8 version; - u8 header_size; - u8 entry_size; - u8 entry_count; - u8 clocks_hal; - u16 cntr_sampling_periodms; - u16 reference_window; -} __packed; - -#define VBIOS_CLOCKS_TABLE_1X_ENTRY_SIZE_09 0x09U -struct vbios_clocks_table_1x_entry { - u8 flags0; - u16 param0; - u32 param1; - u16 param2; -} __packed; - -#define VBIOS_CLOCKS_TABLE_35_ENTRY_SIZE_11 0x0BU -struct vbios_clocks_table_35_entry { - u8 flags0; - u16 param0; - u32 param1; - u16 param2; - u16 param3; -} __packed; - -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_MASK 0x1F -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_SHIFT 0 -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_FIXED 0x00 -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_MASTER 0x01 -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_SLAVE 0x02 - -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST_MASK 0xFF -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST_SHIFT 0 -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST_MASK 0xFF00 -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST_SHIFT 0x08 - -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_FIXED_FREQUENCY_MHZ_MASK 0xFFFF -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_FIXED_FREQUENCY_MHZ_SHIFT 0 -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MIN_MHZ_MASK 0xFFFF -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MIN_MHZ_SHIFT 0 - -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MAX_MHZ_MASK 0xFFFF0000 -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MAX_MHZ_SHIFT 0 - -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_SLAVE_MASTER_DOMAIN_MASK 0xF -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_SLAVE_MASTER_DOMAIN_SHIFT 0 - -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX_MASK 0xF -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX_SHIFT 0 - -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_AWARE_ORDERING_IDX_MASK 0xF0 -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_AWARE_ORDERING_IDX_SHIFT 4 - -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_MASK 0x100 -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_SHIFT 8 -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_FALSE 0x00 -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_TRUE 0x01 - -#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_PRE_VOLT_ORDERING_IDX_MASK 0xF -#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_PRE_VOLT_ORDERING_IDX_SHIFT 0 - -#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_POST_VOLT_ORDERING_IDX_MASK 0xF0 -#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_POST_VOLT_ORDERING_IDX_SHIFT 4 - -#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MIN_MASK 0xFF -#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MIN_SHIFT 0 -#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MAX_MASK 0xFF00 -#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MAX_SHIFT 0x08 - -#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_HEADER_SIZE_08 0x08U -struct vbios_clock_programming_table_1x_header { - u8 version; - u8 header_size; - u8 entry_size; - u8 entry_count; - u8 slave_entry_size; - u8 slave_entry_count; - u8 vf_entry_size; - u8 vf_entry_count; -} __packed; - -#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_SIZE_05 0x05U -#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_SIZE_0D 0x0DU -struct vbios_clock_programming_table_1x_entry { - u8 flags0; - u16 freq_max_mhz; - u8 param0; - u8 param1; - u32 rsvd; - u32 rsvd1; -} __packed; - -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASK 0xF -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_SHIFT 0 -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASTER_RATIO 0x00 -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASTER_TABLE 0x01 -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_SLAVE 0x02 - -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_MASK 0x70 -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_SHIFT 4 -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_PLL 0x00 -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_ONE_SOURCE 0x01 -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_FLL 0x02 - -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_MASK 0x80 -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_SHIFT 7 -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_FALSE 0x00 -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_TRUE 0x01 - -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM0_PLL_PLL_INDEX_MASK 0xFF -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM0_PLL_PLL_INDEX_SHIFT 0 - -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM1_PLL_FREQ_STEP_SIZE_MASK 0xFF -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM1_PLL_FREQ_STEP_SIZE_SHIFT 0 - -#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_SIZE_03 0x03U -struct vbios_clock_programming_table_1x_slave_entry { - u8 clk_dom_idx; - u16 param0; -} __packed; - -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_RATIO_RATIO_MASK 0xFF -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_RATIO_RATIO_SHIFT 0 - -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_TABLE_FREQ_MASK 0x3FFF -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_TABLE_FREQ_SHIFT 0 - -#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_VF_ENTRY_SIZE_02 0x02U -struct vbios_clock_programming_table_1x_vf_entry { - u8 vfe_idx; - u8 param0; -} __packed; - -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_VF_ENTRY_PARAM0_FLL_GAIN_VFE_IDX_MASK 0xFF -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_VF_ENTRY_PARAM0_FLL_GAIN_VFE_IDX_SHIFT 0 - -struct vbios_vfe_3x_header_struct { - u8 version; - u8 header_size; - u8 vfe_var_entry_size; - u8 vfe_var_entry_count; - u8 vfe_equ_entry_size; - u8 vfe_equ_entry_count; - u8 polling_periodms; -} __packed; - -#define VBIOS_VFE_3X_VAR_ENTRY_SIZE_11 0x11U -#define VBIOS_VFE_3X_VAR_ENTRY_SIZE_19 0x19U -struct vbios_vfe_3x_var_entry_struct { - u8 type; - u32 out_range_min; - u32 out_range_max; - u32 param0; - u32 param1; - u32 param2; - u32 param3; -} __packed; - -#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DISABLED 0x00U -#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_FREQUENCY 0x01U -#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_VOLTAGE 0x02U -#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_SENSED_TEMP 0x03U -#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_SENSED_FUSE 0x04U -#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DERIVED_PRODUCT 0x05U -#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DERIVED_SUM 0x06U - -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_TH_CH_IDX_MASK 0xFF -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_TH_CH_IDX_SHIFT 0 - -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_POS_MASK 0xFF00 -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_POS_SHIFT 8 - -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_NEG_MASK 0xFF0000 -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_NEG_SHIFT 16 - -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_MASK 0xFF -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_SHIFT 0 - -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_VER_MASK 0xFF00 -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_VER_SHIFT 8 - -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_EXPECTED_VER_MASK 0xFF0000 -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_EXPECTED_VER_SHIFT 16 - -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_MASK 0x1000000 -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_SHIFT 24 - -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VALUE_SIGNED_INTEGER_MASK 0x2000000 -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VALUE_SIGNED_INTEGER_SHIFT 25 - -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_YES 0x00000001 -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_NO 0x00000000 -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_0_MASK 0xFF -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_0_SHIFT 0 - -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_1_MASK 0xFF00 -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_1_SHIFT 8 - -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_0_MASK 0xFF -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_0_SHIFT 0 - -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_1_MASK 0xFF00 -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_1_SHIFT 8 - -#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_DEFAULT_VAL_MASK 0xFFFFFFFF -#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_DEFAULT_VAL_SHIFT 0 - -#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_SCALE_MASK 0xFFFFFFFF -#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_SCALE_SHIFT 0 - -#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_OFFSET_MASK 0xFFFFFFFF -#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_OFFSET_SHIFT 0 - -#define VBIOS_VFE_3X_EQU_ENTRY_SIZE_17 0x17U -#define VBIOS_VFE_3X_EQU_ENTRY_SIZE_18 0x18U - -struct vbios_vfe_3x_equ_entry_struct { - u8 type; - u8 var_idx; - u8 equ_idx_next; - u32 out_range_min; - u32 out_range_max; - u32 param0; - u32 param1; - u32 param2; - u8 param3; -} __packed; - - -#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_DISABLED 0x00U -#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_QUADRATIC 0x01U -#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_MINMAX 0x02U -#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_COMPARE 0x03U -#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_QUADRATIC_FXP 0x04U -#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_MINMAX_FXP 0x05U - -#define VBIOS_VFE_3X_EQU_ENTRY_IDX_INVALID 0xFFU - -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_QUADRATIC_C0_MASK 0xFFFFFFFF -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_QUADRATIC_C0_SHIFT 0 - -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_0_MASK 0xFF -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_0_SHIFT 0 - -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_1_MASK 0xFF00 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_1_SHIFT 8 - -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MASK 0x10000 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_SHIFT 16 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MIN 0x00000000 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MAX 0x00000001 - -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_COMPARE_CRIT_MASK 0xFFFFFFFF -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_COMPARE_CRIT_SHIFT 0 - -#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_QUADRATIC_C1_MASK 0xFFFFFFFF -#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_QUADRATIC_C1_SHIFT 0 - -#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_TRUE_MASK 0xFF -#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_TRUE_SHIFT 0 - -#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_FALSE_MASK 0xFF00 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_FALSE_SHIFT 8 - -#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_MASK 0x70000 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_SHIFT 16 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_EQUAL 0x00000000 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_GREATER_EQ 0x00000001 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_GREATER 0x00000002 - -#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_MASK 0xF -#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_SHIFT 0 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_UNITLESS 0x0 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_FREQ_MHZ 0x1 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VOLT_UV 0x2 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VF_GAIN 0x3 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VOLT_DELTA_UV 0x4 - -#define NV_VFIELD_DESC_SIZE_BYTE 0x00000000U -#define NV_VFIELD_DESC_SIZE_WORD 0x00000001U -#define NV_VFIELD_DESC_SIZE_DWORD 0x00000002U -#define VFIELD_SIZE(pvregentry) ((pvregentry->strap_reg_desc & 0x18U) >> 3U) - -#define NV_PMU_BIOS_VFIELD_DESC_CODE_INVALID 0x00000000U -#define NV_PMU_BIOS_VFIELD_DESC_CODE_REG 0x00000001U -#define NV_PMU_BIOS_VFIELD_DESC_CODE_INDEX_REG 0x00000002U - -#define NV_VFIELD_DESC_CODE_INVALID NV_PMU_BIOS_VFIELD_DESC_CODE_INVALID -#define NV_VFIELD_DESC_CODE_REG NV_PMU_BIOS_VFIELD_DESC_CODE_REG -#define NV_VFIELD_DESC_CODE_INDEX_REG NV_PMU_BIOS_VFIELD_DESC_CODE_INDEX_REG - -#define VFIELD_CODE(pvregentry) ((pvregentry->strap_reg_desc & 0xE0U) >> 5U) - -#define VFIELD_ID_STRAP_IDDQ 0x09U -#define VFIELD_ID_STRAP_IDDQ_1 0x0BU - -#define VFIELD_REG_HEADER_SIZE 3U -struct vfield_reg_header { - u8 version; - u8 entry_size; - u8 count; -} __packed; - -#define VBIOS_VFIELD_REG_TABLE_VERSION_1_0 0x10U - - -#define VFIELD_REG_ENTRY_SIZE 13U -struct vfield_reg_entry { - u8 strap_reg_desc; - u32 reg; - u32 reg_index; - u32 index; -} __packed; - -#define VFIELD_HEADER_SIZE 3U - -struct vfield_header { - u8 version; - u8 entry_size; - u8 count; -} __packed; - -#define VBIOS_VFIELD_TABLE_VERSION_1_0 0x10U - -#define VFIELD_BIT_START(ventry) (ventry.strap_desc & 0x1FU) -#define VFIELD_BIT_STOP(ventry) ((ventry.strap_desc & 0x3E0U) >> 5U) -#define VFIELD_BIT_REG(ventry) ((ventry.strap_desc & 0x3C00U) >> 10U) - -#define VFIELD_ENTRY_SIZE 3U - -struct vfield_entry { - u8 strap_id; - u16 strap_desc; -} __packed; - -#define PERF_CLK_DOMAINS_IDX_MAX (32U) -#define PERF_CLK_DOMAINS_IDX_INVALID PERF_CLK_DOMAINS_IDX_MAX - -#define VBIOS_PSTATE_TABLE_VERSION_5X 0x50U -#define VBIOS_PSTATE_HEADER_5X_SIZE_10 (10U) - -struct vbios_pstate_header_5x { - u8 version; - u8 header_size; - u8 base_entry_size; - u8 base_entry_count; - u8 clock_entry_size; - u8 clock_entry_count; - u8 flags0; - u8 initial_pstate; - u8 cpi_support_level; -u8 cpi_features; -} __packed; - -#define VBIOS_PSTATE_CLOCK_ENTRY_5X_SIZE_6 6U - -#define VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_2 0x2U -#define VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_3 0x3U - -struct vbios_pstate_entry_clock_5x { - u16 param0; - u32 param1; -} __packed; - -struct vbios_pstate_entry_5x { - u8 pstate_level; - u8 flags0; - u8 lpwr_entry_idx; - struct vbios_pstate_entry_clock_5x clockEntry[PERF_CLK_DOMAINS_IDX_MAX]; -} __packed; - -#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM0_NOM_FREQ_MHZ_SHIFT 0 -#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM0_NOM_FREQ_MHZ_MASK 0x00003FFF - -#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MIN_FREQ_MHZ_SHIFT 0 -#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MIN_FREQ_MHZ_MASK 0x00003FFF - -#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MAX_FREQ_MHZ_SHIFT 14 -#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MAX_FREQ_MHZ_MASK 0x0FFFC000 - -#define VBIOS_PERFLEVEL_SKIP_ENTRY 0xFFU - -#define VBIOS_MEMORY_CLOCK_HEADER_11_VERSION 0x11U - -#define VBIOS_MEMORY_CLOCK_HEADER_11_0_SIZE 16U -#define VBIOS_MEMORY_CLOCK_HEADER_11_1_SIZE 21U -#define VBIOS_MEMORY_CLOCK_HEADER_11_2_SIZE 26U - -struct vbios_memory_clock_header_1x { - u8 version; - u8 header_size; - u8 base_entry_size; - u8 strap_entry_size; - u8 strap_entry_count; - u8 entry_count; - u8 flags; - u8 fbvdd_settle_time; - u32 cfg_pwrd_val; - u16 fbvddq_high; - u16 fbvddq_low; - u32 script_list_ptr; - u8 script_list_count; - u32 cmd_script_list_ptr; - u8 cmd_script_list_count; -} __packed; - -#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_2_SIZE 20U - -struct vbios_memory_clock_base_entry_11 { - u16 minimum; - u16 maximum; - u32 script_pointer; - u8 flags0; - u32 fbpa_config; - u32 fbpa_config1; - u8 flags1; - u8 ref_mpllssf_freq_delta; - u8 flags2; -} __packed; - -/* Script Pointer Index */ -/* #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX 3:2*/ -#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX_MASK \ - ((u8)0xc) -#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX_SHIFT 2 -/* #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX 1:0*/ -#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX_MASK \ - ((u8)0x3) -#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX_SHIFT 0 - -#define VBIOS_POWER_SENSORS_VERSION_2X 0x20U -#define VBIOS_POWER_SENSORS_2X_HEADER_SIZE_08 0x00000008U - -struct pwr_sensors_2x_header { - u8 version; - u8 header_size; - u8 table_entry_size; - u8 num_table_entries; - u32 ba_script_pointer; -} __packed; - -#define VBIOS_POWER_SENSORS_2X_ENTRY_SIZE_15 0x00000015U - -struct pwr_sensors_2x_entry { - u8 flags0; - u32 class_param0; - u32 sensor_param0; - u32 sensor_param1; - u32 sensor_param2; - u32 sensor_param3; -} __packed; - -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_MASK 0xF -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_SHIFT 0 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_I2C 0x00000001U - -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_INDEX_MASK 0xFF -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_INDEX_SHIFT 0 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_USE_FXP8_8_MASK 0x100 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_USE_FXP8_8_SHIFT 8 - -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT0_MOHM_MASK 0xFFFF -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT0_MOHM_SHIFT 0 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT1_MOHM_MASK 0xFFFF0000 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT1_MOHM_SHIFT 16 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_RSHUNT2_MOHM_MASK 0xFFFF -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_RSHUNT2_MOHM_SHIFT 0 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_CONFIGURATION_MASK 0xFFFF0000 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_CONFIGURATION_SHIFT 16 - -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_MASKENABLE_MASK 0xFFFF -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_MASKENABLE_SHIFT 0 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_GPIOFUNCTION_MASK 0xFF0000 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_GPIOFUNCTION_SHIFT 16 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_M_MASK 0xFFFF -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_M_SHIFT 0 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_B_MASK 0xFFFF0000 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_B_SHIFT 16 - -#define VBIOS_POWER_TOPOLOGY_VERSION_2X 0x20U -#define VBIOS_POWER_TOPOLOGY_2X_HEADER_SIZE_06 0x00000006U - -struct pwr_topology_2x_header { - u8 version; - u8 header_size; - u8 table_entry_size; - u8 num_table_entries; - u8 rel_entry_size; - u8 num_rel_entries; -} __packed; - -#define VBIOS_POWER_TOPOLOGY_2X_ENTRY_SIZE_16 0x00000016U - -struct pwr_topology_2x_entry { - u8 flags0; - u8 pwr_rail; - u32 param0; - u32 curr_corr_slope; - u32 curr_corr_offset; - u32 param1; - u32 param2; -} __packed; - -#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_MASK 0xF -#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_SHIFT 0 -#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_SENSOR U8(0x00000001) - -#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_INDEX_MASK 0xFF -#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_INDEX_SHIFT 0 -#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_PROVIDER_INDEX_MASK 0xFF00 -#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_PROVIDER_INDEX_SHIFT 8 - -#define VBIOS_POWER_POLICY_VERSION_3X 0x30U -#define VBIOS_POWER_POLICY_3X_HEADER_SIZE_25 0x00000025U - -struct pwr_policy_3x_header_struct { - u8 version; - u8 header_size; - u8 table_entry_size; - u8 num_table_entries; - u16 base_sample_period; - u16 min_client_sample_period; - u8 table_rel_entry_size; - u8 num_table_rel_entries; - u8 tgp_policy_idx; - u8 rtp_policy_idx; - u8 mxm_policy_idx; - u8 dnotifier_policy_idx; - u32 d2_limit; - u32 d3_limit; - u32 d4_limit; - u32 d5_limit; - u8 low_sampling_mult; - u8 pwr_tgt_policy_idx; - u8 pwr_tgt_floor_policy_idx; - u8 sm_bus_policy_idx; - u8 table_viol_entry_size; - u8 num_table_viol_entries; -} __packed; - -#define VBIOS_POWER_POLICY_3X_ENTRY_SIZE_2E 0x0000002EU - -struct pwr_policy_3x_entry_struct { - u8 flags0; - u8 ch_idx; - u32 limit_min; - u32 limit_rated; - u32 limit_max; - u32 param0; - u32 param1; - u32 param2; - u32 param3; - u32 limit_batt; - u8 flags1; - u8 past_length; - u8 next_length; - u16 ratio_min; - u16 ratio_max; - u8 sample_mult; - u32 filter_param; -} __packed; - -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_MASK 0xF -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_SHIFT 0 -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_HW_THRESHOLD 0x00000005U -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_LIMIT_UNIT_MASK 0x10 -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_LIMIT_UNIT_SHIFT 4 - -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FULL_DEFLECTION_LIMIT_MASK 0x1 -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FULL_DEFLECTION_LIMIT_SHIFT 0 -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_INTEGRAL_CONTROL_MASK 0x2 -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_INTEGRAL_CONTROL_SHIFT 1 -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FILTER_TYPE_MASK 0x3C -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FILTER_TYPE_SHIFT 2 - -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_THRES_IDX_MASK 0xFF -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_THRES_IDX_SHIFT 0 -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_IDX_MASK 0xFF00 -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_IDX_SHIFT 8 -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_USE_MASK 0x10000 -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_USE_SHIFT 16 - -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM1_HW_THRESHOLD_LOW_THRESHOLD_VAL_MASK 0xFFFF -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM1_HW_THRESHOLD_LOW_THRESHOLD_VAL_SHIFT 0 - -/* Voltage Rail Table */ -struct vbios_voltage_rail_table_1x_header { - u8 version; - u8 header_size; - u8 table_entry_size; - u8 num_table_entries; - u8 volt_domain_hal; -} __packed; - -#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_07 0X00000007U -#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_08 0X00000008U -#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_09 0X00000009U -#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0A 0X0000000AU -#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0B 0X0000000BU -#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0C 0X0000000CU - -struct vbios_voltage_rail_table_1x_entry { - u32 boot_voltage_uv; - u8 rel_limit_vfe_equ_idx; - u8 alt_rel_limit_vfe_equidx; - u8 ov_limit_vfe_equ_idx; - u8 pwr_equ_idx; - u8 boot_volt_vfe_equ_idx; - u8 vmin_limit_vfe_equ_idx; - u8 volt_margin_limit_vfe_equ_idx; - u8 volt_scale_exp_pwr_equ_idx; -} __packed; - -/* Voltage Device Table */ -struct vbios_voltage_device_table_1x_header { - u8 version; - u8 header_size; - u8 table_entry_size; - u8 num_table_entries; -} __packed; - -struct vbios_voltage_device_table_1x_entry { - u8 type; - u8 volt_domain; - u16 settle_time_us; - u32 param0; - u32 param1; - u32 param2; - u32 param3; - u32 param4; -} __packed; - -#define NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_INVALID 0x00U -#define NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_PSV 0x02U - -#define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_INPUT_FREQUENCY_MASK \ - GENMASK(23, 0) -#define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_INPUT_FREQUENCY_SHIFT 0 -#define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_EXT_DEVICE_INDEX_MASK \ - GENMASK(31, 24) -#define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_EXT_DEVICE_INDEX_SHIFT 24 - -#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_VOLTAGE_MINIMUM_MASK \ - GENMASK(23, 0) -#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_VOLTAGE_MINIMUM_SHIFT 0 -#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_MASK \ - GENMASK(31, 24) -#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_SHIFT 24 -#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_DEFAULT 0x00 -#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_LPWR_STEADY_STATE \ - 0x01 -#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_LPWR_SLEEP_STATE \ - 0x02 -#define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_VOLTAGE_MAXIMUM_MASK \ - GENMASK(23, 0) -#define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_VOLTAGE_MAXIMUM_SHIFT 0 -#define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_RSVD_MASK \ - GENMASK(31, 24) -#define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_RSVD_SHIFT 24 - -#define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_BASE_MASK \ - GENMASK(23, 0) -#define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_BASE_SHIFT 0 -#define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_STEPS_MASK \ - GENMASK(31, 24) -#define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_STEPS_SHIFT 24 - -#define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_OFFSET_SCALE_MASK \ - GENMASK(23, 0) -#define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_OFFSET_SCALE_SHIFT 0 -#define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_RSVD_MASK \ - GENMASK(31, 24) -#define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_RSVD_SHIFT 24 - -/* Voltage Policy Table */ -struct vbios_voltage_policy_table_1x_header { - u8 version; - u8 header_size; - u8 table_entry_size; - u8 num_table_entries; - u8 perf_core_vf_seq_policy_idx; -} __packed; - -struct vbios_voltage_policy_table_1x_entry { - u8 type; - u32 param0; - u32 param1; - u32 param2; - u32 param3; -} __packed; - -#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_INVALID 0x00U -#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL 0x01U -#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_MULTI_STEP 0x02U -#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_SINGLE_STEP 0x03U -#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL_MULTI_STEP 0x04U - -#define NV_VBIOS_VPT_ENTRY_PARAM0_SINGLE_RAIL_VOLT_DOMAIN_MASK \ - GENMASK(7, 0) -#define NV_VBIOS_VPT_ENTRY_PARAM0_SINGLE_RAIL_VOLT_DOMAIN_SHIFT 0 -#define NV_VBIOS_VPT_ENTRY_PARAM0_RSVD_MASK GENMASK(8, 31) -#define NV_VBIOS_VPT_ENTRY_PARAM0_RSVD_SHIFT 8 - -#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_MASTER_MASK \ - GENMASK(7, 0) -#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_MASTER_SHIFT 0 -#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_SLAVE_MASK \ - GENMASK(15, 8) -#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_SLAVE_SHIFT 8 -#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MIN_MASK \ - GENMASK(23, 16) -#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MIN_SHIFT 16 -#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MAX_MASK \ - GENMASK(31, 24) -#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MAX_SHIFT 24 - -#define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_MASK \ - GENMASK(15, 0) -#define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_SHIFT 0 -#define NV_VBIOS_VPT_ENTRY_PARAM2_SR_RAMP_UP_STEP_SIZE_UV_MASK \ - GENMASK(31, 0) -#define NV_VBIOS_VPT_ENTRY_PARAM2_SR_RAMP_UP_STEP_SIZE_UV_SHIFT 0 -#define NV_VBIOS_VPT_ENTRY_PARAM3_SR_RAMP_DOWN_STEP_SIZE_UV_MASK \ - GENMASK(31, 0) -#define NV_VBIOS_VPT_ENTRY_PARAM3_SR_RAMP_DOWN_STEP_SIZE_UV_SHIFT 0 - -/* Type-Specific Parameter DWORD 0 - Type = _SR_MULTI_STEP */ -#define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_MASK \ - GENMASK(15, 0) -#define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_SHIFT \ - 0 - -#define VBIOS_THERM_DEVICE_VERSION_1X 0x10U - -#define VBIOS_THERM_DEVICE_1X_HEADER_SIZE_04 0x00000004U - -struct therm_device_1x_header { - u8 version; - u8 header_size; - u8 table_entry_size; - u8 num_table_entries; -} ; - -struct therm_device_1x_entry { - u8 class_id; - u8 param0; - u8 flags; -} ; - -#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_INVALID 0x00U -#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU 0x01U -#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU_GPC_TSOSC 0x02U -#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU_GPC_SCI 0x03U -#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_HBM2_SITE 0x70U -#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_HBM2_COMBINED 0x71U - -#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_PARAM0_I2C_DEVICE_INDEX_MASK 0xFF -#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_PARAM0_I2C_DEVICE_INDEX_SHIFT 0 - -#define VBIOS_THERM_CHANNEL_VERSION_1X 0x10U - -#define VBIOS_THERM_CHANNEL_1X_HEADER_SIZE_09 0x00000009U - -struct therm_channel_1x_header { - u8 version; - u8 header_size; - u8 table_entry_size; - u8 num_table_entries; - u8 gpu_avg_pri_ch_idx; - u8 gpu_max_pri_ch_idx; - u8 board_pri_ch_idx; - u8 mem_pri_ch_idx; - u8 pwr_supply_pri_ch_idx; -} __packed; - -struct therm_channel_1x_entry { - u8 class_id; - u8 param0; - u8 param1; - u8 param2; - u8 flags; -} __packed; - -#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_CLASS_DEVICE 0x01U - -#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM0_DEVICE_INDEX_MASK 0xFF -#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM0_DEVICE_INDEX_SHIFT 0 - -#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM1_DEVICE_PROVIDER_INDEX_MASK 0xFF -#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM1_DEVICE_PROVIDER_INDEX_SHIFT 0 - -/* Frequency Controller Table */ -struct vbios_fct_1x_header { - u8 version; - u8 header_size; - u8 entry_size; - u8 entry_count; - u16 sampling_period_ms; -} __packed; - -struct vbios_fct_1x_entry { - u8 flags0; - u8 clk_domain_idx; - u16 param0; - u16 param1; - u32 param2; - u32 param3; - u32 param4; - u32 param5; - u32 param6; - u32 param7; - u32 param8; -} __packed; - -#define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_MASK GENMASK(3, 0) -#define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_SHIFT 0 -#define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_DISABLED 0x0 -#define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_PI 0x1 - -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_MASK GENMASK(7, 0) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_SHIFT 0 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_SYS 0x00 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_LTC 0x01 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_XBAR 0x02 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC0 0x03 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC1 0x04 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC2 0x05 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC3 0x06 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC4 0x07 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC5 0x08 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPCS 0x09 - -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_MASK GENMASK(9, 8) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_SHIFT 8 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_BCAST 0x0 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_MIN 0x1 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_MAX 0x2 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_AVG 0x3 - -#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_SLOWDOWN_PCT_MIN_MASK GENMASK(7, 0) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_SLOWDOWN_PCT_MIN_SHIFT 0 - -#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_MASK GENMASK(8, 8) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_SHIFT 8 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_NO 0x0 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_YES 0x1 - -#define NV_VBIOS_FCT_1X_ENTRY_PARAM2_PROP_GAIN_MASK GENMASK(31, 0) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM2_PROP_GAIN_SHIFT 0 - -#define NV_VBIOS_FCT_1X_ENTRY_PARAM3_INTEG_GAIN_MASK GENMASK(31, 0) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM3_INTEG_GAIN_SHIFT 0 - - -#define NV_VBIOS_FCT_1X_ENTRY_PARAM4_INTEG_DECAY_MASK GENMASK(31, 0) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM4_INTEG_DECAY_SHIFT 0 - -#define NV_VBIOS_FCT_1X_ENTRY_PARAM5_VOLT_DELTA_MIN_MASK GENMASK(31, 0) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM5_VOLT_DELTA_MIN_SHIFT 0 - - -#define NV_VBIOS_FCT_1X_ENTRY_PARAM6_VOLT_DELTA_MAX_MASK GENMASK(31, 0) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM6_VOLT_DELTA_MAX_SHIFT 0 - -#define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VF_MASK GENMASK(15, 0) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VF_SHIFT 0 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VMIN_MASK GENMASK(31, 16) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VMIN_SHIFT 16 - -#define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_POS_MASK GENMASK(15, 0) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_POS_SHIFT 0 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_NEG_MASK GENMASK(31, 16) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_NEG_SHIFT 16 - -/* LPWR Index Table */ -struct nvgpu_bios_lpwr_idx_table_1x_header { - u8 version; - u8 header_size; - u8 entry_size; - u8 entry_count; - u16 base_sampling_period; -} __packed; - -struct nvgpu_bios_lpwr_idx_table_1x_entry { - u8 pcie_idx; - u8 gr_idx; - u8 ms_idx; - u8 di_idx; - u8 gc6_idx; -} __packed; - -/* LPWR MS Table*/ -struct nvgpu_bios_lpwr_ms_table_1x_header { - u8 version; - u8 header_size; - u8 entry_size; - u8 entry_count; - u8 default_entry_idx; - u16 idle_threshold_us; -} __packed; - -struct nvgpu_bios_lpwr_ms_table_1x_entry { - u32 feautre_mask; - u16 dynamic_current_logic; - u16 dynamic_current_sram; -} __packed; - -#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_MASK GENMASK(0, 0) -#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_SHIFT 0 -#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_SWASR_MASK GENMASK(2, 2) -#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_SWASR_SHIFT 2 -#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_CLOCK_GATING_MASK \ - GENMASK(3, 3) -#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_CLOCK_GATING_SHIFT 3 -#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_RPPG_MASK GENMASK(5, 5) -#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_RPPG_SHIFT 5 - -/* LPWR GR Table */ -struct nvgpu_bios_lpwr_gr_table_1x_header { - u8 version; - u8 header_size; - u8 entry_size; - u8 entry_count; - u8 default_entry_idx; - u16 idle_threshold_us; - u8 adaptive_gr_multiplier; -} __packed; - -struct nvgpu_bios_lpwr_gr_table_1x_entry { - u32 feautre_mask; -} __packed; - -#define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_MASK GENMASK(0, 0) -#define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_SHIFT 0 - -#define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG_MASK GENMASK(4, 4) -#define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG_SHIFT 4 -int nvgpu_bios_parse_rom(struct gk20a *g); -u8 nvgpu_bios_read_u8(struct gk20a *g, u32 offset); -s8 nvgpu_bios_read_s8(struct gk20a *g, u32 offset); -u16 nvgpu_bios_read_u16(struct gk20a *g, u32 offset); -u32 nvgpu_bios_read_u32(struct gk20a *g, u32 offset); -void *nvgpu_bios_get_perf_table_ptrs(struct gk20a *g, - struct bit_token *ptoken, u8 table_id); -int nvgpu_bios_execute_script(struct gk20a *g, u32 offset); -u32 nvgpu_bios_get_nvlink_config_data(struct gk20a *g); -#endif diff --git a/include/nvgpu/bitops.h b/include/nvgpu/bitops.h deleted file mode 100644 index 00336d0..0000000 --- a/include/nvgpu/bitops.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_BITOPS_H -#define NVGPU_BITOPS_H - -#include - -/* - * Explicit sizes for bit definitions. Please use these instead of BIT(). - */ -#define BIT8(i) (U8(1) << (i)) -#define BIT16(i) (U16(1) << (i)) -#define BIT32(i) (U32(1) << (i)) -#define BIT64(i) (U64(1) << (i)) - -#ifdef __KERNEL__ -#include -#include -#elif defined(__NVGPU_POSIX__) -#include -#else -#include -#endif - -#endif /* NVGPU_BITOPS_H */ diff --git a/include/nvgpu/bsearch.h b/include/nvgpu/bsearch.h deleted file mode 100644 index 46a2d04..0000000 --- a/include/nvgpu/bsearch.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_BSEARCH_H -#define NVGPU_BSEARCH_H - -#ifdef __KERNEL__ -#include -#elif defined(__NVGPU_POSIX__) -#include -#endif - -#endif /*NVGPU_BSEARCH_H*/ diff --git a/include/nvgpu/bug.h b/include/nvgpu/bug.h deleted file mode 100644 index 82d641b..0000000 --- a/include/nvgpu/bug.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_BUG_H -#define NVGPU_BUG_H - -#ifdef __KERNEL__ -#include -/* - * Define an assert macro that code within nvgpu can use. - * - * The goal of this macro is for debugging but what that means varies from OS - * to OS. On Linux wee don't want to BUG() for general driver misbehaving. BUG() - * is a very heavy handed tool - in fact there's probably no where within the - * nvgpu core code where it makes sense to use a BUG() when running under Linux. - * - * However, on QNX (and POSIX) BUG() will just kill the current process. This - * means we can use it for handling bugs in nvgpu. - * - * As a result this macro varies depending on platform. - */ -#define nvgpu_assert(cond) ((void) WARN_ON(!(cond))) -#define nvgpu_do_assert_print(g, fmt, arg...) \ - do { \ - nvgpu_err(g, fmt, ##arg); \ - } while (false) -#elif defined(__NVGPU_POSIX__) -#include -#else -#include -#endif - -#endif /* NVGPU_BUG_H */ diff --git a/include/nvgpu/channel.h b/include/nvgpu/channel.h deleted file mode 100644 index 764d047..0000000 --- a/include/nvgpu/channel.h +++ /dev/null @@ -1,478 +0,0 @@ -/* - * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_CHANNEL_H -#define NVGPU_CHANNEL_H - -#include -#include -#include -#include -#include -#include -#include - -struct gk20a; -struct dbg_session_gk20a; -struct gk20a_fence; -struct fifo_profile_gk20a; -struct nvgpu_channel_sync; -struct nvgpu_gpfifo_userdata; - -/* Flags to be passed to nvgpu_channel_setup_bind() */ -#define NVGPU_SETUP_BIND_FLAGS_SUPPORT_VPR (1U << 0U) -#define NVGPU_SETUP_BIND_FLAGS_SUPPORT_DETERMINISTIC (1U << 1U) -#define NVGPU_SETUP_BIND_FLAGS_REPLAYABLE_FAULTS_ENABLE (1U << 2U) -#define NVGPU_SETUP_BIND_FLAGS_USERMODE_SUPPORT (1U << 3U) - -/* Flags to be passed to nvgpu_submit_channel_gpfifo() */ -#define NVGPU_SUBMIT_FLAGS_FENCE_WAIT (1U << 0U) -#define NVGPU_SUBMIT_FLAGS_FENCE_GET (1U << 1U) -#define NVGPU_SUBMIT_FLAGS_HW_FORMAT (1U << 2U) -#define NVGPU_SUBMIT_FLAGS_SYNC_FENCE (1U << 3U) -#define NVGPU_SUBMIT_FLAGS_SUPPRESS_WFI (1U << 4U) -#define NVGPU_SUBMIT_FLAGS_SKIP_BUFFER_REFCOUNTING (1U << 5U) - -/* - * The binary format of 'struct nvgpu_channel_fence' introduced here - * should match that of 'struct nvgpu_fence' defined in uapi header, since - * this struct is intended to be a mirror copy of the uapi struct. This is - * not a hard requirement though because of nvgpu_get_fence_args conversion - * function. - */ -struct nvgpu_channel_fence { - u32 id; - u32 value; -}; - -/* - * The binary format of 'struct nvgpu_gpfifo_entry' introduced here - * should match that of 'struct nvgpu_gpfifo' defined in uapi header, since - * this struct is intended to be a mirror copy of the uapi struct. This is - * a rigid requirement because there's no conversion function and there are - * memcpy's present between the user gpfifo (of type nvgpu_gpfifo) and the - * kern gpfifo (of type nvgpu_gpfifo_entry). - */ -struct nvgpu_gpfifo_entry { - u32 entry0; - u32 entry1; -}; - -struct gpfifo_desc { - struct nvgpu_mem mem; - u32 entry_num; - - u32 get; - u32 put; - - bool wrap; - - /* if gpfifo lives in vidmem or is forced to go via PRAMIN, first copy - * from userspace to pipe and then from pipe to gpu buffer */ - void *pipe; -}; - -struct nvgpu_setup_bind_args { - u32 num_gpfifo_entries; - u32 num_inflight_jobs; - u32 userd_dmabuf_fd; - u64 userd_dmabuf_offset; - u32 gpfifo_dmabuf_fd; - u64 gpfifo_dmabuf_offset; - u32 work_submit_token; - u32 flags; -}; - -struct notification { - struct { - u32 nanoseconds[2]; - } timestamp; - u32 info32; - u16 info16; - u16 status; -}; - -struct priv_cmd_queue { - struct nvgpu_mem mem; - u32 size; /* num of entries in words */ - u32 put; /* put for priv cmd queue */ - u32 get; /* get for priv cmd queue */ -}; - -struct priv_cmd_entry { - bool valid; - struct nvgpu_mem *mem; - u32 off; /* offset in mem, in u32 entries */ - u64 gva; - u32 get; /* start of entry in queue */ - u32 size; /* in words */ -}; - -struct channel_gk20a_job { - struct nvgpu_mapped_buf **mapped_buffers; - int num_mapped_buffers; - struct gk20a_fence *post_fence; - struct priv_cmd_entry *wait_cmd; - struct priv_cmd_entry *incr_cmd; - struct nvgpu_list_node list; -}; - -static inline struct channel_gk20a_job * -channel_gk20a_job_from_list(struct nvgpu_list_node *node) -{ - return (struct channel_gk20a_job *) - ((uintptr_t)node - offsetof(struct channel_gk20a_job, list)); -}; - -struct channel_gk20a_joblist { - struct { - bool enabled; - unsigned int length; - unsigned int put; - unsigned int get; - struct channel_gk20a_job *jobs; - struct nvgpu_mutex read_lock; - } pre_alloc; - - struct { - struct nvgpu_list_node jobs; - struct nvgpu_spinlock lock; - } dynamic; - - /* - * Synchronize abort cleanup (when closing a channel) and job cleanup - * (asynchronously from worker) - protect from concurrent access when - * job resources are being freed. - */ - struct nvgpu_mutex cleanup_lock; -}; - -struct channel_gk20a_timeout { - /* lock protects the running timer state */ - struct nvgpu_spinlock lock; - struct nvgpu_timeout timer; - bool running; - u32 gp_get; - u64 pb_get; - - /* lock not needed */ - u32 limit_ms; - bool enabled; - bool debug_dump; -}; - -/* - * Track refcount actions, saving their stack traces. This number specifies how - * many most recent actions are stored in a buffer. Set to 0 to disable. 128 - * should be enough to track moderately hard problems from the start. - */ -#define GK20A_CHANNEL_REFCOUNT_TRACKING 0 -/* Stack depth for the saved actions. */ -#define GK20A_CHANNEL_REFCOUNT_TRACKING_STACKLEN 8 - -/* - * Because the puts and gets are not linked together explicitly (although they - * should always come in pairs), it's not possible to tell which ref holder to - * delete from the list when doing a put. So, just store some number of most - * recent gets and puts in a ring buffer, to obtain a history. - * - * These are zeroed when a channel is closed, so a new one starts fresh. - */ - -enum channel_gk20a_ref_action_type { - channel_gk20a_ref_action_get, - channel_gk20a_ref_action_put -}; - -#if GK20A_CHANNEL_REFCOUNT_TRACKING - -#include - -struct channel_gk20a_ref_action { - enum channel_gk20a_ref_action_type type; - s64 timestamp_ms; - /* - * Many of these traces will be similar. Simpler to just capture - * duplicates than to have a separate database for the entries. - */ - struct stack_trace trace; - unsigned long trace_entries[GK20A_CHANNEL_REFCOUNT_TRACKING_STACKLEN]; -}; -#endif - -/* this is the priv element of struct nvhost_channel */ -struct channel_gk20a { - struct gk20a *g; /* set only when channel is active */ - - struct nvgpu_list_node free_chs; - - struct nvgpu_spinlock ref_obtain_lock; - nvgpu_atomic_t ref_count; - struct nvgpu_cond ref_count_dec_wq; -#if GK20A_CHANNEL_REFCOUNT_TRACKING - /* - * Ring buffer for most recent refcount gets and puts. Protected by - * ref_actions_lock when getting or putting refs (i.e., adding - * entries), and when reading entries. - */ - struct channel_gk20a_ref_action ref_actions[ - GK20A_CHANNEL_REFCOUNT_TRACKING]; - size_t ref_actions_put; /* index of next write */ - struct nvgpu_spinlock ref_actions_lock; -#endif - - struct nvgpu_semaphore_int *hw_sema; - - nvgpu_atomic_t bound; - - u32 chid; - u32 tsgid; - pid_t pid; - pid_t tgid; - struct nvgpu_mutex ioctl_lock; - - struct nvgpu_list_node ch_entry; /* channel's entry in TSG */ - - struct channel_gk20a_joblist joblist; - struct nvgpu_allocator fence_allocator; - - struct vm_gk20a *vm; - - struct gpfifo_desc gpfifo; - - struct nvgpu_mem usermode_userd; /* Used for Usermode Submission */ - struct nvgpu_mem usermode_gpfifo; - struct nvgpu_mem inst_block; - - u64 userd_iova; - u64 userd_gpu_va; - - struct priv_cmd_queue priv_cmd_q; - - struct nvgpu_cond notifier_wq; - struct nvgpu_cond semaphore_wq; - - /* kernel watchdog to kill stuck jobs */ - struct channel_gk20a_timeout timeout; - - /* for job cleanup handling in the background worker */ - struct nvgpu_list_node worker_item; - -#if defined(CONFIG_GK20A_CYCLE_STATS) - struct { - void *cyclestate_buffer; - u32 cyclestate_buffer_size; - struct nvgpu_mutex cyclestate_buffer_mutex; - } cyclestate; - - struct nvgpu_mutex cs_client_mutex; - struct gk20a_cs_snapshot_client *cs_client; -#endif - struct nvgpu_mutex dbg_s_lock; - struct nvgpu_list_node dbg_s_list; - - struct nvgpu_mutex sync_lock; - struct nvgpu_channel_sync *sync; - struct nvgpu_channel_sync *user_sync; - -#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION - u64 virt_ctx; -#endif - - struct nvgpu_mem ctx_header; - - struct nvgpu_spinlock ch_timedout_lock; - bool ch_timedout; - /* Any operating system specific data. */ - void *os_priv; - - u32 obj_class; /* we support only one obj per channel */ - - u32 timeout_accumulated_ms; - u32 timeout_gpfifo_get; - - u32 subctx_id; - u32 runqueue_sel; - - u32 timeout_ms_max; - u32 runlist_id; - - bool mmu_nack_handled; - bool referenceable; - bool vpr; - bool deterministic; - /* deterministic, but explicitly idle and submits disallowed */ - bool deterministic_railgate_allowed; - bool cde; - bool usermode_submit_enabled; - bool timeout_debug_dump; - bool has_os_fence_framework_support; - - bool is_privileged_channel; - - /** - * MMU Debugger Mode is enabled for this channel if refcnt > 0 - */ - u32 mmu_debug_mode_refcnt; -}; - -static inline struct channel_gk20a * -channel_gk20a_from_free_chs(struct nvgpu_list_node *node) -{ - return (struct channel_gk20a *) - ((uintptr_t)node - offsetof(struct channel_gk20a, free_chs)); -}; - -static inline struct channel_gk20a * -channel_gk20a_from_ch_entry(struct nvgpu_list_node *node) -{ - return (struct channel_gk20a *) - ((uintptr_t)node - offsetof(struct channel_gk20a, ch_entry)); -}; - -static inline struct channel_gk20a * -channel_gk20a_from_worker_item(struct nvgpu_list_node *node) -{ - return (struct channel_gk20a *) - ((uintptr_t)node - offsetof(struct channel_gk20a, worker_item)); -}; - -static inline bool gk20a_channel_as_bound(struct channel_gk20a *ch) -{ - return !!ch->vm; -} -int channel_gk20a_commit_va(struct channel_gk20a *c); -int gk20a_init_channel_support(struct gk20a *, u32 chid); - -/* must be inside gk20a_busy()..gk20a_idle() */ -void gk20a_channel_close(struct channel_gk20a *ch); -void __gk20a_channel_kill(struct channel_gk20a *ch); - -bool gk20a_channel_update_and_check_timeout(struct channel_gk20a *ch, - u32 timeout_delta_ms, bool *progress); -void gk20a_disable_channel(struct channel_gk20a *ch); -void gk20a_channel_abort(struct channel_gk20a *ch, bool channel_preempt); -void gk20a_channel_abort_clean_up(struct channel_gk20a *ch); -void gk20a_channel_semaphore_wakeup(struct gk20a *g, bool post_events); -int gk20a_channel_alloc_priv_cmdbuf(struct channel_gk20a *c, u32 size, - struct priv_cmd_entry *entry); -int gk20a_free_priv_cmdbuf(struct channel_gk20a *c, struct priv_cmd_entry *e); - -int gk20a_enable_channel_tsg(struct gk20a *g, struct channel_gk20a *ch); -int gk20a_disable_channel_tsg(struct gk20a *g, struct channel_gk20a *ch); - -int gk20a_channel_suspend(struct gk20a *g); -int gk20a_channel_resume(struct gk20a *g); - -void gk20a_channel_deterministic_idle(struct gk20a *g); -void gk20a_channel_deterministic_unidle(struct gk20a *g); - -int nvgpu_channel_worker_init(struct gk20a *g); -void nvgpu_channel_worker_deinit(struct gk20a *g); - -struct channel_gk20a *gk20a_get_channel_from_file(int fd); -void gk20a_channel_update(struct channel_gk20a *c); - -/* returns ch if reference was obtained */ -struct channel_gk20a *__must_check _gk20a_channel_get(struct channel_gk20a *ch, - const char *caller); -#define gk20a_channel_get(ch) _gk20a_channel_get(ch, __func__) - - -void _gk20a_channel_put(struct channel_gk20a *ch, const char *caller); -#define gk20a_channel_put(ch) _gk20a_channel_put(ch, __func__) - -/* returns NULL if could not take a ref to the channel */ -struct channel_gk20a *__must_check _gk20a_channel_from_id(struct gk20a *g, - u32 chid, const char *caller); -#define gk20a_channel_from_id(g, chid) _gk20a_channel_from_id(g, chid, __func__) - -int gk20a_wait_channel_idle(struct channel_gk20a *ch); - -/* runlist_id -1 is synonym for ENGINE_GR_GK20A runlist id */ -struct channel_gk20a *gk20a_open_new_channel(struct gk20a *g, - s32 runlist_id, - bool is_privileged_channel, - pid_t pid, pid_t tid); - -int nvgpu_channel_setup_bind(struct channel_gk20a *c, - struct nvgpu_setup_bind_args *args); - -void gk20a_channel_timeout_restart_all_channels(struct gk20a *g); - -bool channel_gk20a_is_prealloc_enabled(struct channel_gk20a *c); -void channel_gk20a_joblist_lock(struct channel_gk20a *c); -void channel_gk20a_joblist_unlock(struct channel_gk20a *c); -bool channel_gk20a_joblist_is_empty(struct channel_gk20a *c); - -int channel_gk20a_update_runlist(struct channel_gk20a *c, bool add); -int gk20a_channel_get_timescale_from_timeslice(struct gk20a *g, - unsigned int timeslice_period, - unsigned int *__timeslice_timeout, unsigned int *__timeslice_scale); - -void gk20a_wait_until_counter_is_N( - struct channel_gk20a *ch, nvgpu_atomic_t *counter, int wait_value, - struct nvgpu_cond *c, const char *caller, const char *counter_name); -int channel_gk20a_alloc_job(struct channel_gk20a *c, - struct channel_gk20a_job **job_out); -void channel_gk20a_free_job(struct channel_gk20a *c, - struct channel_gk20a_job *job); -u32 nvgpu_get_gp_free_count(struct channel_gk20a *c); -u32 nvgpu_gp_free_count(struct channel_gk20a *c); -int gk20a_channel_add_job(struct channel_gk20a *c, - struct channel_gk20a_job *job, - bool skip_buffer_refcounting); -void free_priv_cmdbuf(struct channel_gk20a *c, - struct priv_cmd_entry *e); -void gk20a_channel_clean_up_jobs(struct channel_gk20a *c, - bool clean_all); - -void gk20a_channel_free_usermode_buffers(struct channel_gk20a *c); -u32 nvgpu_get_gpfifo_entry_size(void); - -int nvgpu_submit_channel_gpfifo_user(struct channel_gk20a *c, - struct nvgpu_gpfifo_userdata userdata, - u32 num_entries, - u32 flags, - struct nvgpu_channel_fence *fence, - struct gk20a_fence **fence_out, - struct fifo_profile_gk20a *profile); - -int nvgpu_submit_channel_gpfifo_kernel(struct channel_gk20a *c, - struct nvgpu_gpfifo_entry *gpfifo, - u32 num_entries, - u32 flags, - struct nvgpu_channel_fence *fence, - struct gk20a_fence **fence_out); - -#ifdef CONFIG_DEBUG_FS -void trace_write_pushbuffers(struct channel_gk20a *c, u32 count); -#else -static inline void trace_write_pushbuffers(struct channel_gk20a *c, u32 count) -{ -} -#endif - -void gk20a_channel_set_timedout(struct channel_gk20a *ch); -bool gk20a_channel_check_timedout(struct channel_gk20a *ch); - -#endif diff --git a/include/nvgpu/channel_sync.h b/include/nvgpu/channel_sync.h deleted file mode 100644 index f0b2b86..0000000 --- a/include/nvgpu/channel_sync.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * - * Nvgpu Channel Synchronization Abstraction - * - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_CHANNEL_SYNC_H -#define NVGPU_CHANNEL_SYNC_H - -#include - -struct nvgpu_channel_sync; -struct priv_cmd_entry; -struct channel_gk20a; -struct gk20a_fence; -struct gk20a; -struct nvgpu_semaphore; - -struct nvgpu_channel_sync { - nvgpu_atomic_t refcount; - - /* Generate a gpu wait cmdbuf from syncpoint. - * Returns a gpu cmdbuf that performs the wait when executed - */ - int (*wait_syncpt)(struct nvgpu_channel_sync *s, u32 id, u32 thresh, - struct priv_cmd_entry *entry); - - /* Generate a gpu wait cmdbuf from sync fd. - * Returns a gpu cmdbuf that performs the wait when executed - */ - int (*wait_fd)(struct nvgpu_channel_sync *s, int fd, - struct priv_cmd_entry *entry, int max_wait_cmds); - - /* Increment syncpoint/semaphore. - * Returns - * - a gpu cmdbuf that performs the increment when executed, - * - a fence that can be passed to wait_cpu() and is_expired(). - */ - int (*incr)(struct nvgpu_channel_sync *s, - struct priv_cmd_entry *entry, - struct gk20a_fence *fence, - bool need_sync_fence, - bool register_irq); - - /* Increment syncpoint/semaphore, so that the returned fence represents - * work completion (may need wfi) and can be returned to user space. - * Returns - * - a gpu cmdbuf that performs the increment when executed, - * - a fence that can be passed to wait_cpu() and is_expired(), - * - a gk20a_fence that signals when the incr has happened. - */ - int (*incr_user)(struct nvgpu_channel_sync *s, - int wait_fence_fd, - struct priv_cmd_entry *entry, - struct gk20a_fence *fence, - bool wfi, - bool need_sync_fence, - bool register_irq); - - /* Reset the channel syncpoint/semaphore. */ - void (*set_min_eq_max)(struct nvgpu_channel_sync *s); - - /* - * Set the channel syncpoint/semaphore to safe state - * This should be used to reset User managed syncpoint since we don't - * track threshold values for those syncpoints - */ - void (*set_safe_state)(struct nvgpu_channel_sync *s); - - /* Returns the sync point id or negative number if no syncpt*/ - int (*syncpt_id)(struct nvgpu_channel_sync *s); - - /* Returns the sync point address of sync point or 0 if not supported */ - u64 (*syncpt_address)(struct nvgpu_channel_sync *s); - - /* Free the resources allocated by nvgpu_channel_sync_create. */ - void (*destroy)(struct nvgpu_channel_sync *s); -}; - -void channel_sync_semaphore_gen_wait_cmd(struct channel_gk20a *c, - struct nvgpu_semaphore *sema, struct priv_cmd_entry *wait_cmd, - u32 wait_cmd_size, u32 pos); - -int channel_sync_syncpt_gen_wait_cmd(struct channel_gk20a *c, - u32 id, u32 thresh, struct priv_cmd_entry *wait_cmd, - u32 wait_cmd_size, u32 pos, bool preallocated); - -void nvgpu_channel_sync_destroy(struct nvgpu_channel_sync *sync, - bool set_safe_state); -struct nvgpu_channel_sync *nvgpu_channel_sync_create(struct channel_gk20a *c, - bool user_managed); -bool nvgpu_channel_sync_needs_os_fence_framework(struct gk20a *g); - -#endif /* NVGPU_CHANNEL_SYNC_H */ diff --git a/include/nvgpu/circ_buf.h b/include/nvgpu/circ_buf.h deleted file mode 100644 index 76998ca..0000000 --- a/include/nvgpu/circ_buf.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_CIRC_BUF_H -#define NVGPU_CIRC_BUF_H - -#ifdef __KERNEL__ -#include -#elif defined(__NVGPU_POSIX__) -#include -#endif - -#endif /* NVGPU_CIRC_BUF_H */ diff --git a/include/nvgpu/clk.h b/include/nvgpu/clk.h deleted file mode 100644 index 62bb0f9..0000000 --- a/include/nvgpu/clk.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NVGPU_CLK_H__ -#define __NVGPU_CLK_H__ - -#define CLK_NAME_MAX 24 - -struct namemap_cfg { - u32 namemap; - u32 is_enable; /* Namemap enabled */ - u32 is_counter; /* Using cntr */ - struct gk20a *g; - struct { - u32 reg_ctrl_addr; - u32 reg_ctrl_idx; - u32 reg_cntr_addr; - } cntr; - u32 scale; - char name[CLK_NAME_MAX]; -}; - -#endif diff --git a/include/nvgpu/clk_arb.h b/include/nvgpu/clk_arb.h deleted file mode 100644 index 43af631..0000000 --- a/include/nvgpu/clk_arb.h +++ /dev/null @@ -1,378 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_CLK_ARB_H -#define NVGPU_CLK_ARB_H - -struct gk20a; - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "clk/clk.h" -#include "pstate/pstate.h" -#include "lpwr/lpwr.h" -#include "volt/volt.h" - -#define MAX_F_POINTS 256 -#define DEFAULT_EVENT_NUMBER 32 - -struct nvgpu_clk_dev; -struct nvgpu_clk_arb_target; -struct nvgpu_clk_notification_queue; -struct nvgpu_clk_session; - -#define VF_POINT_INVALID_PSTATE ~0U -#define VF_POINT_SET_PSTATE_SUPPORTED(a, b) ((a)->pstates |= (1UL << (b))) -#define VF_POINT_GET_PSTATE(a) (((a)->pstates) ?\ - __fls((a)->pstates) :\ - VF_POINT_INVALID_PSTATE) -#define VF_POINT_COMMON_PSTATE(a, b) (((a)->pstates & (b)->pstates) ?\ - __fls((a)->pstates & (b)->pstates) :\ - VF_POINT_INVALID_PSTATE) - -/* - * These events, defined in common code are the counterparts of the uapi - * events. There should be a conversion function to take care to convert - * these to the uapi events. - */ -/* Event associated to a VF update */ -#define NVGPU_EVENT_VF_UPDATE 0 - -/* Recoverable alarms (POLLPRI) */ -/* Alarm when target frequency on any session is not possible */ -#define NVGPU_EVENT_ALARM_TARGET_VF_NOT_POSSIBLE 1 -/* Alarm when target frequency on current session is not possible */ -#define NVGPU_EVENT_ALARM_LOCAL_TARGET_VF_NOT_POSSIBLE 2 -/* Alarm when Clock Arbiter failed */ -#define NVGPU_EVENT_ALARM_CLOCK_ARBITER_FAILED 3 -/* Alarm when VF table update failed */ -#define NVGPU_EVENT_ALARM_VF_TABLE_UPDATE_FAILED 4 -/* Alarm on thermal condition */ -#define NVGPU_EVENT_ALARM_THERMAL_ABOVE_THRESHOLD 5 -/* Alarm on power condition */ -#define NVGPU_EVENT_ALARM_POWER_ABOVE_THRESHOLD 6 - -/* Non recoverable alarm (POLLHUP) */ -/* Alarm on GPU shutdown/fall from bus */ -#define NVGPU_EVENT_ALARM_GPU_LOST 7 - -#define NVGPU_EVENT_LAST NVGPU_EVENT_ALARM_GPU_LOST - -/* Local Alarms */ -#define EVENT(alarm) (0x1UL << NVGPU_EVENT_##alarm) - -#define LOCAL_ALARM_MASK (EVENT(ALARM_LOCAL_TARGET_VF_NOT_POSSIBLE) | \ - EVENT(VF_UPDATE)) - -#define _WRAPGTEQ(a, b) ((a-b) > 0) - -/* - * NVGPU_POLL* defines equivalent to the POLL* linux defines - */ -#define NVGPU_POLLIN (1 << 0) -#define NVGPU_POLLPRI (1 << 1) -#define NVGPU_POLLOUT (1 << 2) -#define NVGPU_POLLRDNORM (1 << 3) -#define NVGPU_POLLHUP (1 << 4) - -/* NVGPU_CLK_DOMAIN_* defines equivalent to NVGPU_GPU_CLK_DOMAIN_* - * defines in uapi header - */ -/* Memory clock */ -#define NVGPU_CLK_DOMAIN_MCLK (0) -/* Main graphics core clock */ -#define NVGPU_CLK_DOMAIN_GPCCLK (1) - -#define NVGPU_CLK_DOMAIN_MAX (NVGPU_CLK_DOMAIN_GPCCLK) - -#define clk_arb_dbg(g, fmt, args...) \ - do { \ - nvgpu_log(g, gpu_dbg_clk_arb, \ - fmt, ##args); \ - } while (0) - -struct nvgpu_clk_notification { - u32 notification; - u64 timestamp; -}; - -struct nvgpu_clk_notification_queue { - u32 size; - nvgpu_atomic_t head; - nvgpu_atomic_t tail; - struct nvgpu_clk_notification *notifications; -}; - -struct nvgpu_clk_vf_point { - u16 pstates; - union { - struct { - u16 gpc_mhz; - u16 sys_mhz; - u16 xbar_mhz; - }; - u16 mem_mhz; - }; - u32 uvolt; - u32 uvolt_sram; -}; - -struct nvgpu_clk_vf_table { - u32 mclk_num_points; - struct nvgpu_clk_vf_point *mclk_points; - u32 gpc2clk_num_points; - struct nvgpu_clk_vf_point *gpc2clk_points; -}; -#ifdef CONFIG_DEBUG_FS -struct nvgpu_clk_arb_debug { - s64 switch_max; - s64 switch_min; - u64 switch_num; - s64 switch_avg; - s64 switch_std; -}; -#endif - -struct nvgpu_clk_arb_target { - u16 mclk; - u16 gpc2clk; - u32 pstate; -}; - -enum clk_arb_work_item_type { - CLK_ARB_WORK_UPDATE_VF_TABLE, - CLK_ARB_WORK_UPDATE_ARB -}; - -struct nvgpu_clk_arb_work_item { - enum clk_arb_work_item_type item_type; - struct nvgpu_clk_arb *arb; - struct nvgpu_list_node worker_item; -}; - -struct nvgpu_clk_arb { - struct nvgpu_spinlock sessions_lock; - struct nvgpu_spinlock users_lock; - struct nvgpu_spinlock requests_lock; - - struct nvgpu_mutex pstate_lock; - struct nvgpu_list_node users; - struct nvgpu_list_node sessions; - struct nvgpu_list_node requests; - - struct gk20a *g; - int status; - - struct nvgpu_clk_arb_target actual_pool[2]; - struct nvgpu_clk_arb_target *actual; - - u16 gpc2clk_default_mhz; - u16 mclk_default_mhz; - u32 voltuv_actual; - - u16 gpc2clk_min, gpc2clk_max; - u16 mclk_min, mclk_max; - - struct nvgpu_clk_arb_work_item update_vf_table_work_item; - struct nvgpu_clk_arb_work_item update_arb_work_item; - - struct nvgpu_cond request_wq; - - struct nvgpu_clk_vf_table *current_vf_table; - struct nvgpu_clk_vf_table vf_table_pool[2]; - u32 vf_table_index; - - u16 *mclk_f_points; - nvgpu_atomic_t req_nr; - - u32 mclk_f_numpoints; - u16 *gpc2clk_f_points; - u32 gpc2clk_f_numpoints; - - bool clk_arb_events_supported; - - nvgpu_atomic64_t alarm_mask; - struct nvgpu_clk_notification_queue notification_queue; - -#ifdef CONFIG_DEBUG_FS - struct nvgpu_clk_arb_debug debug_pool[2]; - struct nvgpu_clk_arb_debug *debug; - bool debugfs_set; -#endif -}; - -struct nvgpu_clk_dev { - struct nvgpu_clk_session *session; - union { - struct nvgpu_list_node link; - struct nvgpu_list_node node; - }; - struct nvgpu_cond readout_wq; - nvgpu_atomic_t poll_mask; - u16 gpc2clk_target_mhz; - u16 mclk_target_mhz; - u32 alarms_reported; - nvgpu_atomic_t enabled_mask; - struct nvgpu_clk_notification_queue queue; - u32 arb_queue_head; - struct nvgpu_ref refcount; -}; - -struct nvgpu_clk_session { - bool zombie; - struct gk20a *g; - struct nvgpu_ref refcount; - struct nvgpu_list_node link; - struct nvgpu_list_node targets; - - struct nvgpu_spinlock session_lock; - struct nvgpu_clk_arb_target target_pool[2]; - struct nvgpu_clk_arb_target *target; -}; - -static inline struct nvgpu_clk_session * -nvgpu_clk_session_from_link(struct nvgpu_list_node *node) -{ - return (struct nvgpu_clk_session *) - ((uintptr_t)node - offsetof(struct nvgpu_clk_session, link)); -}; - -static inline struct nvgpu_clk_dev * -nvgpu_clk_dev_from_node(struct nvgpu_list_node *node) -{ - return (struct nvgpu_clk_dev *) - ((uintptr_t)node - offsetof(struct nvgpu_clk_dev, node)); -}; - -static inline struct nvgpu_clk_dev * -nvgpu_clk_dev_from_link(struct nvgpu_list_node *node) -{ - return (struct nvgpu_clk_dev *) - ((uintptr_t)node - offsetof(struct nvgpu_clk_dev, link)); -}; - -static inline struct nvgpu_clk_arb_work_item * -nvgpu_clk_arb_work_item_from_worker_item(struct nvgpu_list_node *node) -{ - return (struct nvgpu_clk_arb_work_item *) - ((uintptr_t)node - offsetof(struct nvgpu_clk_arb_work_item, worker_item)); -}; - -void nvgpu_clk_arb_worker_enqueue(struct gk20a *g, - struct nvgpu_clk_arb_work_item *work_item); - -int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb); - -int nvgpu_clk_arb_worker_init(struct gk20a *g); - -int nvgpu_clk_arb_init_arbiter(struct gk20a *g); - -bool nvgpu_clk_arb_has_active_req(struct gk20a *g); - -int nvgpu_clk_arb_get_arbiter_clk_range(struct gk20a *g, u32 api_domain, - u16 *min_mhz, u16 *max_mhz); - -int nvgpu_clk_arb_get_arbiter_actual_mhz(struct gk20a *g, - u32 api_domain, u16 *actual_mhz); - -int nvgpu_clk_arb_get_arbiter_effective_mhz(struct gk20a *g, - u32 api_domain, u16 *effective_mhz); - -int nvgpu_clk_arb_get_arbiter_clk_f_points(struct gk20a *g, - u32 api_domain, u32 *max_points, u16 *fpoints); - -u32 nvgpu_clk_arb_get_arbiter_clk_domains(struct gk20a *g); -bool nvgpu_clk_arb_is_valid_domain(struct gk20a *g, u32 api_domain); - -void nvgpu_clk_arb_cleanup_arbiter(struct gk20a *g); - -int nvgpu_clk_arb_install_session_fd(struct gk20a *g, - struct nvgpu_clk_session *session); - -int nvgpu_clk_arb_init_session(struct gk20a *g, - struct nvgpu_clk_session **_session); - -void nvgpu_clk_arb_release_session(struct gk20a *g, - struct nvgpu_clk_session *session); - -int nvgpu_clk_arb_commit_request_fd(struct gk20a *g, - struct nvgpu_clk_session *session, int request_fd); - -int nvgpu_clk_arb_set_session_target_mhz(struct nvgpu_clk_session *session, - int fd, u32 api_domain, u16 target_mhz); - -int nvgpu_clk_arb_get_session_target_mhz(struct nvgpu_clk_session *session, - u32 api_domain, u16 *target_mhz); - -int nvgpu_clk_arb_install_event_fd(struct gk20a *g, - struct nvgpu_clk_session *session, int *event_fd, u32 alarm_mask); - -int nvgpu_clk_arb_install_request_fd(struct gk20a *g, - struct nvgpu_clk_session *session, int *event_fd); - -void nvgpu_clk_arb_schedule_vf_table_update(struct gk20a *g); - -int nvgpu_clk_arb_get_current_pstate(struct gk20a *g); - -void nvgpu_clk_arb_pstate_change_lock(struct gk20a *g, bool lock); - -void nvgpu_clk_arb_send_thermal_alarm(struct gk20a *g); - -void nvgpu_clk_arb_set_global_alarm(struct gk20a *g, u32 alarm); - -void nvgpu_clk_arb_schedule_alarm(struct gk20a *g, u32 alarm); - -void nvgpu_clk_arb_clear_global_alarm(struct gk20a *g, u32 alarm); - -void nvgpu_clk_arb_free_session(struct nvgpu_ref *refcount); - -void nvgpu_clk_arb_free_fd(struct nvgpu_ref *refcount); - -u32 nvgpu_clk_arb_notify(struct nvgpu_clk_dev *dev, - struct nvgpu_clk_arb_target *target, - u32 alarm); - -int nvgpu_clk_notification_queue_alloc(struct gk20a *g, - struct nvgpu_clk_notification_queue *queue, - size_t events_number); - -void nvgpu_clk_notification_queue_free(struct gk20a *g, - struct nvgpu_clk_notification_queue *queue); - -void nvgpu_clk_arb_event_post_event(struct nvgpu_clk_dev *dev); - -unsigned long nvgpu_clk_measure_freq(struct gk20a *g, u32 api_domain); - -#ifdef CONFIG_DEBUG_FS -int nvgpu_clk_arb_debugfs_init(struct gk20a *g); -#endif -#endif /* NVGPU_CLK_ARB_H */ - diff --git a/include/nvgpu/comptags.h b/include/nvgpu/comptags.h deleted file mode 100644 index 3df1b6f..0000000 --- a/include/nvgpu/comptags.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_COMPTAGS_H -#define NVGPU_COMPTAGS_H - -#include -#include - -struct gk20a; -struct nvgpu_os_buffer; - -struct gk20a_comptags { - u32 offset; - u32 lines; - - /* - * This signals whether allocation has been attempted. Observe 'lines' - * to see whether the comptags were actually allocated. We try alloc - * only once per buffer in order not to break multiple compressible-kind - * mappings. - */ - bool allocated; - - /* - * Do comptags need to be cleared before mapping? - */ - bool needs_clear; -}; - -struct gk20a_comptag_allocator { - struct gk20a *g; - - struct nvgpu_mutex lock; - - /* This bitmap starts at ctag 1. 0th cannot be taken. */ - unsigned long *bitmap; - - /* Size of bitmap, not max ctags, so one less. */ - unsigned long size; -}; - -/* real size here, but first (ctag 0) isn't used */ -int gk20a_comptag_allocator_init(struct gk20a *g, - struct gk20a_comptag_allocator *allocator, - unsigned long size); -void gk20a_comptag_allocator_destroy(struct gk20a *g, - struct gk20a_comptag_allocator *allocator); - -int gk20a_comptaglines_alloc(struct gk20a_comptag_allocator *allocator, - u32 *offset, u32 len); -void gk20a_comptaglines_free(struct gk20a_comptag_allocator *allocator, - u32 offset, u32 len); - -/* - * Defined by OS specific code since comptags are stored in a highly OS specific - * way. - */ -int gk20a_alloc_or_get_comptags(struct gk20a *g, - struct nvgpu_os_buffer *buf, - struct gk20a_comptag_allocator *allocator, - struct gk20a_comptags *comptags); -void gk20a_get_comptags(struct nvgpu_os_buffer *buf, - struct gk20a_comptags *comptags); - -/* - * These functions must be used to synchronize comptags clear. The usage: - * - * if (gk20a_comptags_start_clear(os_buf)) { - * // we now hold the buffer lock for clearing - * - * bool successful = hw_clear_comptags(); - * - * // mark the buf cleared (or not) and release the buffer lock - * gk20a_comptags_finish_clear(os_buf, successful); - * } - * - * If gk20a_start_comptags_clear() returns false, another caller has - * already cleared the comptags. - */ -bool gk20a_comptags_start_clear(struct nvgpu_os_buffer *buf); -void gk20a_comptags_finish_clear(struct nvgpu_os_buffer *buf, - bool clear_successful); - -#endif /* NVGPU_COMPTAGS_H */ diff --git a/include/nvgpu/cond.h b/include/nvgpu/cond.h deleted file mode 100644 index 49e9d1f..0000000 --- a/include/nvgpu/cond.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_COND_H -#define NVGPU_COND_H - -#ifdef __KERNEL__ -#include -#elif defined(__NVGPU_POSIX__) -#include -#else -#include -#endif - -/* - * struct nvgpu_cond - * - * Should be implemented per-OS in a separate library - */ -struct nvgpu_cond; - -/** - * nvgpu_cond_init - Initialize a condition variable - * - * @cond - The condition variable to initialize - * - * Initialize a condition variable before using it. - */ -int nvgpu_cond_init(struct nvgpu_cond *cond); - -/** - * nvgpu_cond_signal - Signal a condition variable - * - * @cond - The condition variable to signal - * - * Wake up a waiter for a condition variable to check if its condition has been - * satisfied. - * - * The waiter is using an uninterruptible wait. - */ -int nvgpu_cond_signal(struct nvgpu_cond *cond); - -/** - * nvgpu_cond_signal_interruptible - Signal a condition variable - * - * @cond - The condition variable to signal - * - * Wake up a waiter for a condition variable to check if its condition has been - * satisfied. - * - * The waiter is using an interruptible wait. - */ -int nvgpu_cond_signal_interruptible(struct nvgpu_cond *cond); - -/** - * nvgpu_cond_broadcast - Signal all waiters of a condition variable - * - * @cond - The condition variable to signal - * - * Wake up all waiters for a condition variable to check if their conditions - * have been satisfied. - * - * The waiters are using an uninterruptible wait. - */ -int nvgpu_cond_broadcast(struct nvgpu_cond *cond); - -/** - * nvgpu_cond_broadcast_interruptible - Signal all waiters of a condition - * variable - * - * @cond - The condition variable to signal - * - * Wake up all waiters for a condition variable to check if their conditions - * have been satisfied. - * - * The waiters are using an interruptible wait. - */ -int nvgpu_cond_broadcast_interruptible(struct nvgpu_cond *cond); - -/** - * nvgpu_cond_destroy - Destroy a condition variable - * - * @cond - The condition variable to destroy - */ -void nvgpu_cond_destroy(struct nvgpu_cond *cond); - -#endif /* NVGPU_COND_H */ diff --git a/include/nvgpu/ctxsw_trace.h b/include/nvgpu/ctxsw_trace.h deleted file mode 100644 index 033e020..0000000 --- a/include/nvgpu/ctxsw_trace.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_CTXSW_TRACE_H -#define NVGPU_CTXSW_TRACE_H - -#include - -struct gk20a; -struct tsg_gk20a; -struct channel_gk20a; - -#define NVGPU_GPU_CTXSW_TAG_SOF 0x00 -#define NVGPU_GPU_CTXSW_TAG_CTXSW_REQ_BY_HOST 0x01 -#define NVGPU_GPU_CTXSW_TAG_FE_ACK 0x02 -#define NVGPU_GPU_CTXSW_TAG_FE_ACK_WFI 0x0a -#define NVGPU_GPU_CTXSW_TAG_FE_ACK_GFXP 0x0b -#define NVGPU_GPU_CTXSW_TAG_FE_ACK_CTAP 0x0c -#define NVGPU_GPU_CTXSW_TAG_FE_ACK_CILP 0x0d -#define NVGPU_GPU_CTXSW_TAG_SAVE_END 0x03 -#define NVGPU_GPU_CTXSW_TAG_RESTORE_START 0x04 -#define NVGPU_GPU_CTXSW_TAG_CONTEXT_START 0x05 -#define NVGPU_GPU_CTXSW_TAG_ENGINE_RESET 0xfe -#define NVGPU_GPU_CTXSW_TAG_INVALID_TIMESTAMP 0xff -#define NVGPU_GPU_CTXSW_TAG_LAST \ - NVGPU_GPU_CTXSW_TAG_INVALID_TIMESTAMP - -#define NVGPU_GPU_CTXSW_FILTER_ISSET(n, p) \ - ((p)->tag_bits[(n) / 64] & (1 << ((n) & 63))) - -#define NVGPU_GPU_CTXSW_FILTER_SIZE (NVGPU_GPU_CTXSW_TAG_LAST + 1) -#define NVGPU_FECS_TRACE_FEATURE_CONTROL_BIT 31 - -struct nvgpu_gpu_ctxsw_trace_filter { - u64 tag_bits[(NVGPU_GPU_CTXSW_FILTER_SIZE + 63) / 64]; -}; - -/* - * The binary format of 'struct nvgpu_gpu_ctxsw_trace_entry' introduced here - * should match that of 'struct nvgpu_ctxsw_trace_entry' defined in uapi - * header, since this struct is intended to be a mirror copy of the uapi - * struct. - */ -struct nvgpu_gpu_ctxsw_trace_entry { - u8 tag; - u8 vmid; - u16 seqno; /* sequence number to detect drops */ - u32 context_id; /* context_id as allocated by FECS */ - u64 pid; /* 64-bit is max bits of different OS pid */ - u64 timestamp; /* 64-bit time */ -}; - -int gk20a_ctxsw_trace_init(struct gk20a *g); - -void gk20a_ctxsw_trace_channel_reset(struct gk20a *g, struct channel_gk20a *ch); -void gk20a_ctxsw_trace_tsg_reset(struct gk20a *g, struct tsg_gk20a *tsg); - -void gk20a_ctxsw_trace_cleanup(struct gk20a *g); -int gk20a_ctxsw_trace_write(struct gk20a *g, - struct nvgpu_gpu_ctxsw_trace_entry *entry); -void gk20a_ctxsw_trace_wake_up(struct gk20a *g, int vmid); - -#ifdef CONFIG_GK20A_CTXSW_TRACE -struct file; -struct vm_area_struct; - -int gk20a_ctxsw_dev_mmap(struct file *filp, struct vm_area_struct *vma); -int gk20a_ctxsw_dev_ring_alloc(struct gk20a *g, void **buf, size_t *size); -int gk20a_ctxsw_dev_ring_free(struct gk20a *g); -int gk20a_ctxsw_dev_mmap_buffer(struct gk20a *g, struct vm_area_struct *vma); -#endif - -u8 nvgpu_gpu_ctxsw_tags_to_common_tags(u8 tags); - -#endif /*NVGPU_CTXSW_TRACE_H */ diff --git a/include/nvgpu/debug.h b/include/nvgpu/debug.h deleted file mode 100644 index 33bf621..0000000 --- a/include/nvgpu/debug.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * GK20A Debug functionality - * - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_DEBUG_H -#define NVGPU_DEBUG_H - -#include - -struct gk20a; -struct gpu_ops; - -struct gk20a_debug_output { - void (*fn)(void *ctx, const char *str, size_t len); - void *ctx; - char buf[256]; -}; - -#ifdef CONFIG_DEBUG_FS -extern unsigned int gk20a_debug_trace_cmdbuf; - -void gk20a_debug_output(struct gk20a_debug_output *o, - const char *fmt, ...); - -void gk20a_debug_dump(struct gk20a *g); -void gk20a_debug_show_dump(struct gk20a *g, struct gk20a_debug_output *o); -int gk20a_gr_debug_dump(struct gk20a *g); -void gk20a_init_debug_ops(struct gpu_ops *gops); - -void gk20a_debug_init(struct gk20a *g, const char *debugfs_symlink); -void gk20a_debug_deinit(struct gk20a *g); -#else -static inline void gk20a_debug_output(struct gk20a_debug_output *o, - const char *fmt, ...) {} - -static inline void gk20a_debug_dump(struct gk20a *g) {} -static inline void gk20a_debug_show_dump(struct gk20a *g, struct gk20a_debug_output *o) {} -static inline int gk20a_gr_debug_dump(struct gk20a *g) { return 0;} -static inline void gk20a_debug_init(struct gk20a *g, const char *debugfs_symlink) {} -static inline void gk20a_debug_deinit(struct gk20a *g) {} -#endif - -#endif /* NVGPU_DEBUG_H */ diff --git a/include/nvgpu/defaults.h b/include/nvgpu/defaults.h deleted file mode 100644 index cae380a..0000000 --- a/include/nvgpu/defaults.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NVGPU_DEFAULTS_H__ -#define __NVGPU_DEFAULTS_H__ - -/* - * Default timeout used for channel watchdog and ctxsw timeout. - */ -#define NVGPU_DEFAULT_GR_IDLE_TIMEOUT 3000 - -#define NVGPU_DEFAULT_RAILGATE_IDLE_TIMEOUT 500 - -#endif diff --git a/include/nvgpu/dma.h b/include/nvgpu/dma.h deleted file mode 100644 index cbb829b..0000000 --- a/include/nvgpu/dma.h +++ /dev/null @@ -1,361 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_DMA_H -#define NVGPU_DMA_H - -#include - -struct gk20a; -struct vm_gk20a; -struct nvgpu_mem; - -/* - * Flags for the below nvgpu_dma_{alloc,alloc_map}_flags* - */ - -/* - * Don't create a virtual kernel mapping for the buffer but only allocate it; - * this may save some resources. The buffer can be mapped later explicitly. - */ -#define NVGPU_DMA_NO_KERNEL_MAPPING BIT32(0) - -/* - * Don't allow building the buffer from individual pages but require a - * physically contiguous block. - */ -#define NVGPU_DMA_FORCE_CONTIGUOUS BIT32(1) - -/* - * Make the mapping read-only. - */ -#define NVGPU_DMA_READ_ONLY BIT32(2) - -/** - * nvgpu_iommuable - Check if GPU is behind IOMMU - * - * @g - The GPU. - * - * Returns true if the passed GPU is behind an IOMMU; false otherwise. If the - * GPU is iommuable then the DMA address in nvgpu_mem_sgl is valid. - * - * Note that even if a GPU is behind an IOMMU that does not necessarily mean the - * GPU _must_ use DMA addresses. GPUs may still use physical addresses if it - * makes sense. - */ -bool nvgpu_iommuable(struct gk20a *g); - -/** - * nvgpu_dma_alloc - Allocate DMA memory - * - * @g - The GPU. - * @size - Size of the allocation in bytes. - * @mem - Struct for storing the allocation information. - * - * Allocate memory suitable for doing DMA. Store the allocation info in @mem. - * Returns 0 on success and a suitable error code when there's an error. This - * memory can be either placed in VIDMEM or SYSMEM, which ever is more - * convenient for the driver. - */ -int nvgpu_dma_alloc(struct gk20a *g, size_t size, struct nvgpu_mem *mem); - -/** - * nvgpu_dma_alloc_flags - Allocate DMA memory - * - * @g - The GPU. - * @flags - Flags modifying the operation of the DMA allocation. - * @size - Size of the allocation in bytes. - * @mem - Struct for storing the allocation information. - * - * Allocate memory suitable for doing DMA. Store the allocation info in @mem. - * Returns 0 on success and a suitable error code when there's an error. This - * memory can be either placed in VIDMEM or SYSMEM, which ever is more - * convenient for the driver. - * - * The following flags are accepted: - * - * %NVGPU_DMA_NO_KERNEL_MAPPING - * %NVGPU_DMA_FORCE_CONTIGUOUS - * %NVGPU_DMA_READ_ONLY - */ -int nvgpu_dma_alloc_flags(struct gk20a *g, unsigned long flags, size_t size, - struct nvgpu_mem *mem); - -/** - * nvgpu_dma_alloc_sys - Allocate DMA memory - * - * @g - The GPU. - * @size - Size of the allocation in bytes. - * @mem - Struct for storing the allocation information. - * - * Allocate memory suitable for doing DMA. Store the allocation info in @mem. - * Returns 0 on success and a suitable error code when there's an error. This - * allocates memory specifically in SYSMEM. - */ -int nvgpu_dma_alloc_sys(struct gk20a *g, size_t size, struct nvgpu_mem *mem); - -/** - * nvgpu_dma_alloc_flags_sys - Allocate DMA memory - * - * @g - The GPU. - * @flags - Flags modifying the operation of the DMA allocation. - * @size - Size of the allocation in bytes. - * @mem - Struct for storing the allocation information. - * - * Allocate memory suitable for doing DMA. Store the allocation info in @mem. - * Returns 0 on success and a suitable error code when there's an error. This - * allocates memory specifically in SYSMEM. - * - * The following flags are accepted: - * - * %NVGPU_DMA_NO_KERNEL_MAPPING - * %NVGPU_DMA_FORCE_CONTIGUOUS - * %NVGPU_DMA_READ_ONLY - */ -int nvgpu_dma_alloc_flags_sys(struct gk20a *g, unsigned long flags, - size_t size, struct nvgpu_mem *mem); - -/** - * nvgpu_dma_alloc_vid - Allocate DMA memory - * - * @g - The GPU. - * @size - Size of the allocation in bytes. - * @mem - Struct for storing the allocation information. - * - * Allocate memory suitable for doing DMA. Store the allocation info in @mem. - * Returns 0 on success and a suitable error code when there's an error. This - * allocates memory specifically in VIDMEM. - */ -int nvgpu_dma_alloc_vid(struct gk20a *g, size_t size, struct nvgpu_mem *mem); - -/** - * nvgpu_dma_alloc_flags_vid - Allocate DMA memory - * - * @g - The GPU. - * @flags - Flags modifying the operation of the DMA allocation. - * @size - Size of the allocation in bytes. - * @mem - Struct for storing the allocation information. - * - * Allocate memory suitable for doing DMA. Store the allocation info in @mem. - * Returns 0 on success and a suitable error code when there's an error. This - * allocates memory specifically in VIDMEM. - * - * Only the following flags are accepted: - * - * %NVGPU_DMA_NO_KERNEL_MAPPING - * - */ -int nvgpu_dma_alloc_flags_vid(struct gk20a *g, unsigned long flags, - size_t size, struct nvgpu_mem *mem); - - -/** - * nvgpu_dma_alloc_flags_vid_at - Allocate DMA memory - * - * @g - The GPU. - * @size - Size of the allocation in bytes. - * @mem - Struct for storing the allocation information. - * @at - A specific location to attempt to allocate memory from or 0 if the - * caller does not care what the address is. - * - * Allocate memory suitable for doing DMA. Store the allocation info in @mem. - * Returns 0 on success and a suitable error code when there's an error. This - * allocates memory specifically in VIDMEM. - * - */ -int nvgpu_dma_alloc_vid_at(struct gk20a *g, - size_t size, struct nvgpu_mem *mem, u64 at); - -/** - * nvgpu_dma_alloc_flags_vid_at - Allocate DMA memory - * - * @g - The GPU. - * @flags - Flags modifying the operation of the DMA allocation. - * @size - Size of the allocation in bytes. - * @mem - Struct for storing the allocation information. - * @at - A specific location to attempt to allocate memory from or 0 if the - * caller does not care what the address is. - * - * Allocate memory suitable for doing DMA. Store the allocation info in @mem. - * Returns 0 on success and a suitable error code when there's an error. This - * allocates memory specifically in VIDMEM. - * - * Only the following flags are accepted: - * - * %NVGPU_DMA_NO_KERNEL_MAPPING - */ -int nvgpu_dma_alloc_flags_vid_at(struct gk20a *g, unsigned long flags, - size_t size, struct nvgpu_mem *mem, u64 at); - -/** - * nvgpu_dma_free - Free a DMA allocation - * - * @g - The GPU. - * @mem - An allocation to free. - * - * Free memory created with any of: - * - * nvgpu_dma_alloc() - * nvgpu_dma_alloc_flags() - * nvgpu_dma_alloc_sys() - * nvgpu_dma_alloc_flags_sys() - * nvgpu_dma_alloc_vid() - * nvgpu_dma_alloc_flags_vid() - * nvgpu_dma_alloc_flags_vid_at() - */ -void nvgpu_dma_free(struct gk20a *g, struct nvgpu_mem *mem); - -/** - * nvgpu_dma_alloc_map - Allocate DMA memory and map into GMMU. - * - * @vm - VM context for GMMU mapping. - * @size - Size of the allocation in bytes. - * @mem - Struct for storing the allocation information. - * - * Allocate memory suitable for doing DMA and map that memory into the GMMU. - * Note this is different than mapping it into the CPU. This memory can be - * either placed in VIDMEM or SYSMEM, which ever is more convenient for the - * driver. - * - * Note: currently a bug exists in the nvgpu_dma_alloc_map*() routines: you - * cannot use nvgpu_gmmu_map() on said buffer - it will overwrite the necessary - * information for the DMA unmap routines to actually unmap the buffer. You - * will either leak mappings or see GMMU faults. - */ -int nvgpu_dma_alloc_map(struct vm_gk20a *vm, size_t size, - struct nvgpu_mem *mem); - -/** - * nvgpu_dma_alloc_map_flags - Allocate DMA memory and map into GMMU. - * - * @vm - VM context for GMMU mapping. - * @flags - Flags modifying the operation of the DMA allocation. - * @size - Size of the allocation in bytes. - * @mem - Struct for storing the allocation information. - * - * Allocate memory suitable for doing DMA and map that memory into the GMMU. - * Note this is different than mapping it into the CPU. This memory can be - * either placed in VIDMEM or SYSMEM, which ever is more convenient for the - * driver. - * - * This version passes @flags on to the underlying DMA allocation. The accepted - * flags are: - * - * %NVGPU_DMA_NO_KERNEL_MAPPING - * %NVGPU_DMA_FORCE_CONTIGUOUS - * %NVGPU_DMA_READ_ONLY - */ -int nvgpu_dma_alloc_map_flags(struct vm_gk20a *vm, unsigned long flags, - size_t size, struct nvgpu_mem *mem); - -/** - * nvgpu_dma_alloc_map_sys - Allocate DMA memory and map into GMMU. - * - * @vm - VM context for GMMU mapping. - * @size - Size of the allocation in bytes. - * @mem - Struct for storing the allocation information. - * - * Allocate memory suitable for doing DMA and map that memory into the GMMU. - * This memory will be placed in SYSMEM. - */ -int nvgpu_dma_alloc_map_sys(struct vm_gk20a *vm, size_t size, - struct nvgpu_mem *mem); - -/** - * nvgpu_dma_alloc_map_flags_sys - Allocate DMA memory and map into GMMU. - * - * @vm - VM context for GMMU mapping. - * @flags - Flags modifying the operation of the DMA allocation. - * @size - Size of the allocation in bytes. - * @mem - Struct for storing the allocation information. - * - * Allocate memory suitable for doing DMA and map that memory into the GMMU. - * This memory will be placed in SYSMEM. - * - * This version passes @flags on to the underlying DMA allocation. The accepted - * flags are: - * - * %NVGPU_DMA_NO_KERNEL_MAPPING - * %NVGPU_DMA_FORCE_CONTIGUOUS - * %NVGPU_DMA_READ_ONLY - */ -int nvgpu_dma_alloc_map_flags_sys(struct vm_gk20a *vm, unsigned long flags, - size_t size, struct nvgpu_mem *mem); - -/** - * nvgpu_dma_alloc_map_vid - Allocate DMA memory and map into GMMU. - * - * @vm - VM context for GMMU mapping. - * @size - Size of the allocation in bytes. - * @mem - Struct for storing the allocation information. - * - * Allocate memory suitable for doing DMA and map that memory into the GMMU. - * This memory will be placed in VIDMEM. - */ -int nvgpu_dma_alloc_map_vid(struct vm_gk20a *vm, size_t size, - struct nvgpu_mem *mem); - -/** - * nvgpu_dma_alloc_map_flags_vid - Allocate DMA memory and map into GMMU. - * - * @vm - VM context for GMMU mapping. - * @flags - Flags modifying the operation of the DMA allocation. - * @size - Size of the allocation in bytes. - * @mem - Struct for storing the allocation information. - * - * Allocate memory suitable for doing DMA and map that memory into the GMMU. - * This memory will be placed in VIDMEM. - * - * This version passes @flags on to the underlying DMA allocation. The accepted - * flags are: - * - * %NVGPU_DMA_NO_KERNEL_MAPPING - * %NVGPU_DMA_FORCE_CONTIGUOUS - * %NVGPU_DMA_READ_ONLY - */ -int nvgpu_dma_alloc_map_flags_vid(struct vm_gk20a *vm, unsigned long flags, - size_t size, struct nvgpu_mem *mem); - -/** - * nvgpu_dma_unmap_free - Free a DMA allocation - * - * @g - The GPU. - * @mem - An allocation to free. - * - * Free memory created with any of: - * - * nvgpu_dma_alloc_map() - * nvgpu_dma_alloc_map_flags() - * nvgpu_dma_alloc_map_sys() - * nvgpu_dma_alloc_map_flags_sys() - * nvgpu_dma_alloc_map_vid() - * nvgpu_dma_alloc_map_flags_vid() - */ -void nvgpu_dma_unmap_free(struct vm_gk20a *vm, struct nvgpu_mem *mem); - -/* - * Don't use these directly. Instead use nvgpu_dma_free(). - */ -void nvgpu_dma_free_sys(struct gk20a *g, struct nvgpu_mem *mem); -void nvgpu_dma_free_vid(struct gk20a *g, struct nvgpu_mem *mem); - -#endif /* NVGPU_DMA_H */ diff --git a/include/nvgpu/dt.h b/include/nvgpu/dt.h deleted file mode 100644 index b5fdbfc..0000000 --- a/include/nvgpu/dt.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include - -struct gk20a; - -int nvgpu_dt_read_u32_index(struct gk20a *g, const char *name, - u32 index, u32 *value); diff --git a/include/nvgpu/ecc.h b/include/nvgpu/ecc.h deleted file mode 100644 index 9b211ef..0000000 --- a/include/nvgpu/ecc.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_ECC_H -#define NVGPU_ECC_H - -#include -#include - -#define NVGPU_ECC_STAT_NAME_MAX_SIZE 100 - -struct gk20a; - -struct nvgpu_ecc_stat { - char name[NVGPU_ECC_STAT_NAME_MAX_SIZE]; - u32 counter; - struct nvgpu_list_node node; -}; - -static inline struct nvgpu_ecc_stat *nvgpu_ecc_stat_from_node( - struct nvgpu_list_node *node) -{ - return (struct nvgpu_ecc_stat *)( - (uintptr_t)node - offsetof(struct nvgpu_ecc_stat, node) - ); -} - -struct nvgpu_ecc { - struct { - /* stats per tpc */ - - struct nvgpu_ecc_stat **sm_lrf_ecc_single_err_count; - struct nvgpu_ecc_stat **sm_lrf_ecc_double_err_count; - - struct nvgpu_ecc_stat **sm_shm_ecc_sec_count; - struct nvgpu_ecc_stat **sm_shm_ecc_sed_count; - struct nvgpu_ecc_stat **sm_shm_ecc_ded_count; - - struct nvgpu_ecc_stat **tex_ecc_total_sec_pipe0_count; - struct nvgpu_ecc_stat **tex_ecc_total_ded_pipe0_count; - struct nvgpu_ecc_stat **tex_unique_ecc_sec_pipe0_count; - struct nvgpu_ecc_stat **tex_unique_ecc_ded_pipe0_count; - struct nvgpu_ecc_stat **tex_ecc_total_sec_pipe1_count; - struct nvgpu_ecc_stat **tex_ecc_total_ded_pipe1_count; - struct nvgpu_ecc_stat **tex_unique_ecc_sec_pipe1_count; - struct nvgpu_ecc_stat **tex_unique_ecc_ded_pipe1_count; - - struct nvgpu_ecc_stat **sm_l1_tag_ecc_corrected_err_count; - struct nvgpu_ecc_stat **sm_l1_tag_ecc_uncorrected_err_count; - struct nvgpu_ecc_stat **sm_cbu_ecc_corrected_err_count; - struct nvgpu_ecc_stat **sm_cbu_ecc_uncorrected_err_count; - struct nvgpu_ecc_stat **sm_l1_data_ecc_corrected_err_count; - struct nvgpu_ecc_stat **sm_l1_data_ecc_uncorrected_err_count; - struct nvgpu_ecc_stat **sm_icache_ecc_corrected_err_count; - struct nvgpu_ecc_stat **sm_icache_ecc_uncorrected_err_count; - - /* stats per gpc */ - - struct nvgpu_ecc_stat *gcc_l15_ecc_corrected_err_count; - struct nvgpu_ecc_stat *gcc_l15_ecc_uncorrected_err_count; - - struct nvgpu_ecc_stat *gpccs_ecc_corrected_err_count; - struct nvgpu_ecc_stat *gpccs_ecc_uncorrected_err_count; - struct nvgpu_ecc_stat *mmu_l1tlb_ecc_corrected_err_count; - struct nvgpu_ecc_stat *mmu_l1tlb_ecc_uncorrected_err_count; - - /* stats per device */ - struct nvgpu_ecc_stat *fecs_ecc_corrected_err_count; - struct nvgpu_ecc_stat *fecs_ecc_uncorrected_err_count; - } gr; - - struct { - /* stats per lts */ - struct nvgpu_ecc_stat **ecc_sec_count; - struct nvgpu_ecc_stat **ecc_ded_count; - } ltc; - - struct { - /* stats per device */ - struct nvgpu_ecc_stat *mmu_l2tlb_ecc_corrected_err_count; - struct nvgpu_ecc_stat *mmu_l2tlb_ecc_uncorrected_err_count; - struct nvgpu_ecc_stat *mmu_hubtlb_ecc_corrected_err_count; - struct nvgpu_ecc_stat *mmu_hubtlb_ecc_uncorrected_err_count; - struct nvgpu_ecc_stat *mmu_fillunit_ecc_corrected_err_count; - struct nvgpu_ecc_stat *mmu_fillunit_ecc_uncorrected_err_count; - } fb; - - struct { - /* stats per device */ - struct nvgpu_ecc_stat *pmu_ecc_corrected_err_count; - struct nvgpu_ecc_stat *pmu_ecc_uncorrected_err_count; - } pmu; - - struct { - /* stats per fbpa */ - struct nvgpu_ecc_stat *fbpa_ecc_sec_err_count; - struct nvgpu_ecc_stat *fbpa_ecc_ded_err_count; - } fbpa; - - struct nvgpu_list_node stats_list; - int stats_count; -}; - -int nvgpu_ecc_counter_init_per_tpc(struct gk20a *g, - struct nvgpu_ecc_stat ***stat, const char *name); -#define NVGPU_ECC_COUNTER_INIT_PER_TPC(stat) \ - nvgpu_ecc_counter_init_per_tpc(g, &g->ecc.gr.stat, #stat) - -int nvgpu_ecc_counter_init_per_gpc(struct gk20a *g, - struct nvgpu_ecc_stat **stat, const char *name); -#define NVGPU_ECC_COUNTER_INIT_PER_GPC(stat) \ - nvgpu_ecc_counter_init_per_gpc(g, &g->ecc.gr.stat, #stat) - -int nvgpu_ecc_counter_init(struct gk20a *g, - struct nvgpu_ecc_stat **stat, const char *name); -#define NVGPU_ECC_COUNTER_INIT_GR(stat) \ - nvgpu_ecc_counter_init(g, &g->ecc.gr.stat, #stat) -#define NVGPU_ECC_COUNTER_INIT_FB(stat) \ - nvgpu_ecc_counter_init(g, &g->ecc.fb.stat, #stat) -#define NVGPU_ECC_COUNTER_INIT_PMU(stat) \ - nvgpu_ecc_counter_init(g, &g->ecc.pmu.stat, #stat) - -int nvgpu_ecc_counter_init_per_lts(struct gk20a *g, - struct nvgpu_ecc_stat ***stat, const char *name); -#define NVGPU_ECC_COUNTER_INIT_PER_LTS(stat) \ - nvgpu_ecc_counter_init_per_lts(g, &g->ecc.ltc.stat, #stat) - -int nvgpu_ecc_counter_init_per_fbpa(struct gk20a *g, - struct nvgpu_ecc_stat **stat, const char *name); -#define NVGPU_ECC_COUNTER_INIT_PER_FBPA(stat) \ - nvgpu_ecc_counter_init_per_fbpa(g, &g->ecc.fbpa.stat, #stat) - -void nvgpu_ecc_free(struct gk20a *g); - -int nvgpu_ecc_init_support(struct gk20a *g); -void nvgpu_ecc_remove_support(struct gk20a *g); - -/* OSes to implement */ - -int nvgpu_ecc_sysfs_init(struct gk20a *g); -void nvgpu_ecc_sysfs_remove(struct gk20a *g); - -#endif diff --git a/include/nvgpu/enabled.h b/include/nvgpu/enabled.h deleted file mode 100644 index 51e9358..0000000 --- a/include/nvgpu/enabled.h +++ /dev/null @@ -1,221 +0,0 @@ -/* - * Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_ENABLED_H -#define NVGPU_ENABLED_H - -struct gk20a; - -#include - -/* - * Available flags that describe what's enabled and what's not in the GPU. Each - * flag here is defined by it's offset in a bitmap. - */ -#define NVGPU_IS_FMODEL 1 -#define NVGPU_DRIVER_IS_DYING 2 -#define NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP 3 -#define NVGPU_FECS_TRACE_VA 4 -#define NVGPU_CAN_RAILGATE 5 -#define NVGPU_KERNEL_IS_DYING 6 -#define NVGPU_FECS_TRACE_FEATURE_CONTROL 7 - -/* - * ECC flags - */ -/* SM LRF ECC is enabled */ -#define NVGPU_ECC_ENABLED_SM_LRF 8 -/* SM SHM ECC is enabled */ -#define NVGPU_ECC_ENABLED_SM_SHM 9 -/* TEX ECC is enabled */ -#define NVGPU_ECC_ENABLED_TEX 10 -/* L2 ECC is enabled */ -#define NVGPU_ECC_ENABLED_LTC 11 -/* SM L1 DATA ECC is enabled */ -#define NVGPU_ECC_ENABLED_SM_L1_DATA 12 -/* SM L1 TAG ECC is enabled */ -#define NVGPU_ECC_ENABLED_SM_L1_TAG 13 -/* SM CBU ECC is enabled */ -#define NVGPU_ECC_ENABLED_SM_CBU 14 -/* SM ICAHE ECC is enabled */ -#define NVGPU_ECC_ENABLED_SM_ICACHE 15 - -/* - * MM flags. - */ -#define NVGPU_MM_UNIFY_ADDRESS_SPACES 16 -/* false if vidmem aperture actually points to sysmem */ -#define NVGPU_MM_HONORS_APERTURE 17 -/* unified or split memory with separate vidmem? */ -#define NVGPU_MM_UNIFIED_MEMORY 18 -/* User-space managed address spaces support */ -#define NVGPU_SUPPORT_USERSPACE_MANAGED_AS 20 -/* IO coherence support is available */ -#define NVGPU_SUPPORT_IO_COHERENCE 21 -/* MAP_BUFFER_EX with partial mappings */ -#define NVGPU_SUPPORT_PARTIAL_MAPPINGS 22 -/* MAP_BUFFER_EX with sparse allocations */ -#define NVGPU_SUPPORT_SPARSE_ALLOCS 23 -/* Direct PTE kind control is supported (map_buffer_ex) */ -#define NVGPU_SUPPORT_MAP_DIRECT_KIND_CTRL 24 -/* Support batch mapping */ -#define NVGPU_SUPPORT_MAP_BUFFER_BATCH 25 -/* Use coherent aperture for sysmem. */ -#define NVGPU_USE_COHERENT_SYSMEM 26 -/* Use physical scatter tables instead of IOMMU */ -#define NVGPU_MM_USE_PHYSICAL_SG 27 -/* WAR for gm20b chips. */ -#define NVGPU_MM_FORCE_128K_PMU_VM 28 -/* SW ERRATA to disable L3 alloc Bit of the physical address. - * Bit number varies between SOCs. - * E.g. 64GB physical RAM support for gv11b requires this SW errata - * to be enabled. - */ -#define NVGPU_DISABLE_L3_SUPPORT 29 -/* - * Host flags - */ -#define NVGPU_HAS_SYNCPOINTS 30 -/* sync fence FDs are available in, e.g., submit_gpfifo */ -#define NVGPU_SUPPORT_SYNC_FENCE_FDS 31 -/* NVGPU_DBG_GPU_IOCTL_CYCLE_STATS is available */ -#define NVGPU_SUPPORT_CYCLE_STATS 32 -/* NVGPU_DBG_GPU_IOCTL_CYCLE_STATS_SNAPSHOT is available */ -#define NVGPU_SUPPORT_CYCLE_STATS_SNAPSHOT 33 -/* Both gpu driver and device support TSG */ -#define NVGPU_SUPPORT_TSG 34 -/* Fast deterministic submits with no job tracking are supported */ -#define NVGPU_SUPPORT_DETERMINISTIC_SUBMIT_NO_JOBTRACKING 35 -/* Deterministic submits are supported even with job tracking */ -#define NVGPU_SUPPORT_DETERMINISTIC_SUBMIT_FULL 36 -/* NVGPU_IOCTL_CHANNEL_RESCHEDULE_RUNLIST is available */ -#define NVGPU_SUPPORT_RESCHEDULE_RUNLIST 37 - -/* NVGPU_GPU_IOCTL_GET_EVENT_FD is available */ -#define NVGPU_SUPPORT_DEVICE_EVENTS 38 -/* FECS context switch tracing is available */ -#define NVGPU_SUPPORT_FECS_CTXSW_TRACE 39 - -/* NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS is available */ -#define NVGPU_SUPPORT_DETERMINISTIC_OPTS 40 - -/* - * Security flags - */ - -#define NVGPU_SEC_SECUREGPCCS 41 -#define NVGPU_SEC_PRIVSECURITY 42 -/* VPR is supported */ -#define NVGPU_SUPPORT_VPR 43 - -/* - * Nvlink flags - */ - -#define NVGPU_SUPPORT_NVLINK 45 -/* - * PMU flags. - */ -/* perfmon enabled or disabled for PMU */ -#define NVGPU_PMU_PERFMON 48 -#define NVGPU_PMU_PSTATE 49 -#define NVGPU_PMU_ZBC_SAVE 50 -#define NVGPU_PMU_FECS_BOOTSTRAP_DONE 51 -#define NVGPU_GPU_CAN_BLCG 52 -#define NVGPU_GPU_CAN_SLCG 53 -#define NVGPU_GPU_CAN_ELCG 54 -/* Clock control support */ -#define NVGPU_SUPPORT_CLOCK_CONTROLS 55 -/* NVGPU_GPU_IOCTL_GET_VOLTAGE is available */ -#define NVGPU_SUPPORT_GET_VOLTAGE 56 -/* NVGPU_GPU_IOCTL_GET_CURRENT is available */ -#define NVGPU_SUPPORT_GET_CURRENT 57 -/* NVGPU_GPU_IOCTL_GET_POWER is available */ -#define NVGPU_SUPPORT_GET_POWER 58 -/* NVGPU_GPU_IOCTL_GET_TEMPERATURE is available */ -#define NVGPU_SUPPORT_GET_TEMPERATURE 59 -/* NVGPU_GPU_IOCTL_SET_THERM_ALERT_LIMIT is available */ -#define NVGPU_SUPPORT_SET_THERM_ALERT_LIMIT 60 - -/* whether to run PREOS binary on dGPUs */ -#define NVGPU_PMU_RUN_PREOS 61 - -/* set if ASPM is enabled; only makes sense for PCI */ -#define NVGPU_SUPPORT_ASPM 62 -/* subcontexts are available */ -#define NVGPU_SUPPORT_TSG_SUBCONTEXTS 63 -/* Simultaneous Compute and Graphics (SCG) is available */ -#define NVGPU_SUPPORT_SCG 64 - -/* GPU_VA address of a syncpoint is supported */ -#define NVGPU_SUPPORT_SYNCPOINT_ADDRESS 65 -/* Allocating per-channel syncpoint in user space is supported */ -#define NVGPU_SUPPORT_USER_SYNCPOINT 66 - -/* USERMODE enable bit */ -#define NVGPU_SUPPORT_USERMODE_SUBMIT 67 - -/* Multiple WPR support */ -#define NVGPU_SUPPORT_MULTIPLE_WPR 68 - -/* SEC2 RTOS support*/ -#define NVGPU_SUPPORT_SEC2_RTOS 69 - -/* NVGPU_GPU_IOCTL_GET_GPU_LOAD is available */ -#define NVGPU_SUPPORT_GET_GPU_LOAD 70 - -/* PLATFORM_ATOMIC support */ -#define NVGPU_SUPPORT_PLATFORM_ATOMIC 71 - -/* NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE is available */ -#define NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE 72 - -/* - * Must be greater than the largest bit offset in the above list. - */ -#define NVGPU_MAX_ENABLED_BITS 73U - -/** - * nvgpu_is_enabled - Check if the passed flag is enabled. - * - * @g - The GPU. - * @flag - Which flag to check. - * - * Returns true if the passed @flag is true; false otherwise. - */ -bool nvgpu_is_enabled(struct gk20a *g, int flag); - -/** - * __nvgpu_set_enabled - Set the state of a flag. - * - * @g - The GPU. - * @flag - Which flag to modify. - * @state - The state to set the flag to. - * - * Set the state of the passed @flag to @state. - */ -void __nvgpu_set_enabled(struct gk20a *g, int flag, bool state); - -int nvgpu_init_enabled_flags(struct gk20a *g); -void nvgpu_free_enabled_flags(struct gk20a *g); - -#endif /* NVGPU_ENABLED_H */ diff --git a/include/nvgpu/errno.h b/include/nvgpu/errno.h deleted file mode 100644 index 7e8b110..0000000 --- a/include/nvgpu/errno.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_ERRNO_H -#define NVGPU_ERRNO_H - -/* - * Explicit include to get all the -E* error messages. Useful for header files - * with static inlines that return error messages. In actual C code normally - * enough Linux/QNX headers bleed in to get the error messages but header files - * with sparse includes do not have this luxury. - */ - -#ifdef __KERNEL__ -#include -#endif - -/* - * TODO: add else path above for QNX. - */ - -#endif /* NVGPU_ERRNO_H */ diff --git a/include/nvgpu/error_notifier.h b/include/nvgpu/error_notifier.h deleted file mode 100644 index 7ba01e9..0000000 --- a/include/nvgpu/error_notifier.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_ERROR_NOTIFIER_H -#define NVGPU_ERROR_NOTIFIER_H - -#include - -struct channel_gk20a; - -enum { - NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT = 0, - NVGPU_ERR_NOTIFIER_GR_ERROR_SW_METHOD, - NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY, - NVGPU_ERR_NOTIFIER_GR_EXCEPTION, - NVGPU_ERR_NOTIFIER_GR_SEMAPHORE_TIMEOUT, - NVGPU_ERR_NOTIFIER_GR_ILLEGAL_NOTIFY, - NVGPU_ERR_NOTIFIER_FIFO_ERROR_MMU_ERR_FLT, - NVGPU_ERR_NOTIFIER_PBDMA_ERROR, - NVGPU_ERR_NOTIFIER_FECS_ERR_UNIMP_FIRMWARE_METHOD, - NVGPU_ERR_NOTIFIER_RESETCHANNEL_VERIF_ERROR, - NVGPU_ERR_NOTIFIER_PBDMA_PUSHBUFFER_CRC_MISMATCH, -}; - -void nvgpu_set_error_notifier_locked(struct channel_gk20a *ch, u32 error); -void nvgpu_set_error_notifier(struct channel_gk20a *ch, u32 error); -void nvgpu_set_error_notifier_if_empty(struct channel_gk20a *ch, u32 error); -bool nvgpu_is_error_notifier_set(struct channel_gk20a *ch, u32 error_notifier); - -#endif /* NVGPU_ERROR_NOTIFIER_H */ diff --git a/include/nvgpu/falcon.h b/include/nvgpu/falcon.h deleted file mode 100644 index 4fc97ee..0000000 --- a/include/nvgpu/falcon.h +++ /dev/null @@ -1,335 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_FALCON_H -#define NVGPU_FALCON_H - -#include -#include - -/* - * Falcon Id Defines - */ -#define FALCON_ID_PMU (0U) -#define FALCON_ID_GSPLITE (1U) -#define FALCON_ID_FECS (2U) -#define FALCON_ID_GPCCS (3U) -#define FALCON_ID_NVDEC (4U) -#define FALCON_ID_SEC2 (7U) -#define FALCON_ID_MINION (10U) - -/* - * Falcon Base address Defines - */ -#define FALCON_NVDEC_BASE 0x00084000 -#define FALCON_PWR_BASE 0x0010a000 -#define FALCON_SEC_BASE 0x00087000 -#define FALCON_FECS_BASE 0x00409000 -#define FALCON_GPCCS_BASE 0x0041a000 - -/* Falcon Register index */ -#define FALCON_REG_R0 (0) -#define FALCON_REG_R1 (1) -#define FALCON_REG_R2 (2) -#define FALCON_REG_R3 (3) -#define FALCON_REG_R4 (4) -#define FALCON_REG_R5 (5) -#define FALCON_REG_R6 (6) -#define FALCON_REG_R7 (7) -#define FALCON_REG_R8 (8) -#define FALCON_REG_R9 (9) -#define FALCON_REG_R10 (10) -#define FALCON_REG_R11 (11) -#define FALCON_REG_R12 (12) -#define FALCON_REG_R13 (13) -#define FALCON_REG_R14 (14) -#define FALCON_REG_R15 (15) -#define FALCON_REG_IV0 (16) -#define FALCON_REG_IV1 (17) -#define FALCON_REG_UNDEFINED (18) -#define FALCON_REG_EV (19) -#define FALCON_REG_SP (20) -#define FALCON_REG_PC (21) -#define FALCON_REG_IMB (22) -#define FALCON_REG_DMB (23) -#define FALCON_REG_CSW (24) -#define FALCON_REG_CCR (25) -#define FALCON_REG_SEC (26) -#define FALCON_REG_CTX (27) -#define FALCON_REG_EXCI (28) -#define FALCON_REG_RSVD0 (29) -#define FALCON_REG_RSVD1 (30) -#define FALCON_REG_RSVD2 (31) -#define FALCON_REG_SIZE (32) - -#define FALCON_MAILBOX_0 0x0 -#define FALCON_MAILBOX_1 0x1 -#define FALCON_MAILBOX_COUNT 0x02 -#define FALCON_BLOCK_SIZE 0x100U - -#define GET_IMEM_TAG(IMEM_ADDR) (IMEM_ADDR >> 8) - -#define GET_NEXT_BLOCK(ADDR) \ - ((((ADDR + (FALCON_BLOCK_SIZE - 1)) & ~(FALCON_BLOCK_SIZE-1)) \ - / FALCON_BLOCK_SIZE) << 8) - -/* - * Falcon HWCFG request read types defines - */ -enum flcn_hwcfg_read { - FALCON_IMEM_SIZE = 0, - FALCON_DMEM_SIZE, - FALCON_CORE_REV, - FALCON_SECURITY_MODEL, - FLACON_MAILBOX_COUNT -}; - -/* - * Falcon HWCFG request write types defines - */ -enum flcn_hwcfg_write { - FALCON_STARTCPU = 0, - FALCON_STARTCPU_SECURE, - FALCON_BOOTVEC, - FALCON_ITF_EN -}; - -#define FALCON_MEM_SCRUBBING_TIMEOUT_MAX 1000 -#define FALCON_MEM_SCRUBBING_TIMEOUT_DEFAULT 10 - -enum flcn_dma_dir { - DMA_TO_FB = 0, - DMA_FROM_FB -}; - -enum flcn_mem_type { - MEM_DMEM = 0, - MEM_IMEM -}; - -/* Falcon ucode header format - * OS Code Offset - * OS Code Size - * OS Data Offset - * OS Data Size - * NumApps (N) - * App 0 Code Offset - * App 0 Code Size - * . . . . - * App N - 1 Code Offset - * App N - 1 Code Size - * App 0 Data Offset - * App 0 Data Size - * . . . . - * App N - 1 Data Offset - * App N - 1 Data Size - * OS Ovl Offset - * OS Ovl Size -*/ -#define OS_CODE_OFFSET 0x0 -#define OS_CODE_SIZE 0x1 -#define OS_DATA_OFFSET 0x2 -#define OS_DATA_SIZE 0x3 -#define NUM_APPS 0x4 -#define APP_0_CODE_OFFSET 0x5 -#define APP_0_CODE_SIZE 0x6 - -struct nvgpu_falcon_dma_info { - u32 fb_base; - u32 fb_off; - u32 flcn_mem_off; - u32 size_in_bytes; - enum flcn_dma_dir dir; - u32 ctx_dma; - enum flcn_mem_type flcn_mem; - u32 is_wait_complete; -}; - -struct gk20a; -struct nvgpu_falcon; -struct nvgpu_falcon_bl_info; - -/* Queue Type */ -#define QUEUE_TYPE_DMEM 0x0U -#define QUEUE_TYPE_EMEM 0x1U - -struct nvgpu_falcon_queue { - - /* Queue Type (queue_type) */ - u8 queue_type; - - /* used by nvgpu, for command LPQ/HPQ */ - struct nvgpu_mutex mutex; - - /* current write position */ - u32 position; - /* physical dmem offset where this queue begins */ - u32 offset; - /* logical queue identifier */ - u32 id; - /* physical queue index */ - u32 index; - /* in bytes */ - u32 size; - /* open-flag */ - u32 oflag; - - /* queue type(DMEM-Q/FB-Q) specific ops */ - int (*rewind)(struct nvgpu_falcon *flcn, - struct nvgpu_falcon_queue *queue); - int (*pop)(struct nvgpu_falcon *flcn, - struct nvgpu_falcon_queue *queue, void *data, u32 size, - u32 *bytes_read); - int (*push)(struct nvgpu_falcon *flcn, - struct nvgpu_falcon_queue *queue, void *data, u32 size); - bool (*has_room)(struct nvgpu_falcon *flcn, - struct nvgpu_falcon_queue *queue, u32 size, - bool *need_rewind); - int (*tail)(struct nvgpu_falcon *flcn, - struct nvgpu_falcon_queue *queue, u32 *tail, bool set); - int (*head)(struct nvgpu_falcon *flcn, - struct nvgpu_falcon_queue *queue, u32 *head, bool set); -}; - -struct nvgpu_falcon_version_ops { - void (*start_cpu_secure)(struct nvgpu_falcon *flcn); - void (*write_dmatrfbase)(struct nvgpu_falcon *flcn, u32 addr); -}; - -/* ops which are falcon engine specific */ -struct nvgpu_falcon_engine_dependency_ops { - int (*reset_eng)(struct gk20a *g); - int (*queue_head)(struct gk20a *g, struct nvgpu_falcon_queue *queue, - u32 *head, bool set); - int (*queue_tail)(struct gk20a *g, struct nvgpu_falcon_queue *queue, - u32 *tail, bool set); - void (*msgq_tail)(struct gk20a *g, u32 *tail, bool set); - int (*copy_from_emem)(struct nvgpu_falcon *flcn, u32 src, u8 *dst, - u32 size, u8 port); - int (*copy_to_emem)(struct nvgpu_falcon *flcn, u32 dst, u8 *src, - u32 size, u8 port); -}; - -struct nvgpu_falcon_ops { - int (*reset)(struct nvgpu_falcon *flcn); - void (*set_irq)(struct nvgpu_falcon *flcn, bool enable); - bool (*clear_halt_interrupt_status)(struct nvgpu_falcon *flcn); - bool (*is_falcon_cpu_halted)(struct nvgpu_falcon *flcn); - bool (*is_falcon_idle)(struct nvgpu_falcon *flcn); - bool (*is_falcon_scrubbing_done)(struct nvgpu_falcon *flcn); - int (*copy_from_dmem)(struct nvgpu_falcon *flcn, u32 src, u8 *dst, - u32 size, u8 port); - int (*copy_to_dmem)(struct nvgpu_falcon *flcn, u32 dst, u8 *src, - u32 size, u8 port); - int (*copy_from_imem)(struct nvgpu_falcon *flcn, u32 src, u8 *dst, - u32 size, u8 port); - int (*copy_to_imem)(struct nvgpu_falcon *flcn, u32 dst, u8 *src, - u32 size, u8 port, bool sec, u32 tag); - int (*dma_copy)(struct nvgpu_falcon *flcn, - struct nvgpu_falcon_dma_info *dma_info); - u32 (*mailbox_read)(struct nvgpu_falcon *flcn, u32 mailbox_index); - void (*mailbox_write)(struct nvgpu_falcon *flcn, u32 mailbox_index, - u32 data); - int (*bootstrap)(struct nvgpu_falcon *flcn, u32 boot_vector); - void (*dump_falcon_stats)(struct nvgpu_falcon *flcn); - int (*bl_bootstrap)(struct nvgpu_falcon *flcn, - struct nvgpu_falcon_bl_info *bl_info); -}; - -struct nvgpu_falcon_bl_info { - void *bl_src; - u8 *bl_desc; - u32 bl_desc_size; - u32 bl_size; - u32 bl_start_tag; -}; - -struct nvgpu_falcon { - struct gk20a *g; - u32 flcn_id; - u32 flcn_base; - u32 flcn_core_rev; - bool is_falcon_supported; - bool is_interrupt_enabled; - u32 intr_mask; - u32 intr_dest; - bool isr_enabled; - struct nvgpu_mutex isr_mutex; - struct nvgpu_mutex copy_lock; - struct nvgpu_falcon_ops flcn_ops; - struct nvgpu_falcon_version_ops flcn_vops; - struct nvgpu_falcon_engine_dependency_ops flcn_engine_dep_ops; -}; - -int nvgpu_flcn_wait_idle(struct nvgpu_falcon *flcn); -int nvgpu_flcn_wait_for_halt(struct nvgpu_falcon *flcn, unsigned int timeout); -int nvgpu_flcn_clear_halt_intr_status(struct nvgpu_falcon *flcn, - unsigned int timeout); -int nvgpu_flcn_reset(struct nvgpu_falcon *flcn); -void nvgpu_flcn_set_irq(struct nvgpu_falcon *flcn, bool enable, - u32 intr_mask, u32 intr_dest); -bool nvgpu_flcn_get_mem_scrubbing_status(struct nvgpu_falcon *flcn); -int nvgpu_flcn_mem_scrub_wait(struct nvgpu_falcon *flcn); -bool nvgpu_flcn_get_cpu_halted_status(struct nvgpu_falcon *flcn); -bool nvgpu_flcn_get_idle_status(struct nvgpu_falcon *flcn); -int nvgpu_flcn_copy_from_emem(struct nvgpu_falcon *flcn, - u32 src, u8 *dst, u32 size, u8 port); -int nvgpu_flcn_copy_to_emem(struct nvgpu_falcon *flcn, - u32 dst, u8 *src, u32 size, u8 port); -int nvgpu_flcn_copy_from_dmem(struct nvgpu_falcon *flcn, - u32 src, u8 *dst, u32 size, u8 port); -int nvgpu_flcn_copy_to_dmem(struct nvgpu_falcon *flcn, - u32 dst, u8 *src, u32 size, u8 port); -int nvgpu_flcn_copy_to_imem(struct nvgpu_falcon *flcn, - u32 dst, u8 *src, u32 size, u8 port, bool sec, u32 tag); -int nvgpu_flcn_copy_from_imem(struct nvgpu_falcon *flcn, - u32 src, u8 *dst, u32 size, u8 port); -int nvgpu_flcn_dma_copy(struct nvgpu_falcon *flcn, - struct nvgpu_falcon_dma_info *dma_info); -u32 nvgpu_flcn_mailbox_read(struct nvgpu_falcon *flcn, u32 mailbox_index); -void nvgpu_flcn_mailbox_write(struct nvgpu_falcon *flcn, u32 mailbox_index, - u32 data); -int nvgpu_flcn_bootstrap(struct nvgpu_falcon *flcn, u32 boot_vector); -void nvgpu_flcn_print_dmem(struct nvgpu_falcon *flcn, u32 src, u32 size); -void nvgpu_flcn_print_imem(struct nvgpu_falcon *flcn, u32 src, u32 size); -void nvgpu_flcn_dump_stats(struct nvgpu_falcon *flcn); -int nvgpu_flcn_bl_bootstrap(struct nvgpu_falcon *flcn, - struct nvgpu_falcon_bl_info *bl_info); - -/* queue public functions */ -int nvgpu_flcn_queue_init(struct nvgpu_falcon *flcn, - struct nvgpu_falcon_queue *queue); -bool nvgpu_flcn_queue_is_empty(struct nvgpu_falcon *flcn, - struct nvgpu_falcon_queue *queue); -int nvgpu_flcn_queue_rewind(struct nvgpu_falcon *flcn, - struct nvgpu_falcon_queue *queue); -int nvgpu_flcn_queue_pop(struct nvgpu_falcon *flcn, - struct nvgpu_falcon_queue *queue, void *data, u32 size, - u32 *bytes_read); -int nvgpu_flcn_queue_push(struct nvgpu_falcon *flcn, - struct nvgpu_falcon_queue *queue, void *data, u32 size); -void nvgpu_flcn_queue_free(struct nvgpu_falcon *flcn, - struct nvgpu_falcon_queue *queue); - -int nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id); - -#endif /* NVGPU_FALCON_H */ diff --git a/include/nvgpu/fecs_trace.h b/include/nvgpu/fecs_trace.h deleted file mode 100644 index 5dc3530..0000000 --- a/include/nvgpu/fecs_trace.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_FECS_TRACE_H -#define NVGPU_FECS_TRACE_H - -struct gk20a; - -/* - * If HW circular buffer is getting too many "buffer full" conditions, - * increasing this constant should help (it drives Linux' internal buffer size). - */ -#define GK20A_FECS_TRACE_NUM_RECORDS (1 << 10) -#define GK20A_FECS_TRACE_HASH_BITS 8 /* 2^8 */ -#define GK20A_FECS_TRACE_FRAME_PERIOD_US (1000000ULL/60ULL) -#define GK20A_FECS_TRACE_PTIMER_SHIFT 5 - -struct gk20a_fecs_trace_record { - u32 magic_lo; - u32 magic_hi; - u32 context_id; - u32 context_ptr; - u32 new_context_id; - u32 new_context_ptr; - u64 ts[]; -}; - -#ifdef CONFIG_GK20A_CTXSW_TRACE -u32 gk20a_fecs_trace_record_ts_tag_invalid_ts_v(void); -u32 gk20a_fecs_trace_record_ts_tag_v(u64 ts); -u64 gk20a_fecs_trace_record_ts_timestamp_v(u64 ts); -int gk20a_fecs_trace_num_ts(void); -struct gk20a_fecs_trace_record *gk20a_fecs_trace_get_record(struct gk20a *g, - int idx); -bool gk20a_fecs_trace_is_valid_record(struct gk20a_fecs_trace_record *r); -int gk20a_fecs_trace_get_read_index(struct gk20a *g); -int gk20a_fecs_trace_get_write_index(struct gk20a *g); - -#endif /* CONFIG_GK20A_CTXSW_TRACE */ - -#endif diff --git a/include/nvgpu/firmware.h b/include/nvgpu/firmware.h deleted file mode 100644 index 54d6795..0000000 --- a/include/nvgpu/firmware.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_FIRMWARE_H -#define NVGPU_FIRMWARE_H - -#include - -struct gk20a; - -#define NVGPU_REQUEST_FIRMWARE_NO_WARN (1UL << 0) -#define NVGPU_REQUEST_FIRMWARE_NO_SOC (1UL << 1) - -struct nvgpu_firmware { - u8 *data; - size_t size; -}; - -/** - * nvgpu_request_firmware - load a firmware blob from filesystem. - * - * @g The GPU driver struct for device to load firmware for - * @fw_name The base name of the firmware file. - * @flags Flags for loading; - * - * NVGPU_REQUEST_FIRMWARE_NO_WARN: Do not display warning on - * failed load. - * - * NVGPU_REQUEST_FIRMWARE_NO_SOC: Do not attempt loading from - * path . - * - * nvgpu_request_firmware() will load firmware from: - * - * // - * - * If that fails and NO_SOC is not enabled, it'll try next from: - * - * // - * - * It'll allocate a nvgpu_firmware structure and initializes it and returns - * it to caller. - */ -struct nvgpu_firmware *nvgpu_request_firmware(struct gk20a *g, - const char *fw_name, - int flags); - -/** - * nvgpu_release_firmware - free firmware and associated nvgpu_firmware blob - * - * @g The GPU driver struct for device to free firmware for - * @fw The firmware to free. fw blob will also be freed. - */ -void nvgpu_release_firmware(struct gk20a *g, struct nvgpu_firmware *fw); - -#endif /* NVGPU_FIRMWARE_H */ diff --git a/include/nvgpu/flcnif_cmn.h b/include/nvgpu/flcnif_cmn.h deleted file mode 100644 index 273da1e..0000000 --- a/include/nvgpu/flcnif_cmn.h +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_FLCNIF_CMN_H -#define NVGPU_FLCNIF_CMN_H - -#define PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED 0 - -struct falc_u64 { - u32 lo; - u32 hi; -}; - -struct falc_dma_addr { - u32 dma_base; - /* - * dma_base1 is 9-bit MSB for FB Base - * address for the transfer in FB after - * address using 49b FB address - */ - u16 dma_base1; - u8 dma_offset; -}; - -struct pmu_mem_v1 { - u32 dma_base; - u8 dma_offset; - u8 dma_idx; - u16 fb_size; -}; - -struct pmu_mem_desc_v0 { - struct falc_u64 dma_addr; - u16 dma_sizemax; - u8 dma_idx; -}; - -struct pmu_dmem { - u16 size; - u32 offset; -}; - -struct flcn_mem_desc_v0 { - struct falc_u64 address; - u32 params; -}; - -#define nv_flcn_mem_desc flcn_mem_desc_v0 - -struct pmu_allocation_v1 { - struct { - struct pmu_dmem dmem; - struct pmu_mem_v1 fb; - } alloc; -}; - -struct pmu_allocation_v2 { - struct { - struct pmu_dmem dmem; - struct pmu_mem_desc_v0 fb; - } alloc; -}; - -struct pmu_allocation_v3 { - struct { - struct pmu_dmem dmem; - struct flcn_mem_desc_v0 fb; - } alloc; -}; - -#define nv_pmu_allocation pmu_allocation_v3 - -struct pmu_hdr { - u8 unit_id; - u8 size; - u8 ctrl_flags; - u8 seq_id; -}; - -#define NV_FLCN_UNIT_ID_REWIND (0x00U) - -#define PMU_MSG_HDR_SIZE sizeof(struct pmu_hdr) -#define PMU_CMD_HDR_SIZE sizeof(struct pmu_hdr) - -#define nv_pmu_hdr pmu_hdr -typedef u8 flcn_status; - -#define PMU_DMEM_ALLOC_ALIGNMENT (32) -#define PMU_DMEM_ALIGNMENT (4) - -#define PMU_CMD_FLAGS_PMU_MASK (0xF0) - -#define PMU_CMD_FLAGS_STATUS BIT(0) -#define PMU_CMD_FLAGS_INTR BIT(1) -#define PMU_CMD_FLAGS_EVENT BIT(2) -#define PMU_CMD_FLAGS_WATERMARK BIT(3) - -#define ALIGN_UP(v, gran) (((v) + ((gran) - 1)) & ~((gran)-1)) - -#define NV_UNSIGNED_ROUNDED_DIV(a, b) (((a) + ((b) / 2)) / (b)) - -#endif /* NVGPU_FLCNIF_CMN_H */ diff --git a/include/nvgpu/fuse.h b/include/nvgpu/fuse.h deleted file mode 100644 index 1d459a9..0000000 --- a/include/nvgpu/fuse.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_FUSE_H -#define NVGPU_FUSE_H - -struct gk20a; - -#include - -int nvgpu_tegra_get_gpu_speedo_id(struct gk20a *g); - -void nvgpu_tegra_fuse_write_bypass(struct gk20a *g, u32 val); -void nvgpu_tegra_fuse_write_access_sw(struct gk20a *g, u32 val); -void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(struct gk20a *g, u32 val); -void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(struct gk20a *g, u32 val); -int nvgpu_tegra_fuse_read_gcplex_config_fuse(struct gk20a *g, u32 *val); -int nvgpu_tegra_fuse_read_reserved_calib(struct gk20a *g, u32 *val); - -#endif /* NVGPU_FUSE_H */ diff --git a/include/nvgpu/gk20a.h b/include/nvgpu/gk20a.h deleted file mode 100644 index 19bfaee..0000000 --- a/include/nvgpu/gk20a.h +++ /dev/null @@ -1,1807 +0,0 @@ -/* - * Copyright (c) 2011-2022, NVIDIA CORPORATION. All rights reserved. - * - * GK20A Graphics - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef GK20A_H -#define GK20A_H - -struct gk20a; -struct fifo_gk20a; -struct channel_gk20a; -struct gr_gk20a; -struct sim_nvgpu; -struct gk20a_ctxsw_ucode_segments; -struct gk20a_fecs_trace; -struct gk20a_ctxsw_trace; -struct acr_desc; -struct nvgpu_mem_alloc_tracker; -struct dbg_profiler_object_data; -struct gk20a_debug_output; -struct nvgpu_clk_pll_debug_data; -struct nvgpu_nvhost_dev; -struct nvgpu_cpu_time_correlation_sample; -struct nvgpu_mem_sgt; -struct nvgpu_warpstate; -struct nvgpu_clk_session; -struct nvgpu_clk_arb; -#ifdef CONFIG_GK20A_CTXSW_TRACE -struct nvgpu_gpu_ctxsw_trace_filter; -#endif -struct priv_cmd_entry; -struct nvgpu_setup_bind_args; - -#ifdef __KERNEL__ -#include -#endif -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "gk20a/clk_gk20a.h" -#include "gk20a/ce2_gk20a.h" -#include "gk20a/fifo_gk20a.h" -#include "clk/clk.h" -#include "pmu_perf/pmu_perf.h" -#include "pmgr/pmgr.h" -#include "therm/thrm.h" - -#ifdef CONFIG_DEBUG_FS -struct railgate_stats { - unsigned long last_rail_gate_start; - unsigned long last_rail_gate_complete; - unsigned long last_rail_ungate_start; - unsigned long last_rail_ungate_complete; - unsigned long total_rail_gate_time_ms; - unsigned long total_rail_ungate_time_ms; - unsigned long railgating_cycle_count; -}; -#endif - -enum gk20a_cbc_op { - gk20a_cbc_op_clear, - gk20a_cbc_op_clean, - gk20a_cbc_op_invalidate, -}; - -#define MC_INTR_UNIT_DISABLE false -#define MC_INTR_UNIT_ENABLE true - -#define GPU_LIT_NUM_GPCS 0 -#define GPU_LIT_NUM_PES_PER_GPC 1 -#define GPU_LIT_NUM_ZCULL_BANKS 2 -#define GPU_LIT_NUM_TPC_PER_GPC 3 -#define GPU_LIT_NUM_SM_PER_TPC 4 -#define GPU_LIT_NUM_FBPS 5 -#define GPU_LIT_GPC_BASE 6 -#define GPU_LIT_GPC_STRIDE 7 -#define GPU_LIT_GPC_SHARED_BASE 8 -#define GPU_LIT_TPC_IN_GPC_BASE 9 -#define GPU_LIT_TPC_IN_GPC_STRIDE 10 -#define GPU_LIT_TPC_IN_GPC_SHARED_BASE 11 -#define GPU_LIT_PPC_IN_GPC_BASE 12 -#define GPU_LIT_PPC_IN_GPC_STRIDE 13 -#define GPU_LIT_PPC_IN_GPC_SHARED_BASE 14 -#define GPU_LIT_ROP_BASE 15 -#define GPU_LIT_ROP_STRIDE 16 -#define GPU_LIT_ROP_SHARED_BASE 17 -#define GPU_LIT_HOST_NUM_ENGINES 18 -#define GPU_LIT_HOST_NUM_PBDMA 19 -#define GPU_LIT_LTC_STRIDE 20 -#define GPU_LIT_LTS_STRIDE 21 -#define GPU_LIT_NUM_FBPAS 22 -#define GPU_LIT_FBPA_STRIDE 23 -#define GPU_LIT_FBPA_BASE 24 -#define GPU_LIT_FBPA_SHARED_BASE 25 -#define GPU_LIT_SM_PRI_STRIDE 26 -#define GPU_LIT_SMPC_PRI_BASE 27 -#define GPU_LIT_SMPC_PRI_SHARED_BASE 28 -#define GPU_LIT_SMPC_PRI_UNIQUE_BASE 29 -#define GPU_LIT_SMPC_PRI_STRIDE 30 -#define GPU_LIT_TWOD_CLASS 31 -#define GPU_LIT_THREED_CLASS 32 -#define GPU_LIT_COMPUTE_CLASS 33 -#define GPU_LIT_GPFIFO_CLASS 34 -#define GPU_LIT_I2M_CLASS 35 -#define GPU_LIT_DMA_COPY_CLASS 36 -#define GPU_LIT_GPC_PRIV_STRIDE 37 -#define GPU_LIT_PERFMON_PMMGPCTPCA_DOMAIN_START 38 -#define GPU_LIT_PERFMON_PMMGPCTPCB_DOMAIN_START 39 -#define GPU_LIT_PERFMON_PMMGPCTPC_DOMAIN_COUNT 40 -#define GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_START 41 -#define GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_COUNT 42 -#define GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_START 43 -#define GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_COUNT 44 - -#define nvgpu_get_litter_value(g, v) (g)->ops.get_litter_value((g), v) - -#define MAX_TPC_PG_CONFIGS 9 - -enum nvgpu_unit; - -enum nvgpu_flush_op; -enum gk20a_mem_rw_flag; - -struct _resmgr_context; -struct nvgpu_gpfifo_entry; - -struct nvgpu_gpfifo_userdata { - struct nvgpu_gpfifo_entry __user *entries; - struct _resmgr_context *context; -}; - -/* - * gpu_ops should only contain function pointers! Non-function pointer members - * should go in struct gk20a or be implemented with the boolean flag API defined - * in nvgpu/enabled.h - */ - -/* index for FB fault buffer functions */ -#define NVGPU_FB_MMU_FAULT_NONREPLAY_REG_INDEX 0U -#define NVGPU_FB_MMU_FAULT_REPLAY_REG_INDEX 1U -#define NVGPU_FB_MMU_FAULT_BUF_DISABLED 0U -#define NVGPU_FB_MMU_FAULT_BUF_ENABLED 1U - -/* Parameters for init_elcg_mode/init_blcg_mode */ -enum { - ELCG_RUN, /* clk always run, i.e. disable elcg */ - ELCG_STOP, /* clk is stopped */ - ELCG_AUTO /* clk will run when non-idle, standard elcg mode */ -}; - -enum { - BLCG_RUN, /* clk always run, i.e. disable blcg */ - BLCG_AUTO /* clk will run when non-idle, standard blcg mode */ -}; - -struct gpu_ops { - struct { - int (*determine_L2_size_bytes)(struct gk20a *gk20a); - u64 (*get_cbc_base_divisor)(struct gk20a *g); - int (*init_comptags)(struct gk20a *g, struct gr_gk20a *gr); - int (*cbc_ctrl)(struct gk20a *g, enum gk20a_cbc_op op, - u32 min, u32 max); - void (*set_zbc_color_entry)(struct gk20a *g, - struct zbc_entry *color_val, - u32 index); - void (*set_zbc_depth_entry)(struct gk20a *g, - struct zbc_entry *depth_val, - u32 index); - void (*set_zbc_s_entry)(struct gk20a *g, - struct zbc_entry *s_val, - u32 index); - void (*init_cbc)(struct gk20a *g, struct gr_gk20a *gr); - void (*set_enabled)(struct gk20a *g, bool enabled); - void (*init_fs_state)(struct gk20a *g); - void (*isr)(struct gk20a *g); - u32 (*cbc_fix_config)(struct gk20a *g, int base); - void (*flush)(struct gk20a *g); - void (*intr_en_illegal_compstat)(struct gk20a *g, bool enable); - bool (*pri_is_ltc_addr)(struct gk20a *g, u32 addr); - bool (*is_ltcs_ltss_addr)(struct gk20a *g, u32 addr); - bool (*is_ltcn_ltss_addr)(struct gk20a *g, u32 addr); - void (*split_lts_broadcast_addr)(struct gk20a *g, u32 addr, - u32 *priv_addr_table, - u32 *priv_addr_table_index); - void (*split_ltc_broadcast_addr)(struct gk20a *g, u32 addr, - u32 *priv_addr_table, - u32 *priv_addr_table_index); - } ltc; - struct { - void (*isr_stall)(struct gk20a *g, u32 inst_id, u32 pri_base); - u32 (*isr_nonstall)(struct gk20a *g, u32 inst_id, u32 pri_base); - u32 (*get_num_pce)(struct gk20a *g); - void (*init_prod_values)(struct gk20a *g); - } ce2; - struct { - u32 (*get_patch_slots)(struct gk20a *g); - int (*init_fs_state)(struct gk20a *g); - int (*init_preemption_state)(struct gk20a *g); - void (*access_smpc_reg)(struct gk20a *g, u32 quad, u32 offset); - void (*bundle_cb_defaults)(struct gk20a *g); - void (*cb_size_default)(struct gk20a *g); - int (*calc_global_ctx_buffer_size)(struct gk20a *g); - void (*commit_global_attrib_cb)(struct gk20a *g, - struct nvgpu_gr_ctx *ch_ctx, - u64 addr, bool patch); - void (*commit_global_bundle_cb)(struct gk20a *g, - struct nvgpu_gr_ctx *ch_ctx, - u64 addr, u64 size, bool patch); - int (*commit_global_cb_manager)(struct gk20a *g, - struct channel_gk20a *ch, - bool patch); - void (*commit_global_pagepool)(struct gk20a *g, - struct nvgpu_gr_ctx *ch_ctx, - u64 addr, u32 size, bool patch); - void (*init_gpc_mmu)(struct gk20a *g); - int (*handle_sw_method)(struct gk20a *g, u32 addr, - u32 class_num, u32 offset, u32 data); - void (*set_alpha_circular_buffer_size)(struct gk20a *g, - u32 data); - void (*set_circular_buffer_size)(struct gk20a *g, u32 data); - void (*set_bes_crop_debug3)(struct gk20a *g, u32 data); - void (*set_bes_crop_debug4)(struct gk20a *g, u32 data); - void (*enable_hww_exceptions)(struct gk20a *g); - bool (*is_valid_class)(struct gk20a *g, u32 class_num); - bool (*is_valid_gfx_class)(struct gk20a *g, u32 class_num); - bool (*is_valid_compute_class)(struct gk20a *g, u32 class_num); - void (*get_sm_dsm_perf_regs)(struct gk20a *g, - u32 *num_sm_dsm_perf_regs, - u32 **sm_dsm_perf_regs, - u32 *perf_register_stride); - void (*get_sm_dsm_perf_ctrl_regs)(struct gk20a *g, - u32 *num_sm_dsm_perf_regs, - u32 **sm_dsm_perf_regs, - u32 *perf_register_stride); - void (*get_ovr_perf_regs)(struct gk20a *g, - u32 *num_ovr_perf_regs, - u32 **ovr_perf_regsr); - void (*set_hww_esr_report_mask)(struct gk20a *g); - int (*setup_alpha_beta_tables)(struct gk20a *g, - struct gr_gk20a *gr); - int (*falcon_load_ucode)(struct gk20a *g, - u64 addr_base, - struct gk20a_ctxsw_ucode_segments *segments, - u32 reg_offset); - int (*load_ctxsw_ucode)(struct gk20a *g); - u32 (*get_gpc_mask)(struct gk20a *g); - u32 (*get_gpc_tpc_mask)(struct gk20a *g, u32 gpc_index); - void (*set_gpc_tpc_mask)(struct gk20a *g, u32 gpc_index); - int (*alloc_obj_ctx)(struct channel_gk20a *c, - u32 class_num, u32 flags); - int (*bind_ctxsw_zcull)(struct gk20a *g, struct gr_gk20a *gr, - struct channel_gk20a *c, u64 zcull_va, - u32 mode); - int (*get_zcull_info)(struct gk20a *g, struct gr_gk20a *gr, - struct gr_zcull_info *zcull_params); - int (*decode_egpc_addr)(struct gk20a *g, - u32 addr, enum ctxsw_addr_type *addr_type, - u32 *gpc_num, u32 *tpc_num, u32 *broadcast_flags); - void (*egpc_etpc_priv_addr_table)(struct gk20a *g, u32 addr, - u32 gpc, u32 tpc, u32 broadcast_flags, - u32 *priv_addr_table, - u32 *priv_addr_table_index); - bool (*is_tpc_addr)(struct gk20a *g, u32 addr); - bool (*is_egpc_addr)(struct gk20a *g, u32 addr); - bool (*is_etpc_addr)(struct gk20a *g, u32 addr); - void (*get_egpc_etpc_num)(struct gk20a *g, u32 addr, - u32 *gpc_num, u32 *tpc_num); - u32 (*get_tpc_num)(struct gk20a *g, u32 addr); - u32 (*get_egpc_base)(struct gk20a *g); - void (*detect_sm_arch)(struct gk20a *g); - int (*add_zbc_color)(struct gk20a *g, struct gr_gk20a *gr, - struct zbc_entry *color_val, u32 index); - int (*add_zbc_depth)(struct gk20a *g, struct gr_gk20a *gr, - struct zbc_entry *depth_val, u32 index); - int (*add_zbc_s)(struct gk20a *g, struct gr_gk20a *gr, - struct zbc_entry *s_val, u32 index); - int (*zbc_set_table)(struct gk20a *g, struct gr_gk20a *gr, - struct zbc_entry *zbc_val); - int (*zbc_query_table)(struct gk20a *g, struct gr_gk20a *gr, - struct zbc_query_params *query_params); - int (*zbc_s_query_table)(struct gk20a *g, struct gr_gk20a *gr, - struct zbc_query_params *query_params); - int (*load_zbc_s_default_tbl)(struct gk20a *g, - struct gr_gk20a *gr); - int (*load_zbc_s_tbl)(struct gk20a *g, - struct gr_gk20a *gr); - void (*pmu_save_zbc)(struct gk20a *g, u32 entries); - int (*add_zbc)(struct gk20a *g, struct gr_gk20a *gr, - struct zbc_entry *zbc_val); - bool (*add_zbc_type_s)(struct gk20a *g, struct gr_gk20a *gr, - struct zbc_entry *zbc_val, int *ret_val); - u32 (*pagepool_default_size)(struct gk20a *g); - int (*init_ctx_state)(struct gk20a *g); - int (*alloc_gr_ctx)(struct gk20a *g, - struct nvgpu_gr_ctx *gr_ctx, struct vm_gk20a *vm, - u32 class, u32 padding); - void (*free_gr_ctx)(struct gk20a *g, - struct vm_gk20a *vm, struct nvgpu_gr_ctx *gr_ctx); - void (*powergate_tpc)(struct gk20a *g); - void (*update_ctxsw_preemption_mode)(struct gk20a *g, - struct channel_gk20a *c, - struct nvgpu_mem *mem); - int (*update_smpc_ctxsw_mode)(struct gk20a *g, - struct channel_gk20a *c, - bool enable); - u32 (*get_hw_accessor_stream_out_mode)(void); - int (*update_hwpm_ctxsw_mode)(struct gk20a *g, - struct channel_gk20a *c, - u64 gpu_va, - u32 mode); - void (*init_hwpm_pmm_register)(struct gk20a *g); - void (*get_num_hwpm_perfmon)(struct gk20a *g, u32 *num_sys_perfmon, - u32 *num_fbp_perfmon, u32 *num_gpc_perfmon); - void (*set_pmm_register)(struct gk20a *g, u32 offset, u32 val, - u32 num_chiplets, u32 num_perfmons); - int (*dump_gr_regs)(struct gk20a *g, - struct gk20a_debug_output *o); - int (*update_pc_sampling)(struct channel_gk20a *ch, - bool enable); - u32 (*get_max_fbps_count)(struct gk20a *g); - u32 (*get_fbp_en_mask)(struct gk20a *g); - u32 (*get_max_ltc_per_fbp)(struct gk20a *g); - u32 (*get_max_lts_per_ltc)(struct gk20a *g); - u32* (*get_rop_l2_en_mask)(struct gk20a *g); - void (*init_sm_dsm_reg_info)(void); - void (*init_ovr_sm_dsm_perf)(void); - int (*wait_empty)(struct gk20a *g, unsigned long duration_ms, - u32 expect_delay); - void (*init_cyclestats)(struct gk20a *g); - void (*enable_cde_in_fecs)(struct gk20a *g, - struct nvgpu_mem *mem); - int (*set_sm_debug_mode)(struct gk20a *g, struct channel_gk20a *ch, - u64 sms, bool enable); - void (*bpt_reg_info)(struct gk20a *g, - struct nvgpu_warpstate *w_state); - void (*get_access_map)(struct gk20a *g, - u32 **whitelist, int *num_entries); - int (*handle_fecs_error)(struct gk20a *g, - struct channel_gk20a *ch, - struct gr_gk20a_isr_data *isr_data); - int (*pre_process_sm_exception)(struct gk20a *g, - u32 gpc, u32 tpc, u32 sm, u32 global_esr, u32 warp_esr, - bool sm_debugger_attached, - struct channel_gk20a *fault_ch, - bool *early_exit, bool *ignore_debugger); - u32 (*get_sm_hww_warp_esr)(struct gk20a *g, - u32 gpc, u32 tpc, u32 sm); - u32 (*get_sm_hww_global_esr)(struct gk20a *g, - u32 gpc, u32 tpc, u32 sm); - u32 (*get_sm_no_lock_down_hww_global_esr_mask)(struct gk20a *g); - int (*lock_down_sm)(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, - u32 global_esr_mask, bool check_errors); - int (*wait_for_sm_lock_down)(struct gk20a *g, u32 gpc, u32 tpc, - u32 sm, u32 global_esr_mask, bool check_errors); - void (*clear_sm_hww)(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, - u32 global_esr); - void (*get_esr_sm_sel)(struct gk20a *g, u32 gpc, u32 tpc, - u32 *esr_sm_sel); - int (*handle_tpc_sm_ecc_exception)(struct gk20a *g, - u32 gpc, u32 tpc, - bool *post_event, struct channel_gk20a *fault_ch, - u32 *hww_global_esr); - int (*handle_sm_exception)(struct gk20a *g, - u32 gpc, u32 tpc, u32 sm, - bool *post_event, struct channel_gk20a *fault_ch, - u32 *hww_global_esr); - int (*handle_gcc_exception)(struct gk20a *g, u32 gpc, u32 tpc, - bool *post_event, struct channel_gk20a *fault_ch, - u32 *hww_global_esr); - int (*handle_tex_exception)(struct gk20a *g, u32 gpc, u32 tpc, - bool *post_event); - int (*handle_tpc_mpc_exception)(struct gk20a *g, - u32 gpc, u32 tpc, bool *post_event); - int (*handle_gpc_gpccs_exception)(struct gk20a *g, u32 gpc, - u32 gpc_exception); - int (*handle_gpc_gpcmmu_exception)(struct gk20a *g, u32 gpc, - u32 gpc_exception); - void (*enable_gpc_exceptions)(struct gk20a *g); - void (*enable_exceptions)(struct gk20a *g); - int (*init_ecc)(struct gk20a *g); - u32 (*get_lrf_tex_ltc_dram_override)(struct gk20a *g); - int (*record_sm_error_state)(struct gk20a *g, u32 gpc, u32 tpc, - u32 sm, struct channel_gk20a *fault_ch); - int (*clear_sm_error_state)(struct gk20a *g, - struct channel_gk20a *ch, u32 sm_id); - int (*suspend_contexts)(struct gk20a *g, - struct dbg_session_gk20a *dbg_s, - int *ctx_resident_ch_fd); - int (*resume_contexts)(struct gk20a *g, - struct dbg_session_gk20a *dbg_s, - int *ctx_resident_ch_fd); - int (*set_preemption_mode)(struct channel_gk20a *ch, - u32 graphics_preempt_mode, - u32 compute_preempt_mode); - int (*get_preemption_mode_flags)(struct gk20a *g, - struct nvgpu_preemption_modes_rec *preemption_modes_rec); - int (*set_ctxsw_preemption_mode)(struct gk20a *g, - struct nvgpu_gr_ctx *gr_ctx, - struct vm_gk20a *vm, u32 class, - u32 graphics_preempt_mode, - u32 compute_preempt_mode); - int (*set_boosted_ctx)(struct channel_gk20a *ch, bool boost); - void (*update_boosted_ctx)(struct gk20a *g, - struct nvgpu_mem *mem, - struct nvgpu_gr_ctx *gr_ctx); - int (*init_sm_id_table)(struct gk20a *g); - int (*load_smid_config)(struct gk20a *g); - void (*program_sm_id_numbering)(struct gk20a *g, - u32 gpc, u32 tpc, u32 smid); - void (*program_active_tpc_counts)(struct gk20a *g, u32 gpc); - int (*setup_rop_mapping)(struct gk20a *g, struct gr_gk20a *gr); - int (*init_sw_veid_bundle)(struct gk20a *g); - void (*program_zcull_mapping)(struct gk20a *g, - u32 zcull_alloc_num, u32 *zcull_map_tiles); - int (*commit_global_timeslice)(struct gk20a *g, - struct channel_gk20a *c); - int (*commit_inst)(struct channel_gk20a *c, u64 gpu_va); - void (*write_zcull_ptr)(struct gk20a *g, - struct nvgpu_mem *mem, u64 gpu_va); - void (*write_pm_ptr)(struct gk20a *g, - struct nvgpu_mem *mem, u64 gpu_va); - void (*set_preemption_buffer_va)(struct gk20a *g, - struct nvgpu_mem *mem, u64 gpu_va); - void (*load_tpc_mask)(struct gk20a *g); - int (*trigger_suspend)(struct gk20a *g); - int (*wait_for_pause)(struct gk20a *g, struct nvgpu_warpstate *w_state); - int (*resume_from_pause)(struct gk20a *g); - int (*clear_sm_errors)(struct gk20a *g); - u32 (*tpc_enabled_exceptions)(struct gk20a *g); - int (*set_czf_bypass)(struct gk20a *g, - struct channel_gk20a *ch); - void (*init_czf_bypass)(struct gk20a *g); - bool (*sm_debugger_attached)(struct gk20a *g); - void (*suspend_single_sm)(struct gk20a *g, - u32 gpc, u32 tpc, u32 sm, - u32 global_esr_mask, bool check_errors); - void (*suspend_all_sms)(struct gk20a *g, - u32 global_esr_mask, bool check_errors); - void (*resume_single_sm)(struct gk20a *g, - u32 gpc, u32 tpc, u32 sm); - void (*resume_all_sms)(struct gk20a *g); - void (*disable_rd_coalesce)(struct gk20a *g); - void (*init_ctxsw_hdr_data)(struct gk20a *g, - struct nvgpu_mem *mem); - void (*init_gfxp_wfi_timeout_count)(struct gk20a *g); - unsigned long (*get_max_gfxp_wfi_timeout_count) - (struct gk20a *g); - void (*ecc_init_scrub_reg)(struct gk20a *g); - u32 (*get_gpcs_swdx_dss_zbc_c_format_reg)(struct gk20a *g); - u32 (*get_gpcs_swdx_dss_zbc_z_format_reg)(struct gk20a *g); - void (*dump_ctxsw_stats)(struct gk20a *g, struct vm_gk20a *vm, - struct nvgpu_gr_ctx *gr_ctx); - void (*fecs_host_int_enable)(struct gk20a *g); - int (*handle_ssync_hww)(struct gk20a *g); - int (*handle_notify_pending)(struct gk20a *g, - struct gr_gk20a_isr_data *isr_data); - int (*handle_semaphore_pending)(struct gk20a *g, - struct gr_gk20a_isr_data *isr_data); - int (*add_ctxsw_reg_pm_fbpa)(struct gk20a *g, - struct ctxsw_buf_offset_map_entry *map, - struct aiv_list_gk20a *regs, - u32 *count, u32 *offset, - u32 max_cnt, u32 base, - u32 num_fbpas, u32 stride, u32 mask); - int (*add_ctxsw_reg_perf_pma)(struct ctxsw_buf_offset_map_entry *map, - struct aiv_list_gk20a *regs, - u32 *count, u32 *offset, - u32 max_cnt, u32 base, u32 mask); - int (*decode_priv_addr)(struct gk20a *g, u32 addr, - enum ctxsw_addr_type *addr_type, - u32 *gpc_num, u32 *tpc_num, - u32 *ppc_num, u32 *be_num, - u32 *broadcast_flags); - int (*create_priv_addr_table)(struct gk20a *g, - u32 addr, - u32 *priv_addr_table, - u32 *num_registers); - u32 (*get_pmm_per_chiplet_offset)(void); - void (*split_fbpa_broadcast_addr)(struct gk20a *g, u32 addr, - u32 num_fbpas, - u32 *priv_addr_table, - u32 *priv_addr_table_index); - u32 (*fecs_ctxsw_mailbox_size)(void); - u32 (*gpc0_gpccs_ctxsw_mailbox_size)(void); - int (*init_sw_bundle64)(struct gk20a *g); - int (*alloc_global_ctx_buffers)(struct gk20a *g); - int (*map_global_ctx_buffers)(struct gk20a *g, - struct channel_gk20a *c); - int (*commit_global_ctx_buffers)(struct gk20a *g, - struct channel_gk20a *c, bool patch); - u32 (*get_nonpes_aware_tpc)(struct gk20a *g, u32 gpc, u32 tpc); - int (*get_offset_in_gpccs_segment)(struct gk20a *g, - enum ctxsw_addr_type addr_type, u32 num_tpcs, - u32 num_ppcs, u32 reg_list_ppc_count, - u32 *__offset_in_segment); - void (*set_debug_mode)(struct gk20a *g, bool enable); - int (*set_mmu_debug_mode)(struct gk20a *g, - struct channel_gk20a *ch, bool enable); - int (*set_fecs_watchdog_timeout)(struct gk20a *g); - } gr; - struct { - void (*init_hw)(struct gk20a *g); - void (*init_cbc)(struct gk20a *g, struct gr_gk20a *gr); - void (*init_fs_state)(struct gk20a *g); - void (*init_uncompressed_kind_map)(struct gk20a *g); - void (*init_kind_attr)(struct gk20a *g); - void (*set_mmu_page_size)(struct gk20a *g); - bool (*set_use_full_comp_tag_line)(struct gk20a *g); - u32 (*mmu_ctrl)(struct gk20a *g); - u32 (*mmu_debug_ctrl)(struct gk20a *g); - u32 (*mmu_debug_wr)(struct gk20a *g); - u32 (*mmu_debug_rd)(struct gk20a *g); - - /* - * Compression tag line coverage. When mapping a compressible - * buffer, ctagline is increased when the virtual address - * crosses over the compression page boundary. - */ - unsigned int (*compression_page_size)(struct gk20a *g); - - /* - * Minimum page size that can be used for compressible kinds. - */ - unsigned int (*compressible_page_size)(struct gk20a *g); - - /* - * Compressible kind mappings: Mask for the virtual and physical - * address bits that must match. - */ - u32 (*compression_align_mask)(struct gk20a *g); - - void (*dump_vpr_info)(struct gk20a *g); - void (*dump_wpr_info)(struct gk20a *g); - int (*vpr_info_fetch)(struct gk20a *g); - void (*read_wpr_info)(struct gk20a *g, - struct wpr_carveout_info *inf); - bool (*is_debug_mode_enabled)(struct gk20a *g); - void (*set_debug_mode)(struct gk20a *g, bool enable); - void (*set_mmu_debug_mode)(struct gk20a *g, bool enable); - int (*tlb_invalidate)(struct gk20a *g, struct nvgpu_mem *pdb); - void (*hub_isr)(struct gk20a *g); - void (*handle_replayable_fault)(struct gk20a *g); - int (*mem_unlock)(struct gk20a *g); - int (*init_nvlink)(struct gk20a *g); - int (*enable_nvlink)(struct gk20a *g); - void (*enable_hub_intr)(struct gk20a *g); - void (*disable_hub_intr)(struct gk20a *g); - int (*init_fbpa)(struct gk20a *g); - void (*handle_fbpa_intr)(struct gk20a *g, u32 fbpa_id); - void (*write_mmu_fault_buffer_lo_hi)(struct gk20a *g, u32 index, - u32 addr_lo, u32 addr_hi); - void (*write_mmu_fault_buffer_get)(struct gk20a *g, u32 index, - u32 reg_val); - void (*write_mmu_fault_buffer_size)(struct gk20a *g, u32 index, - u32 reg_val); - void (*write_mmu_fault_status)(struct gk20a *g, u32 reg_val); - u32 (*read_mmu_fault_buffer_get)(struct gk20a *g, u32 index); - u32 (*read_mmu_fault_buffer_put)(struct gk20a *g, u32 index); - u32 (*read_mmu_fault_buffer_size)(struct gk20a *g, u32 index); - void (*read_mmu_fault_addr_lo_hi)(struct gk20a *g, - u32 *addr_lo, u32 *addr_hi); - void (*read_mmu_fault_inst_lo_hi)(struct gk20a *g, - u32 *inst_lo, u32 *inst_hi); - u32 (*read_mmu_fault_info)(struct gk20a *g); - u32 (*read_mmu_fault_status)(struct gk20a *g); - int (*mmu_invalidate_replay)(struct gk20a *g, - u32 invalidate_replay_val); - bool (*mmu_fault_pending)(struct gk20a *g); - bool (*is_fault_buf_enabled)(struct gk20a *g, u32 index); - void (*fault_buf_set_state_hw)(struct gk20a *g, - u32 index, u32 state); - void (*fault_buf_configure_hw)(struct gk20a *g, u32 index); - size_t (*get_vidmem_size)(struct gk20a *g); - int (*apply_pdb_cache_war)(struct gk20a *g); - } fb; - struct { - void (*slcg_bus_load_gating_prod)(struct gk20a *g, bool prod); - void (*slcg_ce2_load_gating_prod)(struct gk20a *g, bool prod); - void (*slcg_chiplet_load_gating_prod)(struct gk20a *g, bool prod); - void (*slcg_ctxsw_firmware_load_gating_prod)(struct gk20a *g, bool prod); - void (*slcg_fb_load_gating_prod)(struct gk20a *g, bool prod); - void (*slcg_fifo_load_gating_prod)(struct gk20a *g, bool prod); - void (*slcg_gr_load_gating_prod)(struct gk20a *g, bool prod); - void (*slcg_ltc_load_gating_prod)(struct gk20a *g, bool prod); - void (*slcg_perf_load_gating_prod)(struct gk20a *g, bool prod); - void (*slcg_priring_load_gating_prod)(struct gk20a *g, bool prod); - void (*slcg_pmu_load_gating_prod)(struct gk20a *g, bool prod); - void (*slcg_therm_load_gating_prod)(struct gk20a *g, bool prod); - void (*slcg_xbar_load_gating_prod)(struct gk20a *g, bool prod); - void (*slcg_hshub_load_gating_prod)(struct gk20a *g, bool prod); - void (*slcg_acb_load_gating_prod)(struct gk20a *g, bool prod); - void (*blcg_bus_load_gating_prod)(struct gk20a *g, bool prod); - void (*blcg_ce_load_gating_prod)(struct gk20a *g, bool prod); - void (*blcg_ctxsw_firmware_load_gating_prod)(struct gk20a *g, bool prod); - void (*blcg_fb_load_gating_prod)(struct gk20a *g, bool prod); - void (*blcg_fifo_load_gating_prod)(struct gk20a *g, bool prod); - void (*blcg_gr_load_gating_prod)(struct gk20a *g, bool prod); - void (*blcg_ltc_load_gating_prod)(struct gk20a *g, bool prod); - void (*blcg_pwr_csb_load_gating_prod)(struct gk20a *g, bool prod); - void (*blcg_pmu_load_gating_prod)(struct gk20a *g, bool prod); - void (*blcg_xbar_load_gating_prod)(struct gk20a *g, bool prod); - void (*blcg_hshub_load_gating_prod)(struct gk20a *g, bool prod); - void (*pg_gr_load_gating_prod)(struct gk20a *g, bool prod); - } clock_gating; - struct { - void (*post_events)(struct channel_gk20a *ch); - } debugger; - struct { - int (*setup_sw)(struct gk20a *g); - int (*init_fifo_setup_hw)(struct gk20a *g); - void (*bind_channel)(struct channel_gk20a *ch_gk20a); - void (*unbind_channel)(struct channel_gk20a *ch_gk20a); - void (*disable_channel)(struct channel_gk20a *ch); - void (*enable_channel)(struct channel_gk20a *ch); - int (*alloc_inst)(struct gk20a *g, struct channel_gk20a *ch); - void (*free_inst)(struct gk20a *g, struct channel_gk20a *ch); - int (*setup_ramfc)(struct channel_gk20a *c, u64 gpfifo_base, - u32 gpfifo_entries, - unsigned long acquire_timeout, - u32 flags); - int (*resetup_ramfc)(struct channel_gk20a *c); - int (*preempt_channel)(struct gk20a *g, struct channel_gk20a *ch); - int (*preempt_tsg)(struct gk20a *g, struct tsg_gk20a *tsg); - int (*enable_tsg)(struct tsg_gk20a *tsg); - int (*disable_tsg)(struct tsg_gk20a *tsg); - int (*tsg_verify_channel_status)(struct channel_gk20a *ch); - void (*tsg_verify_status_ctx_reload)(struct channel_gk20a *ch); - void (*tsg_verify_status_faulted)(struct channel_gk20a *ch); - int (*reschedule_runlist)(struct channel_gk20a *ch, - bool preempt_next); - int (*update_runlist)(struct gk20a *g, u32 runlist_id, - u32 chid, bool add, - bool wait_for_finish); - void (*trigger_mmu_fault)(struct gk20a *g, - unsigned long engine_ids); - void (*get_mmu_fault_info)(struct gk20a *g, u32 mmu_fault_id, - struct mmu_fault_info *mmfault); - void (*get_mmu_fault_desc)(struct mmu_fault_info *mmfault); - void (*get_mmu_fault_client_desc)( - struct mmu_fault_info *mmfault); - void (*get_mmu_fault_gpc_desc)(struct mmu_fault_info *mmfault); - void (*apply_pb_timeout)(struct gk20a *g); - void (*apply_ctxsw_timeout_intr)(struct gk20a *g); - int (*wait_engine_idle)(struct gk20a *g); - u32 (*get_num_fifos)(struct gk20a *g); - u32 (*get_pbdma_signature)(struct gk20a *g); - int (*set_runlist_interleave)(struct gk20a *g, u32 id, - u32 runlist_id, - u32 new_level); - int (*tsg_set_timeslice)(struct tsg_gk20a *tsg, u32 timeslice); - u32 (*default_timeslice_us)(struct gk20a *); - int (*force_reset_ch)(struct channel_gk20a *ch, - u32 err_code, bool verbose); - int (*engine_enum_from_type)(struct gk20a *g, u32 engine_type, - u32 *inst_id); - void (*device_info_data_parse)(struct gk20a *g, - u32 table_entry, u32 *inst_id, - u32 *pri_base, u32 *fault_id); - u32 (*device_info_fault_id)(u32 table_entry); - int (*tsg_bind_channel)(struct tsg_gk20a *tsg, - struct channel_gk20a *ch); - int (*tsg_unbind_channel)(struct channel_gk20a *ch); - int (*tsg_open)(struct tsg_gk20a *tsg); - void (*tsg_release)(struct tsg_gk20a *tsg); - u32 (*eng_runlist_base_size)(void); - int (*init_engine_info)(struct fifo_gk20a *f); - u32 (*runlist_entry_size)(void); - void (*get_tsg_runlist_entry)(struct tsg_gk20a *tsg, - u32 *runlist); - void (*get_ch_runlist_entry)(struct channel_gk20a *ch, - u32 *runlist); - u32 (*userd_gp_get)(struct gk20a *g, struct channel_gk20a *ch); - void (*userd_gp_put)(struct gk20a *g, struct channel_gk20a *ch); - u64 (*userd_pb_get)(struct gk20a *g, struct channel_gk20a *ch); - void (*free_channel_ctx_header)(struct channel_gk20a *ch); - bool (*is_fault_engine_subid_gpc)(struct gk20a *g, - u32 engine_subid); - void (*dump_pbdma_status)(struct gk20a *g, - struct gk20a_debug_output *o); - void (*dump_eng_status)(struct gk20a *g, - struct gk20a_debug_output *o); - void (*dump_channel_status_ramfc)(struct gk20a *g, - struct gk20a_debug_output *o, u32 chid, - struct ch_state *ch_state); - u32 (*intr_0_error_mask)(struct gk20a *g); - int (*is_preempt_pending)(struct gk20a *g, u32 id, - unsigned int id_type, bool preempt_retries_left); - void (*init_pbdma_intr_descs)(struct fifo_gk20a *f); - int (*reset_enable_hw)(struct gk20a *g); - int (*setup_userd)(struct channel_gk20a *c); - u32 (*pbdma_acquire_val)(u64 timeout); - void (*teardown_ch_tsg)(struct gk20a *g, u32 act_eng_bitmask, - u32 id, unsigned int id_type, unsigned int rc_type, - struct mmu_fault_info *mmfault); - void (*teardown_mask_intr)(struct gk20a *g); - void (*teardown_unmask_intr)(struct gk20a *g); - bool (*handle_sched_error)(struct gk20a *g); - bool (*handle_ctxsw_timeout)(struct gk20a *g, u32 fifo_intr); - unsigned int (*handle_pbdma_intr_0)(struct gk20a *g, - u32 pbdma_id, u32 pbdma_intr_0, - u32 *handled, u32 *error_notifier); - unsigned int (*handle_pbdma_intr_1)(struct gk20a *g, - u32 pbdma_id, u32 pbdma_intr_1, - u32 *handled, u32 *error_notifier); - void (*init_eng_method_buffers)(struct gk20a *g, - struct tsg_gk20a *tsg); - void (*deinit_eng_method_buffers)(struct gk20a *g, - struct tsg_gk20a *tsg); - u32 (*get_preempt_timeout)(struct gk20a *g); - void (*post_event_id)(struct tsg_gk20a *tsg, int event_id); - void (*ch_abort_clean_up)(struct channel_gk20a *ch); - bool (*check_tsg_ctxsw_timeout)(struct tsg_gk20a *tsg, - bool *verbose, u32 *ms); - bool (*check_ch_ctxsw_timeout)(struct channel_gk20a *ch, - bool *verbose, u32 *ms); - int (*channel_suspend)(struct gk20a *g); - int (*channel_resume)(struct gk20a *g); - void (*set_error_notifier)(struct channel_gk20a *ch, u32 error); -#ifdef CONFIG_TEGRA_GK20A_NVHOST - int (*alloc_syncpt_buf)(struct channel_gk20a *c, - u32 syncpt_id, struct nvgpu_mem *syncpt_buf); - void (*free_syncpt_buf)(struct channel_gk20a *c, - struct nvgpu_mem *syncpt_buf); - void (*add_syncpt_wait_cmd)(struct gk20a *g, - struct priv_cmd_entry *cmd, u32 off, - u32 id, u32 thresh, u64 gpu_va); - u32 (*get_syncpt_wait_cmd_size)(void); - void (*add_syncpt_incr_cmd)(struct gk20a *g, - bool wfi_cmd, struct priv_cmd_entry *cmd, - u32 id, u64 gpu_va); - u32 (*get_syncpt_incr_cmd_size)(bool wfi_cmd); - int (*get_sync_ro_map)(struct vm_gk20a *vm, - u64 *base_gpuva, u32 *sync_size); - u32 (*get_syncpt_incr_per_release)(void); -#endif - void (*runlist_hw_submit)(struct gk20a *g, u32 runlist_id, - u32 count, u32 buffer_index); - int (*runlist_wait_pending)(struct gk20a *g, u32 runlist_id); - void (*ring_channel_doorbell)(struct channel_gk20a *c); - u64 (*usermode_base)(struct gk20a *g); - u32 (*get_sema_wait_cmd_size)(void); - u32 (*get_sema_incr_cmd_size)(void); - void (*add_sema_cmd)(struct gk20a *g, - struct nvgpu_semaphore *s, u64 sema_va, - struct priv_cmd_entry *cmd, - u32 off, bool acquire, bool wfi); - int (*init_pdb_cache_war)(struct gk20a *g); - void (*deinit_pdb_cache_war)(struct gk20a *g); - } fifo; - struct pmu_v { - u32 (*get_pmu_cmdline_args_size)(struct nvgpu_pmu *pmu); - void (*set_pmu_cmdline_args_cpu_freq)(struct nvgpu_pmu *pmu, - u32 freq); - void (*set_pmu_cmdline_args_trace_size)(struct nvgpu_pmu *pmu, - u32 size); - void (*set_pmu_cmdline_args_trace_dma_base)( - struct nvgpu_pmu *pmu); - void (*config_pmu_cmdline_args_super_surface)( - struct nvgpu_pmu *pmu); - void (*set_pmu_cmdline_args_trace_dma_idx)( - struct nvgpu_pmu *pmu, u32 idx); - void * (*get_pmu_cmdline_args_ptr)(struct nvgpu_pmu *pmu); - u32 (*get_pmu_allocation_struct_size)(struct nvgpu_pmu *pmu); - void (*set_pmu_allocation_ptr)(struct nvgpu_pmu *pmu, - void **pmu_alloc_ptr, void *assign_ptr); - void (*pmu_allocation_set_dmem_size)(struct nvgpu_pmu *pmu, - void *pmu_alloc_ptr, u16 size); - u16 (*pmu_allocation_get_dmem_size)(struct nvgpu_pmu *pmu, - void *pmu_alloc_ptr); - u32 (*pmu_allocation_get_dmem_offset)(struct nvgpu_pmu *pmu, - void *pmu_alloc_ptr); - u32 * (*pmu_allocation_get_dmem_offset_addr)( - struct nvgpu_pmu *pmu, void *pmu_alloc_ptr); - void (*pmu_allocation_set_dmem_offset)(struct nvgpu_pmu *pmu, - void *pmu_alloc_ptr, u32 offset); - void * (*pmu_allocation_get_fb_addr)( - struct nvgpu_pmu *pmu, void *pmu_alloc_ptr); - u32 (*pmu_allocation_get_fb_size)( - struct nvgpu_pmu *pmu, void *pmu_alloc_ptr); - void (*get_pmu_init_msg_pmu_queue_params)( - struct nvgpu_falcon_queue *queue, u32 id, - void *pmu_init_msg); - void *(*get_pmu_msg_pmu_init_msg_ptr)( - struct pmu_init_msg *init); - u16 (*get_pmu_init_msg_pmu_sw_mg_off)( - union pmu_init_msg_pmu *init_msg); - u16 (*get_pmu_init_msg_pmu_sw_mg_size)( - union pmu_init_msg_pmu *init_msg); - u32 (*get_pmu_perfmon_cmd_start_size)(void); - int (*get_perfmon_cmd_start_offsetofvar)( - enum pmu_perfmon_cmd_start_fields field); - void (*perfmon_start_set_cmd_type)(struct pmu_perfmon_cmd *pc, - u8 value); - void (*perfmon_start_set_group_id)(struct pmu_perfmon_cmd *pc, - u8 value); - void (*perfmon_start_set_state_id)(struct pmu_perfmon_cmd *pc, - u8 value); - void (*perfmon_start_set_flags)(struct pmu_perfmon_cmd *pc, - u8 value); - u8 (*perfmon_start_get_flags)(struct pmu_perfmon_cmd *pc); - u32 (*get_pmu_perfmon_cmd_init_size)(void); - int (*get_perfmon_cmd_init_offsetofvar)( - enum pmu_perfmon_cmd_start_fields field); - void (*perfmon_cmd_init_set_sample_buffer)( - struct pmu_perfmon_cmd *pc, u16 value); - void (*perfmon_cmd_init_set_dec_cnt)( - struct pmu_perfmon_cmd *pc, u8 value); - void (*perfmon_cmd_init_set_base_cnt_id)( - struct pmu_perfmon_cmd *pc, u8 value); - void (*perfmon_cmd_init_set_samp_period_us)( - struct pmu_perfmon_cmd *pc, u32 value); - void (*perfmon_cmd_init_set_num_cnt)(struct pmu_perfmon_cmd *pc, - u8 value); - void (*perfmon_cmd_init_set_mov_avg)(struct pmu_perfmon_cmd *pc, - u8 value); - void *(*get_pmu_seq_in_a_ptr)( - struct pmu_sequence *seq); - void *(*get_pmu_seq_out_a_ptr)( - struct pmu_sequence *seq); - void (*set_pmu_cmdline_args_secure_mode)(struct nvgpu_pmu *pmu, - u32 val); - u32 (*get_perfmon_cntr_sz)(struct nvgpu_pmu *pmu); - void * (*get_perfmon_cntr_ptr)(struct nvgpu_pmu *pmu); - void (*set_perfmon_cntr_ut)(struct nvgpu_pmu *pmu, u16 ut); - void (*set_perfmon_cntr_lt)(struct nvgpu_pmu *pmu, u16 lt); - void (*set_perfmon_cntr_valid)(struct nvgpu_pmu *pmu, u8 val); - void (*set_perfmon_cntr_index)(struct nvgpu_pmu *pmu, u8 val); - void (*set_perfmon_cntr_group_id)(struct nvgpu_pmu *pmu, - u8 gid); - - u8 (*pg_cmd_eng_buf_load_size)(struct pmu_pg_cmd *pg); - void (*pg_cmd_eng_buf_load_set_cmd_type)(struct pmu_pg_cmd *pg, - u8 value); - void (*pg_cmd_eng_buf_load_set_engine_id)(struct pmu_pg_cmd *pg, - u8 value); - void (*pg_cmd_eng_buf_load_set_buf_idx)(struct pmu_pg_cmd *pg, - u8 value); - void (*pg_cmd_eng_buf_load_set_pad)(struct pmu_pg_cmd *pg, - u8 value); - void (*pg_cmd_eng_buf_load_set_buf_size)(struct pmu_pg_cmd *pg, - u16 value); - void (*pg_cmd_eng_buf_load_set_dma_base)(struct pmu_pg_cmd *pg, - u32 value); - void (*pg_cmd_eng_buf_load_set_dma_offset)(struct pmu_pg_cmd *pg, - u8 value); - void (*pg_cmd_eng_buf_load_set_dma_idx)(struct pmu_pg_cmd *pg, - u8 value); - struct { - int (*boardobjgrp_pmucmd_construct_impl) - (struct gk20a *g, - struct boardobjgrp *pboardobjgrp, - struct boardobjgrp_pmu_cmd *cmd, u8 id, u8 msgid, - u16 hdrsize, u16 entrysize, u16 fbsize, u32 ss_offset, - u8 rpc_func_id); - int (*boardobjgrp_pmuset_impl)(struct gk20a *g, - struct boardobjgrp *pboardobjgrp); - int (*boardobjgrp_pmugetstatus_impl)(struct gk20a *g, - struct boardobjgrp *pboardobjgrp, - struct boardobjgrpmask *mask); - int (*is_boardobjgrp_pmucmd_id_valid)(struct gk20a *g, - struct boardobjgrp *pboardobjgrp, - struct boardobjgrp_pmu_cmd *cmd); - } boardobj; - struct { - u32 (*volt_set_voltage)(struct gk20a *g, - u32 logic_voltage_uv, u32 sram_voltage_uv); - u32 (*volt_get_voltage)(struct gk20a *g, - u8 volt_domain, u32 *pvoltage_uv); - u32 (*volt_send_load_cmd_to_pmu)(struct gk20a *g); - } volt; - struct { - u32 (*get_vbios_clk_domain)(u32 vbios_domain); - u32 (*clk_avfs_get_vin_cal_data)(struct gk20a *g, - struct avfsvinobjs *pvinobjs, - struct vin_device_v20 *pvindev); - u32 (*clk_vf_change_inject_data_fill)(struct gk20a *g, - struct nv_pmu_clk_rpc *rpccall, - struct set_fll_clk *setfllclk); - u32 (*clk_set_boot_clk)(struct gk20a *g); - }clk; - } pmu_ver; - struct { - int (*get_netlist_name)(struct gk20a *g, int index, char *name); - bool (*is_fw_defined)(void); - } gr_ctx; -#ifdef CONFIG_GK20A_CTXSW_TRACE - /* - * Currently only supported on Linux due to the extremely tight - * integration with Linux device driver structure (in particular - * mmap). - */ - struct { - int (*init)(struct gk20a *g); - int (*max_entries)(struct gk20a *, - struct nvgpu_gpu_ctxsw_trace_filter *filter); - int (*flush)(struct gk20a *g); - int (*poll)(struct gk20a *g); - int (*enable)(struct gk20a *g); - int (*disable)(struct gk20a *g); - bool (*is_enabled)(struct gk20a *g); - int (*reset)(struct gk20a *g); - int (*bind_channel)(struct gk20a *g, struct channel_gk20a *ch); - int (*unbind_channel)(struct gk20a *g, - struct channel_gk20a *ch); - int (*deinit)(struct gk20a *g); - int (*alloc_user_buffer)(struct gk20a *g, - void **buf, size_t *size); - int (*free_user_buffer)(struct gk20a *g); - int (*mmap_user_buffer)(struct gk20a *g, - struct vm_area_struct *vma); - int (*set_filter)(struct gk20a *g, - struct nvgpu_gpu_ctxsw_trace_filter *filter); - } fecs_trace; -#endif - struct { - bool (*support_sparse)(struct gk20a *g); - u64 (*gmmu_map)(struct vm_gk20a *vm, - u64 map_offset, - struct nvgpu_sgt *sgt, - u64 buffer_offset, - u64 size, - u32 pgsz_idx, - u8 kind_v, - u32 ctag_offset, - u32 flags, - enum gk20a_mem_rw_flag rw_flag, - bool clear_ctags, - bool sparse, - bool priv, - struct vm_gk20a_mapping_batch *batch, - enum nvgpu_aperture aperture); - void (*gmmu_unmap)(struct vm_gk20a *vm, - u64 vaddr, - u64 size, - u32 pgsz_idx, - bool va_allocated, - enum gk20a_mem_rw_flag rw_flag, - bool sparse, - struct vm_gk20a_mapping_batch *batch); - int (*vm_bind_channel)(struct vm_gk20a *vm, - struct channel_gk20a *ch); - int (*fb_flush)(struct gk20a *g); - void (*l2_invalidate)(struct gk20a *g); - void (*l2_flush)(struct gk20a *g, bool invalidate); - void (*cbc_clean)(struct gk20a *g); - void (*set_big_page_size)(struct gk20a *g, - struct nvgpu_mem *mem, int size); - u32 (*get_big_page_sizes)(void); - u32 (*get_default_big_page_size)(void); - u32 (*get_iommu_bit)(struct gk20a *g); - int (*init_mm_setup_hw)(struct gk20a *g); - bool (*is_bar1_supported)(struct gk20a *g); - int (*init_bar2_vm)(struct gk20a *g); - void (*remove_bar2_vm)(struct gk20a *g); - const struct gk20a_mmu_level * - (*get_mmu_levels)(struct gk20a *g, u32 big_page_size); - void (*init_pdb)(struct gk20a *g, struct nvgpu_mem *inst_block, - struct vm_gk20a *vm); - u64 (*gpu_phys_addr)(struct gk20a *g, - struct nvgpu_gmmu_attrs *attrs, u64 phys); - int (*alloc_inst_block)(struct gk20a *g, - struct nvgpu_mem *inst_block); - void (*init_inst_block)(struct nvgpu_mem *inst_block, - struct vm_gk20a *vm, u32 big_page_size); - bool (*mmu_fault_pending)(struct gk20a *g); - void (*fault_info_mem_destroy)(struct gk20a *g); - void (*mmu_fault_disable_hw)(struct gk20a *g); - u32 (*get_kind_invalid)(void); - u32 (*get_kind_pitch)(void); - u32 (*get_flush_retries)(struct gk20a *g, - enum nvgpu_flush_op op); - } mm; - /* - * This function is called to allocate secure memory (memory - * that the CPU cannot see). The function should fill the - * context buffer descriptor (especially fields destroy, sgt, - * size). - */ - int (*secure_alloc)(struct gk20a *g, - struct gr_ctx_buffer_desc *desc, - size_t size); - struct { - void (*exit)(struct gk20a *g, struct nvgpu_mem *mem, - struct nvgpu_sgl *sgl); - u32 (*data032_r)(u32 i); - } pramin; - struct { - int (*init_therm_setup_hw)(struct gk20a *g); - void (*init_elcg_mode)(struct gk20a *g, u32 mode, u32 engine); - void (*init_blcg_mode)(struct gk20a *g, u32 mode, u32 engine); - int (*elcg_init_idle_filters)(struct gk20a *g); -#ifdef CONFIG_DEBUG_FS - void (*therm_debugfs_init)(struct gk20a *g); -#endif - int (*get_internal_sensor_curr_temp)(struct gk20a *g, u32 *temp_f24_8); - void (*get_internal_sensor_limits)(s32 *max_24_8, - s32 *min_24_8); - u32 (*configure_therm_alert)(struct gk20a *g, s32 curr_warn_temp); - } therm; - struct { - bool (*is_pmu_supported)(struct gk20a *g); - int (*prepare_ucode)(struct gk20a *g); - int (*pmu_setup_hw_and_bootstrap)(struct gk20a *g); - int (*pmu_nsbootstrap)(struct nvgpu_pmu *pmu); - int (*pmu_init_perfmon)(struct nvgpu_pmu *pmu); - int (*pmu_perfmon_start_sampling)(struct nvgpu_pmu *pmu); - int (*pmu_perfmon_stop_sampling)(struct nvgpu_pmu *pmu); - int (*pmu_perfmon_get_samples_rpc)(struct nvgpu_pmu *pmu); - int (*pmu_setup_elpg)(struct gk20a *g); - u32 (*pmu_get_queue_head)(u32 i); - u32 (*pmu_get_queue_head_size)(void); - u32 (*pmu_get_queue_tail_size)(void); - u32 (*pmu_get_queue_tail)(u32 i); - int (*pmu_queue_head)(struct gk20a *g, - struct nvgpu_falcon_queue *queue, u32 *head, bool set); - int (*pmu_queue_tail)(struct gk20a *g, - struct nvgpu_falcon_queue *queue, u32 *tail, bool set); - void (*pmu_msgq_tail)(struct nvgpu_pmu *pmu, - u32 *tail, bool set); - u32 (*pmu_mutex_size)(void); - int (*pmu_mutex_acquire)(struct nvgpu_pmu *pmu, - u32 id, u32 *token); - int (*pmu_mutex_release)(struct nvgpu_pmu *pmu, - u32 id, u32 *token); - bool (*pmu_is_interrupted)(struct nvgpu_pmu *pmu); - void (*pmu_isr)(struct gk20a *g); - void (*pmu_init_perfmon_counter)(struct gk20a *g); - void (*pmu_pg_idle_counter_config)(struct gk20a *g, u32 pg_engine_id); - u32 (*pmu_read_idle_counter)(struct gk20a *g, u32 counter_id); - u32 (*pmu_read_idle_intr_status)(struct gk20a *g); - void (*pmu_clear_idle_intr_status)(struct gk20a *g); - void (*pmu_reset_idle_counter)(struct gk20a *g, u32 counter_id); - void (*pmu_dump_elpg_stats)(struct nvgpu_pmu *pmu); - void (*pmu_dump_falcon_stats)(struct nvgpu_pmu *pmu); - void (*pmu_enable_irq)(struct nvgpu_pmu *pmu, bool enable); - int (*init_wpr_region)(struct gk20a *g); - int (*load_lsfalcon_ucode)(struct gk20a *g, u32 falconidmask); - void (*write_dmatrfbase)(struct gk20a *g, u32 addr); - void (*pmu_elpg_statistics)(struct gk20a *g, u32 pg_engine_id, - struct pmu_pg_stats_data *pg_stat_data); - int (*pmu_pg_init_param)(struct gk20a *g, u32 pg_engine_id); - int (*pmu_pg_set_sub_feature_mask)(struct gk20a *g, - u32 pg_engine_id); - u32 (*pmu_pg_supported_engines_list)(struct gk20a *g); - u32 (*pmu_pg_engines_feature_list)(struct gk20a *g, - u32 pg_engine_id); - int (*pmu_process_pg_event)(struct gk20a *g, void *pmumsg); - bool (*pmu_is_lpwr_feature_supported)(struct gk20a *g, - u32 feature_id); - int (*pmu_lpwr_enable_pg)(struct gk20a *g, bool pstate_lock); - int (*pmu_lpwr_disable_pg)(struct gk20a *g, bool pstate_lock); - u32 (*pmu_pg_param_post_init)(struct gk20a *g); - void (*dump_secure_fuses)(struct gk20a *g); - int (*reset_engine)(struct gk20a *g, bool do_reset); - bool (*is_engine_in_reset)(struct gk20a *g); - bool (*is_lazy_bootstrap)(u32 falcon_id); - bool (*is_priv_load)(u32 falcon_id); - int (*pmu_populate_loader_cfg)(struct gk20a *g, - void *lsfm, u32 *p_bl_gen_desc_size); - int (*flcn_populate_bl_dmem_desc)(struct gk20a *g, - void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid); - void (*handle_ext_irq)(struct gk20a *g, u32 intr); - void (*set_irqmask)(struct gk20a *g); - void (*update_lspmu_cmdline_args)(struct gk20a *g); - void (*setup_apertures)(struct gk20a *g); - u32 (*get_irqdest)(struct gk20a *g); - int (*alloc_super_surface)(struct gk20a *g, - struct nvgpu_mem *super_surface, u32 size); - bool (*is_debug_mode_enabled)(struct gk20a *g); - void (*secured_pmu_start)(struct gk20a *g); - } pmu; - struct { - int (*init_debugfs)(struct gk20a *g); - void (*disable_slowboot)(struct gk20a *g); - int (*init_clk_support)(struct gk20a *g); - int (*suspend_clk_support)(struct gk20a *g); - u32 (*get_crystal_clk_hz)(struct gk20a *g); - int (*clk_domain_get_f_points)(struct gk20a *g, - u32 clkapidomain, u32 *pfpointscount, - u16 *pfreqpointsinmhz); - int (*clk_get_round_rate)(struct gk20a *g, u32 api_domain, - unsigned long rate_target, unsigned long *rounded_rate); - int (*get_clk_range)(struct gk20a *g, u32 api_domain, - u16 *min_mhz, u16 *max_mhz); - unsigned long (*measure_freq)(struct gk20a *g, u32 api_domain); - u32 (*get_rate_cntr)(struct gk20a *g, struct namemap_cfg *c); - unsigned long (*get_rate)(struct gk20a *g, u32 api_domain); - int (*set_rate)(struct gk20a *g, u32 api_domain, unsigned long rate); - unsigned long (*get_fmax_at_vmin_safe)(struct gk20a *g); - u32 (*get_ref_clock_rate)(struct gk20a *g); - int (*predict_mv_at_hz_cur_tfloor)(struct clk_gk20a *clk, - unsigned long rate); - unsigned long (*get_maxrate)(struct gk20a *g, u32 api_domain); - int (*prepare_enable)(struct clk_gk20a *clk); - void (*disable_unprepare)(struct clk_gk20a *clk); - int (*get_voltage)(struct clk_gk20a *clk, u64 *val); - int (*get_gpcclk_clock_counter)(struct clk_gk20a *clk, u64 *val); - int (*pll_reg_write)(struct gk20a *g, u32 reg, u32 val); - int (*get_pll_debug_data)(struct gk20a *g, - struct nvgpu_clk_pll_debug_data *d); - int (*mclk_init)(struct gk20a *g); - void (*mclk_deinit)(struct gk20a *g); - int (*mclk_change)(struct gk20a *g, u16 val); - bool split_rail_support; - bool support_clk_freq_controller; - bool support_pmgr_domain; - bool support_lpwr_pg; - u32 (*perf_pmu_vfe_load)(struct gk20a *g); - u32 lut_num_entries; - } clk; - struct { - int (*arbiter_clk_init)(struct gk20a *g); - u32 (*get_arbiter_clk_domains)(struct gk20a *g); - int (*get_arbiter_f_points)(struct gk20a *g,u32 api_domain, - u32 *num_points, u16 *freqs_in_mhz); - int (*get_arbiter_clk_range)(struct gk20a *g, u32 api_domain, - u16 *min_mhz, u16 *max_mhz); - int (*get_arbiter_clk_default)(struct gk20a *g, u32 api_domain, - u16 *default_mhz); - void (*clk_arb_run_arbiter_cb)(struct nvgpu_clk_arb *arb); - /* This function is inherently unsafe to call while - * arbiter is running arbiter must be blocked - * before calling this function */ - int (*get_current_pstate)(struct gk20a *g); - void (*clk_arb_cleanup)(struct nvgpu_clk_arb *arb); - } clk_arb; - struct { - int (*handle_pmu_perf_event)(struct gk20a *g, void *pmu_msg); - } pmu_perf; - struct { - int (*exec_regops)(struct dbg_session_gk20a *dbg_s, - struct nvgpu_dbg_reg_op *ops, - u64 num_ops, - bool *is_current_ctx); - const struct regop_offset_range* ( - *get_global_whitelist_ranges)(void); - u64 (*get_global_whitelist_ranges_count)(void); - const struct regop_offset_range* ( - *get_context_whitelist_ranges)(void); - u64 (*get_context_whitelist_ranges_count)(void); - const u32* (*get_runcontrol_whitelist)(void); - u64 (*get_runcontrol_whitelist_count)(void); - const u32* (*get_qctl_whitelist)(void); - u64 (*get_qctl_whitelist_count)(void); - } regops; - struct { - void (*intr_mask)(struct gk20a *g); - void (*intr_enable)(struct gk20a *g); - void (*intr_unit_config)(struct gk20a *g, - bool enable, bool is_stalling, u32 mask); - void (*isr_stall)(struct gk20a *g); - bool (*is_intr_hub_pending)(struct gk20a *g, u32 mc_intr); - bool (*is_intr_nvlink_pending)(struct gk20a *g, u32 mc_intr); - bool (*is_stall_and_eng_intr_pending)(struct gk20a *g, - u32 act_eng_id, u32 *eng_intr_pending); - u32 (*intr_stall)(struct gk20a *g); - void (*intr_stall_pause)(struct gk20a *g); - void (*intr_stall_resume)(struct gk20a *g); - u32 (*intr_nonstall)(struct gk20a *g); - void (*intr_nonstall_pause)(struct gk20a *g); - void (*intr_nonstall_resume)(struct gk20a *g); - u32 (*isr_nonstall)(struct gk20a *g); - void (*enable)(struct gk20a *g, u32 units); - void (*disable)(struct gk20a *g, u32 units); - void (*reset)(struct gk20a *g, u32 units); - bool (*is_enabled)(struct gk20a *g, enum nvgpu_unit unit); - bool (*is_intr1_pending)(struct gk20a *g, enum nvgpu_unit unit, u32 mc_intr_1); - void (*log_pending_intrs)(struct gk20a *g); - void (*fbpa_isr)(struct gk20a *g); - u32 (*reset_mask)(struct gk20a *g, enum nvgpu_unit unit); - void (*fb_reset)(struct gk20a *g); - } mc; - struct { - void (*show_dump)(struct gk20a *g, - struct gk20a_debug_output *o); - } debug; - struct { - int (*dbg_set_powergate)(struct dbg_session_gk20a *dbg_s, - bool disable_powergate); - bool (*check_and_set_global_reservation)( - struct dbg_session_gk20a *dbg_s, - struct dbg_profiler_object_data *prof_obj); - bool (*check_and_set_context_reservation)( - struct dbg_session_gk20a *dbg_s, - struct dbg_profiler_object_data *prof_obj); - void (*release_profiler_reservation)( - struct dbg_session_gk20a *dbg_s, - struct dbg_profiler_object_data *prof_obj); - int (*perfbuffer_enable)(struct gk20a *g, u64 offset, u32 size); - int (*perfbuffer_disable)(struct gk20a *g); - } dbg_session_ops; - - u32 (*get_litter_value)(struct gk20a *g, int value); - int (*chip_init_gpu_characteristics)(struct gk20a *g); - - struct { - void (*init_hw)(struct gk20a *g); - void (*isr)(struct gk20a *g); - int (*bar1_bind)(struct gk20a *g, struct nvgpu_mem *bar1_inst); - int (*bar2_bind)(struct gk20a *g, struct nvgpu_mem *bar1_inst); - u32 (*set_bar0_window)(struct gk20a *g, struct nvgpu_mem *mem, - struct nvgpu_sgt *sgt, struct nvgpu_sgl *sgl, - u32 w); - u32 (*read_sw_scratch)(struct gk20a *g, u32 index); - void (*write_sw_scratch)(struct gk20a *g, u32 index, u32 val); - } bus; - - struct { - void (*isr)(struct gk20a *g); - int (*read_ptimer)(struct gk20a *g, u64 *value); - int (*get_timestamps_zipper)(struct gk20a *g, - u32 source_id, u32 count, - struct nvgpu_cpu_time_correlation_sample *); - } ptimer; - - struct { - int (*init)(struct gk20a *g); - int (*preos_wait_for_halt)(struct gk20a *g); - void (*preos_reload_check)(struct gk20a *g); - int (*devinit)(struct gk20a *g); - int (*preos)(struct gk20a *g); - int (*verify_devinit)(struct gk20a *g); - } bios; - -#if defined(CONFIG_GK20A_CYCLE_STATS) - struct { - int (*enable_snapshot)(struct channel_gk20a *ch, - struct gk20a_cs_snapshot_client *client); - void (*disable_snapshot)(struct gr_gk20a *gr); - int (*check_data_available)(struct channel_gk20a *ch, - u32 *pending, - bool *hw_overflow); - void (*set_handled_snapshots)(struct gk20a *g, u32 num); - u32 (*allocate_perfmon_ids)(struct gk20a_cs_snapshot *data, - u32 count); - u32 (*release_perfmon_ids)(struct gk20a_cs_snapshot *data, - u32 start, - u32 count); - int (*detach_snapshot)(struct channel_gk20a *ch, - struct gk20a_cs_snapshot_client *client); - bool (*get_overflow_status)(struct gk20a *g); - u32 (*get_pending_snapshots)(struct gk20a *g); - } css; -#endif - struct { - int (*get_speed)(struct gk20a *g, u32 *xve_link_speed); - int (*set_speed)(struct gk20a *g, u32 xve_link_speed); - void (*available_speeds)(struct gk20a *g, u32 *speed_mask); - u32 (*xve_readl)(struct gk20a *g, u32 reg); - void (*xve_writel)(struct gk20a *g, u32 reg, u32 val); - void (*disable_aspm)(struct gk20a *g); - void (*reset_gpu)(struct gk20a *g); -#if defined(CONFIG_PCI_MSI) - void (*rearm_msi)(struct gk20a *g); -#endif - void (*enable_shadow_rom)(struct gk20a *g); - void (*disable_shadow_rom)(struct gk20a *g); - u32 (*get_link_control_status)(struct gk20a *g); - } xve; - struct { - int (*falcon_hal_sw_init)(struct nvgpu_falcon *flcn); - } falcon; - struct { - void (*enable_priv_ring)(struct gk20a *g); - void (*isr)(struct gk20a *g); - void (*decode_error_code)(struct gk20a *g, u32 error_code); - void (*set_ppriv_timeout_settings)(struct gk20a *g); - u32 (*enum_ltc)(struct gk20a *g); - } priv_ring; - struct { - int (*check_priv_security)(struct gk20a *g); - bool (*is_opt_ecc_enable)(struct gk20a *g); - bool (*is_opt_feature_override_disable)(struct gk20a *g); - u32 (*fuse_status_opt_fbio)(struct gk20a *g); - u32 (*fuse_status_opt_fbp)(struct gk20a *g); - u32 (*fuse_status_opt_rop_l2_fbp)(struct gk20a *g, u32 fbp); - u32 (*fuse_status_opt_gpc)(struct gk20a *g); - u32 (*fuse_status_opt_tpc_gpc)(struct gk20a *g, u32 gpc); - void (*fuse_ctrl_opt_tpc_gpc)(struct gk20a *g, u32 gpc, u32 val); - u32 (*fuse_opt_sec_debug_en)(struct gk20a *g); - u32 (*fuse_opt_priv_sec_en)(struct gk20a *g); - u32 (*read_vin_cal_fuse_rev)(struct gk20a *g); - u32 (*read_vin_cal_slope_intercept_fuse)(struct gk20a *g, - u32 vin_id, u32 *slope, - u32 *intercept); - u32 (*read_vin_cal_gain_offset_fuse)(struct gk20a *g, - u32 vin_id, s8 *gain, - s8 *offset); - } fuse; - struct { - int (*init)(struct gk20a *g); - int (*discover_ioctrl)(struct gk20a *g); - int (*discover_link)(struct gk20a *g); - int (*isr)(struct gk20a *g); - int (*rxdet)(struct gk20a *g, u32 link_id); - int (*setup_pll)(struct gk20a *g, unsigned long link_mask); - int (*minion_data_ready_en)(struct gk20a *g, - unsigned long link_mask, bool sync); - void (*get_connected_link_mask)(u32 *link_mask); - void (*set_sw_war)(struct gk20a *g, u32 link_id); - /* API */ - int (*link_early_init)(struct gk20a *g, unsigned long mask); - u32 (*link_get_mode)(struct gk20a *g, u32 link_id); - u32 (*link_get_state)(struct gk20a *g, u32 link_id); - int (*link_set_mode)(struct gk20a *g, u32 link_id, u32 mode); - u32 (*get_sublink_mode)(struct gk20a *g, u32 link_id, - bool is_rx_sublink); - u32 (*get_rx_sublink_state)(struct gk20a *g, u32 link_id); - u32 (*get_tx_sublink_state)(struct gk20a *g, u32 link_id); - int (*set_sublink_mode)(struct gk20a *g, u32 link_id, - bool is_rx_sublink, u32 mode); - int (*interface_init)(struct gk20a *g); - int (*interface_disable)(struct gk20a *g); - int (*reg_init)(struct gk20a *g); - int (*shutdown)(struct gk20a *g); - int (*early_init)(struct gk20a *g); - } nvlink; - struct { - u32 (*get_nvhsclk_ctrl_e_clk_nvl)(struct gk20a *g); - void (*set_nvhsclk_ctrl_e_clk_nvl)(struct gk20a *g, u32 val); - u32 (*get_nvhsclk_ctrl_swap_clk_nvl)(struct gk20a *g); - void (*set_nvhsclk_ctrl_swap_clk_nvl)(struct gk20a *g, u32 val); - } top; - struct { - void (*acr_sw_init)(struct gk20a *g, struct nvgpu_acr *acr); - } acr; - struct { - int (*tpc_powergate)(struct gk20a *g, u32 fuse_status); - } tpc; - void (*semaphore_wakeup)(struct gk20a *g, bool post_events); -}; - -struct nvgpu_bios_ucode { - u8 *bootloader; - u32 bootloader_phys_base; - u32 bootloader_size; - u8 *ucode; - u32 phys_base; - u32 size; - u8 *dmem; - u32 dmem_phys_base; - u32 dmem_size; - u32 code_entry_point; -}; - -struct nvgpu_bios { - u32 vbios_version; - u8 vbios_oem_version; - - u8 *data; - size_t size; - - struct nvgpu_bios_ucode devinit; - struct nvgpu_bios_ucode preos; - - u8 *devinit_tables; - u32 devinit_tables_size; - u8 *bootscripts; - u32 bootscripts_size; - - u8 mem_strap_data_count; - u16 mem_strap_xlat_tbl_ptr; - - u32 condition_table_ptr; - - u32 devinit_tables_phys_base; - u32 devinit_script_phys_base; - - struct bit_token *perf_token; - struct bit_token *clock_token; - struct bit_token *virt_token; - u32 expansion_rom_offset; - - u32 nvlink_config_data_offset; -}; - -struct nvgpu_gpu_params { - /* GPU architecture ID */ - u32 gpu_arch; - /* GPU implementation ID */ - u32 gpu_impl; - /* GPU revision ID */ - u32 gpu_rev; - /* sm version */ - u32 sm_arch_sm_version; - /* sm instruction set */ - u32 sm_arch_spa_version; - u32 sm_arch_warp_count; -}; - -struct gk20a { - void (*free)(struct gk20a *g); - struct nvgpu_nvhost_dev *nvhost_dev; - - /* - * Used by . Do not access directly! - */ - unsigned long *enabled_flags; - -#ifdef __KERNEL__ - struct notifier_block nvgpu_reboot_nb; -#endif - - nvgpu_atomic_t usage_count; - - struct nvgpu_mutex ctxsw_disable_lock; - int ctxsw_disable_count; - - struct nvgpu_ref refcount; - - const char *name; - - bool gpu_reset_done; - bool power_on; - bool suspended; - bool sw_ready; - - u64 log_mask; - u32 log_trace; - - struct nvgpu_mutex tpc_pg_lock; - - struct nvgpu_gpu_params params; - - /* - * Guards access to hardware when usual gk20a_{busy,idle} are skipped - * for submits and held for channel lifetime but dropped for an ongoing - * gk20a_do_idle(). - */ - struct nvgpu_rwsem deterministic_busy; - - struct nvgpu_falcon pmu_flcn; - struct nvgpu_falcon sec2_flcn; - struct nvgpu_falcon fecs_flcn; - struct nvgpu_falcon gpccs_flcn; - struct nvgpu_falcon nvdec_flcn; - struct nvgpu_falcon minion_flcn; - struct nvgpu_falcon gsp_flcn; - struct clk_gk20a clk; - struct fifo_gk20a fifo; - struct nvgpu_nvlink_dev nvlink; - struct gr_gk20a gr; - struct sim_nvgpu *sim; - struct mm_gk20a mm; - struct nvgpu_pmu pmu; - struct nvgpu_acr acr; - struct nvgpu_ecc ecc; - struct clk_pmupstate clk_pmu; - struct perf_pmupstate perf_pmu; - struct pmgr_pmupstate pmgr_pmu; - struct therm_pmupstate therm_pmu; - struct nvgpu_sec2 sec2; - struct nvgpu_sched_ctrl sched_ctrl; - -#ifdef CONFIG_DEBUG_FS - struct railgate_stats pstats; -#endif - u32 gr_idle_timeout_default; - bool timeouts_disabled_by_user; - unsigned int ch_wdt_timeout_ms; - u32 fifo_eng_timeout_us; - - struct nvgpu_mutex power_lock; - - /* Channel priorities */ - u32 timeslice_low_priority_us; - u32 timeslice_medium_priority_us; - u32 timeslice_high_priority_us; - u32 min_timeslice_us; - u32 max_timeslice_us; - bool runlist_interleave; - - struct nvgpu_mutex cg_pg_lock; - bool slcg_enabled; - bool blcg_enabled; - bool elcg_enabled; - bool elpg_enabled; - bool aelpg_enabled; - bool can_elpg; - bool mscg_enabled; - bool forced_idle; - bool forced_reset; - bool allow_all; - - u32 ptimer_src_freq; - - int railgate_delay; - u8 ldiv_slowdown_factor; - unsigned int aggressive_sync_destroy_thresh; - bool aggressive_sync_destroy; - - /* Debugfs knob for forcing syncpt support off in runtime. */ - u32 disable_syncpoints; - - bool support_pmu; - - bool is_virtual; - - bool has_cde; - - u32 emc3d_ratio; - - struct nvgpu_spinlock ltc_enabled_lock; - - struct gk20a_ctxsw_ucode_info ctxsw_ucode_info; - - /* - * A group of semaphore pools. One for each channel. - */ - struct nvgpu_semaphore_sea *sema_sea; - - /* held while manipulating # of debug/profiler sessions present */ - /* also prevents debug sessions from attaching until released */ - struct nvgpu_mutex dbg_sessions_lock; - int dbg_powergating_disabled_refcount; /*refcount for pg disable */ - /*refcount for timeout disable */ - nvgpu_atomic_t timeouts_disabled_refcount; - - /* must have dbg_sessions_lock before use */ - struct nvgpu_dbg_reg_op *dbg_regops_tmp_buf; - u32 dbg_regops_tmp_buf_ops; - - /* For perfbuf mapping */ - struct { - struct dbg_session_gk20a *owner; - u64 offset; - } perfbuf; - - /* For profiler reservations */ - struct nvgpu_list_node profiler_objects; - bool global_profiler_reservation_held; - int profiler_reservation_count; - - void (*remove_support)(struct gk20a *); - - u64 pg_ingating_time_us; - u64 pg_ungating_time_us; - u32 pg_gating_cnt; - - struct nvgpu_spinlock mc_enable_lock; - - struct gk20a_as as; - - struct nvgpu_mutex client_lock; - int client_refcount; /* open channels and ctrl nodes */ - - struct gpu_ops ops; - u32 mc_intr_mask_restore[4]; - /*used for change of enum zbc update cmd id from ver 0 to ver1*/ - u32 pmu_ver_cmd_id_zbc_table_update; - u32 pmu_lsf_pmu_wpr_init_done; - u32 pmu_lsf_loaded_falcon_id; - - int irqs_enabled; - int irq_stall; /* can be same as irq_nonstall in case of PCI */ - int irq_nonstall; - u32 max_ltc_count; - u32 ltc_count; - u32 ltc_streamid; - - struct gk20a_worker { - struct nvgpu_thread poll_task; - nvgpu_atomic_t put; - struct nvgpu_cond wq; - struct nvgpu_list_node items; - struct nvgpu_spinlock items_lock; - struct nvgpu_mutex start_lock; - } channel_worker, clk_arb_worker; - - struct { - void (*open)(struct channel_gk20a *ch); - void (*close)(struct channel_gk20a *ch); - void (*work_completion_signal)(struct channel_gk20a *ch); - void (*work_completion_cancel_sync)(struct channel_gk20a *ch); - bool (*os_fence_framework_inst_exists)(struct channel_gk20a *ch); - int (*init_os_fence_framework)( - struct channel_gk20a *ch, const char *fmt, ...); - void (*signal_os_fence_framework)(struct channel_gk20a *ch); - void (*destroy_os_fence_framework)(struct channel_gk20a *ch); - int (*copy_user_gpfifo)(struct nvgpu_gpfifo_entry *dest, - struct nvgpu_gpfifo_userdata userdata, - u32 start, u32 length); - int (*alloc_usermode_buffers)(struct channel_gk20a *c, - struct nvgpu_setup_bind_args *args); - void (*free_usermode_buffers)(struct channel_gk20a *c); - } os_channel; - - struct gk20a_scale_profile *scale_profile; - unsigned long last_freq; - - struct gk20a_ctxsw_trace *ctxsw_trace; - struct gk20a_fecs_trace *fecs_trace; - - bool mmu_debug_ctrl; - u32 mmu_debug_mode_refcnt; - - u32 tpc_fs_mask_user; - - u32 tpc_pg_mask; - u32 tpc_count; - bool can_tpc_powergate; - - u32 valid_tpc_mask[MAX_TPC_PG_CONFIGS]; - - struct nvgpu_bios bios; - bool bios_is_init; - - struct nvgpu_clk_arb *clk_arb; - - struct nvgpu_mutex clk_arb_enable_lock; - - nvgpu_atomic_t clk_arb_global_nr; - - struct gk20a_ce_app ce_app; - - bool ltc_intr_en_illegal_compstat; - - /* PCI device identifier */ - u16 pci_vendor_id, pci_device_id; - u16 pci_subsystem_vendor_id, pci_subsystem_device_id; - u16 pci_class; - u8 pci_revision; - - /* - * PCI power management: i2c device index, port and address for - * INA3221. - */ - u32 ina3221_dcb_index; - u32 ina3221_i2c_address; - u32 ina3221_i2c_port; - bool hardcode_sw_threshold; - - /* PCIe power states. */ - bool xve_l0s; - bool xve_l1; - - /* Current warning temp in sfxp24.8 */ - s32 curr_warn_temp; - -#if defined(CONFIG_PCI_MSI) - /* Check if msi is enabled */ - bool msi_enabled; -#endif -#ifdef CONFIG_NVGPU_TRACK_MEM_USAGE - struct nvgpu_mem_alloc_tracker *vmallocs; - struct nvgpu_mem_alloc_tracker *kmallocs; -#endif - - /* The minimum VBIOS version supported */ - u32 vbios_min_version; - - /* memory training sequence and mclk switch scripts */ - u32 mem_config_idx; - - u64 dma_memory_used; - -#if defined(CONFIG_TEGRA_GK20A_NVHOST) - u64 syncpt_unit_base; - size_t syncpt_unit_size; - u32 syncpt_size; -#endif - struct nvgpu_mem syncpt_mem; - - struct nvgpu_list_node boardobj_head; - struct nvgpu_list_node boardobjgrp_head; - - struct nvgpu_mem pdb_cache_war_mem; -}; - -static inline bool nvgpu_is_timeouts_enabled(struct gk20a *g) -{ - return nvgpu_atomic_read(&g->timeouts_disabled_refcount) == 0; -} - -static inline u32 gk20a_get_gr_idle_timeout(struct gk20a *g) -{ - return nvgpu_is_timeouts_enabled(g) ? - g->gr_idle_timeout_default : UINT_MAX; -} - -#define MULTICHAR_TAG(a, b, c, d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d)) -enum BAR0_DEBUG_OPERATION { - BARO_ZERO_NOP = 0, - OP_END = MULTICHAR_TAG('D', 'O', 'N', 'E'), - BAR0_READ32 = MULTICHAR_TAG('0', 'R', '3', '2'), - BAR0_WRITE32 = MULTICHAR_TAG('0', 'W', '3', '2'), -}; - -struct share_buffer_head { - enum BAR0_DEBUG_OPERATION operation; -/* size of the operation item */ - u32 size; - u32 completed; - u32 failed; - u64 context; - u64 completion_callback; -}; - -struct gk20a_cyclestate_buffer_elem { - struct share_buffer_head head; -/* in */ - u64 p_data; - u64 p_done; - u32 offset_bar0; - u16 first_bit; - u16 last_bit; -/* out */ -/* keep 64 bits to be consistent */ - u64 data; -}; - -/* operations that will need to be executed on non stall workqueue */ -#define GK20A_NONSTALL_OPS_WAKEUP_SEMAPHORE BIT32(0) -#define GK20A_NONSTALL_OPS_POST_EVENTS BIT32(1) - -/* register accessors */ -void __nvgpu_check_gpu_state(struct gk20a *g); -void __gk20a_warn_on_no_regs(void); - -/* classes that the device supports */ -/* TBD: get these from an open-sourced SDK? */ -enum { - FERMI_TWOD_A = 0x902D, - KEPLER_INLINE_TO_MEMORY_A = 0xA040, - KEPLER_DMA_COPY_A = 0xA0B5, -}; - -#define GK20A_BAR0_IORESOURCE_MEM 0 -#define GK20A_BAR1_IORESOURCE_MEM 1 -#define GK20A_SIM_IORESOURCE_MEM 2 - -void gk20a_busy_noresume(struct gk20a *g); -void gk20a_idle_nosuspend(struct gk20a *g); -int __must_check gk20a_busy(struct gk20a *g); -void gk20a_idle(struct gk20a *g); -int __gk20a_do_idle(struct gk20a *g, bool force_reset); -int __gk20a_do_unidle(struct gk20a *g); - -int gk20a_wait_for_idle(struct gk20a *g); - -#define NVGPU_GPU_ARCHITECTURE_SHIFT 4 - -/* constructs unique and compact GPUID from nvgpu_gpu_characteristics - * arch/impl fields */ -#define GK20A_GPUID(arch, impl) ((u32) ((arch) | (impl))) - -#define GK20A_GPUID_GK20A 0x000000EA -#define GK20A_GPUID_GM20B 0x0000012B -#define GK20A_GPUID_GM20B_B 0x0000012E -#define NVGPU_GPUID_GP10B 0x0000013B -#define NVGPU_GPUID_GP104 0x00000134 -#define NVGPU_GPUID_GP106 0x00000136 -#define NVGPU_GPUID_GV11B 0x0000015B -#define NVGPU_GPUID_GV100 0x00000140 - -int gk20a_init_gpu_characteristics(struct gk20a *g); - -bool gk20a_check_poweron(struct gk20a *g); -int gk20a_prepare_poweroff(struct gk20a *g); -int gk20a_finalize_poweron(struct gk20a *g); - -int nvgpu_wait_for_stall_interrupts(struct gk20a *g, u32 timeout); -int nvgpu_wait_for_nonstall_interrupts(struct gk20a *g, u32 timeout); -void nvgpu_wait_for_deferred_interrupts(struct gk20a *g); - -struct gk20a * __must_check gk20a_get(struct gk20a *g); -void gk20a_put(struct gk20a *g); - -bool nvgpu_has_syncpoints(struct gk20a *g); - -#endif /* GK20A_H */ diff --git a/include/nvgpu/gmmu.h b/include/nvgpu/gmmu.h deleted file mode 100644 index 2fc0d44..0000000 --- a/include/nvgpu/gmmu.h +++ /dev/null @@ -1,369 +0,0 @@ -/* - * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_GMMU_H -#define NVGPU_GMMU_H - -#include -#include -#include -#include -#include -#include -#include - -/* - * This is the GMMU API visible to blocks outside of the GMMU. Basically this - * API supports all the different types of mappings that might be done in the - * GMMU. - */ - -struct vm_gk20a; -struct nvgpu_mem; - -#define GMMU_PAGE_SIZE_SMALL 0U -#define GMMU_PAGE_SIZE_BIG 1U -#define GMMU_PAGE_SIZE_KERNEL 2U -#define GMMU_NR_PAGE_SIZES 3U - -enum gk20a_mem_rw_flag { - gk20a_mem_flag_none = 0, /* RW */ - gk20a_mem_flag_read_only = 1, /* RO */ - gk20a_mem_flag_write_only = 2, /* WO */ -}; - -/* - * Minimum size of a cache. The number of different caches in the nvgpu_pd_cache - * structure is of course depending on this. The MIN_SHIFT define is the right - * number of bits to shift to determine which list to use in the array of lists. - * - * For Linux, limit the use of the cache to entries less than the page size, to - * avoid potential problems with running out of CMA memory when allocating large, - * contiguous slabs, as would be required for non-iommmuable chips. - */ -#define NVGPU_PD_CACHE_MIN 256U -#define NVGPU_PD_CACHE_MIN_SHIFT 9U - -#ifdef __KERNEL__ - -#if PAGE_SIZE == 4096 -#define NVGPU_PD_CACHE_COUNT 4U -#elif PAGE_SIZE == 65536 -#define NVGPU_PD_CACHE_COUNT 8U -#else -#error "Unsupported page size." -#endif - -#else -#define NVGPU_PD_CACHE_COUNT 8U -#endif - -#define NVGPU_PD_CACHE_SIZE (NVGPU_PD_CACHE_MIN * (1U << NVGPU_PD_CACHE_COUNT)) - -struct nvgpu_pd_mem_entry { - struct nvgpu_mem mem; - - /* - * Size of the page directories (not the mem). alloc_map is a bitmap - * showing which PDs have been allocated. - * - * The size of mem will be NVGPU_PD_CACHE_SIZE - * and pd_size will always be a power of 2. - * - */ - u32 pd_size; - DECLARE_BITMAP(alloc_map, NVGPU_PD_CACHE_SIZE / NVGPU_PD_CACHE_MIN); - - /* Total number of allocations in this PD. */ - u32 allocs; - - struct nvgpu_list_node list_entry; - struct nvgpu_rbtree_node tree_entry; -}; - -static inline struct nvgpu_pd_mem_entry * -nvgpu_pd_mem_entry_from_list_entry(struct nvgpu_list_node *node) -{ - return (struct nvgpu_pd_mem_entry *) - ((uintptr_t)node - - offsetof(struct nvgpu_pd_mem_entry, list_entry)); -}; - -static inline struct nvgpu_pd_mem_entry * -nvgpu_pd_mem_entry_from_tree_entry(struct nvgpu_rbtree_node *node) -{ - return (struct nvgpu_pd_mem_entry *) - ((uintptr_t)node - - offsetof(struct nvgpu_pd_mem_entry, tree_entry)); -}; - -/* - * A cache for allocating PD memory from. This enables smaller PDs to be packed - * into single pages. - * - * This is fairly complex so see the documentation in pd_cache.c for a full - * description of how this is organized. - */ -struct nvgpu_pd_cache { - /* - * Array of lists of full nvgpu_pd_mem_entries and partially full (or - * empty) nvgpu_pd_mem_entries. - */ - struct nvgpu_list_node full[NVGPU_PD_CACHE_COUNT]; - struct nvgpu_list_node partial[NVGPU_PD_CACHE_COUNT]; - - /* - * Tree of all allocated struct nvgpu_mem's for fast look up. - */ - struct nvgpu_rbtree_node *mem_tree; - - /* - * All access to the cache much be locked. This protects the lists and - * the rb tree. - */ - struct nvgpu_mutex lock; -}; - -/* - * GMMU page directory. This is the kernel's tracking of a list of PDEs or PTEs - * in the GMMU. - */ -struct nvgpu_gmmu_pd { - /* - * DMA memory describing the PTEs or PDEs. @mem_offs describes the - * offset of the PDE table in @mem. @cached specifies if this PD is - * using pd_cache memory. - */ - struct nvgpu_mem *mem; - u32 mem_offs; - bool cached; - - /* - * List of pointers to the next level of page tables. Does not - * need to be populated when this PD is pointing to PTEs. - */ - struct nvgpu_gmmu_pd *entries; - int num_entries; -}; - -/* - * Reduce the number of arguments getting passed through the various levels of - * GMMU mapping functions. - * - * The following fields are set statically and do not change throughout the - * mapping call: - * - * pgsz: Index into the page size table. - * kind_v: Kind attributes for mapping. - * cacheable: Cacheability of the mapping. - * rw_flag: Flag from enum gk20a_mem_rw_flag - * sparse: Set if the mapping should be sparse. - * priv: Privilidged mapping. - * coherent: Set if the mapping should be IO coherent. - * valid: Set if the PTE should be marked valid. - * aperture: VIDMEM or SYSMEM. - * debug: When set print debugging info. - * platform_atomic: True if platform_atomic flag is valid. - * - * These fields are dynamically updated as necessary during the map: - * - * ctag: Comptag line in the comptag cache; - * updated every time we write a PTE. - */ -struct nvgpu_gmmu_attrs { - u32 pgsz; - u32 kind_v; - u64 ctag; - bool cacheable; - enum gk20a_mem_rw_flag rw_flag; - bool sparse; - bool priv; - bool valid; - enum nvgpu_aperture aperture; - bool debug; - bool l3_alloc; - bool platform_atomic; -}; - -struct gk20a_mmu_level { - int hi_bit[2]; - int lo_bit[2]; - - /* - * Build map from virt_addr -> phys_addr. - */ - void (*update_entry)(struct vm_gk20a *vm, - const struct gk20a_mmu_level *l, - struct nvgpu_gmmu_pd *pd, - u32 pd_idx, - u64 phys_addr, - u64 virt_addr, - struct nvgpu_gmmu_attrs *attrs); - u32 entry_size; - /* - * Get pde page size - */ - u32 (*get_pgsz)(struct gk20a *g, const struct gk20a_mmu_level *l, - struct nvgpu_gmmu_pd *pd, u32 pd_idx); -}; - -static inline const char *nvgpu_gmmu_perm_str(enum gk20a_mem_rw_flag p) -{ - switch (p) { - case gk20a_mem_flag_none: - return "RW"; - case gk20a_mem_flag_write_only: - return "WO"; - case gk20a_mem_flag_read_only: - return "RO"; - default: - return "??"; - } -} - -int nvgpu_gmmu_init_page_table(struct vm_gk20a *vm); - -/** - * nvgpu_gmmu_map - Map memory into the GMMU. - * - * Kernel space. - */ -u64 nvgpu_gmmu_map(struct vm_gk20a *vm, - struct nvgpu_mem *mem, - u64 size, - u32 flags, - enum gk20a_mem_rw_flag rw_flag, - bool priv, - enum nvgpu_aperture aperture); - -/** - * nvgpu_gmmu_map_fixed - Map memory into the GMMU. - * - * Kernel space. - */ -u64 nvgpu_gmmu_map_fixed(struct vm_gk20a *vm, - struct nvgpu_mem *mem, - u64 addr, - u64 size, - u32 flags, - enum gk20a_mem_rw_flag rw_flag, - bool priv, - enum nvgpu_aperture aperture); - -/** - * nvgpu_gmmu_unmap - Unmap a buffer. - * - * Kernel space. - */ -void nvgpu_gmmu_unmap(struct vm_gk20a *vm, - struct nvgpu_mem *mem, - u64 gpu_va); - -int nvgpu_pd_alloc(struct vm_gk20a *vm, - struct nvgpu_gmmu_pd *pd, - u32 bytes); - -void nvgpu_pd_free(struct vm_gk20a *vm, struct nvgpu_gmmu_pd *pd); -int nvgpu_pd_cache_alloc_direct(struct gk20a *g, - struct nvgpu_gmmu_pd *pd, u32 bytes); -void nvgpu_pd_cache_free_direct(struct gk20a *g, struct nvgpu_gmmu_pd *pd); -int nvgpu_pd_cache_init(struct gk20a *g); -void nvgpu_pd_cache_fini(struct gk20a *g); - -/* - * Some useful routines that are shared across chips. - */ -static inline u32 pd_offset_from_index(const struct gk20a_mmu_level *l, - u32 pd_idx) -{ - return (pd_idx * l->entry_size) / sizeof(u32); -} - -static inline void pd_write(struct gk20a *g, struct nvgpu_gmmu_pd *pd, - size_t w, size_t data) -{ - nvgpu_mem_wr32(g, pd->mem, (pd->mem_offs / sizeof(u32)) + w, data); -} - -/** - * __nvgpu_pte_words - Compute number of words in a PTE. - * - * @g - The GPU. - * - * This computes and returns the size of a PTE for the passed chip. - */ -u32 __nvgpu_pte_words(struct gk20a *g); - -/** - * __nvgpu_get_pte - Get the contents of a PTE by virtual address - * - * @g - The GPU. - * @vm - VM to look in. - * @vaddr - GPU virtual address. - * @pte - [out] Set to the contents of the PTE. - * - * Find a PTE in the passed VM based on the passed GPU virtual address. This - * will @pte with a copy of the contents of the PTE. @pte must be an array of - * u32s large enough to contain the PTE. This can be computed using - * __nvgpu_pte_words(). - * - * If you wish to write to this PTE then you may modify @pte and then use the - * __nvgpu_set_pte(). - * - * This function returns 0 if the PTE is found and -EINVAL otherwise. - */ -int __nvgpu_get_pte(struct gk20a *g, struct vm_gk20a *vm, u64 vaddr, u32 *pte); - -/** - * __nvgpu_set_pte - Set a PTE based on virtual address - * - * @g - The GPU. - * @vm - VM to look in. - * @vaddr - GPU virtual address. - * @pte - The contents of the PTE to write. - * - * Find a PTE and overwrite the contents of that PTE with the passed in data - * located in @pte. If the PTE does not exist then no writing will happen. That - * is this function will not fill out the page tables for you. The expectation - * is that the passed @vaddr has already been mapped and this is just modifying - * the mapping (for instance changing invalid to valid). - * - * @pte must contain at least the required words for the PTE. See - * __nvgpu_pte_words(). - * - * This function returns 0 on success and -EINVAL otherwise. - */ -int __nvgpu_set_pte(struct gk20a *g, struct vm_gk20a *vm, u64 vaddr, u32 *pte); - - -/* - * Internal debugging routines. Probably not something you want to use. - */ -#define pte_dbg(g, attrs, fmt, args...) \ - do { \ - if ((attrs != NULL) && (attrs->debug)) \ - nvgpu_info(g, fmt, ##args); \ - else \ - nvgpu_log(g, gpu_dbg_pte, fmt, ##args); \ - } while (0) - -#endif /* NVGPU_GMMU_H */ diff --git a/include/nvgpu/hal_init.h b/include/nvgpu/hal_init.h deleted file mode 100644 index 06e58e7..0000000 --- a/include/nvgpu/hal_init.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * NVIDIA GPU Hardware Abstraction Layer functions definitions. - * - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_HAL_INIT_H -#define NVGPU_HAL_INIT_H - -struct gk20a; - -int nvgpu_init_hal(struct gk20a *g); -int nvgpu_detect_chip(struct gk20a *g); - -#endif /* NVGPU_HAL_INIT_H */ diff --git a/include/nvgpu/hashtable.h b/include/nvgpu/hashtable.h deleted file mode 100644 index 5ce56f0..0000000 --- a/include/nvgpu/hashtable.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef __NVGPU_SORT_H__ -#define __NVGPU_SORT_H__ - -#ifdef __KERNEL__ -#include -#endif - -#endif diff --git a/include/nvgpu/hw/gk20a/hw_bus_gk20a.h b/include/nvgpu/hw/gk20a/hw_bus_gk20a.h deleted file mode 100644 index d3bb9e9..0000000 --- a/include/nvgpu/hw/gk20a/hw_bus_gk20a.h +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_bus_gk20a_h_ -#define _hw_bus_gk20a_h_ - -static inline u32 bus_bar0_window_r(void) -{ - return 0x00001700U; -} -static inline u32 bus_bar0_window_base_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 bus_bar0_window_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) -{ - return 0x2000000U; -} -static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) -{ - return 0x3000000U; -} -static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) -{ - return 0x00000010U; -} -static inline u32 bus_bar1_block_r(void) -{ - return 0x00001704U; -} -static inline u32 bus_bar1_block_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 bus_bar1_block_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar1_block_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 bus_bar1_block_mode_virtual_f(void) -{ - return 0x80000000U; -} -static inline u32 bus_bar2_block_r(void) -{ - return 0x00001714U; -} -static inline u32 bus_bar2_block_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 bus_bar2_block_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar2_block_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 bus_bar2_block_mode_virtual_f(void) -{ - return 0x80000000U; -} -static inline u32 bus_bar1_block_ptr_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 bus_bar2_block_ptr_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 bus_intr_0_r(void) -{ - return 0x00001100U; -} -static inline u32 bus_intr_0_pri_squash_m(void) -{ - return 0x1U << 1U; -} -static inline u32 bus_intr_0_pri_fecserr_m(void) -{ - return 0x1U << 2U; -} -static inline u32 bus_intr_0_pri_timeout_m(void) -{ - return 0x1U << 3U; -} -static inline u32 bus_intr_en_0_r(void) -{ - return 0x00001140U; -} -static inline u32 bus_intr_en_0_pri_squash_m(void) -{ - return 0x1U << 1U; -} -static inline u32 bus_intr_en_0_pri_fecserr_m(void) -{ - return 0x1U << 2U; -} -static inline u32 bus_intr_en_0_pri_timeout_m(void) -{ - return 0x1U << 3U; -} -#endif diff --git a/include/nvgpu/hw/gk20a/hw_ccsr_gk20a.h b/include/nvgpu/hw/gk20a/hw_ccsr_gk20a.h deleted file mode 100644 index 95151f6..0000000 --- a/include/nvgpu/hw/gk20a/hw_ccsr_gk20a.h +++ /dev/null @@ -1,163 +0,0 @@ -/* - * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ccsr_gk20a_h_ -#define _hw_ccsr_gk20a_h_ - -static inline u32 ccsr_channel_inst_r(u32 i) -{ - return 0x00800000U + i*8U; -} -static inline u32 ccsr_channel_inst__size_1_v(void) -{ - return 0x00000080U; -} -static inline u32 ccsr_channel_inst_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 ccsr_channel_inst_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 ccsr_channel_inst_bind_false_f(void) -{ - return 0x0U; -} -static inline u32 ccsr_channel_inst_bind_true_f(void) -{ - return 0x80000000U; -} -static inline u32 ccsr_channel_r(u32 i) -{ - return 0x00800004U + i*8U; -} -static inline u32 ccsr_channel__size_1_v(void) -{ - return 0x00000080U; -} -static inline u32 ccsr_channel_enable_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ccsr_channel_enable_set_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 ccsr_channel_enable_set_true_f(void) -{ - return 0x400U; -} -static inline u32 ccsr_channel_enable_clr_true_f(void) -{ - return 0x800U; -} -static inline u32 ccsr_channel_runlist_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 ccsr_channel_status_v(u32 r) -{ - return (r >> 24U) & 0xfU; -} -static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) -{ - return 0x00000002U; -} -static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) -{ - return 0x00000004U; -} -static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) -{ - return 0x0000000aU; -} -static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) -{ - return 0x0000000bU; -} -static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) -{ - return 0x0000000cU; -} -static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) -{ - return 0x0000000dU; -} -static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) -{ - return 0x0000000eU; -} -static inline u32 ccsr_channel_next_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ccsr_channel_next_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_busy_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -#endif diff --git a/include/nvgpu/hw/gk20a/hw_ce2_gk20a.h b/include/nvgpu/hw/gk20a/hw_ce2_gk20a.h deleted file mode 100644 index 87481cd..0000000 --- a/include/nvgpu/hw/gk20a/hw_ce2_gk20a.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ce2_gk20a_h_ -#define _hw_ce2_gk20a_h_ - -static inline u32 ce2_intr_status_r(void) -{ - return 0x00106908U; -} -static inline u32 ce2_intr_status_blockpipe_pending_f(void) -{ - return 0x1U; -} -static inline u32 ce2_intr_status_blockpipe_reset_f(void) -{ - return 0x1U; -} -static inline u32 ce2_intr_status_nonblockpipe_pending_f(void) -{ - return 0x2U; -} -static inline u32 ce2_intr_status_nonblockpipe_reset_f(void) -{ - return 0x2U; -} -static inline u32 ce2_intr_status_launcherr_pending_f(void) -{ - return 0x4U; -} -static inline u32 ce2_intr_status_launcherr_reset_f(void) -{ - return 0x4U; -} -#endif diff --git a/include/nvgpu/hw/gk20a/hw_ctxsw_prog_gk20a.h b/include/nvgpu/hw/gk20a/hw_ctxsw_prog_gk20a.h deleted file mode 100644 index 131fd12..0000000 --- a/include/nvgpu/hw/gk20a/hw_ctxsw_prog_gk20a.h +++ /dev/null @@ -1,447 +0,0 @@ -/* - * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ctxsw_prog_gk20a_h_ -#define _hw_ctxsw_prog_gk20a_h_ - -static inline u32 ctxsw_prog_fecs_header_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) -{ - return 0x00000008U; -} -static inline u32 ctxsw_prog_main_image_patch_count_o(void) -{ - return 0x00000010U; -} -static inline u32 ctxsw_prog_main_image_context_id_o(void) -{ - return 0x000000f0U; -} -static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) -{ - return 0x00000014U; -} -static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) -{ - return 0x00000018U; -} -static inline u32 ctxsw_prog_main_image_zcull_o(void) -{ - return 0x0000001cU; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) -{ - return 0x00000001U; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) -{ - return 0x00000020U; -} -static inline u32 ctxsw_prog_main_image_pm_o(void) -{ - return 0x00000028U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_m(void) -{ - return 0x7U << 0U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_ctxsw_f(void) -{ - return 0x1U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) -{ - return 0x7U << 3U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) -{ - return 0x8U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) -{ - return 0x0000002cU; -} -static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) -{ - return 0x000000f4U; -} -static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) -{ - return 0x000000f8U; -} -static inline u32 ctxsw_prog_main_image_magic_value_o(void) -{ - return 0x000000fcU; -} -static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) -{ - return 0x600dc0deU; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_ppc_info_o(void) -{ - return 0x000000f4U; -} -static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) -{ - return 0x000000f8U; -} -static inline u32 ctxsw_prog_local_magic_value_o(void) -{ - return 0x000000fcU; -} -static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) -{ - return 0xad0becabU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) -{ - return 0x000000ecU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) -{ - return 0x00000005U; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_extended_num_smpc_quadrants_v(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) -{ - return 0x000000a0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) -{ - return 2U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) -{ - return 0x3U << 0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) -{ - return 0x2U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) -{ - return 0x000000a4U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) -{ - return 0x000000a8U; -} -static inline u32 ctxsw_prog_main_image_misc_options_o(void) -{ - return 0x0000003cU; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) -{ - return 0x1U << 3U; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_o(void) -{ - return 0x000000acU; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(void) -{ - return 0x000000b0U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m(void) -{ - return 0xfffffffU << 0U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_m(void) -{ - return 0x3U << 28U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_coherent_f(void) -{ - return 0x20000000U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_noncoherent_f(void) -{ - return 0x30000000U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(void) -{ - return 0x000000b4U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_record_timestamp_record_size_in_bytes_v(void) -{ - return 0x00000080U; -} -static inline u32 ctxsw_prog_record_timestamp_record_size_in_words_v(void) -{ - return 0x00000020U; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_o(void) -{ - return 0x00000000U; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_v_value_v(void) -{ - return 0x00000000U; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_o(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_v_value_v(void) -{ - return 0x600dbeefU; -} -static inline u32 ctxsw_prog_record_timestamp_context_id_o(void) -{ - return 0x00000008U; -} -static inline u32 ctxsw_prog_record_timestamp_context_ptr_o(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_record_timestamp_new_context_id_o(void) -{ - return 0x00000010U; -} -static inline u32 ctxsw_prog_record_timestamp_new_context_ptr_o(void) -{ - return 0x00000014U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_lo_o(void) -{ - return 0x00000018U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_o(void) -{ - return 0x0000001cU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_m(void) -{ - return 0xffU << 24U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_v(u32 r) -{ - return (r >> 24U) & 0xffU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v(void) -{ - return 0x00000001U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_f(void) -{ - return 0x1000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_f(void) -{ - return 0x2000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_v(void) -{ - return 0x0000000aU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_f(void) -{ - return 0xa000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_v(void) -{ - return 0x0000000bU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_f(void) -{ - return 0xb000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_v(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_f(void) -{ - return 0xc000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_v(void) -{ - return 0x0000000dU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_f(void) -{ - return 0xd000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_v(void) -{ - return 0x00000003U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_f(void) -{ - return 0x3000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_v(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_f(void) -{ - return 0x4000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_v(void) -{ - return 0x00000005U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_f(void) -{ - return 0x5000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v(void) -{ - return 0x000000ffU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f(void) -{ - return 0xff000000U; -} -#endif diff --git a/include/nvgpu/hw/gk20a/hw_falcon_gk20a.h b/include/nvgpu/hw/gk20a/hw_falcon_gk20a.h deleted file mode 100644 index 7b4d87b..0000000 --- a/include/nvgpu/hw/gk20a/hw_falcon_gk20a.h +++ /dev/null @@ -1,559 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_falcon_gk20a_h_ -#define _hw_falcon_gk20a_h_ - -static inline u32 falcon_falcon_irqsset_r(void) -{ - return 0x00000000U; -} -static inline u32 falcon_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 falcon_falcon_irqsclr_r(void) -{ - return 0x00000004U; -} -static inline u32 falcon_falcon_irqstat_r(void) -{ - return 0x00000008U; -} -static inline u32 falcon_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 falcon_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 falcon_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 falcon_falcon_irqmode_r(void) -{ - return 0x0000000cU; -} -static inline u32 falcon_falcon_irqmset_r(void) -{ - return 0x00000010U; -} -static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqmclr_r(void) -{ - return 0x00000014U; -} -static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_irqmask_r(void) -{ - return 0x00000018U; -} -static inline u32 falcon_falcon_irqdest_r(void) -{ - return 0x0000001cU; -} -static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 falcon_falcon_curctx_r(void) -{ - return 0x00000050U; -} -static inline u32 falcon_falcon_nxtctx_r(void) -{ - return 0x00000054U; -} -static inline u32 falcon_falcon_mailbox0_r(void) -{ - return 0x00000040U; -} -static inline u32 falcon_falcon_mailbox1_r(void) -{ - return 0x00000044U; -} -static inline u32 falcon_falcon_itfen_r(void) -{ - return 0x00000048U; -} -static inline u32 falcon_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 falcon_falcon_idlestate_r(void) -{ - return 0x0000004cU; -} -static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 falcon_falcon_os_r(void) -{ - return 0x00000080U; -} -static inline u32 falcon_falcon_engctl_r(void) -{ - return 0x000000a4U; -} -static inline u32 falcon_falcon_cpuctl_r(void) -{ - return 0x00000100U; -} -static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_m(void) -{ - return 0x1U << 4U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 falcon_falcon_cpuctl_stopped_m(void) -{ - return 0x1U << 5U; -} -static inline u32 falcon_falcon_imemc_r(u32 i) -{ - return 0x00000180U + i*16U; -} -static inline u32 falcon_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 falcon_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 falcon_falcon_imemc_secure_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 falcon_falcon_imemd_r(u32 i) -{ - return 0x00000184U + i*16U; -} -static inline u32 falcon_falcon_imemt_r(u32 i) -{ - return 0x00000188U + i*16U; -} -static inline u32 falcon_falcon_bootvec_r(void) -{ - return 0x00000104U; -} -static inline u32 falcon_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 falcon_falcon_dmactl_r(void) -{ - return 0x0000010cU; -} -static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void) -{ - return 0x1U << 1U; -} -static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void) -{ - return 0x1U << 2U; -} -static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_hwcfg_r(void) -{ - return 0x00000108U; -} -static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 falcon_falcon_dmatrfbase_r(void) -{ - return 0x00000110U; -} -static inline u32 falcon_falcon_dmatrfmoffs_r(void) -{ - return 0x00000114U; -} -static inline u32 falcon_falcon_dmatrfcmd_r(void) -{ - return 0x00000118U; -} -static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 falcon_falcon_dmatrffboffs_r(void) -{ - return 0x0000011cU; -} -static inline u32 falcon_falcon_imstat_r(void) -{ - return 0x00000144U; -} -static inline u32 falcon_falcon_traceidx_r(void) -{ - return 0x00000148U; -} -static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 falcon_falcon_traceidx_idx_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 falcon_falcon_tracepc_r(void) -{ - return 0x0000014cU; -} -static inline u32 falcon_falcon_tracepc_pc_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 falcon_falcon_exterraddr_r(void) -{ - return 0x00000168U; -} -static inline u32 falcon_falcon_exterrstat_r(void) -{ - return 0x0000016cU; -} -static inline u32 falcon_falcon_exterrstat_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 falcon_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 falcon_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 falcon_falcon_icd_cmd_r(void) -{ - return 0x00000200U; -} -static inline u32 falcon_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 falcon_falcon_icd_cmd_opc_m(void) -{ - return 0xfU << 0U; -} -static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 falcon_falcon_icd_rdata_r(void) -{ - return 0x0000020cU; -} -static inline u32 falcon_falcon_dmemc_r(u32 i) -{ - return 0x000001c0U + i*8U; -} -static inline u32 falcon_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 falcon_falcon_dmemc_offs_m(void) -{ - return 0x3fU << 2U; -} -static inline u32 falcon_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_dmemc_blk_m(void) -{ - return 0xffU << 8U; -} -static inline u32 falcon_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 falcon_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 falcon_falcon_dmemd_r(u32 i) -{ - return 0x000001c4U + i*8U; -} -static inline u32 falcon_falcon_debug1_r(void) -{ - return 0x00000090U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void) -{ - return 1U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void) -{ - return 0x1U << 16U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void) -{ - return 0x0U; -} -static inline u32 falcon_falcon_debuginfo_r(void) -{ - return 0x00000094U; -} -#endif diff --git a/include/nvgpu/hw/gk20a/hw_fb_gk20a.h b/include/nvgpu/hw/gk20a/hw_fb_gk20a.h deleted file mode 100644 index 42df4f5..0000000 --- a/include/nvgpu/hw/gk20a/hw_fb_gk20a.h +++ /dev/null @@ -1,263 +0,0 @@ -/* - * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_fb_gk20a_h_ -#define _hw_fb_gk20a_h_ - -static inline u32 fb_mmu_ctrl_r(void) -{ - return 0x00100c80U; -} -static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 fb_mmu_invalidate_pdb_r(void) -{ - return 0x00100cb8U; -} -static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_invalidate_r(void) -{ - return 0x00100cbcU; -} -static inline u32 fb_mmu_invalidate_all_va_true_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_invalidate_trigger_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_trigger_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_invalidate_trigger_m(void) -{ - return 0x1U << 31U; -} -static inline u32 fb_mmu_invalidate_trigger_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_trigger_true_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_debug_wr_r(void) -{ - return 0x00100cc8U; -} -static inline u32 fb_mmu_debug_wr_aperture_s(void) -{ - return 2U; -} -static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 fb_mmu_debug_wr_aperture_m(void) -{ - return 0x3U << 0U; -} -static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_debug_wr_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_wr_vol_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_debug_wr_vol_true_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_debug_wr_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) -{ - return 0x0000000cU; -} -static inline u32 fb_mmu_debug_rd_r(void) -{ - return 0x00100cccU; -} -static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_debug_rd_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_rd_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) -{ - return 0x0000000cU; -} -static inline u32 fb_mmu_debug_ctrl_r(void) -{ - return 0x00100cc4U; -} -static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 fb_mmu_debug_ctrl_debug_m(void) -{ - return 0x1U << 16U; -} -static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_debug_ctrl_debug_enabled_f(void) -{ - return 0x10000U; -} -static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_debug_ctrl_debug_disabled_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_vpr_info_r(void) -{ - return 0x00100cd0U; -} -static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 fb_mmu_vpr_info_fetch_false_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_vpr_info_fetch_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_niso_flush_sysmem_addr_r(void) -{ - return 0x00100c10U; -} -#endif diff --git a/include/nvgpu/hw/gk20a/hw_fifo_gk20a.h b/include/nvgpu/hw/gk20a/hw_fifo_gk20a.h deleted file mode 100644 index e61e386..0000000 --- a/include/nvgpu/hw/gk20a/hw_fifo_gk20a.h +++ /dev/null @@ -1,619 +0,0 @@ -/* - * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_fifo_gk20a_h_ -#define _hw_fifo_gk20a_h_ - -static inline u32 fifo_bar1_base_r(void) -{ - return 0x00002254U; -} -static inline u32 fifo_bar1_base_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 fifo_bar1_base_ptr_align_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 fifo_bar1_base_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 fifo_bar1_base_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 fifo_runlist_base_r(void) -{ - return 0x00002270U; -} -static inline u32 fifo_runlist_base_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 fifo_runlist_base_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 fifo_runlist_r(void) -{ - return 0x00002274U; -} -static inline u32 fifo_runlist_engine_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 fifo_eng_runlist_base_r(u32 i) -{ - return 0x00002280U + i*8U; -} -static inline u32 fifo_eng_runlist_base__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_eng_runlist_r(u32 i) -{ - return 0x00002284U + i*8U; -} -static inline u32 fifo_eng_runlist__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_eng_runlist_length_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fifo_eng_runlist_length_max_v(void) -{ - return 0x0000ffffU; -} -static inline u32 fifo_eng_runlist_pending_true_f(void) -{ - return 0x100000U; -} -static inline u32 fifo_runlist_timeslice_r(u32 i) -{ - return 0x00002310U + i*4U; -} -static inline u32 fifo_runlist_timeslice_timeout_128_f(void) -{ - return 0x80U; -} -static inline u32 fifo_runlist_timeslice_timescale_3_f(void) -{ - return 0x3000U; -} -static inline u32 fifo_runlist_timeslice_enable_true_f(void) -{ - return 0x10000000U; -} -static inline u32 fifo_eng_timeout_r(void) -{ - return 0x00002a0cU; -} -static inline u32 fifo_eng_timeout_period_max_f(void) -{ - return 0x7fffffffU; -} -static inline u32 fifo_eng_timeout_detection_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 fifo_eng_timeout_detection_disabled_f(void) -{ - return 0x0U; -} -static inline u32 fifo_pb_timeslice_r(u32 i) -{ - return 0x00002350U + i*4U; -} -static inline u32 fifo_pb_timeslice_timeout_16_f(void) -{ - return 0x10U; -} -static inline u32 fifo_pb_timeslice_timescale_0_f(void) -{ - return 0x0U; -} -static inline u32 fifo_pb_timeslice_enable_true_f(void) -{ - return 0x10000000U; -} -static inline u32 fifo_pbdma_map_r(u32 i) -{ - return 0x00002390U + i*4U; -} -static inline u32 fifo_intr_0_r(void) -{ - return 0x00002100U; -} -static inline u32 fifo_intr_0_bind_error_pending_f(void) -{ - return 0x1U; -} -static inline u32 fifo_intr_0_bind_error_reset_f(void) -{ - return 0x1U; -} -static inline u32 fifo_intr_0_pio_error_pending_f(void) -{ - return 0x10U; -} -static inline u32 fifo_intr_0_pio_error_reset_f(void) -{ - return 0x10U; -} -static inline u32 fifo_intr_0_sched_error_pending_f(void) -{ - return 0x100U; -} -static inline u32 fifo_intr_0_sched_error_reset_f(void) -{ - return 0x100U; -} -static inline u32 fifo_intr_0_chsw_error_pending_f(void) -{ - return 0x10000U; -} -static inline u32 fifo_intr_0_chsw_error_reset_f(void) -{ - return 0x10000U; -} -static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void) -{ - return 0x800000U; -} -static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void) -{ - return 0x800000U; -} -static inline u32 fifo_intr_0_lb_error_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_intr_0_lb_error_reset_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void) -{ - return 0x8000000U; -} -static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void) -{ - return 0x8000000U; -} -static inline u32 fifo_intr_0_mmu_fault_pending_f(void) -{ - return 0x10000000U; -} -static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 fifo_intr_0_runlist_event_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 fifo_intr_0_channel_intr_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 fifo_intr_en_0_r(void) -{ - return 0x00002140U; -} -static inline u32 fifo_intr_en_0_sched_error_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 fifo_intr_en_0_sched_error_m(void) -{ - return 0x1U << 8U; -} -static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 fifo_intr_en_0_mmu_fault_m(void) -{ - return 0x1U << 28U; -} -static inline u32 fifo_intr_en_1_r(void) -{ - return 0x00002528U; -} -static inline u32 fifo_intr_bind_error_r(void) -{ - return 0x0000252cU; -} -static inline u32 fifo_intr_sched_error_r(void) -{ - return 0x0000254cU; -} -static inline u32 fifo_intr_sched_error_code_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void) -{ - return 0x0000000aU; -} -static inline u32 fifo_intr_chsw_error_r(void) -{ - return 0x0000256cU; -} -static inline u32 fifo_intr_mmu_fault_id_r(void) -{ - return 0x0000259cU; -} -static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void) -{ - return 0x0U; -} -static inline u32 fifo_intr_mmu_fault_inst_r(u32 i) -{ - return 0x00002800U + i*16U; -} -static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 fifo_intr_mmu_fault_lo_r(u32 i) -{ - return 0x00002804U + i*16U; -} -static inline u32 fifo_intr_mmu_fault_hi_r(u32 i) -{ - return 0x00002808U + i*16U; -} -static inline u32 fifo_intr_mmu_fault_info_r(u32 i) -{ - return 0x0000280cU + i*16U; -} -static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 fifo_intr_mmu_fault_info_write_v(u32 r) -{ - return (r >> 7U) & 0x1U; -} -static inline u32 fifo_intr_mmu_fault_info_engine_subid_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 fifo_intr_mmu_fault_info_engine_subid_gpc_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_intr_mmu_fault_info_engine_subid_hub_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r) -{ - return (r >> 8U) & 0x1fU; -} -static inline u32 fifo_intr_pbdma_id_r(void) -{ - return 0x000025a0U; -} -static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) -{ - return (r >> (0U + i*1U)) & 0x1U; -} -static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_intr_runlist_r(void) -{ - return 0x00002a00U; -} -static inline u32 fifo_fb_timeout_r(void) -{ - return 0x00002a04U; -} -static inline u32 fifo_fb_timeout_period_m(void) -{ - return 0x3fffffffU << 0U; -} -static inline u32 fifo_fb_timeout_period_max_f(void) -{ - return 0x3fffffffU; -} -static inline u32 fifo_pb_timeout_r(void) -{ - return 0x00002a08U; -} -static inline u32 fifo_pb_timeout_detection_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 fifo_error_sched_disable_r(void) -{ - return 0x0000262cU; -} -static inline u32 fifo_sched_disable_r(void) -{ - return 0x00002630U; -} -static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_sched_disable_runlist_m(u32 i) -{ - return 0x1U << (0U + i*1U); -} -static inline u32 fifo_sched_disable_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_preempt_r(void) -{ - return 0x00002634U; -} -static inline u32 fifo_preempt_pending_true_f(void) -{ - return 0x100000U; -} -static inline u32 fifo_preempt_type_channel_f(void) -{ - return 0x0U; -} -static inline u32 fifo_preempt_type_tsg_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_preempt_chid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 fifo_preempt_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 fifo_trigger_mmu_fault_r(u32 i) -{ - return 0x00002a30U + i*4U; -} -static inline u32 fifo_trigger_mmu_fault_id_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 fifo_engine_status_r(u32 i) -{ - return 0x00002640U + i*8U; -} -static inline u32 fifo_engine_status__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fifo_engine_status_id_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 fifo_engine_status_id_type_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 fifo_engine_status_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctx_status_v(u32 r) -{ - return (r >> 13U) & 0x7U; -} -static inline u32 fifo_engine_status_ctx_status_invalid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_ctx_status_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void) -{ - return 0x00000005U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void) -{ - return 0x00000006U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void) -{ - return 0x00000007U; -} -static inline u32 fifo_engine_status_next_id_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 fifo_engine_status_next_id_type_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 fifo_engine_status_next_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_faulted_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fifo_engine_status_faulted_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_engine_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fifo_engine_status_engine_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_engine_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctxsw_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fifo_engine_status_ctxsw_in_progress_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) -{ - return 0x8000U; -} -static inline u32 fifo_pbdma_status_r(u32 i) -{ - return 0x00003080U + i*4U; -} -static inline u32 fifo_pbdma_status__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_id_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 fifo_pbdma_status_id_type_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 fifo_pbdma_status_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chan_status_v(u32 r) -{ - return (r >> 13U) & 0x7U; -} -static inline u32 fifo_pbdma_status_chan_status_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void) -{ - return 0x00000005U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void) -{ - return 0x00000006U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void) -{ - return 0x00000007U; -} -static inline u32 fifo_pbdma_status_next_id_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 fifo_pbdma_status_next_id_type_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 fifo_pbdma_status_next_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_pbdma_status_chsw_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) -{ - return 0x00000001U; -} -#endif diff --git a/include/nvgpu/hw/gk20a/hw_flush_gk20a.h b/include/nvgpu/hw/gk20a/hw_flush_gk20a.h deleted file mode 100644 index d270b5f..0000000 --- a/include/nvgpu/hw/gk20a/hw_flush_gk20a.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_flush_gk20a_h_ -#define _hw_flush_gk20a_h_ - -static inline u32 flush_l2_system_invalidate_r(void) -{ - return 0x00070004U; -} -static inline u32 flush_l2_system_invalidate_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_system_invalidate_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_system_invalidate_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_system_invalidate_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_flush_dirty_r(void) -{ - return 0x00070010U; -} -static inline u32 flush_l2_flush_dirty_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_flush_dirty_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_flush_dirty_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_flush_dirty_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_flush_dirty_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_flush_dirty_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_flush_dirty_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_clean_comptags_r(void) -{ - return 0x0007000cU; -} -static inline u32 flush_l2_clean_comptags_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_clean_comptags_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_clean_comptags_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_clean_comptags_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_clean_comptags_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_clean_comptags_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_clean_comptags_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_clean_comptags_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_fb_flush_r(void) -{ - return 0x00070000U; -} -static inline u32 flush_fb_flush_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_fb_flush_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_fb_flush_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_fb_flush_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_fb_flush_outstanding_true_v(void) -{ - return 0x00000001U; -} -#endif diff --git a/include/nvgpu/hw/gk20a/hw_gmmu_gk20a.h b/include/nvgpu/hw/gk20a/hw_gmmu_gk20a.h deleted file mode 100644 index a788d1d..0000000 --- a/include/nvgpu/hw/gk20a/hw_gmmu_gk20a.h +++ /dev/null @@ -1,283 +0,0 @@ -/* - * Copyright (c) 2012-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_gmmu_gk20a_h_ -#define _hw_gmmu_gk20a_h_ - -static inline u32 gmmu_pde_aperture_big_w(void) -{ - return 0U; -} -static inline u32 gmmu_pde_aperture_big_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pde_aperture_big_video_memory_f(void) -{ - return 0x1U; -} -static inline u32 gmmu_pde_aperture_big_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_pde_aperture_big_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 gmmu_pde_size_w(void) -{ - return 0U; -} -static inline u32 gmmu_pde_size_full_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pde_address_big_sys_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 gmmu_pde_address_big_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_pde_aperture_small_w(void) -{ - return 1U; -} -static inline u32 gmmu_pde_aperture_small_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pde_aperture_small_video_memory_f(void) -{ - return 0x1U; -} -static inline u32 gmmu_pde_aperture_small_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_pde_aperture_small_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 gmmu_pde_vol_small_w(void) -{ - return 1U; -} -static inline u32 gmmu_pde_vol_small_true_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_pde_vol_small_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pde_vol_big_w(void) -{ - return 1U; -} -static inline u32 gmmu_pde_vol_big_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_pde_vol_big_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pde_address_small_sys_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 gmmu_pde_address_small_sys_w(void) -{ - return 1U; -} -static inline u32 gmmu_pde_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_pde__size_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_pte__size_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_pte_valid_w(void) -{ - return 0U; -} -static inline u32 gmmu_pte_valid_true_f(void) -{ - return 0x1U; -} -static inline u32 gmmu_pte_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pte_privilege_w(void) -{ - return 0U; -} -static inline u32 gmmu_pte_privilege_true_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_pte_privilege_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pte_address_sys_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 gmmu_pte_address_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_pte_address_vid_f(u32 v) -{ - return (v & 0x1ffffffU) << 4U; -} -static inline u32 gmmu_pte_address_vid_w(void) -{ - return 0U; -} -static inline u32 gmmu_pte_vol_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_vol_true_f(void) -{ - return 0x1U; -} -static inline u32 gmmu_pte_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pte_aperture_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_aperture_video_memory_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pte_aperture_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_pte_aperture_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_pte_read_only_w(void) -{ - return 0U; -} -static inline u32 gmmu_pte_read_only_true_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_pte_write_disable_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_write_disable_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gmmu_pte_read_disable_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_read_disable_true_f(void) -{ - return 0x40000000U; -} -static inline u32 gmmu_pte_comptagline_s(void) -{ - return 17U; -} -static inline u32 gmmu_pte_comptagline_f(u32 v) -{ - return (v & 0x1ffffU) << 12U; -} -static inline u32 gmmu_pte_comptagline_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_pte_kind_f(u32 v) -{ - return (v & 0xffU) << 4U; -} -static inline u32 gmmu_pte_kind_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_kind_invalid_v(void) -{ - return 0x000000ffU; -} -static inline u32 gmmu_pte_kind_pitch_v(void) -{ - return 0x00000000U; -} -#endif diff --git a/include/nvgpu/hw/gk20a/hw_gr_gk20a.h b/include/nvgpu/hw/gk20a/hw_gr_gk20a.h deleted file mode 100644 index 376cc8f..0000000 --- a/include/nvgpu/hw/gk20a/hw_gr_gk20a.h +++ /dev/null @@ -1,3868 +0,0 @@ -/* - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_gr_gk20a_h_ -#define _hw_gr_gk20a_h_ - -static inline u32 gr_intr_r(void) -{ - return 0x00400100U; -} -static inline u32 gr_intr_notify_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_intr_notify_reset_f(void) -{ - return 0x1U; -} -static inline u32 gr_intr_semaphore_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_semaphore_reset_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_semaphore_timeout_not_pending_f(void) -{ - return 0x0U; -} -static inline u32 gr_intr_semaphore_timeout_pending_f(void) -{ - return 0x4U; -} -static inline u32 gr_intr_semaphore_timeout_reset_f(void) -{ - return 0x4U; -} -static inline u32 gr_intr_illegal_method_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_intr_illegal_method_reset_f(void) -{ - return 0x10U; -} -static inline u32 gr_intr_illegal_notify_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_intr_illegal_notify_reset_f(void) -{ - return 0x40U; -} -static inline u32 gr_intr_firmware_method_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 gr_intr_firmware_method_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_intr_firmware_method_reset_f(void) -{ - return 0x100U; -} -static inline u32 gr_intr_illegal_class_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_intr_illegal_class_reset_f(void) -{ - return 0x20U; -} -static inline u32 gr_intr_fecs_error_pending_f(void) -{ - return 0x80000U; -} -static inline u32 gr_intr_fecs_error_reset_f(void) -{ - return 0x80000U; -} -static inline u32 gr_intr_class_error_pending_f(void) -{ - return 0x100000U; -} -static inline u32 gr_intr_class_error_reset_f(void) -{ - return 0x100000U; -} -static inline u32 gr_intr_exception_pending_f(void) -{ - return 0x200000U; -} -static inline u32 gr_intr_exception_reset_f(void) -{ - return 0x200000U; -} -static inline u32 gr_fecs_intr_r(void) -{ - return 0x00400144U; -} -static inline u32 gr_class_error_r(void) -{ - return 0x00400110U; -} -static inline u32 gr_class_error_code_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_intr_nonstall_r(void) -{ - return 0x00400120U; -} -static inline u32 gr_intr_nonstall_trap_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_en_r(void) -{ - return 0x0040013cU; -} -static inline u32 gr_exception_r(void) -{ - return 0x00400108U; -} -static inline u32 gr_exception_fe_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_exception_gpc_m(void) -{ - return 0x1U << 24U; -} -static inline u32 gr_exception_memfmt_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_exception_ds_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_exception_sked_m(void) -{ - return 0x1U << 8U; -} -static inline u32 gr_exception_pd_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_exception_scc_m(void) -{ - return 0x1U << 3U; -} -static inline u32 gr_exception_ssync_m(void) -{ - return 0x1U << 5U; -} -static inline u32 gr_exception_mme_m(void) -{ - return 0x1U << 7U; -} -static inline u32 gr_exception1_r(void) -{ - return 0x00400118U; -} -static inline u32 gr_exception1_gpc_0_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_exception2_r(void) -{ - return 0x0040011cU; -} -static inline u32 gr_exception_en_r(void) -{ - return 0x00400138U; -} -static inline u32 gr_exception_en_fe_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_exception1_en_r(void) -{ - return 0x00400130U; -} -static inline u32 gr_exception2_en_r(void) -{ - return 0x00400134U; -} -static inline u32 gr_gpfifo_ctl_r(void) -{ - return 0x00400500U; -} -static inline u32 gr_gpfifo_ctl_access_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpfifo_ctl_access_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpfifo_ctl_access_enabled_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void) -{ - return 0x10000U; -} -static inline u32 gr_gpfifo_status_r(void) -{ - return 0x00400504U; -} -static inline u32 gr_trapped_addr_r(void) -{ - return 0x00400704U; -} -static inline u32 gr_trapped_addr_mthd_v(u32 r) -{ - return (r >> 2U) & 0xfffU; -} -static inline u32 gr_trapped_addr_subch_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 gr_trapped_addr_mme_generated_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 gr_trapped_addr_datahigh_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 gr_trapped_addr_priv_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 gr_trapped_addr_status_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_trapped_data_lo_r(void) -{ - return 0x00400708U; -} -static inline u32 gr_trapped_data_hi_r(void) -{ - return 0x0040070cU; -} -static inline u32 gr_trapped_data_mme_r(void) -{ - return 0x00400710U; -} -static inline u32 gr_trapped_data_mme_pc_v(u32 r) -{ - return (r >> 0U) & 0x7ffU; -} -static inline u32 gr_status_r(void) -{ - return 0x00400700U; -} -static inline u32 gr_status_fe_method_upper_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_status_fe_method_lower_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_status_fe_method_lower_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_status_fe_gi_v(u32 r) -{ - return (r >> 21U) & 0x1U; -} -static inline u32 gr_status_mask_r(void) -{ - return 0x00400610U; -} -static inline u32 gr_status_1_r(void) -{ - return 0x00400604U; -} -static inline u32 gr_status_2_r(void) -{ - return 0x00400608U; -} -static inline u32 gr_engine_status_r(void) -{ - return 0x0040060cU; -} -static inline u32 gr_engine_status_value_busy_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_be0_becs_be_exception_r(void) -{ - return 0x00410204U; -} -static inline u32 gr_pri_be0_becs_be_exception_en_r(void) -{ - return 0x00410208U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void) -{ - return 0x00502c90U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void) -{ - return 0x00502c94U; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void) -{ - return 0x00504508U; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void) -{ - return 0x0050450cU; -} -static inline u32 gr_activity_0_r(void) -{ - return 0x00400380U; -} -static inline u32 gr_activity_1_r(void) -{ - return 0x00400384U; -} -static inline u32 gr_activity_2_r(void) -{ - return 0x00400388U; -} -static inline u32 gr_activity_4_r(void) -{ - return 0x00400390U; -} -static inline u32 gr_pri_gpc0_gcc_dbg_r(void) -{ - return 0x00501000U; -} -static inline u32 gr_pri_gpcs_gcc_dbg_r(void) -{ - return 0x00419000U; -} -static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) -{ - return 0x005046a4U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) -{ - return 0x00419ea4U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_pri_sked_activity_r(void) -{ - return 0x00407054U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void) -{ - return 0x00502c80U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void) -{ - return 0x00502c84U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void) -{ - return 0x00502c88U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void) -{ - return 0x00502c8cU; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void) -{ - return 0x00504500U; -} -static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void) -{ - return 0x00501d00U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void) -{ - return 0x0041ac80U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void) -{ - return 0x0041ac84U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void) -{ - return 0x0041ac88U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void) -{ - return 0x0041ac8cU; -} -static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void) -{ - return 0x0041c500U; -} -static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void) -{ - return 0x00419d00U; -} -static inline u32 gr_pri_be0_becs_be_activity0_r(void) -{ - return 0x00410200U; -} -static inline u32 gr_pri_bes_becs_be_activity0_r(void) -{ - return 0x00408a00U; -} -static inline u32 gr_pri_ds_mpipe_status_r(void) -{ - return 0x00405858U; -} -static inline u32 gr_pri_fe_go_idle_on_status_r(void) -{ - return 0x00404150U; -} -static inline u32 gr_pri_fe_go_idle_check_r(void) -{ - return 0x00404158U; -} -static inline u32 gr_pri_fe_go_idle_info_r(void) -{ - return 0x00404194U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) -{ - return 0x00504238U; -} -static inline u32 gr_pri_be0_crop_status1_r(void) -{ - return 0x00410134U; -} -static inline u32 gr_pri_bes_crop_status1_r(void) -{ - return 0x00408934U; -} -static inline u32 gr_pri_be0_zrop_status_r(void) -{ - return 0x00410048U; -} -static inline u32 gr_pri_be0_zrop_status2_r(void) -{ - return 0x0041004cU; -} -static inline u32 gr_pri_bes_zrop_status_r(void) -{ - return 0x00408848U; -} -static inline u32 gr_pri_bes_zrop_status2_r(void) -{ - return 0x0040884cU; -} -static inline u32 gr_pipe_bundle_address_r(void) -{ - return 0x00400200U; -} -static inline u32 gr_pipe_bundle_address_value_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pipe_bundle_data_r(void) -{ - return 0x00400204U; -} -static inline u32 gr_pipe_bundle_config_r(void) -{ - return 0x00400208U; -} -static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fe_hww_esr_r(void) -{ - return 0x00404000U; -} -static inline u32 gr_fe_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_fe_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fe_hww_esr_info_r(void) -{ - return 0x004041b0U; -} -static inline u32 gr_fe_go_idle_timeout_r(void) -{ - return 0x00404154U; -} -static inline u32 gr_fe_go_idle_timeout_count_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) -{ - return 0x800U; -} -static inline u32 gr_fe_object_table_r(u32 i) -{ - return 0x00404200U + i*4U; -} -static inline u32 gr_fe_object_table_nvclass_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_mme_shadow_raw_index_r(void) -{ - return 0x00404488U; -} -static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pri_mme_shadow_raw_data_r(void) -{ - return 0x0040448cU; -} -static inline u32 gr_mme_hww_esr_r(void) -{ - return 0x00404490U; -} -static inline u32 gr_mme_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_mme_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_mme_hww_esr_info_r(void) -{ - return 0x00404494U; -} -static inline u32 gr_memfmt_hww_esr_r(void) -{ - return 0x00404600U; -} -static inline u32 gr_memfmt_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_memfmt_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fecs_cpuctl_r(void) -{ - return 0x00409100U; -} -static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_dmactl_r(void) -{ - return 0x0040910cU; -} -static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_fecs_os_r(void) -{ - return 0x00409080U; -} -static inline u32 gr_fecs_idlestate_r(void) -{ - return 0x0040904cU; -} -static inline u32 gr_fecs_mailbox0_r(void) -{ - return 0x00409040U; -} -static inline u32 gr_fecs_mailbox1_r(void) -{ - return 0x00409044U; -} -static inline u32 gr_fecs_irqstat_r(void) -{ - return 0x00409008U; -} -static inline u32 gr_fecs_irqmode_r(void) -{ - return 0x0040900cU; -} -static inline u32 gr_fecs_irqmask_r(void) -{ - return 0x00409018U; -} -static inline u32 gr_fecs_irqdest_r(void) -{ - return 0x0040901cU; -} -static inline u32 gr_fecs_curctx_r(void) -{ - return 0x00409050U; -} -static inline u32 gr_fecs_nxtctx_r(void) -{ - return 0x00409054U; -} -static inline u32 gr_fecs_engctl_r(void) -{ - return 0x004090a4U; -} -static inline u32 gr_fecs_debug1_r(void) -{ - return 0x00409090U; -} -static inline u32 gr_fecs_debuginfo_r(void) -{ - return 0x00409094U; -} -static inline u32 gr_fecs_icd_cmd_r(void) -{ - return 0x00409200U; -} -static inline u32 gr_fecs_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 gr_fecs_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_fecs_icd_cmd_opc_m(void) -{ - return 0xfU << 0U; -} -static inline u32 gr_fecs_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 gr_fecs_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 gr_fecs_icd_rdata_r(void) -{ - return 0x0040920cU; -} -static inline u32 gr_fecs_imemc_r(u32 i) -{ - return 0x00409180U + i*16U; -} -static inline u32 gr_fecs_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_fecs_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_fecs_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_fecs_imemd_r(u32 i) -{ - return 0x00409184U + i*16U; -} -static inline u32 gr_fecs_imemt_r(u32 i) -{ - return 0x00409188U + i*16U; -} -static inline u32 gr_fecs_imemt_tag_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_fecs_dmemc_r(u32 i) -{ - return 0x004091c0U + i*8U; -} -static inline u32 gr_fecs_dmemc_offs_s(void) -{ - return 6U; -} -static inline u32 gr_fecs_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_fecs_dmemc_offs_m(void) -{ - return 0x3fU << 2U; -} -static inline u32 gr_fecs_dmemc_offs_v(u32 r) -{ - return (r >> 2U) & 0x3fU; -} -static inline u32 gr_fecs_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_fecs_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_fecs_dmemd_r(u32 i) -{ - return 0x004091c4U + i*8U; -} -static inline u32 gr_fecs_dmatrfbase_r(void) -{ - return 0x00409110U; -} -static inline u32 gr_fecs_dmatrfmoffs_r(void) -{ - return 0x00409114U; -} -static inline u32 gr_fecs_dmatrffboffs_r(void) -{ - return 0x0040911cU; -} -static inline u32 gr_fecs_dmatrfcmd_r(void) -{ - return 0x00409118U; -} -static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_fecs_bootvec_r(void) -{ - return 0x00409104U; -} -static inline u32 gr_fecs_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_falcon_hwcfg_r(void) -{ - return 0x00409108U; -} -static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void) -{ - return 0x0041a108U; -} -static inline u32 gr_fecs_falcon_rm_r(void) -{ - return 0x00409084U; -} -static inline u32 gr_fecs_current_ctx_r(void) -{ - return 0x00409b00U; -} -static inline u32 gr_fecs_current_ctx_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_current_ctx_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_current_ctx_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_current_ctx_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_current_ctx_target_m(void) -{ - return 0x3U << 28U; -} -static inline u32 gr_fecs_current_ctx_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 gr_fecs_current_ctx_valid_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_current_ctx_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_fecs_current_ctx_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_fecs_current_ctx_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_fecs_current_ctx_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_method_data_r(void) -{ - return 0x00409500U; -} -static inline u32 gr_fecs_method_push_r(void) -{ - return 0x00409504U; -} -static inline u32 gr_fecs_method_push_adr_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void) -{ - return 0x00000003U; -} -static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void) -{ - return 0x3U; -} -static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void) -{ - return 0x00000009U; -} -static inline u32 gr_fecs_method_push_adr_restore_golden_v(void) -{ - return 0x00000015U; -} -static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void) -{ - return 0x00000016U; -} -static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void) -{ - return 0x00000025U; -} -static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void) -{ - return 0x00000030U; -} -static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void) -{ - return 0x00000031U; -} -static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void) -{ - return 0x00000032U; -} -static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void) -{ - return 0x00000038U; -} -static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void) -{ - return 0x00000039U; -} -static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) -{ - return 0x21U; -} -static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_fecs_host_int_status_r(void) -{ - return 0x00409c18U; -} -static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 gr_fecs_host_int_status_watchdog_active_f(void) -{ - return 0x80000U; -} -static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_fecs_host_int_clear_r(void) -{ - return 0x00409c20U; -} -static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void) -{ - return 0x2U; -} -static inline u32 gr_fecs_host_int_enable_r(void) -{ - return 0x00409c24U; -} -static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void) -{ - return 0x2U; -} -static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void) -{ - return 0x10000U; -} -static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void) -{ - return 0x20000U; -} -static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void) -{ - return 0x40000U; -} -static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void) -{ - return 0x80000U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) -{ - return 0x00409614U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void) -{ - return 0x10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void) -{ - return 0x20U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void) -{ - return 0x40U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void) -{ - return 0x100U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void) -{ - return 0x200U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void) -{ - return 0x1U << 10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r) -{ - return (r >> 10U) & 0x1U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void) -{ - return 0x400U; -} -static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void) -{ - return 0x0040960cU; -} -static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i) -{ - return 0x00409800U + i*4U; -} -static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void) -{ - return 0x00000002U; -} -static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i) -{ - return 0x00409820U + i*4U; -} -static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i) -{ - return 0x00409840U + i*4U; -} -static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_fs_r(void) -{ - return 0x00409604U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_m(void) -{ - return 0x1fU << 0U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_fecs_fs_num_available_fbps_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 gr_fecs_fs_num_available_fbps_m(void) -{ - return 0x1fU << 16U; -} -static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -static inline u32 gr_fecs_cfg_r(void) -{ - return 0x00409620U; -} -static inline u32 gr_fecs_cfg_imem_sz_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_fecs_rc_lanes_r(void) -{ - return 0x00409880U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_s(void) -{ - return 6U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_fecs_ctxsw_status_1_r(void) -{ - return 0x00409400U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void) -{ - return 0x1U << 12U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 gr_fecs_arb_ctx_adr_r(void) -{ - return 0x00409a24U; -} -static inline u32 gr_fecs_new_ctx_r(void) -{ - return 0x00409b04U; -} -static inline u32 gr_fecs_new_ctx_ptr_s(void) -{ - return 28U; -} -static inline u32 gr_fecs_new_ctx_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_new_ctx_ptr_m(void) -{ - return 0xfffffffU << 0U; -} -static inline u32 gr_fecs_new_ctx_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_new_ctx_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_new_ctx_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_new_ctx_target_m(void) -{ - return 0x3U << 28U; -} -static inline u32 gr_fecs_new_ctx_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_new_ctx_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_new_ctx_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 gr_fecs_new_ctx_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_fecs_new_ctx_valid_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_new_ctx_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_fecs_new_ctx_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_fecs_new_ctx_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_fecs_arb_ctx_ptr_r(void) -{ - return 0x00409a0cU; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void) -{ - return 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void) -{ - return 0xfffffffU << 0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_m(void) -{ - return 0x3U << 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_fecs_arb_ctx_cmd_r(void) -{ - return 0x00409a10U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void) -{ - return 0x1fU << 0U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_fecs_ctxsw_status_fe_0_r(void) -{ - return 0x00409c00U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void) -{ - return 0x00502c04U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) -{ - return 0x00502400U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_mailbox__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_fecs_ctxsw_idlestate_r(void) -{ - return 0x00409420U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) -{ - return 0x00502420U; -} -static inline u32 gr_rstr2d_gpc_map0_r(void) -{ - return 0x0040780cU; -} -static inline u32 gr_rstr2d_gpc_map1_r(void) -{ - return 0x00407810U; -} -static inline u32 gr_rstr2d_gpc_map2_r(void) -{ - return 0x00407814U; -} -static inline u32 gr_rstr2d_gpc_map3_r(void) -{ - return 0x00407818U; -} -static inline u32 gr_rstr2d_gpc_map4_r(void) -{ - return 0x0040781cU; -} -static inline u32 gr_rstr2d_gpc_map5_r(void) -{ - return 0x00407820U; -} -static inline u32 gr_rstr2d_map_table_cfg_r(void) -{ - return 0x004078bcU; -} -static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_pd_hww_esr_r(void) -{ - return 0x00406018U; -} -static inline u32 gr_pd_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pd_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i) -{ - return 0x00406028U + i*4U; -} -static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v) -{ - return (v & 0xfU) << 12U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v) -{ - return (v & 0xfU) << 24U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v) -{ - return (v & 0xfU) << 28U; -} -static inline u32 gr_pd_ab_dist_cfg0_r(void) -{ - return 0x004064c0U; -} -static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void) -{ - return 0x0U; -} -static inline u32 gr_pd_ab_dist_cfg1_r(void) -{ - return 0x004064c4U; -} -static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void) -{ - return 0xffffU; -} -static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v) -{ - return (v & 0x7ffU) << 16U; -} -static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void) -{ - return 0x00000080U; -} -static inline u32 gr_pd_ab_dist_cfg2_r(void) -{ - return 0x004064c8U; -} -static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) -{ - return (v & 0xfffU) << 16U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) -{ - return 0x00000062U; -} -static inline u32 gr_pd_pagepool_r(void) -{ - return 0x004064ccU; -} -static inline u32 gr_pd_pagepool_total_pages_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_pd_pagepool_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pd_dist_skip_table_r(u32 i) -{ - return 0x004064d0U + i*4U; -} -static inline u32 gr_pd_dist_skip_table__size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gr_pd_alpha_ratio_table_r(u32 i) -{ - return 0x00406800U + i*4U; -} -static inline u32 gr_pd_alpha_ratio_table__size_1_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_pd_alpha_ratio_table_gpc_4n0_mask_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_pd_alpha_ratio_table_gpc_4n1_mask_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_pd_alpha_ratio_table_gpc_4n2_mask_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_pd_alpha_ratio_table_gpc_4n3_mask_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gr_pd_beta_ratio_table_r(u32 i) -{ - return 0x00406c00U + i*4U; -} -static inline u32 gr_pd_beta_ratio_table__size_1_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_pd_beta_ratio_table_gpc_4n0_mask_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_pd_beta_ratio_table_gpc_4n1_mask_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_pd_beta_ratio_table_gpc_4n2_mask_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_pd_beta_ratio_table_gpc_4n3_mask_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gr_ds_debug_r(void) -{ - return 0x00405800U; -} -static inline u32 gr_ds_debug_timeslice_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_debug_timeslice_mode_enable_f(void) -{ - return 0x8000000U; -} -static inline u32 gr_ds_zbc_color_r_r(void) -{ - return 0x00405804U; -} -static inline u32 gr_ds_zbc_color_r_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_g_r(void) -{ - return 0x00405808U; -} -static inline u32 gr_ds_zbc_color_g_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_b_r(void) -{ - return 0x0040580cU; -} -static inline u32 gr_ds_zbc_color_b_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_a_r(void) -{ - return 0x00405810U; -} -static inline u32 gr_ds_zbc_color_a_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_fmt_r(void) -{ - return 0x00405814U; -} -static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v) -{ - return (v & 0x7fU) << 0U; -} -static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void) -{ - return 0x00000002U; -} -static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) -{ - return 0x00000028U; -} -static inline u32 gr_ds_zbc_z_r(void) -{ - return 0x00405818U; -} -static inline u32 gr_ds_zbc_z_val_s(void) -{ - return 32U; -} -static inline u32 gr_ds_zbc_z_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_z_val_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 gr_ds_zbc_z_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gr_ds_zbc_z_val__init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_ds_zbc_z_val__init_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_z_fmt_r(void) -{ - return 0x0040581cU; -} -static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_zbc_tbl_index_r(void) -{ - return 0x00405820U; -} -static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_ds_zbc_tbl_ld_r(void) -{ - return 0x00405824U; -} -static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) -{ - return 0x4U; -} -static inline u32 gr_ds_tga_constraintlogic_r(void) -{ - return 0x00405830U; -} -static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) -{ - return (v & 0xfffU) << 16U; -} -static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_ds_hww_esr_r(void) -{ - return 0x00405840U; -} -static inline u32 gr_ds_hww_esr_reset_s(void) -{ - return 1U; -} -static inline u32 gr_ds_hww_esr_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_reset_m(void) -{ - return 0x1U << 30U; -} -static inline u32 gr_ds_hww_esr_reset_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_ds_hww_esr_reset_task_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_hww_esr_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_ds_hww_esr_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_ds_hww_report_mask_r(void) -{ - return 0x00405844U; -} -static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void) -{ - return 0x8U; -} -static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void) -{ - return 0x80U; -} -static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void) -{ - return 0x200U; -} -static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void) -{ - return 0x400U; -} -static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void) -{ - return 0x800U; -} -static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void) -{ - return 0x1000U; -} -static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void) -{ - return 0x2000U; -} -static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void) -{ - return 0x4000U; -} -static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void) -{ - return 0x8000U; -} -static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void) -{ - return 0x10000U; -} -static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void) -{ - return 0x20000U; -} -static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void) -{ - return 0x40000U; -} -static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void) -{ - return 0x80000U; -} -static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void) -{ - return 0x100000U; -} -static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void) -{ - return 0x200000U; -} -static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void) -{ - return 0x400000U; -} -static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void) -{ - return 0x800000U; -} -static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i) -{ - return 0x00405870U + i*4U; -} -static inline u32 gr_scc_bundle_cb_base_r(void) -{ - return 0x00408004U; -} -static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_scc_bundle_cb_size_r(void) -{ - return 0x00408008U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7ffU) << 0U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) -{ - return 0x00000018U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_scc_bundle_cb_size_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_scc_bundle_cb_size_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_scc_bundle_cb_size_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_scc_pagepool_base_r(void) -{ - return 0x0040800cU; -} -static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_scc_pagepool_r(void) -{ - return 0x00408010U; -} -static inline u32 gr_scc_pagepool_total_pages_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void) -{ - return 0x00000080U; -} -static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_s(void) -{ - return 8U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_m(void) -{ - return 0xffU << 8U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} -static inline u32 gr_scc_pagepool_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_scc_init_r(void) -{ - return 0x0040802cU; -} -static inline u32 gr_scc_init_ram_trigger_f(void) -{ - return 0x1U; -} -static inline u32 gr_scc_hww_esr_r(void) -{ - return 0x00408030U; -} -static inline u32 gr_scc_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_scc_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_sked_hww_esr_r(void) -{ - return 0x00407020U; -} -static inline u32 gr_sked_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_cwd_fs_r(void) -{ - return 0x00405b00U; -} -static inline u32 gr_cwd_fs_num_gpcs_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_cwd_fs_num_tpcs_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpc0_fs_gpc_r(void) -{ - return 0x00502608U; -} -static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -static inline u32 gr_gpc0_cfg_r(void) -{ - return 0x00502620U; -} -static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpccs_rc_lanes_r(void) -{ - return 0x00502880U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_gpccs_rc_lane_size_r(u32 i) -{ - return 0x00502910U + i*0U; -} -static inline u32 gr_gpccs_rc_lane_size__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_gpccs_rc_lane_size_v_s(void) -{ - return 24U; -} -static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_gpccs_rc_lane_size_v_m(void) -{ - return 0xffffffU << 0U; -} -static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_zcull_fs_r(void) -{ - return 0x00500910U; -} -static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 gr_gpc0_zcull_ram_addr_r(void) -{ - return 0x00500914U; -} -static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void) -{ - return 0x00500918U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void) -{ - return 0x00800000U; -} -static inline u32 gr_gpc0_zcull_total_ram_size_r(void) -{ - return 0x00500920U; -} -static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_zcull_zcsize_r(u32 i) -{ - return 0x00500a04U + i*32U; -} -static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void) -{ - return 0x00000040U; -} -static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_gpc0_gpm_pd_active_tpcs_r(void) -{ - return 0x00500c08U; -} -static inline u32 gr_gpc0_gpm_pd_active_tpcs_num_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i) -{ - return 0x00500c10U + i*4U; -} -static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i) -{ - return 0x00500c30U + i*4U; -} -static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpc0_gpm_sd_active_tpcs_r(void) -{ - return 0x00500c8cU; -} -static inline u32 gr_gpc0_gpm_sd_active_tpcs_num_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void) -{ - return 0x00504088U; -} -static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_tpc0_l1c_cfg_smid_r(void) -{ - return 0x005044e8U; -} -static inline u32 gr_gpc0_tpc0_l1c_cfg_smid_value_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) -{ - return 0x00504698U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_r(void) -{ - return 0x0050469cU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_smkepler_lp_v(void) -{ - return 0x0000000cU; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) -{ - return 0x00503018U; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg_r(void) -{ - return 0x005030c0U; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg_start_offset_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg_start_offset_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg_start_offset_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg_size_f(u32 v) -{ - return (v & 0xfffU) << 16U; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg_size_m(void) -{ - return 0xfffU << 16U; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg_size_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg_size_default_v(void) -{ - return 0x00000240U; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg_size_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg_timeslice_mode_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg2_r(void) -{ - return 0x005030e4U; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg2_start_offset_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg2_size_f(u32 v) -{ - return (v & 0xfffU) << 16U; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg2_size_m(void) -{ - return 0xfffU << 16U; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg2_size_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg2_size_default_v(void) -{ - return 0x00000648U; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg2_size_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_gpccs_falcon_addr_r(void) -{ - return 0x0041a0acU; -} -static inline u32 gr_gpccs_falcon_addr_lsb_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpccs_falcon_addr_msb_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v) -{ - return (v & 0x3fU) << 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_m(void) -{ - return 0x3fU << 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r) -{ - return (r >> 6U) & 0x3fU; -} -static inline u32 gr_gpccs_falcon_addr_msb_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_falcon_addr_msb_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_s(void) -{ - return 12U; -} -static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_m(void) -{ - return 0xfffU << 0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 gr_gpccs_cpuctl_r(void) -{ - return 0x0041a100U; -} -static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_gpccs_dmactl_r(void) -{ - return 0x0041a10cU; -} -static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_gpccs_imemc_r(u32 i) -{ - return 0x0041a180U + i*16U; -} -static inline u32 gr_gpccs_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_gpccs_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpccs_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_gpccs_imemd_r(u32 i) -{ - return 0x0041a184U + i*16U; -} -static inline u32 gr_gpccs_imemt_r(u32 i) -{ - return 0x0041a188U + i*16U; -} -static inline u32 gr_gpccs_imemt__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_gpccs_imemt_tag_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpccs_dmemc_r(u32 i) -{ - return 0x0041a1c0U + i*8U; -} -static inline u32 gr_gpccs_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_gpccs_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpccs_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_gpccs_dmemd_r(u32 i) -{ - return 0x0041a1c4U + i*8U; -} -static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i) -{ - return 0x0041a800U + i*4U; -} -static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_setup_bundle_cb_base_r(void) -{ - return 0x00418808U; -} -static inline u32 gr_gpcs_setup_bundle_cb_base_addr_39_8_s(void) -{ - return 32U; -} -static inline u32 gr_gpcs_setup_bundle_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_setup_bundle_cb_base_addr_39_8_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 gr_gpcs_setup_bundle_cb_base_addr_39_8_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gr_gpcs_setup_bundle_cb_base_addr_39_8_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_setup_bundle_cb_base_addr_39_8_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_r(void) -{ - return 0x0041880cU; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b_s(void) -{ - return 11U; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7ffU) << 0U; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b_m(void) -{ - return 0x7ffU << 0U; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b_v(u32 r) -{ - return (r >> 0U) & 0x7ffU; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b__prod_v(void) -{ - return 0x00000018U; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b__prod_f(void) -{ - return 0x18U; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_valid_s(void) -{ - return 1U; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) -{ - return 0x00418810U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void) -{ - return 0x0000000cU; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_crstr_gpc_map0_r(void) -{ - return 0x00418b08U; -} -static inline u32 gr_crstr_gpc_map0_tile0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map0_tile1_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map0_tile2_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map0_tile3_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map0_tile4_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map0_tile5_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map1_r(void) -{ - return 0x00418b0cU; -} -static inline u32 gr_crstr_gpc_map1_tile6_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map1_tile7_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map1_tile8_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map1_tile9_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map1_tile10_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map1_tile11_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map2_r(void) -{ - return 0x00418b10U; -} -static inline u32 gr_crstr_gpc_map2_tile12_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map2_tile13_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map2_tile14_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map2_tile15_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map2_tile16_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map2_tile17_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map3_r(void) -{ - return 0x00418b14U; -} -static inline u32 gr_crstr_gpc_map3_tile18_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map3_tile19_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map3_tile20_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map3_tile21_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map3_tile22_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map3_tile23_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map4_r(void) -{ - return 0x00418b18U; -} -static inline u32 gr_crstr_gpc_map4_tile24_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map4_tile25_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map4_tile26_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map4_tile27_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map4_tile28_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map4_tile29_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map5_r(void) -{ - return 0x00418b1cU; -} -static inline u32 gr_crstr_gpc_map5_tile30_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map5_tile31_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map5_tile32_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map5_tile33_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map5_tile34_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map5_tile35_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_map_table_cfg_r(void) -{ - return 0x00418bb8U; -} -static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_r(void) -{ - return 0x00418980U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_r(void) -{ - return 0x00418984U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_r(void) -{ - return 0x00418988U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s(void) -{ - return 3U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void) -{ - return 0x7U << 28U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r) -{ - return (r >> 28U) & 0x7U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_r(void) -{ - return 0x0041898cU; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_gpm_pd_cfg_r(void) -{ - return 0x00418c6cU; -} -static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpcs_gcc_pagepool_base_r(void) -{ - return 0x00419004U; -} -static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_gcc_pagepool_r(void) -{ - return 0x00419008U; -} -static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_pe_vaf_r(void) -{ - return 0x0041980cU; -} -static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void) -{ - return 0x00419848U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) -{ - return 0x00419c00U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void) -{ - return 0x00419e44U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f(void) -{ - return 0x80U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) -{ - return 0x200U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f(void) -{ - return 0x400U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) -{ - return 0x800U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f(void) -{ - return 0x1000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f(void) -{ - return 0x2000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f(void) -{ - return 0x4000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f(void) -{ - return 0x8000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) -{ - return 0x10000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f(void) -{ - return 0x20000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) -{ - return 0x40000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f(void) -{ - return 0x80000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(void) -{ - return 0x100000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void) -{ - return 0x00419e4cU; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) -{ - return 0x00419d0cU; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) -{ - return 0x0050450cU; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) -{ - return 0x0041ac94U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) -{ - return 0x00502c90U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) -{ - return 0x00504508U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void) -{ - return 0x00504610U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_warp_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_sm_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void) -{ - return 0x00504614U; -} -static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_1_r(void) -{ - return 0x00504618U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void) -{ - return 0x00504624U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_1_r(void) -{ - return 0x00504628U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void) -{ - return 0x00504634U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_1_r(void) -{ - return 0x00504638U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void) -{ - return 0x00419e24U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) -{ - return 0x0050460cU; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void) -{ - return 0x00419e50U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void) -{ - return 0x00504650U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void) -{ - return 0x00504224U; -} -static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void) -{ - return 0x00504648U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) -{ - return 0x00504770U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) -{ - return 0x00419f70U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) -{ - return 0x0050477cU; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) -{ - return 0x00419f7cU; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) -{ - return 0x0041be08U; -} -static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) -{ - return 0x4U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map0_r(void) -{ - return 0x0041bf00U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map1_r(void) -{ - return 0x0041bf04U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map2_r(void) -{ - return 0x0041bf08U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map3_r(void) -{ - return 0x0041bf0cU; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map4_r(void) -{ - return 0x0041bf10U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map5_r(void) -{ - return 0x0041bf14U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) -{ - return 0x0041bfd0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) -{ - return (v & 0x7U) << 21U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 24U; -} -static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) -{ - return 0x0041bfd4U; -} -static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_r(void) -{ - return 0x0041bfe4U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 5U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 10U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 15U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 20U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 25U; -} -static inline u32 gr_gpcs_ppcs_cbm_cfg_r(void) -{ - return 0x0041bec0U; -} -static inline u32 gr_gpcs_ppcs_cbm_cfg_timeslice_mode_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_bes_zrop_settings_r(void) -{ - return 0x00408850U; -} -static inline u32 gr_bes_zrop_settings_num_active_fbps_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_bes_crop_settings_r(void) -{ - return 0x00408958U; -} -static inline u32 gr_bes_crop_settings_num_active_fbps_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void) -{ - return 0x000000c0U; -} -static inline u32 gr_zcull_subregion_qty_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void) -{ - return 0x00504604U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void) -{ - return 0x00504608U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void) -{ - return 0x0050465cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void) -{ - return 0x00504660U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void) -{ - return 0x00504664U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void) -{ - return 0x00504668U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void) -{ - return 0x0050466cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void) -{ - return 0x00504658U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_r(void) -{ - return 0x00504670U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r(void) -{ - return 0x00504694U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void) -{ - return 0x00504730U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void) -{ - return 0x00504734U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void) -{ - return 0x00504738U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void) -{ - return 0x0050473cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void) -{ - return 0x00504740U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void) -{ - return 0x00504744U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void) -{ - return 0x00504748U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void) -{ - return 0x0050474cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_r(void) -{ - return 0x00504674U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_r(void) -{ - return 0x00504678U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_r(void) -{ - return 0x0050467cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_r(void) -{ - return 0x00504680U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_r(void) -{ - return 0x00504684U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_r(void) -{ - return 0x00504688U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_r(void) -{ - return 0x0050468cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_r(void) -{ - return 0x00504690U; -} -static inline u32 gr_fe_pwr_mode_r(void) -{ - return 0x00404170U; -} -static inline u32 gr_fe_pwr_mode_mode_auto_f(void) -{ - return 0x0U; -} -static inline u32 gr_fe_pwr_mode_mode_force_on_f(void) -{ - return 0x2U; -} -static inline u32 gr_fe_pwr_mode_req_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 gr_fe_pwr_mode_req_send_f(void) -{ - return 0x10U; -} -static inline u32 gr_fe_pwr_mode_req_done_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_l1c_dbg_r(void) -{ - return 0x005044b0U; -} -static inline u32 gr_gpc0_tpc0_l1c_dbg_cya15_en_f(void) -{ - return 0x8000000U; -} -static inline u32 gr_gpcs_tpcs_sm_sch_texlock_r(void) -{ - return 0x00419ec8U; -} -static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tile_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tile_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_phase_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_phase_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tex_m(void) -{ - return 0x1U << 3U; -} -static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tex_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_timeout_m(void) -{ - return 0xffU << 4U; -} -static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_timeout_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_sch_texlock_dot_t_unlock_m(void) -{ - return 0x1U << 16U; -} -static inline u32 gr_gpcs_tpcs_sm_sch_texlock_dot_t_unlock_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_sch_macro_sched_r(void) -{ - return 0x00419eacU; -} -static inline u32 gr_gpcs_tpcs_sm_sch_macro_sched_lockboost_size_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 gr_gpcs_tpcs_sm_sch_macro_sched_lockboost_size_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void) -{ - return 0x00419e10U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(void) -{ - return 0x1U << 3U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) -{ - return 0x1U << 30U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void) -{ - return 0x40000000U; -} - -static inline u32 gr_gpc0_gpccs_falcon_irqstat_r(void) -{ - return 0x00502008U; -} -static inline u32 gr_gpc0_gpccs_falcon_irqmode_r(void) -{ - return 0x0050200cU; -} -static inline u32 gr_gpc0_gpccs_falcon_irqmask_r(void) -{ - return 0x00502018U; -} -static inline u32 gr_gpc0_gpccs_falcon_irqdest_r(void) -{ - return 0x0050201cU; -} -static inline u32 gr_gpc0_gpccs_falcon_debug1_r(void) -{ - return 0x00502090U; -} -static inline u32 gr_gpc0_gpccs_falcon_debuginfo_r(void) -{ - return 0x00502094U; -} -static inline u32 gr_gpc0_gpccs_falcon_engctl_r(void) -{ - return 0x005020a4U; -} -static inline u32 gr_gpc0_gpccs_falcon_curctx_r(void) -{ - return 0x00502050U; -} -static inline u32 gr_gpc0_gpccs_falcon_nxtctx_r(void) -{ - return 0x00502054U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_mailbox_r(u32 i) -{ - return 0x00502800U + i*4U; -} -static inline u32 gr_gpc0_gpccs_falcon_icd_cmd_r(void) -{ - return 0x00502200U; -} -static inline u32 gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpc0_gpccs_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 gr_gpc_gpccs_falcon_icd_rdata_r(void) -{ - return 0x0050220cU; -} -#endif diff --git a/include/nvgpu/hw/gk20a/hw_ltc_gk20a.h b/include/nvgpu/hw/gk20a/hw_ltc_gk20a.h deleted file mode 100644 index efe7f98..0000000 --- a/include/nvgpu/hw/gk20a/hw_ltc_gk20a.h +++ /dev/null @@ -1,455 +0,0 @@ -/* - * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ltc_gk20a_h_ -#define _hw_ltc_gk20a_h_ - -static inline u32 ltc_pltcg_base_v(void) -{ - return 0x00140000U; -} -static inline u32 ltc_pltcg_extent_v(void) -{ - return 0x0017ffffU; -} -static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) -{ - return 0x001410c8U; -} -static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) -{ - return 0x00141200U; -} -static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) -{ - return 0x0017ea00U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) -{ - return 0x00141104U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) -{ - return (r >> 16U) & 0x3U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) -{ - return 0x00000000U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) -{ - return 0x00000002U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) -{ - return 0x0017e8c8U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) -{ - return 0x2U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) -{ - return 0x4U; -} -static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) -{ - return 0x001410c8U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) -{ - return 0x0017e8ccU; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) -{ - return 0x0017e8d0U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) -{ - return 0x0001ffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_base_r(void) -{ - return 0x0017e8d4U; -} -static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) -{ - return 0x0000000bU; -} -static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) -{ - return (r >> 0U) & 0x3ffffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_param_r(void) -{ - return 0x0017e8dcU; -} -static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r) -{ - return (r >> 24U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_fbp_v(u32 r) -{ - return (r >> 28U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) -{ - return 0x0017e91cU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) -{ - return 0x0017ea44U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) -{ - return 0x0017ea48U + i*4U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) -{ - return 0x0017ea58U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) -{ - return 32U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) -{ - return 0x0017e924U; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_r(void) -{ - return 0x0017e828U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_r(void) -{ - return 0x00140828U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_ltss_intr_r(void) -{ - return 0x00140820U; -} -static inline u32 ltc_ltcs_ltss_intr_r(void) -{ - return 0x0017e820U; -} -static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) -{ - return 0x1U << 20U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_m(void) -{ - return 0x1U << 21U; -} -static inline u32 ltc_ltc0_lts0_intr_r(void) -{ - return 0x00141020U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) -{ - return 0x0017e910U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) -{ - return 0x300U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) -{ - return 0x20000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) -{ - return 0x40000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) -{ - return 0x0017e914U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) -{ - return 0x300U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) -{ - return 0x10000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) -{ - return 0x20000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) -{ - return 0x40000000U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) -{ - return 0x00140910U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) -{ - return 0x00140914U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} -#endif diff --git a/include/nvgpu/hw/gk20a/hw_mc_gk20a.h b/include/nvgpu/hw/gk20a/hw_mc_gk20a.h deleted file mode 100644 index 3ca2a29..0000000 --- a/include/nvgpu/hw/gk20a/hw_mc_gk20a.h +++ /dev/null @@ -1,291 +0,0 @@ -/* - * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_mc_gk20a_h_ -#define _hw_mc_gk20a_h_ - -static inline u32 mc_boot_0_r(void) -{ - return 0x00000000U; -} -static inline u32 mc_boot_0_architecture_v(u32 r) -{ - return (r >> 24U) & 0x1fU; -} -static inline u32 mc_boot_0_implementation_v(u32 r) -{ - return (r >> 20U) & 0xfU; -} -static inline u32 mc_boot_0_major_revision_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 mc_boot_0_minor_revision_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 mc_intr_0_r(void) -{ - return 0x00000100U; -} -static inline u32 mc_intr_0_pfifo_pending_f(void) -{ - return 0x100U; -} -static inline u32 mc_intr_0_pgraph_pending_f(void) -{ - return 0x1000U; -} -static inline u32 mc_intr_0_pmu_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 mc_intr_0_ltc_pending_f(void) -{ - return 0x2000000U; -} -static inline u32 mc_intr_0_priv_ring_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 mc_intr_0_pbus_pending_f(void) -{ - return 0x10000000U; -} -static inline u32 mc_intr_1_r(void) -{ - return 0x00000104U; -} -static inline u32 mc_intr_mask_0_r(void) -{ - return 0x00000640U; -} -static inline u32 mc_intr_mask_0_pmu_enabled_f(void) -{ - return 0x1000000U; -} -static inline u32 mc_intr_en_0_r(void) -{ - return 0x00000140U; -} -static inline u32 mc_intr_en_0_inta_disabled_f(void) -{ - return 0x0U; -} -static inline u32 mc_intr_en_0_inta_hardware_f(void) -{ - return 0x1U; -} -static inline u32 mc_intr_mask_1_r(void) -{ - return 0x00000644U; -} -static inline u32 mc_intr_mask_1_pmu_s(void) -{ - return 1U; -} -static inline u32 mc_intr_mask_1_pmu_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 mc_intr_mask_1_pmu_m(void) -{ - return 0x1U << 24U; -} -static inline u32 mc_intr_mask_1_pmu_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 mc_intr_mask_1_pmu_enabled_f(void) -{ - return 0x1000000U; -} -static inline u32 mc_intr_en_1_r(void) -{ - return 0x00000144U; -} -static inline u32 mc_intr_en_1_inta_disabled_f(void) -{ - return 0x0U; -} -static inline u32 mc_intr_en_1_inta_hardware_f(void) -{ - return 0x1U; -} -static inline u32 mc_enable_r(void) -{ - return 0x00000200U; -} -static inline u32 mc_enable_xbar_enabled_f(void) -{ - return 0x4U; -} -static inline u32 mc_enable_l2_enabled_f(void) -{ - return 0x8U; -} -static inline u32 mc_enable_pmedia_s(void) -{ - return 1U; -} -static inline u32 mc_enable_pmedia_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 mc_enable_pmedia_m(void) -{ - return 0x1U << 4U; -} -static inline u32 mc_enable_pmedia_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 mc_enable_priv_ring_enabled_f(void) -{ - return 0x20U; -} -static inline u32 mc_enable_ce0_m(void) -{ - return 0x1U << 6U; -} -static inline u32 mc_enable_pfifo_enabled_f(void) -{ - return 0x100U; -} -static inline u32 mc_enable_pgraph_enabled_f(void) -{ - return 0x1000U; -} -static inline u32 mc_enable_pwr_v(u32 r) -{ - return (r >> 13U) & 0x1U; -} -static inline u32 mc_enable_pwr_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 mc_enable_pwr_enabled_f(void) -{ - return 0x2000U; -} -static inline u32 mc_enable_pfb_enabled_f(void) -{ - return 0x100000U; -} -static inline u32 mc_enable_ce2_m(void) -{ - return 0x1U << 21U; -} -static inline u32 mc_enable_ce2_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 mc_enable_blg_enabled_f(void) -{ - return 0x8000000U; -} -static inline u32 mc_enable_perfmon_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 mc_enable_hub_enabled_f(void) -{ - return 0x20000000U; -} -static inline u32 mc_enable_pb_r(void) -{ - return 0x00000204U; -} -static inline u32 mc_enable_pb_0_s(void) -{ - return 1U; -} -static inline u32 mc_enable_pb_0_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 mc_enable_pb_0_m(void) -{ - return 0x1U << 0U; -} -static inline u32 mc_enable_pb_0_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 mc_enable_pb_0_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 mc_enable_pb_sel_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 mc_elpg_enable_r(void) -{ - return 0x0000020cU; -} -static inline u32 mc_elpg_enable_xbar_enabled_f(void) -{ - return 0x4U; -} -static inline u32 mc_elpg_enable_pfb_enabled_f(void) -{ - return 0x100000U; -} -static inline u32 mc_elpg_enable_hub_enabled_f(void) -{ - return 0x20000000U; -} -#endif diff --git a/include/nvgpu/hw/gk20a/hw_pbdma_gk20a.h b/include/nvgpu/hw/gk20a/hw_pbdma_gk20a.h deleted file mode 100644 index 2c8f48d..0000000 --- a/include/nvgpu/hw/gk20a/hw_pbdma_gk20a.h +++ /dev/null @@ -1,575 +0,0 @@ -/* - * Copyright (c) 2012-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pbdma_gk20a_h_ -#define _hw_pbdma_gk20a_h_ - -static inline u32 pbdma_gp_entry1_r(void) -{ - return 0x10000004U; -} -static inline u32 pbdma_gp_entry1_get_hi_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pbdma_gp_entry1_length_f(u32 v) -{ - return (v & 0x1fffffU) << 10U; -} -static inline u32 pbdma_gp_entry1_length_v(u32 r) -{ - return (r >> 10U) & 0x1fffffU; -} -static inline u32 pbdma_gp_base_r(u32 i) -{ - return 0x00040048U + i*8192U; -} -static inline u32 pbdma_gp_base__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 pbdma_gp_base_offset_f(u32 v) -{ - return (v & 0x1fffffffU) << 3U; -} -static inline u32 pbdma_gp_base_rsvd_s(void) -{ - return 3U; -} -static inline u32 pbdma_gp_base_hi_r(u32 i) -{ - return 0x0004004cU + i*8192U; -} -static inline u32 pbdma_gp_base_hi_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pbdma_gp_base_hi_limit2_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 pbdma_gp_fetch_r(u32 i) -{ - return 0x00040050U + i*8192U; -} -static inline u32 pbdma_gp_get_r(u32 i) -{ - return 0x00040014U + i*8192U; -} -static inline u32 pbdma_gp_put_r(u32 i) -{ - return 0x00040000U + i*8192U; -} -static inline u32 pbdma_timeout_r(u32 i) -{ - return 0x0004012cU + i*8192U; -} -static inline u32 pbdma_timeout__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 pbdma_timeout_period_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 pbdma_timeout_period_max_f(void) -{ - return 0xffffffffU; -} -static inline u32 pbdma_pb_fetch_r(u32 i) -{ - return 0x00040054U + i*8192U; -} -static inline u32 pbdma_pb_fetch_hi_r(u32 i) -{ - return 0x00040058U + i*8192U; -} -static inline u32 pbdma_get_r(u32 i) -{ - return 0x00040018U + i*8192U; -} -static inline u32 pbdma_get_hi_r(u32 i) -{ - return 0x0004001cU + i*8192U; -} -static inline u32 pbdma_put_r(u32 i) -{ - return 0x0004005cU + i*8192U; -} -static inline u32 pbdma_put_hi_r(u32 i) -{ - return 0x00040060U + i*8192U; -} -static inline u32 pbdma_formats_r(u32 i) -{ - return 0x0004009cU + i*8192U; -} -static inline u32 pbdma_formats_gp_fermi0_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_formats_pb_fermi1_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_formats_mp_fermi0_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_r(u32 i) -{ - return 0x00040084U + i*8192U; -} -static inline u32 pbdma_pb_header_priv_user_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_method_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_subchannel_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_level_main_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_first_true_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_pb_header_type_inc_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_pb_header_type_non_inc_f(void) -{ - return 0x60000000U; -} -static inline u32 pbdma_hdr_shadow_r(u32 i) -{ - return 0x00040118U + i*8192U; -} -static inline u32 pbdma_gp_shadow_0_r(u32 i) -{ - return 0x00040110U + i*8192U; -} -static inline u32 pbdma_gp_shadow_1_r(u32 i) -{ - return 0x00040114U + i*8192U; -} -static inline u32 pbdma_subdevice_r(u32 i) -{ - return 0x00040094U + i*8192U; -} -static inline u32 pbdma_subdevice_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 pbdma_subdevice_status_active_f(void) -{ - return 0x10000000U; -} -static inline u32 pbdma_subdevice_channel_dma_enable_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_method0_r(u32 i) -{ - return 0x000400c0U + i*8192U; -} -static inline u32 pbdma_method0_addr_f(u32 v) -{ - return (v & 0xfffU) << 2U; -} -static inline u32 pbdma_method0_addr_v(u32 r) -{ - return (r >> 2U) & 0xfffU; -} -static inline u32 pbdma_method0_subch_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 pbdma_method0_first_true_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_method0_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_method1_r(u32 i) -{ - return 0x000400c8U + i*8192U; -} -static inline u32 pbdma_method2_r(u32 i) -{ - return 0x000400d0U + i*8192U; -} -static inline u32 pbdma_method3_r(u32 i) -{ - return 0x000400d8U + i*8192U; -} -static inline u32 pbdma_data0_r(u32 i) -{ - return 0x000400c4U + i*8192U; -} -static inline u32 pbdma_target_r(u32 i) -{ - return 0x000400acU + i*8192U; -} -static inline u32 pbdma_target_engine_sw_f(void) -{ - return 0x1fU; -} -static inline u32 pbdma_acquire_r(u32 i) -{ - return 0x00040030U + i*8192U; -} -static inline u32 pbdma_acquire_retry_man_2_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_acquire_retry_exp_2_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_acquire_timeout_exp_f(u32 v) -{ - return (v & 0xfU) << 11U; -} -static inline u32 pbdma_acquire_timeout_exp_max_v(void) -{ - return 0x0000000fU; -} -static inline u32 pbdma_acquire_timeout_exp_max_f(void) -{ - return 0x7800U; -} -static inline u32 pbdma_acquire_timeout_man_f(u32 v) -{ - return (v & 0xffffU) << 15U; -} -static inline u32 pbdma_acquire_timeout_man_max_v(void) -{ - return 0x0000ffffU; -} -static inline u32 pbdma_acquire_timeout_man_max_f(void) -{ - return 0x7fff8000U; -} -static inline u32 pbdma_acquire_timeout_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_acquire_timeout_en_disable_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_status_r(u32 i) -{ - return 0x00040100U + i*8192U; -} -static inline u32 pbdma_channel_r(u32 i) -{ - return 0x00040120U + i*8192U; -} -static inline u32 pbdma_signature_r(u32 i) -{ - return 0x00040010U + i*8192U; -} -static inline u32 pbdma_signature_hw_valid_f(void) -{ - return 0xfaceU; -} -static inline u32 pbdma_signature_sw_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_userd_r(u32 i) -{ - return 0x00040008U + i*8192U; -} -static inline u32 pbdma_userd_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_userd_target_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 pbdma_userd_addr_f(u32 v) -{ - return (v & 0x7fffffU) << 9U; -} -static inline u32 pbdma_userd_hi_r(u32 i) -{ - return 0x0004000cU + i*8192U; -} -static inline u32 pbdma_userd_hi_addr_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pbdma_hce_ctrl_r(u32 i) -{ - return 0x000400e4U + i*8192U; -} -static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void) -{ - return 0x20U; -} -static inline u32 pbdma_intr_0_r(u32 i) -{ - return 0x00040108U + i*8192U; -} -static inline u32 pbdma_intr_0_memreq_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pbdma_intr_0_memreq_pending_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_intr_0_memack_timeout_pending_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_intr_0_memack_extra_pending_f(void) -{ - return 0x4U; -} -static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void) -{ - return 0x8U; -} -static inline u32 pbdma_intr_0_memdat_extra_pending_f(void) -{ - return 0x10U; -} -static inline u32 pbdma_intr_0_memflush_pending_f(void) -{ - return 0x20U; -} -static inline u32 pbdma_intr_0_memop_pending_f(void) -{ - return 0x40U; -} -static inline u32 pbdma_intr_0_lbconnect_pending_f(void) -{ - return 0x80U; -} -static inline u32 pbdma_intr_0_lbreq_pending_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_0_lback_timeout_pending_f(void) -{ - return 0x200U; -} -static inline u32 pbdma_intr_0_lback_extra_pending_f(void) -{ - return 0x400U; -} -static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void) -{ - return 0x800U; -} -static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void) -{ - return 0x1000U; -} -static inline u32 pbdma_intr_0_gpfifo_pending_f(void) -{ - return 0x2000U; -} -static inline u32 pbdma_intr_0_gpptr_pending_f(void) -{ - return 0x4000U; -} -static inline u32 pbdma_intr_0_gpentry_pending_f(void) -{ - return 0x8000U; -} -static inline u32 pbdma_intr_0_gpcrc_pending_f(void) -{ - return 0x10000U; -} -static inline u32 pbdma_intr_0_pbptr_pending_f(void) -{ - return 0x20000U; -} -static inline u32 pbdma_intr_0_pbentry_pending_f(void) -{ - return 0x40000U; -} -static inline u32 pbdma_intr_0_pbcrc_pending_f(void) -{ - return 0x80000U; -} -static inline u32 pbdma_intr_0_xbarconnect_pending_f(void) -{ - return 0x100000U; -} -static inline u32 pbdma_intr_0_method_pending_f(void) -{ - return 0x200000U; -} -static inline u32 pbdma_intr_0_methodcrc_pending_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_intr_0_device_pending_f(void) -{ - return 0x800000U; -} -static inline u32 pbdma_intr_0_semaphore_pending_f(void) -{ - return 0x2000000U; -} -static inline u32 pbdma_intr_0_acquire_pending_f(void) -{ - return 0x4000000U; -} -static inline u32 pbdma_intr_0_pri_pending_f(void) -{ - return 0x8000000U; -} -static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_intr_0_pbseg_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 pbdma_intr_0_signature_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_intr_1_r(u32 i) -{ - return 0x00040148U + i*8192U; -} -static inline u32 pbdma_intr_en_0_r(u32 i) -{ - return 0x0004010cU + i*8192U; -} -static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_en_1_r(u32 i) -{ - return 0x0004014cU + i*8192U; -} -static inline u32 pbdma_intr_stall_r(u32 i) -{ - return 0x0004013cU + i*8192U; -} -static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_stall_1_r(u32 i) -{ - return 0x00040140U + i*8192U; -} -static inline u32 pbdma_intr_stall_1_hce_illegal_op_enabled_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_udma_nop_r(void) -{ - return 0x00000008U; -} -static inline u32 pbdma_syncpointa_r(u32 i) -{ - return 0x000400a4U + i*8192U; -} -static inline u32 pbdma_syncpointa_payload_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pbdma_syncpointb_r(u32 i) -{ - return 0x000400a8U + i*8192U; -} -static inline u32 pbdma_syncpointb_op_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 pbdma_syncpointb_op_wait_v(void) -{ - return 0x00000000U; -} -static inline u32 pbdma_syncpointb_wait_switch_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 pbdma_syncpointb_wait_switch_en_v(void) -{ - return 0x00000001U; -} -static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} -#endif diff --git a/include/nvgpu/hw/gk20a/hw_perf_gk20a.h b/include/nvgpu/hw/gk20a/hw_perf_gk20a.h deleted file mode 100644 index a93560f..0000000 --- a/include/nvgpu/hw/gk20a/hw_perf_gk20a.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_perf_gk20a_h_ -#define _hw_perf_gk20a_h_ - -static inline u32 perf_pmasys_control_r(void) -{ - return 0x001b4000U; -} -static inline u32 perf_pmasys_control_membuf_status_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void) -{ - return 0x10U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) -{ - return 0x20U; -} -static inline u32 perf_pmasys_mem_block_r(void) -{ - return 0x001b4070U; -} -static inline u32 perf_pmasys_mem_block_base_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 perf_pmasys_mem_block_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 perf_pmasys_mem_block_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 perf_pmasys_mem_block_target_lfb_v(void) -{ - return 0x00000000U; -} -static inline u32 perf_pmasys_mem_block_target_lfb_f(void) -{ - return 0x0U; -} -static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 perf_pmasys_mem_block_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 perf_pmasys_mem_block_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 perf_pmasys_mem_block_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_mem_block_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 perf_pmasys_mem_block_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 perf_pmasys_mem_block_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 perf_pmasys_outbase_r(void) -{ - return 0x001b4074U; -} -static inline u32 perf_pmasys_outbase_ptr_f(u32 v) -{ - return (v & 0x7ffffffU) << 5U; -} -static inline u32 perf_pmasys_outbaseupper_r(void) -{ - return 0x001b4078U; -} -static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 perf_pmasys_outsize_r(void) -{ - return 0x001b407cU; -} -static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) -{ - return (v & 0x7ffffffU) << 5U; -} -static inline u32 perf_pmasys_mem_bytes_r(void) -{ - return 0x001b4084U; -} -static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 perf_pmasys_mem_bump_r(void) -{ - return 0x001b4088U; -} -static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 perf_pmasys_enginestatus_r(void) -{ - return 0x001b40a4U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void) -{ - return 0x10U; -} -#endif diff --git a/include/nvgpu/hw/gk20a/hw_pram_gk20a.h b/include/nvgpu/hw/gk20a/hw_pram_gk20a.h deleted file mode 100644 index 10923e2..0000000 --- a/include/nvgpu/hw/gk20a/hw_pram_gk20a.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pram_gk20a_h_ -#define _hw_pram_gk20a_h_ - -static inline u32 pram_data032_r(u32 i) -{ - return 0x00700000U + i*4U; -} -#endif diff --git a/include/nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h b/include/nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h deleted file mode 100644 index ca2775e..0000000 --- a/include/nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pri_ringmaster_gk20a_h_ -#define _hw_pri_ringmaster_gk20a_h_ - -static inline u32 pri_ringmaster_command_r(void) -{ - return 0x0012004cU; -} -static inline u32 pri_ringmaster_command_cmd_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 pri_ringmaster_command_cmd_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void) -{ - return 0x00000000U; -} -static inline u32 pri_ringmaster_command_cmd_start_ring_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void) -{ - return 0x2U; -} -static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void) -{ - return 0x3U; -} -static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void) -{ - return 0x0U; -} -static inline u32 pri_ringmaster_command_data_r(void) -{ - return 0x00120048U; -} -static inline u32 pri_ringmaster_start_results_r(void) -{ - return 0x00120050U; -} -static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void) -{ - return 0x00000001U; -} -static inline u32 pri_ringmaster_intr_status0_r(void) -{ - return 0x00120058U; -} -static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status1_r(void) -{ - return 0x0012005cU; -} -static inline u32 pri_ringmaster_global_ctl_r(void) -{ - return 0x00120060U; -} -static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void) -{ - return 0x0U; -} -static inline u32 pri_ringmaster_enum_fbp_r(void) -{ - return 0x00120074U; -} -static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 pri_ringmaster_enum_gpc_r(void) -{ - return 0x00120078U; -} -static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -#endif diff --git a/include/nvgpu/hw/gk20a/hw_pri_ringstation_fbp_gk20a.h b/include/nvgpu/hw/gk20a/hw_pri_ringstation_fbp_gk20a.h deleted file mode 100644 index 06e08bd..0000000 --- a/include/nvgpu/hw/gk20a/hw_pri_ringstation_fbp_gk20a.h +++ /dev/null @@ -1,231 +0,0 @@ -/* - * drivers/video/tegra/host/gk20a/hw_pri_ringstation_fbp_gk20a.h - * - * Copyright (c) 2012-2013, NVIDIA Corporation. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - - /* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ - -#ifndef __hw_pri_ringstation_fbp_gk20a_h__ -#define __hw_pri_ringstation_fbp_gk20a_h__ -/*This file is autogenerated. Do not edit. */ - -static inline u32 pri_ringstation_fbp_master_config_r(u32 i) -{ - return 0x00124300+((i)*4); -} -static inline u32 pri_ringstation_fbp_master_config__size_1_v(void) -{ - return 64; -} -static inline u32 pri_ringstation_fbp_master_config_timeout_s(void) -{ - return 18; -} -static inline u32 pri_ringstation_fbp_master_config_timeout_f(u32 v) -{ - return (v & 0x3ffff) << 0; -} -static inline u32 pri_ringstation_fbp_master_config_timeout_m(void) -{ - return 0x3ffff << 0; -} -static inline u32 pri_ringstation_fbp_master_config_timeout_v(u32 r) -{ - return (r >> 0) & 0x3ffff; -} -static inline u32 pri_ringstation_fbp_master_config_timeout_i_v(void) -{ - return 0x00000064; -} -static inline u32 pri_ringstation_fbp_master_config_timeout_i_f(void) -{ - return 0x64; -} -static inline u32 pri_ringstation_fbp_master_config_fs_action_s(void) -{ - return 1; -} -static inline u32 pri_ringstation_fbp_master_config_fs_action_f(u32 v) -{ - return (v & 0x1) << 30; -} -static inline u32 pri_ringstation_fbp_master_config_fs_action_m(void) -{ - return 0x1 << 30; -} -static inline u32 pri_ringstation_fbp_master_config_fs_action_v(u32 r) -{ - return (r >> 30) & 0x1; -} -static inline u32 pri_ringstation_fbp_master_config_fs_action_error_v(void) -{ - return 0x00000000; -} -static inline u32 pri_ringstation_fbp_master_config_fs_action_error_f(void) -{ - return 0x0; -} -static inline u32 pri_ringstation_fbp_master_config_fs_action_soldier_on_v(void) -{ - return 0x00000001; -} -static inline u32 pri_ringstation_fbp_master_config_fs_action_soldier_on_f(void) -{ - return 0x40000000; -} -static inline u32 pri_ringstation_fbp_master_config_reset_action_s(void) -{ - return 1; -} -static inline u32 pri_ringstation_fbp_master_config_reset_action_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 pri_ringstation_fbp_master_config_reset_action_m(void) -{ - return 0x1 << 31; -} -static inline u32 pri_ringstation_fbp_master_config_reset_action_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 pri_ringstation_fbp_master_config_reset_action_error_v(void) -{ - return 0x00000000; -} -static inline u32 pri_ringstation_fbp_master_config_reset_action_error_f(void) -{ - return 0x0; -} -static inline u32 pri_ringstation_fbp_master_config_reset_action_soldier_on_v(void) -{ - return 0x00000001; -} -static inline u32 pri_ringstation_fbp_master_config_reset_action_soldier_on_f(void) -{ - return 0x80000000; -} -static inline u32 pri_ringstation_fbp_master_config_setup_clocks_s(void) -{ - return 3; -} -static inline u32 pri_ringstation_fbp_master_config_setup_clocks_f(u32 v) -{ - return (v & 0x7) << 20; -} -static inline u32 pri_ringstation_fbp_master_config_setup_clocks_m(void) -{ - return 0x7 << 20; -} -static inline u32 pri_ringstation_fbp_master_config_setup_clocks_v(u32 r) -{ - return (r >> 20) & 0x7; -} -static inline u32 pri_ringstation_fbp_master_config_setup_clocks_i_v(void) -{ - return 0x00000000; -} -static inline u32 pri_ringstation_fbp_master_config_setup_clocks_i_f(void) -{ - return 0x0; -} -static inline u32 pri_ringstation_fbp_master_config_wait_clocks_s(void) -{ - return 3; -} -static inline u32 pri_ringstation_fbp_master_config_wait_clocks_f(u32 v) -{ - return (v & 0x7) << 24; -} -static inline u32 pri_ringstation_fbp_master_config_wait_clocks_m(void) -{ - return 0x7 << 24; -} -static inline u32 pri_ringstation_fbp_master_config_wait_clocks_v(u32 r) -{ - return (r >> 24) & 0x7; -} -static inline u32 pri_ringstation_fbp_master_config_wait_clocks_i_v(void) -{ - return 0x00000000; -} -static inline u32 pri_ringstation_fbp_master_config_wait_clocks_i_f(void) -{ - return 0x0; -} -static inline u32 pri_ringstation_fbp_master_config_hold_clocks_s(void) -{ - return 3; -} -static inline u32 pri_ringstation_fbp_master_config_hold_clocks_f(u32 v) -{ - return (v & 0x7) << 27; -} -static inline u32 pri_ringstation_fbp_master_config_hold_clocks_m(void) -{ - return 0x7 << 27; -} -static inline u32 pri_ringstation_fbp_master_config_hold_clocks_v(u32 r) -{ - return (r >> 27) & 0x7; -} -static inline u32 pri_ringstation_fbp_master_config_hold_clocks_i_v(void) -{ - return 0x00000000; -} -static inline u32 pri_ringstation_fbp_master_config_hold_clocks_i_f(void) -{ - return 0x0; -} - -#endif /* __hw_pri_ringstation_fbp_gk20a_h__ */ diff --git a/include/nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h b/include/nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h deleted file mode 100644 index 6b57429..0000000 --- a/include/nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pri_ringstation_gpc_gk20a_h_ -#define _hw_pri_ringstation_gpc_gk20a_h_ - -static inline u32 pri_ringstation_gpc_master_config_r(u32 i) -{ - return 0x00128300U + i*4U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void) -{ - return 0x00128120U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void) -{ - return 0x00128124U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void) -{ - return 0x00128128U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void) -{ - return 0x0012812cU; -} -#endif diff --git a/include/nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h b/include/nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h deleted file mode 100644 index e4d5c3b..0000000 --- a/include/nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pri_ringstation_sys_gk20a_h_ -#define _hw_pri_ringstation_sys_gk20a_h_ - -static inline u32 pri_ringstation_sys_master_config_r(u32 i) -{ - return 0x00122300U + i*4U; -} -static inline u32 pri_ringstation_sys_decode_config_r(void) -{ - return 0x00122204U; -} -static inline u32 pri_ringstation_sys_decode_config_ring_m(void) -{ - return 0x7U << 0U; -} -static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringstation_sys_priv_error_adr_r(void) -{ - return 0x00122120U; -} -static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void) -{ - return 0x00122124U; -} -static inline u32 pri_ringstation_sys_priv_error_info_r(void) -{ - return 0x00122128U; -} -static inline u32 pri_ringstation_sys_priv_error_code_r(void) -{ - return 0x0012212cU; -} -#endif diff --git a/include/nvgpu/hw/gk20a/hw_proj_gk20a.h b/include/nvgpu/hw/gk20a/hw_proj_gk20a.h deleted file mode 100644 index 10509ca..0000000 --- a/include/nvgpu/hw/gk20a/hw_proj_gk20a.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright (c) 2012-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_proj_gk20a_h_ -#define _hw_proj_gk20a_h_ - -static inline u32 proj_gpc_base_v(void) -{ - return 0x00500000U; -} -static inline u32 proj_gpc_shared_base_v(void) -{ - return 0x00418000U; -} -static inline u32 proj_gpc_stride_v(void) -{ - return 0x00008000U; -} -static inline u32 proj_gpc_priv_stride_v(void) -{ - return 0x00000800U; -} -static inline u32 proj_ltc_stride_v(void) -{ - return 0x00002000U; -} -static inline u32 proj_lts_stride_v(void) -{ - return 0x00000400U; -} -static inline u32 proj_fbpa_stride_v(void) -{ - return 0x00001000U; -} -static inline u32 proj_ppc_in_gpc_base_v(void) -{ - return 0x00003000U; -} -static inline u32 proj_ppc_in_gpc_shared_base_v(void) -{ - return 0x00003e00U; -} -static inline u32 proj_ppc_in_gpc_stride_v(void) -{ - return 0x00000200U; -} -static inline u32 proj_rop_base_v(void) -{ - return 0x00410000U; -} -static inline u32 proj_rop_shared_base_v(void) -{ - return 0x00408800U; -} -static inline u32 proj_rop_stride_v(void) -{ - return 0x00000400U; -} -static inline u32 proj_tpc_in_gpc_base_v(void) -{ - return 0x00004000U; -} -static inline u32 proj_tpc_in_gpc_stride_v(void) -{ - return 0x00000800U; -} -static inline u32 proj_tpc_in_gpc_shared_base_v(void) -{ - return 0x00001800U; -} -static inline u32 proj_host_num_engines_v(void) -{ - return 0x00000002U; -} -static inline u32 proj_host_num_pbdma_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_fbps_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_fbpas_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_gpcs_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_zcull_banks_v(void) -{ - return 0x00000004U; -} -static inline u32 proj_scal_max_gpcs_v(void) -{ - return 0x00000020U; -} -static inline u32 proj_scal_max_tpc_per_gpc_v(void) -{ - return 0x00000008U; -} -#endif diff --git a/include/nvgpu/hw/gk20a/hw_pwr_gk20a.h b/include/nvgpu/hw/gk20a/hw_pwr_gk20a.h deleted file mode 100644 index b879563..0000000 --- a/include/nvgpu/hw/gk20a/hw_pwr_gk20a.h +++ /dev/null @@ -1,827 +0,0 @@ -/* - * Copyright (c) 2012-2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pwr_gk20a_h_ -#define _hw_pwr_gk20a_h_ - -static inline u32 pwr_falcon_irqsset_r(void) -{ - return 0x0010a000U; -} -static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 pwr_falcon_irqsclr_r(void) -{ - return 0x0010a004U; -} -static inline u32 pwr_falcon_irqstat_r(void) -{ - return 0x0010a008U; -} -static inline u32 pwr_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 pwr_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 pwr_falcon_irqmode_r(void) -{ - return 0x0010a00cU; -} -static inline u32 pwr_falcon_irqmset_r(void) -{ - return 0x0010a010U; -} -static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqmclr_r(void) -{ - return 0x0010a014U; -} -static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqmask_r(void) -{ - return 0x0010a018U; -} -static inline u32 pwr_falcon_irqdest_r(void) -{ - return 0x0010a01cU; -} -static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 pwr_falcon_curctx_r(void) -{ - return 0x0010a050U; -} -static inline u32 pwr_falcon_nxtctx_r(void) -{ - return 0x0010a054U; -} -static inline u32 pwr_falcon_mailbox0_r(void) -{ - return 0x0010a040U; -} -static inline u32 pwr_falcon_mailbox1_r(void) -{ - return 0x0010a044U; -} -static inline u32 pwr_falcon_itfen_r(void) -{ - return 0x0010a048U; -} -static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 pwr_falcon_idlestate_r(void) -{ - return 0x0010a04cU; -} -static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 pwr_falcon_os_r(void) -{ - return 0x0010a080U; -} -static inline u32 pwr_falcon_engctl_r(void) -{ - return 0x0010a0a4U; -} -static inline u32 pwr_falcon_cpuctl_r(void) -{ - return 0x0010a100U; -} -static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) -{ - return 0x1U << 4U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 pwr_falcon_imemc_r(u32 i) -{ - return 0x0010a180U + i*16U; -} -static inline u32 pwr_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pwr_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_imemd_r(u32 i) -{ - return 0x0010a184U + i*16U; -} -static inline u32 pwr_falcon_imemt_r(u32 i) -{ - return 0x0010a188U + i*16U; -} -static inline u32 pwr_falcon_bootvec_r(void) -{ - return 0x0010a104U; -} -static inline u32 pwr_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_falcon_dmactl_r(void) -{ - return 0x0010a10cU; -} -static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) -{ - return 0x1U << 1U; -} -static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) -{ - return 0x1U << 2U; -} -static inline u32 pwr_falcon_hwcfg_r(void) -{ - return 0x0010a108U; -} -static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 pwr_falcon_dmatrfbase_r(void) -{ - return 0x0010a110U; -} -static inline u32 pwr_falcon_dmatrfmoffs_r(void) -{ - return 0x0010a114U; -} -static inline u32 pwr_falcon_dmatrfcmd_r(void) -{ - return 0x0010a118U; -} -static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 pwr_falcon_dmatrffboffs_r(void) -{ - return 0x0010a11cU; -} -static inline u32 pwr_falcon_exterraddr_r(void) -{ - return 0x0010a168U; -} -static inline u32 pwr_falcon_exterrstat_r(void) -{ - return 0x0010a16cU; -} -static inline u32 pwr_falcon_exterrstat_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 pwr_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_r(void) -{ - return 0x0010a200U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) -{ - return 0xfU << 0U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 pwr_pmu_falcon_icd_rdata_r(void) -{ - return 0x0010a20cU; -} -static inline u32 pwr_falcon_dmemc_r(u32 i) -{ - return 0x0010a1c0U + i*8U; -} -static inline u32 pwr_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pwr_falcon_dmemc_offs_m(void) -{ - return 0x3fU << 2U; -} -static inline u32 pwr_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_dmemc_blk_m(void) -{ - return 0xffU << 8U; -} -static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 pwr_falcon_dmemd_r(u32 i) -{ - return 0x0010a1c4U + i*8U; -} -static inline u32 pwr_pmu_new_instblk_r(void) -{ - return 0x0010a480U; -} -static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 pwr_pmu_new_instblk_target_fb_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 pwr_pmu_mutex_id_r(void) -{ - return 0x0010a488U; -} -static inline u32 pwr_pmu_mutex_id_value_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pwr_pmu_mutex_id_value_init_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) -{ - return 0x000000ffU; -} -static inline u32 pwr_pmu_mutex_id_release_r(void) -{ - return 0x0010a48cU; -} -static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_id_release_value_m(void) -{ - return 0xffU << 0U; -} -static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_mutex_r(u32 i) -{ - return 0x0010a580U + i*4U; -} -static inline u32 pwr_pmu_mutex__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 pwr_pmu_mutex_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_value_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_queue_head_r(u32 i) -{ - return 0x0010a4a0U + i*4U; -} -static inline u32 pwr_pmu_queue_head__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 pwr_pmu_queue_head_address_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_queue_head_address_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_queue_tail_r(u32 i) -{ - return 0x0010a4b0U + i*4U; -} -static inline u32 pwr_pmu_queue_tail__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 pwr_pmu_queue_tail_address_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_queue_tail_address_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_msgq_head_r(void) -{ - return 0x0010a4c8U; -} -static inline u32 pwr_pmu_msgq_head_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_msgq_head_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_msgq_tail_r(void) -{ - return 0x0010a4ccU; -} -static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_idle_mask_r(u32 i) -{ - return 0x0010a504U + i*16U; -} -static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) -{ - return 0x1U; -} -static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 pwr_pmu_idle_mask_1_r(u32 i) -{ - return 0x0010aa34U + i*8U; -} -static inline u32 pwr_pmu_idle_count_r(u32 i) -{ - return 0x0010a508U + i*16U; -} -static inline u32 pwr_pmu_idle_count_value_f(u32 v) -{ - return (v & 0x7fffffffU) << 0U; -} -static inline u32 pwr_pmu_idle_count_value_v(u32 r) -{ - return (r >> 0U) & 0x7fffffffU; -} -static inline u32 pwr_pmu_idle_count_reset_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 pwr_pmu_idle_ctrl_r(u32 i) -{ - return 0x0010a50cU + i*16U; -} -static inline u32 pwr_pmu_idle_ctrl_value_m(void) -{ - return 0x3U << 0U; -} -static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) -{ - return 0x2U; -} -static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) -{ - return 0x3U; -} -static inline u32 pwr_pmu_idle_ctrl_filter_m(void) -{ - return 0x1U << 2U; -} -static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_idle_threshold_r(u32 i) -{ - return 0x0010a8a0U + i*4U; -} -static inline u32 pwr_pmu_idle_threshold_value_f(u32 v) -{ - return (v & 0x7fffffffU) << 0U; -} -static inline u32 pwr_pmu_idle_intr_r(void) -{ - return 0x0010a9e8U; -} -static inline u32 pwr_pmu_idle_intr_en_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_en_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_idle_intr_en_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_intr_status_r(void) -{ - return 0x0010a9ecU; -} -static inline u32 pwr_pmu_idle_intr_status_intr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_m(void) -{ - return 0x1U << 0U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) -{ - return 0x0010a9f0U + i*8U; -} -static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) -{ - return 0x0010a9f4U + i*8U; -} -static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) -{ - return 0x0010aa30U + i*8U; -} -static inline u32 pwr_pmu_debug_r(u32 i) -{ - return 0x0010a5c0U + i*4U; -} -static inline u32 pwr_pmu_debug__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 pwr_pmu_mailbox_r(u32 i) -{ - return 0x0010a450U + i*4U; -} -static inline u32 pwr_pmu_mailbox__size_1_v(void) -{ - return 0x0000000cU; -} -static inline u32 pwr_pmu_bar0_addr_r(void) -{ - return 0x0010a7a0U; -} -static inline u32 pwr_pmu_bar0_data_r(void) -{ - return 0x0010a7a4U; -} -static inline u32 pwr_pmu_bar0_ctl_r(void) -{ - return 0x0010a7acU; -} -static inline u32 pwr_pmu_bar0_timeout_r(void) -{ - return 0x0010a7a8U; -} -static inline u32 pwr_pmu_bar0_fecs_error_r(void) -{ - return 0x0010a988U; -} -static inline u32 pwr_pmu_bar0_error_status_r(void) -{ - return 0x0010a7b0U; -} -static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) -{ - return 0x0010a6c0U + i*4U; -} -static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) -{ - return 0x0010a6e8U + i*4U; -} -static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) -{ - return 0x0010a710U + i*4U; -} -static inline u32 pwr_pmu_pg_intren_r(u32 i) -{ - return 0x0010a760U + i*4U; -} -static inline u32 pwr_fbif_transcfg_r(u32 i) -{ - return 0x0010a600U + i*4U; -} -static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) -{ - return 0x0U; -} -static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) -{ - return 0x1U; -} -static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) -{ - return 0x2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_s(void) -{ - return 1U; -} -static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_m(void) -{ - return 0x1U << 2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) -{ - return 0x0U; -} -static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) -{ - return 0x4U; -} -#endif diff --git a/include/nvgpu/hw/gk20a/hw_ram_gk20a.h b/include/nvgpu/hw/gk20a/hw_ram_gk20a.h deleted file mode 100644 index ed385d9..0000000 --- a/include/nvgpu/hw/gk20a/hw_ram_gk20a.h +++ /dev/null @@ -1,443 +0,0 @@ -/* - * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ram_gk20a_h_ -#define _hw_ram_gk20a_h_ - -static inline u32 ram_in_ramfc_s(void) -{ - return 4096U; -} -static inline u32 ram_in_ramfc_w(void) -{ - return 0U; -} -static inline u32 ram_in_page_dir_base_target_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ram_in_page_dir_base_target_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 ram_in_page_dir_base_vol_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_vol_true_f(void) -{ - return 0x4U; -} -static inline u32 ram_in_page_dir_base_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_page_dir_base_lo_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_hi_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ram_in_page_dir_base_hi_w(void) -{ - return 129U; -} -static inline u32 ram_in_adr_limit_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_adr_limit_lo_w(void) -{ - return 130U; -} -static inline u32 ram_in_adr_limit_hi_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ram_in_adr_limit_hi_w(void) -{ - return 131U; -} -static inline u32 ram_in_engine_cs_w(void) -{ - return 132U; -} -static inline u32 ram_in_engine_cs_wfi_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_engine_cs_wfi_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_engine_cs_fg_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_engine_cs_fg_f(void) -{ - return 0x8U; -} -static inline u32 ram_in_gr_cs_w(void) -{ - return 132U; -} -static inline u32 ram_in_gr_cs_wfi_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_gr_wfi_target_w(void) -{ - return 132U; -} -static inline u32 ram_in_gr_wfi_mode_w(void) -{ - return 132U; -} -static inline u32 ram_in_gr_wfi_mode_physical_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_gr_wfi_mode_physical_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_gr_wfi_mode_virtual_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_gr_wfi_mode_virtual_f(void) -{ - return 0x4U; -} -static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_gr_wfi_ptr_lo_w(void) -{ - return 132U; -} -static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ram_in_gr_wfi_ptr_hi_w(void) -{ - return 133U; -} -static inline u32 ram_in_base_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 ram_in_alloc_size_v(void) -{ - return 0x00001000U; -} -static inline u32 ram_fc_size_val_v(void) -{ - return 0x00000200U; -} -static inline u32 ram_fc_gp_put_w(void) -{ - return 0U; -} -static inline u32 ram_fc_userd_w(void) -{ - return 2U; -} -static inline u32 ram_fc_userd_hi_w(void) -{ - return 3U; -} -static inline u32 ram_fc_signature_w(void) -{ - return 4U; -} -static inline u32 ram_fc_gp_get_w(void) -{ - return 5U; -} -static inline u32 ram_fc_pb_get_w(void) -{ - return 6U; -} -static inline u32 ram_fc_pb_get_hi_w(void) -{ - return 7U; -} -static inline u32 ram_fc_pb_top_level_get_w(void) -{ - return 8U; -} -static inline u32 ram_fc_pb_top_level_get_hi_w(void) -{ - return 9U; -} -static inline u32 ram_fc_acquire_w(void) -{ - return 12U; -} -static inline u32 ram_fc_semaphorea_w(void) -{ - return 14U; -} -static inline u32 ram_fc_semaphoreb_w(void) -{ - return 15U; -} -static inline u32 ram_fc_semaphorec_w(void) -{ - return 16U; -} -static inline u32 ram_fc_semaphored_w(void) -{ - return 17U; -} -static inline u32 ram_fc_gp_base_w(void) -{ - return 18U; -} -static inline u32 ram_fc_gp_base_hi_w(void) -{ - return 19U; -} -static inline u32 ram_fc_gp_fetch_w(void) -{ - return 20U; -} -static inline u32 ram_fc_pb_fetch_w(void) -{ - return 21U; -} -static inline u32 ram_fc_pb_fetch_hi_w(void) -{ - return 22U; -} -static inline u32 ram_fc_pb_put_w(void) -{ - return 23U; -} -static inline u32 ram_fc_pb_put_hi_w(void) -{ - return 24U; -} -static inline u32 ram_fc_pb_header_w(void) -{ - return 33U; -} -static inline u32 ram_fc_pb_count_w(void) -{ - return 34U; -} -static inline u32 ram_fc_subdevice_w(void) -{ - return 37U; -} -static inline u32 ram_fc_formats_w(void) -{ - return 39U; -} -static inline u32 ram_fc_syncpointa_w(void) -{ - return 41U; -} -static inline u32 ram_fc_syncpointb_w(void) -{ - return 42U; -} -static inline u32 ram_fc_target_w(void) -{ - return 43U; -} -static inline u32 ram_fc_hce_ctrl_w(void) -{ - return 57U; -} -static inline u32 ram_fc_chid_w(void) -{ - return 58U; -} -static inline u32 ram_fc_chid_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_fc_chid_id_w(void) -{ - return 0U; -} -static inline u32 ram_fc_runlist_timeslice_w(void) -{ - return 62U; -} -static inline u32 ram_fc_pb_timeslice_w(void) -{ - return 63U; -} -static inline u32 ram_userd_base_shift_v(void) -{ - return 0x00000009U; -} -static inline u32 ram_userd_chan_size_v(void) -{ - return 0x00000200U; -} -static inline u32 ram_userd_put_w(void) -{ - return 16U; -} -static inline u32 ram_userd_get_w(void) -{ - return 17U; -} -static inline u32 ram_userd_ref_w(void) -{ - return 18U; -} -static inline u32 ram_userd_put_hi_w(void) -{ - return 19U; -} -static inline u32 ram_userd_ref_threshold_w(void) -{ - return 20U; -} -static inline u32 ram_userd_top_level_get_w(void) -{ - return 22U; -} -static inline u32 ram_userd_top_level_get_hi_w(void) -{ - return 23U; -} -static inline u32 ram_userd_get_hi_w(void) -{ - return 24U; -} -static inline u32 ram_userd_gp_get_w(void) -{ - return 34U; -} -static inline u32 ram_userd_gp_put_w(void) -{ - return 35U; -} -static inline u32 ram_userd_gp_top_level_get_w(void) -{ - return 22U; -} -static inline u32 ram_userd_gp_top_level_get_hi_w(void) -{ - return 23U; -} -static inline u32 ram_rl_entry_size_v(void) -{ - return 0x00000008U; -} -static inline u32 ram_rl_entry_chid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_type_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 ram_rl_entry_type_chid_f(void) -{ - return 0x0U; -} -static inline u32 ram_rl_entry_type_tsg_f(void) -{ - return 0x2000U; -} -static inline u32 ram_rl_entry_timeslice_scale_f(u32 v) -{ - return (v & 0xfU) << 14U; -} -static inline u32 ram_rl_entry_timeslice_scale_3_f(void) -{ - return 0xc000U; -} -static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v) -{ - return (v & 0xffU) << 18U; -} -static inline u32 ram_rl_entry_timeslice_timeout_128_f(void) -{ - return 0x2000000U; -} -static inline u32 ram_rl_entry_tsg_length_f(u32 v) -{ - return (v & 0x3fU) << 26U; -} -#endif diff --git a/include/nvgpu/hw/gk20a/hw_therm_gk20a.h b/include/nvgpu/hw/gk20a/hw_therm_gk20a.h deleted file mode 100644 index 075c9bc..0000000 --- a/include/nvgpu/hw/gk20a/hw_therm_gk20a.h +++ /dev/null @@ -1,367 +0,0 @@ -/* - * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_therm_gk20a_h_ -#define _hw_therm_gk20a_h_ - -static inline u32 therm_use_a_r(void) -{ - return 0x00020798U; -} -static inline u32 therm_use_a_ext_therm_0_enable_f(void) -{ - return 0x1U; -} -static inline u32 therm_use_a_ext_therm_1_enable_f(void) -{ - return 0x2U; -} -static inline u32 therm_use_a_ext_therm_2_enable_f(void) -{ - return 0x4U; -} -static inline u32 therm_evt_ext_therm_0_r(void) -{ - return 0x00020700U; -} -static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v) -{ - return (v & 0x3fU) << 8U; -} -static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void) -{ - return 0x00000000U; -} -static inline u32 therm_evt_ext_therm_0_priority_f(u32 v) -{ - return (v & 0x1fU) << 24U; -} -static inline u32 therm_evt_ext_therm_1_r(void) -{ - return 0x00020704U; -} -static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v) -{ - return (v & 0x3fU) << 8U; -} -static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void) -{ - return 0x00000000U; -} -static inline u32 therm_evt_ext_therm_1_priority_f(u32 v) -{ - return (v & 0x1fU) << 24U; -} -static inline u32 therm_evt_ext_therm_2_r(void) -{ - return 0x00020708U; -} -static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v) -{ - return (v & 0x3fU) << 8U; -} -static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void) -{ - return 0x00000000U; -} -static inline u32 therm_evt_ext_therm_2_priority_f(u32 v) -{ - return (v & 0x1fU) << 24U; -} -static inline u32 therm_weight_1_r(void) -{ - return 0x00020024U; -} -static inline u32 therm_config1_r(void) -{ - return 0x00020050U; -} -static inline u32 therm_config2_r(void) -{ - return 0x00020130U; -} -static inline u32 therm_config2_slowdown_factor_extended_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 therm_config2_grad_enable_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 therm_gate_ctrl_r(u32 i) -{ - return 0x00020200U + i*4U; -} -static inline u32 therm_gate_ctrl_eng_clk_m(void) -{ - return 0x3U << 0U; -} -static inline u32 therm_gate_ctrl_eng_clk_run_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) -{ - return 0x1U; -} -static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) -{ - return 0x2U; -} -static inline u32 therm_gate_ctrl_blk_clk_m(void) -{ - return 0x3U << 2U; -} -static inline u32 therm_gate_ctrl_blk_clk_run_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) -{ - return 0x4U; -} -static inline u32 therm_gate_ctrl_eng_pwr_m(void) -{ - return 0x3U << 4U; -} -static inline u32 therm_gate_ctrl_eng_pwr_auto_f(void) -{ - return 0x10U; -} -static inline u32 therm_gate_ctrl_eng_pwr_off_v(void) -{ - return 0x00000002U; -} -static inline u32 therm_gate_ctrl_eng_pwr_off_f(void) -{ - return 0x20U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) -{ - return 0x1fU << 8U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) -{ - return (v & 0x7U) << 13U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) -{ - return 0x7U << 13U; -} -static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 therm_gate_ctrl_eng_delay_before_m(void) -{ - return 0xfU << 16U; -} -static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 therm_gate_ctrl_eng_delay_after_m(void) -{ - return 0xfU << 20U; -} -static inline u32 therm_fecs_idle_filter_r(void) -{ - return 0x00020288U; -} -static inline u32 therm_fecs_idle_filter_value_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 therm_hubmmu_idle_filter_r(void) -{ - return 0x0002028cU; -} -static inline u32 therm_hubmmu_idle_filter_value_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 therm_clk_slowdown_r(u32 i) -{ - return 0x00020160U + i*4U; -} -static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) -{ - return (v & 0x3fU) << 16U; -} -static inline u32 therm_clk_slowdown_idle_factor_m(void) -{ - return 0x3fU << 16U; -} -static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) -{ - return (r >> 16U) & 0x3fU; -} -static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) -{ - return 0x0U; -} -static inline u32 therm_grad_stepping_table_r(u32 i) -{ - return 0x000202c8U + i*4U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void) -{ - return 0x1U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void) -{ - return 0x2U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void) -{ - return 0x6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void) -{ - return 0xeU; -} -static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v) -{ - return (v & 0x3fU) << 6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void) -{ - return 0x3fU << 6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) -{ - return (v & 0x3fU) << 12U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void) -{ - return 0x3fU << 12U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) -{ - return (v & 0x3fU) << 18U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void) -{ - return 0x3fU << 18U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) -{ - return (v & 0x3fU) << 24U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void) -{ - return 0x3fU << 24U; -} -static inline u32 therm_grad_stepping0_r(void) -{ - return 0x000202c0U; -} -static inline u32 therm_grad_stepping0_feature_s(void) -{ - return 1U; -} -static inline u32 therm_grad_stepping0_feature_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 therm_grad_stepping0_feature_m(void) -{ - return 0x1U << 0U; -} -static inline u32 therm_grad_stepping0_feature_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 therm_grad_stepping0_feature_enable_f(void) -{ - return 0x1U; -} -static inline u32 therm_grad_stepping1_r(void) -{ - return 0x000202c4U; -} -static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 therm_clk_timing_r(u32 i) -{ - return 0x000203c0U + i*4U; -} -static inline u32 therm_clk_timing_grad_slowdown_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 therm_clk_timing_grad_slowdown_m(void) -{ - return 0x1U << 16U; -} -static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void) -{ - return 0x10000U; -} -#endif diff --git a/include/nvgpu/hw/gk20a/hw_timer_gk20a.h b/include/nvgpu/hw/gk20a/hw_timer_gk20a.h deleted file mode 100644 index 972d68a..0000000 --- a/include/nvgpu/hw/gk20a/hw_timer_gk20a.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright (c) 2013-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_timer_gk20a_h_ -#define _hw_timer_gk20a_h_ - -static inline u32 timer_pri_timeout_r(void) -{ - return 0x00009080U; -} -static inline u32 timer_pri_timeout_period_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 timer_pri_timeout_period_m(void) -{ - return 0xffffffU << 0U; -} -static inline u32 timer_pri_timeout_period_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 timer_pri_timeout_en_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 timer_pri_timeout_en_m(void) -{ - return 0x1U << 31U; -} -static inline u32 timer_pri_timeout_en_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 timer_pri_timeout_en_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 timer_pri_timeout_en_en_disabled_f(void) -{ - return 0x0U; -} -static inline u32 timer_pri_timeout_save_0_r(void) -{ - return 0x00009084U; -} -static inline u32 timer_pri_timeout_save_0_fecs_tgt_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 timer_pri_timeout_save_0_addr_v(u32 r) -{ - return (r >> 2U) & 0x3fffffU; -} -static inline u32 timer_pri_timeout_save_0_write_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 timer_pri_timeout_save_1_r(void) -{ - return 0x00009088U; -} -static inline u32 timer_pri_timeout_fecs_errcode_r(void) -{ - return 0x0000908cU; -} -static inline u32 timer_time_0_r(void) -{ - return 0x00009400U; -} -static inline u32 timer_time_1_r(void) -{ - return 0x00009410U; -} -#endif diff --git a/include/nvgpu/hw/gk20a/hw_top_gk20a.h b/include/nvgpu/hw/gk20a/hw_top_gk20a.h deleted file mode 100644 index be7fa4a..0000000 --- a/include/nvgpu/hw/gk20a/hw_top_gk20a.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_top_gk20a_h_ -#define _hw_top_gk20a_h_ - -static inline u32 top_num_gpcs_r(void) -{ - return 0x00022430U; -} -static inline u32 top_num_gpcs_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_tpc_per_gpc_r(void) -{ - return 0x00022434U; -} -static inline u32 top_tpc_per_gpc_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_num_fbps_r(void) -{ - return 0x00022438U; -} -static inline u32 top_num_fbps_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_device_info_r(u32 i) -{ - return 0x00022700U + i*4U; -} -static inline u32 top_device_info__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 top_device_info_chain_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 top_device_info_chain_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_engine_enum_v(u32 r) -{ - return (r >> 26U) & 0xfU; -} -static inline u32 top_device_info_runlist_enum_v(u32 r) -{ - return (r >> 21U) & 0xfU; -} -static inline u32 top_device_info_intr_enum_v(u32 r) -{ - return (r >> 15U) & 0x1fU; -} -static inline u32 top_device_info_reset_enum_v(u32 r) -{ - return (r >> 9U) & 0x1fU; -} -static inline u32 top_device_info_type_enum_v(u32 r) -{ - return (r >> 2U) & 0x1fffffffU; -} -static inline u32 top_device_info_type_enum_graphics_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_type_enum_graphics_f(void) -{ - return 0x0U; -} -static inline u32 top_device_info_type_enum_copy0_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_type_enum_copy0_f(void) -{ - return 0x4U; -} -static inline u32 top_device_info_type_enum_copy1_v(void) -{ - return 0x00000002U; -} -static inline u32 top_device_info_type_enum_copy1_f(void) -{ - return 0x8U; -} -static inline u32 top_device_info_type_enum_copy2_v(void) -{ - return 0x00000003U; -} -static inline u32 top_device_info_type_enum_copy2_f(void) -{ - return 0xcU; -} -static inline u32 top_device_info_engine_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 top_device_info_runlist_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 top_device_info_intr_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 top_device_info_reset_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 top_device_info_entry_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 top_device_info_entry_not_valid_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_entry_enum_v(void) -{ - return 0x00000002U; -} -static inline u32 top_device_info_entry_engine_type_v(void) -{ - return 0x00000003U; -} -static inline u32 top_device_info_entry_data_v(void) -{ - return 0x00000001U; -} -static inline u32 top_fs_status_fbp_r(void) -{ - return 0x00022548U; -} -static inline u32 top_fs_status_fbp_cluster_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 top_fs_status_fbp_cluster_enable_v(void) -{ - return 0x00000000U; -} -static inline u32 top_fs_status_fbp_cluster_enable_f(void) -{ - return 0x0U; -} -static inline u32 top_fs_status_fbp_cluster_disable_v(void) -{ - return 0x00000001U; -} -static inline u32 top_fs_status_fbp_cluster_disable_f(void) -{ - return 0x1U; -} -#endif diff --git a/include/nvgpu/hw/gk20a/hw_trim_gk20a.h b/include/nvgpu/hw/gk20a/hw_trim_gk20a.h deleted file mode 100644 index f28c21f..0000000 --- a/include/nvgpu/hw/gk20a/hw_trim_gk20a.h +++ /dev/null @@ -1,315 +0,0 @@ -/* - * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_trim_gk20a_h_ -#define _hw_trim_gk20a_h_ - -static inline u32 trim_sys_gpcpll_cfg_r(void) -{ - return 0x00137000U; -} -static inline u32 trim_sys_gpcpll_cfg_enable_m(void) -{ - return 0x1U << 0U; -} -static inline u32 trim_sys_gpcpll_cfg_enable_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 trim_sys_gpcpll_cfg_enable_no_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_gpcpll_cfg_enable_yes_f(void) -{ - return 0x1U; -} -static inline u32 trim_sys_gpcpll_cfg_iddq_m(void) -{ - return 0x1U << 1U; -} -static inline u32 trim_sys_gpcpll_cfg_iddq_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 trim_sys_gpcpll_cfg_iddq_power_on_v(void) -{ - return 0x00000000U; -} -static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_m(void) -{ - return 0x1U << 4U; -} -static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_on_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_off_f(void) -{ - return 0x10U; -} -static inline u32 trim_sys_gpcpll_cfg_pll_lock_v(u32 r) -{ - return (r >> 17U) & 0x1U; -} -static inline u32 trim_sys_gpcpll_cfg_pll_lock_true_f(void) -{ - return 0x20000U; -} -static inline u32 trim_sys_gpcpll_coeff_r(void) -{ - return 0x00137004U; -} -static inline u32 trim_sys_gpcpll_coeff_mdiv_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 trim_sys_gpcpll_coeff_mdiv_m(void) -{ - return 0xffU << 0U; -} -static inline u32 trim_sys_gpcpll_coeff_mdiv_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 trim_sys_gpcpll_coeff_ndiv_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 trim_sys_gpcpll_coeff_ndiv_m(void) -{ - return 0xffU << 8U; -} -static inline u32 trim_sys_gpcpll_coeff_ndiv_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} -static inline u32 trim_sys_gpcpll_coeff_pldiv_f(u32 v) -{ - return (v & 0x3fU) << 16U; -} -static inline u32 trim_sys_gpcpll_coeff_pldiv_m(void) -{ - return 0x3fU << 16U; -} -static inline u32 trim_sys_gpcpll_coeff_pldiv_v(u32 r) -{ - return (r >> 16U) & 0x3fU; -} -static inline u32 trim_sys_sel_vco_r(void) -{ - return 0x00137100U; -} -static inline u32 trim_sys_sel_vco_gpc2clk_out_m(void) -{ - return 0x1U << 0U; -} -static inline u32 trim_sys_sel_vco_gpc2clk_out_init_v(void) -{ - return 0x00000000U; -} -static inline u32 trim_sys_sel_vco_gpc2clk_out_init_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_sel_vco_gpc2clk_out_bypass_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_sel_vco_gpc2clk_out_vco_f(void) -{ - return 0x1U; -} -static inline u32 trim_sys_gpc2clk_out_r(void) -{ - return 0x00137250U; -} -static inline u32 trim_sys_gpc2clk_out_bypdiv_s(void) -{ - return 6U; -} -static inline u32 trim_sys_gpc2clk_out_bypdiv_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 trim_sys_gpc2clk_out_bypdiv_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 trim_sys_gpc2clk_out_bypdiv_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 trim_sys_gpc2clk_out_bypdiv_by31_f(void) -{ - return 0x3cU; -} -static inline u32 trim_sys_gpc2clk_out_vcodiv_s(void) -{ - return 6U; -} -static inline u32 trim_sys_gpc2clk_out_vcodiv_f(u32 v) -{ - return (v & 0x3fU) << 8U; -} -static inline u32 trim_sys_gpc2clk_out_vcodiv_m(void) -{ - return 0x3fU << 8U; -} -static inline u32 trim_sys_gpc2clk_out_vcodiv_v(u32 r) -{ - return (r >> 8U) & 0x3fU; -} -static inline u32 trim_sys_gpc2clk_out_vcodiv_by1_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_gpc2clk_out_sdiv14_m(void) -{ - return 0x1U << 31U; -} -static inline u32 trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f(void) -{ - return 0x80000000U; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_r(u32 i) -{ - return 0x00134124U + i*512U; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(u32 v) -{ - return (v & 0x3fffU) << 0U; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void) -{ - return 0x10000U; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f(void) -{ - return 0x100000U; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f(void) -{ - return 0x1000000U; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_r(u32 i) -{ - return 0x00134128U + i*512U; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(u32 r) -{ - return (r >> 0U) & 0xfffffU; -} -static inline u32 trim_sys_gpcpll_cfg2_r(void) -{ - return 0x0013700cU; -} -static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_m(void) -{ - return 0xffU << 24U; -} -static inline u32 trim_sys_gpcpll_cfg3_r(void) -{ - return 0x00137018U; -} -static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_m(void) -{ - return 0xffU << 16U; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_r(void) -{ - return 0x0013701cU; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m(void) -{ - return 0x1U << 22U; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_yes_f(void) -{ - return 0x400000U; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_no_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(void) -{ - return 0x1U << 31U; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f(void) -{ - return 0x80000000U; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_no_f(void) -{ - return 0x0U; -} -static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r(void) -{ - return 0x001328a0U; -} -static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_synced_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -#endif diff --git a/include/nvgpu/hw/gm20b/hw_bus_gm20b.h b/include/nvgpu/hw/gm20b/hw_bus_gm20b.h deleted file mode 100644 index 15cddae..0000000 --- a/include/nvgpu/hw/gm20b/hw_bus_gm20b.h +++ /dev/null @@ -1,223 +0,0 @@ -/* - * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_bus_gm20b_h_ -#define _hw_bus_gm20b_h_ - -static inline u32 bus_bar0_window_r(void) -{ - return 0x00001700U; -} -static inline u32 bus_bar0_window_base_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 bus_bar0_window_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) -{ - return 0x2000000U; -} -static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) -{ - return 0x3000000U; -} -static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) -{ - return 0x00000010U; -} -static inline u32 bus_bar1_block_r(void) -{ - return 0x00001704U; -} -static inline u32 bus_bar1_block_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 bus_bar1_block_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar1_block_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 bus_bar1_block_mode_virtual_f(void) -{ - return 0x80000000U; -} -static inline u32 bus_bar2_block_r(void) -{ - return 0x00001714U; -} -static inline u32 bus_bar2_block_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 bus_bar2_block_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar2_block_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 bus_bar2_block_mode_virtual_f(void) -{ - return 0x80000000U; -} -static inline u32 bus_bar1_block_ptr_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 bus_bar2_block_ptr_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 bus_bind_status_r(void) -{ - return 0x00001710U; -} -static inline u32 bus_bind_status_bar1_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 bus_bind_status_bar1_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar1_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 bus_bind_status_bar1_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 bus_bind_status_bar1_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar1_outstanding_true_f(void) -{ - return 0x2U; -} -static inline u32 bus_bind_status_bar2_pending_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 bus_bind_status_bar2_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar2_pending_busy_f(void) -{ - return 0x4U; -} -static inline u32 bus_bind_status_bar2_outstanding_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 bus_bind_status_bar2_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar2_outstanding_true_f(void) -{ - return 0x8U; -} -static inline u32 bus_intr_0_r(void) -{ - return 0x00001100U; -} -static inline u32 bus_intr_0_pri_squash_m(void) -{ - return 0x1U << 1U; -} -static inline u32 bus_intr_0_pri_fecserr_m(void) -{ - return 0x1U << 2U; -} -static inline u32 bus_intr_0_pri_timeout_m(void) -{ - return 0x1U << 3U; -} -static inline u32 bus_intr_en_0_r(void) -{ - return 0x00001140U; -} -static inline u32 bus_intr_en_0_pri_squash_m(void) -{ - return 0x1U << 1U; -} -static inline u32 bus_intr_en_0_pri_fecserr_m(void) -{ - return 0x1U << 2U; -} -static inline u32 bus_intr_en_0_pri_timeout_m(void) -{ - return 0x1U << 3U; -} -#endif diff --git a/include/nvgpu/hw/gm20b/hw_ccsr_gm20b.h b/include/nvgpu/hw/gm20b/hw_ccsr_gm20b.h deleted file mode 100644 index adfce72..0000000 --- a/include/nvgpu/hw/gm20b/hw_ccsr_gm20b.h +++ /dev/null @@ -1,163 +0,0 @@ -/* - * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ccsr_gm20b_h_ -#define _hw_ccsr_gm20b_h_ - -static inline u32 ccsr_channel_inst_r(u32 i) -{ - return 0x00800000U + i*8U; -} -static inline u32 ccsr_channel_inst__size_1_v(void) -{ - return 0x00000200U; -} -static inline u32 ccsr_channel_inst_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 ccsr_channel_inst_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 ccsr_channel_inst_bind_false_f(void) -{ - return 0x0U; -} -static inline u32 ccsr_channel_inst_bind_true_f(void) -{ - return 0x80000000U; -} -static inline u32 ccsr_channel_r(u32 i) -{ - return 0x00800004U + i*8U; -} -static inline u32 ccsr_channel__size_1_v(void) -{ - return 0x00000200U; -} -static inline u32 ccsr_channel_enable_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ccsr_channel_enable_set_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 ccsr_channel_enable_set_true_f(void) -{ - return 0x400U; -} -static inline u32 ccsr_channel_enable_clr_true_f(void) -{ - return 0x800U; -} -static inline u32 ccsr_channel_status_v(u32 r) -{ - return (r >> 24U) & 0xfU; -} -static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) -{ - return 0x00000002U; -} -static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) -{ - return 0x00000004U; -} -static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) -{ - return 0x0000000aU; -} -static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) -{ - return 0x0000000bU; -} -static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) -{ - return 0x0000000cU; -} -static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) -{ - return 0x0000000dU; -} -static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) -{ - return 0x0000000eU; -} -static inline u32 ccsr_channel_next_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ccsr_channel_next_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_force_ctx_reload_true_f(void) -{ - return 0x100U; -} -static inline u32 ccsr_channel_busy_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -#endif diff --git a/include/nvgpu/hw/gm20b/hw_ce2_gm20b.h b/include/nvgpu/hw/gm20b/hw_ce2_gm20b.h deleted file mode 100644 index fb741a7..0000000 --- a/include/nvgpu/hw/gm20b/hw_ce2_gm20b.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ce2_gm20b_h_ -#define _hw_ce2_gm20b_h_ - -static inline u32 ce2_intr_status_r(void) -{ - return 0x00106908U; -} -static inline u32 ce2_intr_status_blockpipe_pending_f(void) -{ - return 0x1U; -} -static inline u32 ce2_intr_status_blockpipe_reset_f(void) -{ - return 0x1U; -} -static inline u32 ce2_intr_status_nonblockpipe_pending_f(void) -{ - return 0x2U; -} -static inline u32 ce2_intr_status_nonblockpipe_reset_f(void) -{ - return 0x2U; -} -static inline u32 ce2_intr_status_launcherr_pending_f(void) -{ - return 0x4U; -} -static inline u32 ce2_intr_status_launcherr_reset_f(void) -{ - return 0x4U; -} -#endif diff --git a/include/nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h b/include/nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h deleted file mode 100644 index 6b5632a..0000000 --- a/include/nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h +++ /dev/null @@ -1,475 +0,0 @@ -/* - * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ctxsw_prog_gm20b_h_ -#define _hw_ctxsw_prog_gm20b_h_ - -static inline u32 ctxsw_prog_fecs_header_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) -{ - return 0x00000008U; -} -static inline u32 ctxsw_prog_main_image_ctl_o(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_main_image_ctl_cde_enabled_f(void) -{ - return 0x400U; -} -static inline u32 ctxsw_prog_main_image_ctl_cde_disabled_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_patch_count_o(void) -{ - return 0x00000010U; -} -static inline u32 ctxsw_prog_main_image_context_id_o(void) -{ - return 0x000000f0U; -} -static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) -{ - return 0x00000014U; -} -static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) -{ - return 0x00000018U; -} -static inline u32 ctxsw_prog_main_image_zcull_o(void) -{ - return 0x0000001cU; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) -{ - return 0x00000001U; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) -{ - return 0x00000020U; -} -static inline u32 ctxsw_prog_main_image_pm_o(void) -{ - return 0x00000028U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_m(void) -{ - return 0x7U << 0U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_ctxsw_f(void) -{ - return 0x1U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) -{ - return 0x7U << 3U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) -{ - return 0x8U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_pm_pc_sampling_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 ctxsw_prog_main_image_pm_pc_sampling_m(void) -{ - return 0x1U << 6U; -} -static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) -{ - return 0x0000002cU; -} -static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) -{ - return 0x000000f4U; -} -static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) -{ - return 0x000000f8U; -} -static inline u32 ctxsw_prog_main_image_magic_value_o(void) -{ - return 0x000000fcU; -} -static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) -{ - return 0x600dc0deU; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_ppc_info_o(void) -{ - return 0x000000f4U; -} -static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) -{ - return 0x000000f8U; -} -static inline u32 ctxsw_prog_local_magic_value_o(void) -{ - return 0x000000fcU; -} -static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) -{ - return 0xad0becabU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) -{ - return 0x000000ecU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) -{ - return 0x00000000U; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) -{ - return 0x000000a0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) -{ - return 2U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) -{ - return 0x3U << 0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) -{ - return 0x2U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) -{ - return 0x000000a4U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) -{ - return 0x000000a8U; -} -static inline u32 ctxsw_prog_main_image_misc_options_o(void) -{ - return 0x0000003cU; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) -{ - return 0x1U << 3U; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_o(void) -{ - return 0x000000acU; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(void) -{ - return 0x000000b0U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m(void) -{ - return 0xfffffffU << 0U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_m(void) -{ - return 0x3U << 28U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_coherent_f(void) -{ - return 0x20000000U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_noncoherent_f(void) -{ - return 0x30000000U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(void) -{ - return 0x000000b4U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_record_timestamp_record_size_in_bytes_v(void) -{ - return 0x00000080U; -} -static inline u32 ctxsw_prog_record_timestamp_record_size_in_words_v(void) -{ - return 0x00000020U; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_o(void) -{ - return 0x00000000U; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_v_value_v(void) -{ - return 0x00000000U; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_o(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_v_value_v(void) -{ - return 0x600dbeefU; -} -static inline u32 ctxsw_prog_record_timestamp_context_id_o(void) -{ - return 0x00000008U; -} -static inline u32 ctxsw_prog_record_timestamp_context_ptr_o(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_record_timestamp_new_context_id_o(void) -{ - return 0x00000010U; -} -static inline u32 ctxsw_prog_record_timestamp_new_context_ptr_o(void) -{ - return 0x00000014U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_lo_o(void) -{ - return 0x00000018U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_o(void) -{ - return 0x0000001cU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_m(void) -{ - return 0xffU << 24U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_v(u32 r) -{ - return (r >> 24U) & 0xffU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v(void) -{ - return 0x00000001U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_f(void) -{ - return 0x1000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_f(void) -{ - return 0x2000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_v(void) -{ - return 0x0000000aU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_f(void) -{ - return 0xa000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_v(void) -{ - return 0x0000000bU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_f(void) -{ - return 0xb000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_v(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_f(void) -{ - return 0xc000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_v(void) -{ - return 0x0000000dU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_f(void) -{ - return 0xd000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_v(void) -{ - return 0x00000003U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_f(void) -{ - return 0x3000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_v(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_f(void) -{ - return 0x4000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_v(void) -{ - return 0x00000005U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_f(void) -{ - return 0x5000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v(void) -{ - return 0x000000ffU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f(void) -{ - return 0xff000000U; -} -static inline u32 ctxsw_prog_main_image_preemption_options_o(void) -{ - return 0x00000060U; -} -static inline u32 ctxsw_prog_main_image_preemption_options_control_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_preemption_options_control_cta_enabled_f(void) -{ - return 0x1U; -} -#endif diff --git a/include/nvgpu/hw/gm20b/hw_falcon_gm20b.h b/include/nvgpu/hw/gm20b/hw_falcon_gm20b.h deleted file mode 100644 index c598568..0000000 --- a/include/nvgpu/hw/gm20b/hw_falcon_gm20b.h +++ /dev/null @@ -1,599 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_falcon_gm20b_h_ -#define _hw_falcon_gm20b_h_ - -static inline u32 falcon_falcon_irqsset_r(void) -{ - return 0x00000000U; -} -static inline u32 falcon_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 falcon_falcon_irqsclr_r(void) -{ - return 0x00000004U; -} -static inline u32 falcon_falcon_irqstat_r(void) -{ - return 0x00000008U; -} -static inline u32 falcon_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 falcon_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 falcon_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 falcon_falcon_irqmode_r(void) -{ - return 0x0000000cU; -} -static inline u32 falcon_falcon_irqmset_r(void) -{ - return 0x00000010U; -} -static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqmclr_r(void) -{ - return 0x00000014U; -} -static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_irqmask_r(void) -{ - return 0x00000018U; -} -static inline u32 falcon_falcon_irqdest_r(void) -{ - return 0x0000001cU; -} -static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 falcon_falcon_curctx_r(void) -{ - return 0x00000050U; -} -static inline u32 falcon_falcon_nxtctx_r(void) -{ - return 0x00000054U; -} -static inline u32 falcon_falcon_mailbox0_r(void) -{ - return 0x00000040U; -} -static inline u32 falcon_falcon_mailbox1_r(void) -{ - return 0x00000044U; -} -static inline u32 falcon_falcon_itfen_r(void) -{ - return 0x00000048U; -} -static inline u32 falcon_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 falcon_falcon_idlestate_r(void) -{ - return 0x0000004cU; -} -static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 falcon_falcon_os_r(void) -{ - return 0x00000080U; -} -static inline u32 falcon_falcon_engctl_r(void) -{ - return 0x000000a4U; -} -static inline u32 falcon_falcon_cpuctl_r(void) -{ - return 0x00000100U; -} -static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_m(void) -{ - return 0x1U << 4U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 falcon_falcon_cpuctl_stopped_m(void) -{ - return 0x1U << 5U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void) -{ - return 0x1U << 6U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 falcon_falcon_cpuctl_alias_r(void) -{ - return 0x00000130U; -} -static inline u32 falcon_falcon_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_imemc_r(u32 i) -{ - return 0x00000180U + i*16U; -} -static inline u32 falcon_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 falcon_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 falcon_falcon_imemc_secure_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 falcon_falcon_imemd_r(u32 i) -{ - return 0x00000184U + i*16U; -} -static inline u32 falcon_falcon_imemt_r(u32 i) -{ - return 0x00000188U + i*16U; -} -static inline u32 falcon_falcon_sctl_r(void) -{ - return 0x00000240U; -} -static inline u32 falcon_falcon_mmu_phys_sec_r(void) -{ - return 0x00100ce4U; -} -static inline u32 falcon_falcon_bootvec_r(void) -{ - return 0x00000104U; -} -static inline u32 falcon_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 falcon_falcon_dmactl_r(void) -{ - return 0x0000010cU; -} -static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void) -{ - return 0x1U << 1U; -} -static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void) -{ - return 0x1U << 2U; -} -static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_hwcfg_r(void) -{ - return 0x00000108U; -} -static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 falcon_falcon_dmatrfbase_r(void) -{ - return 0x00000110U; -} -static inline u32 falcon_falcon_dmatrfmoffs_r(void) -{ - return 0x00000114U; -} -static inline u32 falcon_falcon_dmatrfcmd_r(void) -{ - return 0x00000118U; -} -static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 falcon_falcon_dmatrffboffs_r(void) -{ - return 0x0000011cU; -} -static inline u32 falcon_falcon_imctl_debug_r(void) -{ - return 0x0000015cU; -} -static inline u32 falcon_falcon_imctl_debug_addr_blk_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 falcon_falcon_imctl_debug_cmd_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 falcon_falcon_imstat_r(void) -{ - return 0x00000144U; -} -static inline u32 falcon_falcon_traceidx_r(void) -{ - return 0x00000148U; -} -static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 falcon_falcon_traceidx_idx_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 falcon_falcon_tracepc_r(void) -{ - return 0x0000014cU; -} -static inline u32 falcon_falcon_tracepc_pc_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 falcon_falcon_exterraddr_r(void) -{ - return 0x00000168U; -} -static inline u32 falcon_falcon_exterrstat_r(void) -{ - return 0x0000016cU; -} -static inline u32 falcon_falcon_exterrstat_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 falcon_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 falcon_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 falcon_falcon_icd_cmd_r(void) -{ - return 0x00000200U; -} -static inline u32 falcon_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 falcon_falcon_icd_cmd_opc_m(void) -{ - return 0xfU << 0U; -} -static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 falcon_falcon_icd_rdata_r(void) -{ - return 0x0000020cU; -} -static inline u32 falcon_falcon_dmemc_r(u32 i) -{ - return 0x000001c0U + i*8U; -} -static inline u32 falcon_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 falcon_falcon_dmemc_offs_m(void) -{ - return 0x3fU << 2U; -} -static inline u32 falcon_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_dmemc_blk_m(void) -{ - return 0xffU << 8U; -} -static inline u32 falcon_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 falcon_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 falcon_falcon_dmemd_r(u32 i) -{ - return 0x000001c4U + i*8U; -} -static inline u32 falcon_falcon_debug1_r(void) -{ - return 0x00000090U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void) -{ - return 1U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void) -{ - return 0x1U << 16U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void) -{ - return 0x0U; -} -static inline u32 falcon_falcon_debuginfo_r(void) -{ - return 0x00000094U; -} -#endif diff --git a/include/nvgpu/hw/gm20b/hw_fb_gm20b.h b/include/nvgpu/hw/gm20b/hw_fb_gm20b.h deleted file mode 100644 index e6464c1..0000000 --- a/include/nvgpu/hw/gm20b/hw_fb_gm20b.h +++ /dev/null @@ -1,339 +0,0 @@ -/* - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_fb_gm20b_h_ -#define _hw_fb_gm20b_h_ - -static inline u32 fb_fbhub_num_active_ltcs_r(void) -{ - return 0x00100800U; -} -static inline u32 fb_mmu_ctrl_r(void) -{ - return 0x00100c80U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r) -{ - return (r >> 11U) & 0x1U; -} -static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void) -{ - return 0x800U; -} -static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_ctrl_use_full_comp_tag_line_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 fb_mmu_ctrl_use_full_comp_tag_line_true_f(void) -{ - return 0x1000U; -} -static inline u32 fb_priv_mmu_phy_secure_r(void) -{ - return 0x00100ce4U; -} -static inline u32 fb_mmu_invalidate_pdb_r(void) -{ - return 0x00100cb8U; -} -static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_invalidate_r(void) -{ - return 0x00100cbcU; -} -static inline u32 fb_mmu_invalidate_all_va_true_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_invalidate_trigger_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_trigger_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_invalidate_trigger_m(void) -{ - return 0x1U << 31U; -} -static inline u32 fb_mmu_invalidate_trigger_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_trigger_true_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_debug_wr_r(void) -{ - return 0x00100cc8U; -} -static inline u32 fb_mmu_debug_wr_aperture_s(void) -{ - return 2U; -} -static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 fb_mmu_debug_wr_aperture_m(void) -{ - return 0x3U << 0U; -} -static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_debug_wr_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_wr_vol_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_debug_wr_vol_true_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_debug_wr_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) -{ - return 0x0000000cU; -} -static inline u32 fb_mmu_debug_rd_r(void) -{ - return 0x00100cccU; -} -static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_debug_rd_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_rd_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) -{ - return 0x0000000cU; -} -static inline u32 fb_mmu_debug_ctrl_r(void) -{ - return 0x00100cc4U; -} -static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 fb_mmu_debug_ctrl_debug_m(void) -{ - return 0x1U << 16U; -} -static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_debug_ctrl_debug_enabled_f(void) -{ - return 0x10000U; -} -static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_debug_ctrl_debug_disabled_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_vpr_info_r(void) -{ - return 0x00100cd0U; -} -static inline u32 fb_mmu_vpr_info_index_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 fb_mmu_vpr_info_index_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 fb_mmu_vpr_info_index_addr_lo_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_vpr_info_index_addr_hi_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_vpr_info_index_cya_lo_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_vpr_info_index_cya_hi_v(void) -{ - return 0x00000003U; -} -static inline u32 fb_mmu_vpr_info_fetch_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 fb_mmu_vpr_info_fetch_false_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_vpr_info_fetch_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_wpr_info_r(void) -{ - return 0x00100cd4U; -} -static inline u32 fb_mmu_wpr_info_index_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 fb_mmu_wpr_info_index_allow_read_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_wpr_info_index_allow_write_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_wpr_info_index_wpr1_addr_lo_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_wpr_info_index_wpr1_addr_hi_v(void) -{ - return 0x00000003U; -} -static inline u32 fb_mmu_wpr_info_index_wpr2_addr_lo_v(void) -{ - return 0x00000004U; -} -static inline u32 fb_mmu_wpr_info_index_wpr2_addr_hi_v(void) -{ - return 0x00000005U; -} -static inline u32 fb_niso_flush_sysmem_addr_r(void) -{ - return 0x00100c10U; -} -#endif diff --git a/include/nvgpu/hw/gm20b/hw_fifo_gm20b.h b/include/nvgpu/hw/gm20b/hw_fifo_gm20b.h deleted file mode 100644 index d32506d..0000000 --- a/include/nvgpu/hw/gm20b/hw_fifo_gm20b.h +++ /dev/null @@ -1,571 +0,0 @@ -/* - * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_fifo_gm20b_h_ -#define _hw_fifo_gm20b_h_ - -static inline u32 fifo_bar1_base_r(void) -{ - return 0x00002254U; -} -static inline u32 fifo_bar1_base_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 fifo_bar1_base_ptr_align_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 fifo_bar1_base_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 fifo_bar1_base_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 fifo_runlist_base_r(void) -{ - return 0x00002270U; -} -static inline u32 fifo_runlist_base_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 fifo_runlist_base_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 fifo_runlist_r(void) -{ - return 0x00002274U; -} -static inline u32 fifo_runlist_engine_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 fifo_eng_runlist_base_r(u32 i) -{ - return 0x00002280U + i*8U; -} -static inline u32 fifo_eng_runlist_base__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_eng_runlist_r(u32 i) -{ - return 0x00002284U + i*8U; -} -static inline u32 fifo_eng_runlist__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_eng_runlist_length_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fifo_eng_runlist_length_max_v(void) -{ - return 0x0000ffffU; -} -static inline u32 fifo_eng_runlist_pending_true_f(void) -{ - return 0x100000U; -} -static inline u32 fifo_pb_timeslice_r(u32 i) -{ - return 0x00002350U + i*4U; -} -static inline u32 fifo_pb_timeslice_timeout_16_f(void) -{ - return 0x10U; -} -static inline u32 fifo_pb_timeslice_timescale_0_f(void) -{ - return 0x0U; -} -static inline u32 fifo_pb_timeslice_enable_true_f(void) -{ - return 0x10000000U; -} -static inline u32 fifo_pbdma_map_r(u32 i) -{ - return 0x00002390U + i*4U; -} -static inline u32 fifo_intr_0_r(void) -{ - return 0x00002100U; -} -static inline u32 fifo_intr_0_bind_error_pending_f(void) -{ - return 0x1U; -} -static inline u32 fifo_intr_0_bind_error_reset_f(void) -{ - return 0x1U; -} -static inline u32 fifo_intr_0_sched_error_pending_f(void) -{ - return 0x100U; -} -static inline u32 fifo_intr_0_sched_error_reset_f(void) -{ - return 0x100U; -} -static inline u32 fifo_intr_0_chsw_error_pending_f(void) -{ - return 0x10000U; -} -static inline u32 fifo_intr_0_chsw_error_reset_f(void) -{ - return 0x10000U; -} -static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void) -{ - return 0x800000U; -} -static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void) -{ - return 0x800000U; -} -static inline u32 fifo_intr_0_lb_error_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_intr_0_lb_error_reset_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void) -{ - return 0x8000000U; -} -static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void) -{ - return 0x8000000U; -} -static inline u32 fifo_intr_0_mmu_fault_pending_f(void) -{ - return 0x10000000U; -} -static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 fifo_intr_0_runlist_event_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 fifo_intr_0_channel_intr_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 fifo_intr_en_0_r(void) -{ - return 0x00002140U; -} -static inline u32 fifo_intr_en_0_sched_error_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 fifo_intr_en_0_sched_error_m(void) -{ - return 0x1U << 8U; -} -static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 fifo_intr_en_0_mmu_fault_m(void) -{ - return 0x1U << 28U; -} -static inline u32 fifo_intr_en_1_r(void) -{ - return 0x00002528U; -} -static inline u32 fifo_intr_bind_error_r(void) -{ - return 0x0000252cU; -} -static inline u32 fifo_intr_sched_error_r(void) -{ - return 0x0000254cU; -} -static inline u32 fifo_intr_sched_error_code_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void) -{ - return 0x0000000aU; -} -static inline u32 fifo_intr_chsw_error_r(void) -{ - return 0x0000256cU; -} -static inline u32 fifo_intr_mmu_fault_id_r(void) -{ - return 0x0000259cU; -} -static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void) -{ - return 0x0U; -} -static inline u32 fifo_intr_mmu_fault_inst_r(u32 i) -{ - return 0x00002800U + i*16U; -} -static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 fifo_intr_mmu_fault_lo_r(u32 i) -{ - return 0x00002804U + i*16U; -} -static inline u32 fifo_intr_mmu_fault_hi_r(u32 i) -{ - return 0x00002808U + i*16U; -} -static inline u32 fifo_intr_mmu_fault_info_r(u32 i) -{ - return 0x0000280cU + i*16U; -} -static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 fifo_intr_mmu_fault_info_write_v(u32 r) -{ - return (r >> 7U) & 0x1U; -} -static inline u32 fifo_intr_mmu_fault_info_engine_subid_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 fifo_intr_mmu_fault_info_engine_subid_gpc_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_intr_mmu_fault_info_engine_subid_hub_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r) -{ - return (r >> 8U) & 0x3fU; -} -static inline u32 fifo_intr_pbdma_id_r(void) -{ - return 0x000025a0U; -} -static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) -{ - return (r >> (0U + i*1U)) & 0x1U; -} -static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_intr_runlist_r(void) -{ - return 0x00002a00U; -} -static inline u32 fifo_fb_timeout_r(void) -{ - return 0x00002a04U; -} -static inline u32 fifo_fb_timeout_period_m(void) -{ - return 0x3fffffffU << 0U; -} -static inline u32 fifo_fb_timeout_period_max_f(void) -{ - return 0x3fffffffU; -} -static inline u32 fifo_error_sched_disable_r(void) -{ - return 0x0000262cU; -} -static inline u32 fifo_sched_disable_r(void) -{ - return 0x00002630U; -} -static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_sched_disable_runlist_m(u32 i) -{ - return 0x1U << (0U + i*1U); -} -static inline u32 fifo_sched_disable_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_preempt_r(void) -{ - return 0x00002634U; -} -static inline u32 fifo_preempt_pending_true_f(void) -{ - return 0x100000U; -} -static inline u32 fifo_preempt_type_channel_f(void) -{ - return 0x0U; -} -static inline u32 fifo_preempt_type_tsg_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_preempt_chid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 fifo_preempt_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 fifo_trigger_mmu_fault_r(u32 i) -{ - return 0x00002a30U + i*4U; -} -static inline u32 fifo_trigger_mmu_fault_id_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 fifo_engine_status_r(u32 i) -{ - return 0x00002640U + i*8U; -} -static inline u32 fifo_engine_status__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fifo_engine_status_id_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 fifo_engine_status_id_type_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 fifo_engine_status_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctx_status_v(u32 r) -{ - return (r >> 13U) & 0x7U; -} -static inline u32 fifo_engine_status_ctx_status_invalid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_ctx_status_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void) -{ - return 0x00000005U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void) -{ - return 0x00000006U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void) -{ - return 0x00000007U; -} -static inline u32 fifo_engine_status_next_id_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 fifo_engine_status_next_id_type_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 fifo_engine_status_next_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_faulted_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fifo_engine_status_faulted_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_engine_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fifo_engine_status_engine_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_engine_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctxsw_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fifo_engine_status_ctxsw_in_progress_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) -{ - return 0x8000U; -} -static inline u32 fifo_pbdma_status_r(u32 i) -{ - return 0x00003080U + i*4U; -} -static inline u32 fifo_pbdma_status__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_id_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 fifo_pbdma_status_id_type_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 fifo_pbdma_status_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chan_status_v(u32 r) -{ - return (r >> 13U) & 0x7U; -} -static inline u32 fifo_pbdma_status_chan_status_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void) -{ - return 0x00000005U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void) -{ - return 0x00000006U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void) -{ - return 0x00000007U; -} -static inline u32 fifo_pbdma_status_next_id_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 fifo_pbdma_status_next_id_type_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 fifo_pbdma_status_next_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_pbdma_status_chsw_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) -{ - return 0x00000001U; -} -#endif diff --git a/include/nvgpu/hw/gm20b/hw_flush_gm20b.h b/include/nvgpu/hw/gm20b/hw_flush_gm20b.h deleted file mode 100644 index 3b5801b..0000000 --- a/include/nvgpu/hw/gm20b/hw_flush_gm20b.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_flush_gm20b_h_ -#define _hw_flush_gm20b_h_ - -static inline u32 flush_l2_system_invalidate_r(void) -{ - return 0x00070004U; -} -static inline u32 flush_l2_system_invalidate_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_system_invalidate_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_system_invalidate_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_system_invalidate_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_flush_dirty_r(void) -{ - return 0x00070010U; -} -static inline u32 flush_l2_flush_dirty_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_flush_dirty_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_flush_dirty_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_flush_dirty_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_flush_dirty_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_flush_dirty_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_flush_dirty_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_clean_comptags_r(void) -{ - return 0x0007000cU; -} -static inline u32 flush_l2_clean_comptags_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_clean_comptags_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_clean_comptags_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_clean_comptags_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_clean_comptags_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_clean_comptags_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_clean_comptags_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_clean_comptags_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_fb_flush_r(void) -{ - return 0x00070000U; -} -static inline u32 flush_fb_flush_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_fb_flush_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_fb_flush_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_fb_flush_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_fb_flush_outstanding_true_v(void) -{ - return 0x00000001U; -} -#endif diff --git a/include/nvgpu/hw/gm20b/hw_fuse_gm20b.h b/include/nvgpu/hw/gm20b/hw_fuse_gm20b.h deleted file mode 100644 index d97eb7d..0000000 --- a/include/nvgpu/hw/gm20b/hw_fuse_gm20b.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_fuse_gm20b_h_ -#define _hw_fuse_gm20b_h_ - -static inline u32 fuse_status_opt_gpc_r(void) -{ - return 0x00021c1cU; -} -static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) -{ - return 0x00021c38U + i*4U; -} -static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i) -{ - return 0x00021838U + i*4U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void) -{ - return 0x00021944U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void) -{ - return 0x3U << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void) -{ - return 0x00021948U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void) -{ - return 0x1U << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void) -{ - return 0x1U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void) -{ - return 0x0U; -} -static inline u32 fuse_status_opt_fbio_r(void) -{ - return 0x00021c14U; -} -static inline u32 fuse_status_opt_fbio_data_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fuse_status_opt_fbio_data_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 fuse_status_opt_fbio_data_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i) -{ - return 0x00021d70U + i*4U; -} -static inline u32 fuse_status_opt_fbp_r(void) -{ - return 0x00021d38U; -} -static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) -{ - return (r >> (0U + i*1U)) & 0x1U; -} -static inline u32 fuse_opt_sec_debug_en_r(void) -{ - return 0x00021218U; -} -static inline u32 fuse_opt_priv_sec_en_r(void) -{ - return 0x00021434U; -} -#endif diff --git a/include/nvgpu/hw/gm20b/hw_gmmu_gm20b.h b/include/nvgpu/hw/gm20b/hw_gmmu_gm20b.h deleted file mode 100644 index 11cc3d7..0000000 --- a/include/nvgpu/hw/gm20b/hw_gmmu_gm20b.h +++ /dev/null @@ -1,283 +0,0 @@ -/* - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_gmmu_gm20b_h_ -#define _hw_gmmu_gm20b_h_ - -static inline u32 gmmu_pde_aperture_big_w(void) -{ - return 0U; -} -static inline u32 gmmu_pde_aperture_big_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pde_aperture_big_video_memory_f(void) -{ - return 0x1U; -} -static inline u32 gmmu_pde_aperture_big_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_pde_aperture_big_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 gmmu_pde_size_w(void) -{ - return 0U; -} -static inline u32 gmmu_pde_size_full_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pde_address_big_sys_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 gmmu_pde_address_big_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_pde_aperture_small_w(void) -{ - return 1U; -} -static inline u32 gmmu_pde_aperture_small_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pde_aperture_small_video_memory_f(void) -{ - return 0x1U; -} -static inline u32 gmmu_pde_aperture_small_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_pde_aperture_small_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 gmmu_pde_vol_small_w(void) -{ - return 1U; -} -static inline u32 gmmu_pde_vol_small_true_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_pde_vol_small_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pde_vol_big_w(void) -{ - return 1U; -} -static inline u32 gmmu_pde_vol_big_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_pde_vol_big_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pde_address_small_sys_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 gmmu_pde_address_small_sys_w(void) -{ - return 1U; -} -static inline u32 gmmu_pde_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_pde__size_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_pte__size_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_pte_valid_w(void) -{ - return 0U; -} -static inline u32 gmmu_pte_valid_true_f(void) -{ - return 0x1U; -} -static inline u32 gmmu_pte_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pte_privilege_w(void) -{ - return 0U; -} -static inline u32 gmmu_pte_privilege_true_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_pte_privilege_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pte_address_sys_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 gmmu_pte_address_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_pte_address_vid_f(u32 v) -{ - return (v & 0x1ffffffU) << 4U; -} -static inline u32 gmmu_pte_address_vid_w(void) -{ - return 0U; -} -static inline u32 gmmu_pte_vol_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_vol_true_f(void) -{ - return 0x1U; -} -static inline u32 gmmu_pte_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pte_aperture_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_aperture_video_memory_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pte_aperture_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_pte_aperture_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_pte_read_only_w(void) -{ - return 0U; -} -static inline u32 gmmu_pte_read_only_true_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_pte_write_disable_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_write_disable_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gmmu_pte_read_disable_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_read_disable_true_f(void) -{ - return 0x40000000U; -} -static inline u32 gmmu_pte_comptagline_s(void) -{ - return 17U; -} -static inline u32 gmmu_pte_comptagline_f(u32 v) -{ - return (v & 0x1ffffU) << 12U; -} -static inline u32 gmmu_pte_comptagline_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_pte_kind_f(u32 v) -{ - return (v & 0xffU) << 4U; -} -static inline u32 gmmu_pte_kind_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_kind_invalid_v(void) -{ - return 0x000000ffU; -} -static inline u32 gmmu_pte_kind_pitch_v(void) -{ - return 0x00000000U; -} -#endif diff --git a/include/nvgpu/hw/gm20b/hw_gr_gm20b.h b/include/nvgpu/hw/gm20b/hw_gr_gm20b.h deleted file mode 100644 index 79ad326..0000000 --- a/include/nvgpu/hw/gm20b/hw_gr_gm20b.h +++ /dev/null @@ -1,3939 +0,0 @@ -/* - * Copyright (c) 2014-2023, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_gr_gm20b_h_ -#define _hw_gr_gm20b_h_ - -static inline u32 gr_intr_r(void) -{ - return 0x00400100U; -} -static inline u32 gr_intr_notify_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_intr_notify_reset_f(void) -{ - return 0x1U; -} -static inline u32 gr_intr_semaphore_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_semaphore_reset_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_illegal_method_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_intr_illegal_method_reset_f(void) -{ - return 0x10U; -} -static inline u32 gr_intr_illegal_notify_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_intr_illegal_notify_reset_f(void) -{ - return 0x40U; -} -static inline u32 gr_intr_firmware_method_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 gr_intr_firmware_method_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_intr_firmware_method_reset_f(void) -{ - return 0x100U; -} -static inline u32 gr_intr_illegal_class_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_intr_illegal_class_reset_f(void) -{ - return 0x20U; -} -static inline u32 gr_intr_fecs_error_pending_f(void) -{ - return 0x80000U; -} -static inline u32 gr_intr_fecs_error_reset_f(void) -{ - return 0x80000U; -} -static inline u32 gr_intr_class_error_pending_f(void) -{ - return 0x100000U; -} -static inline u32 gr_intr_class_error_reset_f(void) -{ - return 0x100000U; -} -static inline u32 gr_intr_exception_pending_f(void) -{ - return 0x200000U; -} -static inline u32 gr_intr_exception_reset_f(void) -{ - return 0x200000U; -} -static inline u32 gr_fecs_intr_r(void) -{ - return 0x00400144U; -} -static inline u32 gr_class_error_r(void) -{ - return 0x00400110U; -} -static inline u32 gr_class_error_code_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_intr_nonstall_r(void) -{ - return 0x00400120U; -} -static inline u32 gr_intr_nonstall_trap_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_en_r(void) -{ - return 0x0040013cU; -} -static inline u32 gr_exception_r(void) -{ - return 0x00400108U; -} -static inline u32 gr_exception_fe_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_exception_gpc_m(void) -{ - return 0x1U << 24U; -} -static inline u32 gr_exception_memfmt_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_exception_ds_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_exception_sked_m(void) -{ - return 0x1U << 8U; -} -static inline u32 gr_exception_pd_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_exception_scc_m(void) -{ - return 0x1U << 3U; -} -static inline u32 gr_exception_ssync_m(void) -{ - return 0x1U << 5U; -} -static inline u32 gr_exception_mme_m(void) -{ - return 0x1U << 7U; -} -static inline u32 gr_exception1_r(void) -{ - return 0x00400118U; -} -static inline u32 gr_exception1_gpc_0_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_exception2_r(void) -{ - return 0x0040011cU; -} -static inline u32 gr_exception_en_r(void) -{ - return 0x00400138U; -} -static inline u32 gr_exception_en_fe_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_exception1_en_r(void) -{ - return 0x00400130U; -} -static inline u32 gr_exception2_en_r(void) -{ - return 0x00400134U; -} -static inline u32 gr_gpfifo_ctl_r(void) -{ - return 0x00400500U; -} -static inline u32 gr_gpfifo_ctl_access_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpfifo_ctl_access_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpfifo_ctl_access_enabled_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void) -{ - return 0x10000U; -} -static inline u32 gr_gpfifo_status_r(void) -{ - return 0x00400504U; -} -static inline u32 gr_trapped_addr_r(void) -{ - return 0x00400704U; -} -static inline u32 gr_trapped_addr_mthd_v(u32 r) -{ - return (r >> 2U) & 0xfffU; -} -static inline u32 gr_trapped_addr_subch_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 gr_trapped_addr_mme_generated_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 gr_trapped_addr_datahigh_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 gr_trapped_addr_priv_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 gr_trapped_addr_status_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_trapped_data_lo_r(void) -{ - return 0x00400708U; -} -static inline u32 gr_trapped_data_hi_r(void) -{ - return 0x0040070cU; -} -static inline u32 gr_trapped_data_mme_r(void) -{ - return 0x00400710U; -} -static inline u32 gr_trapped_data_mme_pc_v(u32 r) -{ - return (r >> 0U) & 0x7ffU; -} -static inline u32 gr_status_r(void) -{ - return 0x00400700U; -} -static inline u32 gr_status_fe_method_upper_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_status_fe_method_lower_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_status_fe_method_lower_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_status_fe_gi_v(u32 r) -{ - return (r >> 21U) & 0x1U; -} -static inline u32 gr_status_mask_r(void) -{ - return 0x00400610U; -} -static inline u32 gr_status_1_r(void) -{ - return 0x00400604U; -} -static inline u32 gr_status_2_r(void) -{ - return 0x00400608U; -} -static inline u32 gr_engine_status_r(void) -{ - return 0x0040060cU; -} -static inline u32 gr_engine_status_value_busy_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_be0_becs_be_exception_r(void) -{ - return 0x00410204U; -} -static inline u32 gr_pri_be0_becs_be_exception_en_r(void) -{ - return 0x00410208U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void) -{ - return 0x00502c90U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void) -{ - return 0x00502c94U; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void) -{ - return 0x00504508U; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void) -{ - return 0x0050450cU; -} -static inline u32 gr_activity_0_r(void) -{ - return 0x00400380U; -} -static inline u32 gr_activity_1_r(void) -{ - return 0x00400384U; -} -static inline u32 gr_activity_2_r(void) -{ - return 0x00400388U; -} -static inline u32 gr_activity_4_r(void) -{ - return 0x00400390U; -} -static inline u32 gr_pri_gpc0_gcc_dbg_r(void) -{ - return 0x00501000U; -} -static inline u32 gr_pri_gpcs_gcc_dbg_r(void) -{ - return 0x00419000U; -} -static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) -{ - return 0x005046a4U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) -{ - return 0x00419ea4U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_pri_sked_activity_r(void) -{ - return 0x00407054U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void) -{ - return 0x00502c80U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void) -{ - return 0x00502c84U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void) -{ - return 0x00502c88U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void) -{ - return 0x00502c8cU; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void) -{ - return 0x00504500U; -} -static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void) -{ - return 0x00504d00U; -} -static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void) -{ - return 0x00501d00U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void) -{ - return 0x0041ac80U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void) -{ - return 0x0041ac84U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void) -{ - return 0x0041ac88U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void) -{ - return 0x0041ac8cU; -} -static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void) -{ - return 0x0041c500U; -} -static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void) -{ - return 0x0041cd00U; -} -static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void) -{ - return 0x00419d00U; -} -static inline u32 gr_pri_be0_becs_be_activity0_r(void) -{ - return 0x00410200U; -} -static inline u32 gr_pri_be1_becs_be_activity0_r(void) -{ - return 0x00410600U; -} -static inline u32 gr_pri_bes_becs_be_activity0_r(void) -{ - return 0x00408a00U; -} -static inline u32 gr_pri_ds_mpipe_status_r(void) -{ - return 0x00405858U; -} -static inline u32 gr_pri_fe_go_idle_on_status_r(void) -{ - return 0x00404150U; -} -static inline u32 gr_pri_fe_go_idle_check_r(void) -{ - return 0x00404158U; -} -static inline u32 gr_pri_fe_go_idle_info_r(void) -{ - return 0x00404194U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) -{ - return 0x00504238U; -} -static inline u32 gr_pri_be0_crop_status1_r(void) -{ - return 0x00410134U; -} -static inline u32 gr_pri_bes_crop_status1_r(void) -{ - return 0x00408934U; -} -static inline u32 gr_pri_be0_zrop_status_r(void) -{ - return 0x00410048U; -} -static inline u32 gr_pri_be0_zrop_status2_r(void) -{ - return 0x0041004cU; -} -static inline u32 gr_pri_bes_zrop_status_r(void) -{ - return 0x00408848U; -} -static inline u32 gr_pri_bes_zrop_status2_r(void) -{ - return 0x0040884cU; -} -static inline u32 gr_pipe_bundle_address_r(void) -{ - return 0x00400200U; -} -static inline u32 gr_pipe_bundle_address_value_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pipe_bundle_data_r(void) -{ - return 0x00400204U; -} -static inline u32 gr_pipe_bundle_config_r(void) -{ - return 0x00400208U; -} -static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fe_hww_esr_r(void) -{ - return 0x00404000U; -} -static inline u32 gr_fe_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_fe_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fe_hww_esr_info_r(void) -{ - return 0x004041b0U; -} -static inline u32 gr_fe_go_idle_timeout_r(void) -{ - return 0x00404154U; -} -static inline u32 gr_fe_go_idle_timeout_count_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) -{ - return 0x800U; -} -static inline u32 gr_fe_object_table_r(u32 i) -{ - return 0x00404200U + i*4U; -} -static inline u32 gr_fe_object_table_nvclass_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_fe_tpc_fs_r(void) -{ - return 0x004041c4U; -} -static inline u32 gr_pri_mme_shadow_raw_index_r(void) -{ - return 0x00404488U; -} -static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pri_mme_shadow_raw_data_r(void) -{ - return 0x0040448cU; -} -static inline u32 gr_mme_hww_esr_r(void) -{ - return 0x00404490U; -} -static inline u32 gr_mme_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_mme_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_mme_hww_esr_info_r(void) -{ - return 0x00404494U; -} -static inline u32 gr_memfmt_hww_esr_r(void) -{ - return 0x00404600U; -} -static inline u32 gr_memfmt_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_memfmt_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fecs_cpuctl_r(void) -{ - return 0x00409100U; -} -static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_cpuctl_alias_r(void) -{ - return 0x00409130U; -} -static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_dmactl_r(void) -{ - return 0x0040910cU; -} -static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_fecs_os_r(void) -{ - return 0x00409080U; -} -static inline u32 gr_fecs_idlestate_r(void) -{ - return 0x0040904cU; -} -static inline u32 gr_fecs_mailbox0_r(void) -{ - return 0x00409040U; -} -static inline u32 gr_fecs_mailbox1_r(void) -{ - return 0x00409044U; -} -static inline u32 gr_fecs_irqstat_r(void) -{ - return 0x00409008U; -} -static inline u32 gr_fecs_irqmode_r(void) -{ - return 0x0040900cU; -} -static inline u32 gr_fecs_irqmask_r(void) -{ - return 0x00409018U; -} -static inline u32 gr_fecs_irqdest_r(void) -{ - return 0x0040901cU; -} -static inline u32 gr_fecs_curctx_r(void) -{ - return 0x00409050U; -} -static inline u32 gr_fecs_nxtctx_r(void) -{ - return 0x00409054U; -} -static inline u32 gr_fecs_engctl_r(void) -{ - return 0x004090a4U; -} -static inline u32 gr_fecs_debug1_r(void) -{ - return 0x00409090U; -} -static inline u32 gr_fecs_debuginfo_r(void) -{ - return 0x00409094U; -} -static inline u32 gr_fecs_icd_cmd_r(void) -{ - return 0x00409200U; -} -static inline u32 gr_fecs_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 gr_fecs_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_fecs_icd_cmd_opc_m(void) -{ - return 0xfU << 0U; -} -static inline u32 gr_fecs_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 gr_fecs_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 gr_fecs_icd_rdata_r(void) -{ - return 0x0040920cU; -} -static inline u32 gr_fecs_imemc_r(u32 i) -{ - return 0x00409180U + i*16U; -} -static inline u32 gr_fecs_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_fecs_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_fecs_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_fecs_imemd_r(u32 i) -{ - return 0x00409184U + i*16U; -} -static inline u32 gr_fecs_imemt_r(u32 i) -{ - return 0x00409188U + i*16U; -} -static inline u32 gr_fecs_imemt_tag_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_fecs_dmemc_r(u32 i) -{ - return 0x004091c0U + i*8U; -} -static inline u32 gr_fecs_dmemc_offs_s(void) -{ - return 6U; -} -static inline u32 gr_fecs_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_fecs_dmemc_offs_m(void) -{ - return 0x3fU << 2U; -} -static inline u32 gr_fecs_dmemc_offs_v(u32 r) -{ - return (r >> 2U) & 0x3fU; -} -static inline u32 gr_fecs_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_fecs_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_fecs_dmemd_r(u32 i) -{ - return 0x004091c4U + i*8U; -} -static inline u32 gr_fecs_dmatrfbase_r(void) -{ - return 0x00409110U; -} -static inline u32 gr_fecs_dmatrfmoffs_r(void) -{ - return 0x00409114U; -} -static inline u32 gr_fecs_dmatrffboffs_r(void) -{ - return 0x0040911cU; -} -static inline u32 gr_fecs_dmatrfcmd_r(void) -{ - return 0x00409118U; -} -static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_fecs_bootvec_r(void) -{ - return 0x00409104U; -} -static inline u32 gr_fecs_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_falcon_hwcfg_r(void) -{ - return 0x00409108U; -} -static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void) -{ - return 0x0041a108U; -} -static inline u32 gr_fecs_falcon_rm_r(void) -{ - return 0x00409084U; -} -static inline u32 gr_fecs_current_ctx_r(void) -{ - return 0x00409b00U; -} -static inline u32 gr_fecs_current_ctx_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_current_ctx_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_current_ctx_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_current_ctx_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_current_ctx_target_m(void) -{ - return 0x3U << 28U; -} -static inline u32 gr_fecs_current_ctx_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 gr_fecs_current_ctx_valid_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_current_ctx_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_fecs_current_ctx_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_fecs_current_ctx_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_fecs_current_ctx_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_method_data_r(void) -{ - return 0x00409500U; -} -static inline u32 gr_fecs_method_push_r(void) -{ - return 0x00409504U; -} -static inline u32 gr_fecs_method_push_adr_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void) -{ - return 0x00000003U; -} -static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void) -{ - return 0x3U; -} -static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void) -{ - return 0x00000009U; -} -static inline u32 gr_fecs_method_push_adr_restore_golden_v(void) -{ - return 0x00000015U; -} -static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void) -{ - return 0x00000016U; -} -static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void) -{ - return 0x00000025U; -} -static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void) -{ - return 0x00000030U; -} -static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void) -{ - return 0x00000031U; -} -static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void) -{ - return 0x00000032U; -} -static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void) -{ - return 0x00000038U; -} -static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void) -{ - return 0x00000039U; -} -static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) -{ - return 0x21U; -} -static inline u32 gr_fecs_method_push_adr_write_timestamp_record_v(void) -{ - return 0x0000003dU; -} -static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_fecs_host_int_status_r(void) -{ - return 0x00409c18U; -} -static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 gr_fecs_host_int_status_watchdog_active_f(void) -{ - return 0x80000U; -} -static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_fecs_host_int_clear_r(void) -{ - return 0x00409c20U; -} -static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void) -{ - return 0x2U; -} -static inline u32 gr_fecs_host_int_enable_r(void) -{ - return 0x00409c24U; -} -static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void) -{ - return 0x2U; -} -static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void) -{ - return 0x10000U; -} -static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void) -{ - return 0x20000U; -} -static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void) -{ - return 0x40000U; -} -static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void) -{ - return 0x80000U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) -{ - return 0x00409614U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void) -{ - return 0x10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void) -{ - return 0x20U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void) -{ - return 0x40U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void) -{ - return 0x100U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void) -{ - return 0x200U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void) -{ - return 0x1U << 10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r) -{ - return (r >> 10U) & 0x1U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void) -{ - return 0x400U; -} -static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void) -{ - return 0x0040960cU; -} -static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i) -{ - return 0x00409800U + i*4U; -} -static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void) -{ - return 0x00000002U; -} -static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i) -{ - return 0x004098c0U + i*4U; -} -static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i) -{ - return 0x00409840U + i*4U; -} -static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_fs_r(void) -{ - return 0x00409604U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_m(void) -{ - return 0x1fU << 0U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_fecs_fs_num_available_fbps_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 gr_fecs_fs_num_available_fbps_m(void) -{ - return 0x1fU << 16U; -} -static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -static inline u32 gr_fecs_cfg_r(void) -{ - return 0x00409620U; -} -static inline u32 gr_fecs_cfg_imem_sz_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_fecs_rc_lanes_r(void) -{ - return 0x00409880U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_s(void) -{ - return 6U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_fecs_ctxsw_status_1_r(void) -{ - return 0x00409400U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void) -{ - return 0x1U << 12U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 gr_fecs_arb_ctx_adr_r(void) -{ - return 0x00409a24U; -} -static inline u32 gr_fecs_new_ctx_r(void) -{ - return 0x00409b04U; -} -static inline u32 gr_fecs_new_ctx_ptr_s(void) -{ - return 28U; -} -static inline u32 gr_fecs_new_ctx_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_new_ctx_ptr_m(void) -{ - return 0xfffffffU << 0U; -} -static inline u32 gr_fecs_new_ctx_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_new_ctx_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_new_ctx_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_new_ctx_target_m(void) -{ - return 0x3U << 28U; -} -static inline u32 gr_fecs_new_ctx_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_new_ctx_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_new_ctx_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 gr_fecs_new_ctx_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_fecs_new_ctx_valid_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_new_ctx_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_fecs_new_ctx_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_fecs_new_ctx_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_fecs_arb_ctx_ptr_r(void) -{ - return 0x00409a0cU; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void) -{ - return 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void) -{ - return 0xfffffffU << 0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_m(void) -{ - return 0x3U << 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_fecs_arb_ctx_cmd_r(void) -{ - return 0x00409a10U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void) -{ - return 0x1fU << 0U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_fecs_ctxsw_status_fe_0_r(void) -{ - return 0x00409c00U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void) -{ - return 0x00502c04U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) -{ - return 0x00502400U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_mailbox__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_fecs_ctxsw_idlestate_r(void) -{ - return 0x00409420U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) -{ - return 0x00502420U; -} -static inline u32 gr_rstr2d_gpc_map0_r(void) -{ - return 0x0040780cU; -} -static inline u32 gr_rstr2d_gpc_map1_r(void) -{ - return 0x00407810U; -} -static inline u32 gr_rstr2d_gpc_map2_r(void) -{ - return 0x00407814U; -} -static inline u32 gr_rstr2d_gpc_map3_r(void) -{ - return 0x00407818U; -} -static inline u32 gr_rstr2d_gpc_map4_r(void) -{ - return 0x0040781cU; -} -static inline u32 gr_rstr2d_gpc_map5_r(void) -{ - return 0x00407820U; -} -static inline u32 gr_rstr2d_map_table_cfg_r(void) -{ - return 0x004078bcU; -} -static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_pd_hww_esr_r(void) -{ - return 0x00406018U; -} -static inline u32 gr_pd_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pd_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i) -{ - return 0x00406028U + i*4U; -} -static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v) -{ - return (v & 0xfU) << 12U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v) -{ - return (v & 0xfU) << 24U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v) -{ - return (v & 0xfU) << 28U; -} -static inline u32 gr_pd_ab_dist_cfg0_r(void) -{ - return 0x004064c0U; -} -static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void) -{ - return 0x0U; -} -static inline u32 gr_pd_ab_dist_cfg1_r(void) -{ - return 0x004064c4U; -} -static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void) -{ - return 0xffffU; -} -static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void) -{ - return 0x00000080U; -} -static inline u32 gr_pd_ab_dist_cfg2_r(void) -{ - return 0x004064c8U; -} -static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) -{ - return 0x000001c0U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) -{ - return (v & 0xfffU) << 16U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) -{ - return 0x00000182U; -} -static inline u32 gr_pd_pagepool_r(void) -{ - return 0x004064ccU; -} -static inline u32 gr_pd_pagepool_total_pages_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_pd_pagepool_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pd_dist_skip_table_r(u32 i) -{ - return 0x004064d0U + i*4U; -} -static inline u32 gr_pd_dist_skip_table__size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gr_ds_debug_r(void) -{ - return 0x00405800U; -} -static inline u32 gr_ds_debug_timeslice_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_debug_timeslice_mode_enable_f(void) -{ - return 0x8000000U; -} -static inline u32 gr_ds_zbc_color_r_r(void) -{ - return 0x00405804U; -} -static inline u32 gr_ds_zbc_color_r_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_g_r(void) -{ - return 0x00405808U; -} -static inline u32 gr_ds_zbc_color_g_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_b_r(void) -{ - return 0x0040580cU; -} -static inline u32 gr_ds_zbc_color_b_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_a_r(void) -{ - return 0x00405810U; -} -static inline u32 gr_ds_zbc_color_a_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_fmt_r(void) -{ - return 0x00405814U; -} -static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v) -{ - return (v & 0x7fU) << 0U; -} -static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void) -{ - return 0x00000002U; -} -static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) -{ - return 0x00000028U; -} -static inline u32 gr_ds_zbc_z_r(void) -{ - return 0x00405818U; -} -static inline u32 gr_ds_zbc_z_val_s(void) -{ - return 32U; -} -static inline u32 gr_ds_zbc_z_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_z_val_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 gr_ds_zbc_z_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gr_ds_zbc_z_val__init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_ds_zbc_z_val__init_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_z_fmt_r(void) -{ - return 0x0040581cU; -} -static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_zbc_tbl_index_r(void) -{ - return 0x00405820U; -} -static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_ds_zbc_tbl_ld_r(void) -{ - return 0x00405824U; -} -static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) -{ - return 0x4U; -} -static inline u32 gr_ds_tga_constraintlogic_r(void) -{ - return 0x00405830U; -} -static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_ds_hww_esr_r(void) -{ - return 0x00405840U; -} -static inline u32 gr_ds_hww_esr_reset_s(void) -{ - return 1U; -} -static inline u32 gr_ds_hww_esr_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_reset_m(void) -{ - return 0x1U << 30U; -} -static inline u32 gr_ds_hww_esr_reset_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_ds_hww_esr_reset_task_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_hww_esr_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_ds_hww_esr_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_ds_hww_esr_2_r(void) -{ - return 0x00405848U; -} -static inline u32 gr_ds_hww_esr_2_reset_s(void) -{ - return 1U; -} -static inline u32 gr_ds_hww_esr_2_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_2_reset_m(void) -{ - return 0x1U << 30U; -} -static inline u32 gr_ds_hww_esr_2_reset_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_ds_hww_esr_2_reset_task_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_hww_esr_2_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_ds_hww_esr_2_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_ds_hww_report_mask_r(void) -{ - return 0x00405844U; -} -static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void) -{ - return 0x8U; -} -static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void) -{ - return 0x80U; -} -static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void) -{ - return 0x200U; -} -static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void) -{ - return 0x400U; -} -static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void) -{ - return 0x800U; -} -static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void) -{ - return 0x1000U; -} -static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void) -{ - return 0x2000U; -} -static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void) -{ - return 0x4000U; -} -static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void) -{ - return 0x8000U; -} -static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void) -{ - return 0x10000U; -} -static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void) -{ - return 0x20000U; -} -static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void) -{ - return 0x40000U; -} -static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void) -{ - return 0x80000U; -} -static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void) -{ - return 0x100000U; -} -static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void) -{ - return 0x200000U; -} -static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void) -{ - return 0x400000U; -} -static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void) -{ - return 0x800000U; -} -static inline u32 gr_ds_hww_report_mask_2_r(void) -{ - return 0x0040584cU; -} -static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i) -{ - return 0x00405870U + i*4U; -} -static inline u32 gr_scc_bundle_cb_base_r(void) -{ - return 0x00408004U; -} -static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_scc_bundle_cb_size_r(void) -{ - return 0x00408008U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7ffU) << 0U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) -{ - return 0x00000018U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_scc_bundle_cb_size_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_scc_bundle_cb_size_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_scc_bundle_cb_size_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_scc_pagepool_base_r(void) -{ - return 0x0040800cU; -} -static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_scc_pagepool_r(void) -{ - return 0x00408010U; -} -static inline u32 gr_scc_pagepool_total_pages_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void) -{ - return 0x00000080U; -} -static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_s(void) -{ - return 8U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_m(void) -{ - return 0xffU << 8U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} -static inline u32 gr_scc_pagepool_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_scc_init_r(void) -{ - return 0x0040802cU; -} -static inline u32 gr_scc_init_ram_trigger_f(void) -{ - return 0x1U; -} -static inline u32 gr_scc_hww_esr_r(void) -{ - return 0x00408030U; -} -static inline u32 gr_scc_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_scc_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_sked_hww_esr_r(void) -{ - return 0x00407020U; -} -static inline u32 gr_sked_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_cwd_fs_r(void) -{ - return 0x00405b00U; -} -static inline u32 gr_cwd_fs_num_gpcs_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_cwd_fs_num_tpcs_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_cwd_gpc_tpc_id_r(u32 i) -{ - return 0x00405b60U + i*4U; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void) -{ - return 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void) -{ - return 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_cwd_sm_id_r(u32 i) -{ - return 0x00405ba0U + i*4U; -} -static inline u32 gr_cwd_sm_id__size_1_v(void) -{ - return 0x00000006U; -} -static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_cwd_sm_id_tpc1_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpc0_fs_gpc_r(void) -{ - return 0x00502608U; -} -static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -static inline u32 gr_gpc0_cfg_r(void) -{ - return 0x00502620U; -} -static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpccs_rc_lanes_r(void) -{ - return 0x00502880U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_gpccs_rc_lane_size_r(u32 i) -{ - return 0x00502910U + i*0U; -} -static inline u32 gr_gpccs_rc_lane_size__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_gpccs_rc_lane_size_v_s(void) -{ - return 24U; -} -static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_gpccs_rc_lane_size_v_m(void) -{ - return 0xffffffU << 0U; -} -static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_zcull_fs_r(void) -{ - return 0x00500910U; -} -static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 gr_gpc0_zcull_ram_addr_r(void) -{ - return 0x00500914U; -} -static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void) -{ - return 0x00500918U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void) -{ - return 0x00800000U; -} -static inline u32 gr_gpc0_zcull_total_ram_size_r(void) -{ - return 0x00500920U; -} -static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_zcull_zcsize_r(u32 i) -{ - return 0x00500a04U + i*32U; -} -static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void) -{ - return 0x00000040U; -} -static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i) -{ - return 0x00500c10U + i*4U; -} -static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i) -{ - return 0x00500c30U + i*4U; -} -static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void) -{ - return 0x00504088U; -} -static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) -{ - return 0x00504698U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_r(void) -{ - return 0x0050469cU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r) -{ - return (r >> 8U) & 0xfffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r) -{ - return (r >> 20U) & 0xfffU; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) -{ - return 0x00503018U; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void) -{ - return 0x005030c0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) -{ - return 0x00000400U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void) -{ - return 0x005030f4U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void) -{ - return 0x005030e4U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void) -{ - return 0x00000800U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) -{ - return 0x005030f8U; -} -static inline u32 gr_gpcs_tpcs_tex_m_dbg2_r(void) -{ - return 0x00419a3cU; -} -static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_gpcs_tpcs_tex_m_dbg2_tex_rd_coalesce_en_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_gpcs_tpcs_tex_m_dbg2_tex_rd_coalesce_en_m(void) -{ - return 0x1U << 5U; -} -static inline u32 gr_gpccs_falcon_addr_r(void) -{ - return 0x0041a0acU; -} -static inline u32 gr_gpccs_falcon_addr_lsb_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpccs_falcon_addr_msb_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v) -{ - return (v & 0x3fU) << 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_m(void) -{ - return 0x3fU << 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r) -{ - return (r >> 6U) & 0x3fU; -} -static inline u32 gr_gpccs_falcon_addr_msb_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_falcon_addr_msb_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_s(void) -{ - return 12U; -} -static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_m(void) -{ - return 0xfffU << 0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 gr_gpccs_cpuctl_r(void) -{ - return 0x0041a100U; -} -static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_gpccs_dmactl_r(void) -{ - return 0x0041a10cU; -} -static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_gpccs_imemc_r(u32 i) -{ - return 0x0041a180U + i*16U; -} -static inline u32 gr_gpccs_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_gpccs_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpccs_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_gpccs_imemd_r(u32 i) -{ - return 0x0041a184U + i*16U; -} -static inline u32 gr_gpccs_imemt_r(u32 i) -{ - return 0x0041a188U + i*16U; -} -static inline u32 gr_gpccs_imemt__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_gpccs_imemt_tag_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpccs_dmemc_r(u32 i) -{ - return 0x0041a1c0U + i*8U; -} -static inline u32 gr_gpccs_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_gpccs_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpccs_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_gpccs_dmemd_r(u32 i) -{ - return 0x0041a1c4U + i*8U; -} -static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i) -{ - return 0x0041a800U + i*4U; -} -static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void) -{ - return 0x00418e24U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void) -{ - return 32U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void) -{ - return 0x00418e28U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void) -{ - return 11U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7ffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void) -{ - return 0x7ffU << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) -{ - return (r >> 0U) & 0x7ffU; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) -{ - return 0x00000018U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) -{ - return 0x18U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) -{ - return 1U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) -{ - return 0x00418ea0U + i*4U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_div3_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_div3_m(void) -{ - return 0xffffU << 16U; -} -static inline u32 gr_gpcs_swdx_rm_pagepool_r(void) -{ - return 0x00418e30U; -} -static inline u32 gr_gpcs_swdx_rm_pagepool_total_pages_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_gpcs_swdx_rm_pagepool_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) -{ - return 0x00418810U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void) -{ - return 0x0000000cU; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_crstr_gpc_map0_r(void) -{ - return 0x00418b08U; -} -static inline u32 gr_crstr_gpc_map0_tile0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map0_tile1_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map0_tile2_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map0_tile3_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map0_tile4_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map0_tile5_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map1_r(void) -{ - return 0x00418b0cU; -} -static inline u32 gr_crstr_gpc_map1_tile6_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map1_tile7_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map1_tile8_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map1_tile9_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map1_tile10_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map1_tile11_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map2_r(void) -{ - return 0x00418b10U; -} -static inline u32 gr_crstr_gpc_map2_tile12_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map2_tile13_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map2_tile14_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map2_tile15_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map2_tile16_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map2_tile17_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map3_r(void) -{ - return 0x00418b14U; -} -static inline u32 gr_crstr_gpc_map3_tile18_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map3_tile19_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map3_tile20_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map3_tile21_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map3_tile22_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map3_tile23_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map4_r(void) -{ - return 0x00418b18U; -} -static inline u32 gr_crstr_gpc_map4_tile24_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map4_tile25_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map4_tile26_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map4_tile27_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map4_tile28_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map4_tile29_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map5_r(void) -{ - return 0x00418b1cU; -} -static inline u32 gr_crstr_gpc_map5_tile30_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map5_tile31_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map5_tile32_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map5_tile33_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map5_tile34_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map5_tile35_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_map_table_cfg_r(void) -{ - return 0x00418bb8U; -} -static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_r(void) -{ - return 0x00418980U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_r(void) -{ - return 0x00418984U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_r(void) -{ - return 0x00418988U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s(void) -{ - return 3U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void) -{ - return 0x7U << 28U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r) -{ - return (r >> 28U) & 0x7U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_r(void) -{ - return 0x0041898cU; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_gpm_pd_cfg_r(void) -{ - return 0x00418c6cU; -} -static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpcs_gcc_pagepool_base_r(void) -{ - return 0x00419004U; -} -static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_gcc_pagepool_r(void) -{ - return 0x00419008U; -} -static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_pe_vaf_r(void) -{ - return 0x0041980cU; -} -static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void) -{ - return 0x00419848U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) -{ - return 0x00419c00U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void) -{ - return 0x00419c2cU; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void) -{ - return 0x00419e44U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f(void) -{ - return 0x80U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) -{ - return 0x200U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f(void) -{ - return 0x400U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) -{ - return 0x800U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f(void) -{ - return 0x1000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f(void) -{ - return 0x2000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f(void) -{ - return 0x4000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f(void) -{ - return 0x8000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) -{ - return 0x10000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f(void) -{ - return 0x20000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) -{ - return 0x40000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_mmu_fault_report_f(void) -{ - return 0x800000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_overflow_report_f(void) -{ - return 0x400000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f(void) -{ - return 0x80000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(void) -{ - return 0x100000U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_report_mask_r(void) -{ - return 0x00504644U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void) -{ - return 0x00419e4cU; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_report_mask_r(void) -{ - return 0x0050464cU; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) -{ - return 0x00419d0cU; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) -{ - return 0x0050450cU; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) -{ - return 0x0041ac94U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) -{ - return 0x00502c90U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) -{ - return 0x00504508U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void) -{ - return 0x00504610U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_warp_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_sm_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void) -{ - return 0x00504614U; -} -static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_1_r(void) -{ - return 0x00504618U; -} -static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_2_r(void) -{ - return 0x0050461cU; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void) -{ - return 0x00504624U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_1_r(void) -{ - return 0x00504628U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_2_r(void) -{ - return 0x00504750U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void) -{ - return 0x00504634U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_1_r(void) -{ - return 0x00504638U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_2_r(void) -{ - return 0x00504758U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void) -{ - return 0x00419e24U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) -{ - return 0x0050460cU; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void) -{ - return 0x00419e50U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void) -{ - return 0x00504650U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void) -{ - return 0x00504224U; -} -static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void) -{ - return 0x00504648U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_pc_r(void) -{ - return 0x00504654U; -} -static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) -{ - return 0x00504770U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) -{ - return 0x00419f70U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) -{ - return 0x0050477cU; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) -{ - return 0x00419f7cU; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) -{ - return 0x0041be08U; -} -static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) -{ - return 0x4U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map0_r(void) -{ - return 0x0041bf00U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map1_r(void) -{ - return 0x0041bf04U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map2_r(void) -{ - return 0x0041bf08U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map3_r(void) -{ - return 0x0041bf0cU; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map4_r(void) -{ - return 0x0041bf10U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map5_r(void) -{ - return 0x0041bf14U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) -{ - return 0x0041bfd0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) -{ - return (v & 0x7U) << 21U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 24U; -} -static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) -{ - return 0x0041bfd4U; -} -static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_r(void) -{ - return 0x0041bfe4U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 5U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 10U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 15U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 20U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 25U; -} -static inline u32 gr_bes_zrop_settings_r(void) -{ - return 0x00408850U; -} -static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_be0_crop_debug3_r(void) -{ - return 0x00410108U; -} -static inline u32 gr_bes_crop_debug3_r(void) -{ - return 0x00408908U; -} -static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_bes_crop_settings_r(void) -{ - return 0x00408958U; -} -static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void) -{ - return 0x000000c0U; -} -static inline u32 gr_zcull_subregion_qty_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void) -{ - return 0x00504604U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void) -{ - return 0x00504608U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void) -{ - return 0x0050465cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void) -{ - return 0x00504660U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void) -{ - return 0x00504664U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void) -{ - return 0x00504668U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void) -{ - return 0x0050466cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void) -{ - return 0x00504658U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void) -{ - return 0x00504730U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void) -{ - return 0x00504734U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void) -{ - return 0x00504738U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void) -{ - return 0x0050473cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void) -{ - return 0x00504740U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void) -{ - return 0x00504744U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void) -{ - return 0x00504748U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void) -{ - return 0x0050474cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_s1_r(void) -{ - return 0x00504678U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r(void) -{ - return 0x00504694U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s0_r(void) -{ - return 0x005046f0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s1_r(void) -{ - return 0x00504700U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s0_r(void) -{ - return 0x005046f4U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s1_r(void) -{ - return 0x00504704U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s0_r(void) -{ - return 0x005046f8U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s1_r(void) -{ - return 0x00504708U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s0_r(void) -{ - return 0x005046fcU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s1_r(void) -{ - return 0x0050470cU; -} -static inline u32 gr_fe_pwr_mode_r(void) -{ - return 0x00404170U; -} -static inline u32 gr_fe_pwr_mode_mode_auto_f(void) -{ - return 0x0U; -} -static inline u32 gr_fe_pwr_mode_mode_force_on_f(void) -{ - return 0x2U; -} -static inline u32 gr_fe_pwr_mode_req_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 gr_fe_pwr_mode_req_send_f(void) -{ - return 0x10U; -} -static inline u32 gr_fe_pwr_mode_req_done_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) -{ - return 0x00418880U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void) -{ - return 0x1U << 11U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_use_full_comp_tag_line_m(void) -{ - return 0x1U << 12U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void) -{ - return 0x3U << 3U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void) -{ - return 0x3U << 5U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void) -{ - return 0x3U << 28U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void) -{ - return 0x1U << 30U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) -{ - return 0x00418890U; -} -static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void) -{ - return 0x00418894U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) -{ - return 0x004188b0U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_m(void) -{ - return 0x1U << 16U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_f(void) -{ - return 0x10000U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) -{ - return 0x004188b4U; -} -static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void) -{ - return 0x004188b8U; -} -static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) -{ - return 0x004188acU; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void) -{ - return 0x00419e10U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(void) -{ - return 0x1U << 3U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) -{ - return 0x1U << 30U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void) -{ - return 0x40000000U; -} -#endif diff --git a/include/nvgpu/hw/gm20b/hw_ltc_gm20b.h b/include/nvgpu/hw/gm20b/hw_ltc_gm20b.h deleted file mode 100644 index 2c3ebb4..0000000 --- a/include/nvgpu/hw/gm20b/hw_ltc_gm20b.h +++ /dev/null @@ -1,527 +0,0 @@ -/* - * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ltc_gm20b_h_ -#define _hw_ltc_gm20b_h_ - -static inline u32 ltc_pltcg_base_v(void) -{ - return 0x00140000U; -} -static inline u32 ltc_pltcg_extent_v(void) -{ - return 0x0017ffffU; -} -static inline u32 ltc_ltc0_ltss_v(void) -{ - return 0x00140200U; -} -static inline u32 ltc_ltc0_lts0_v(void) -{ - return 0x00140400U; -} -static inline u32 ltc_ltcs_ltss_v(void) -{ - return 0x0017e200U; -} -static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) -{ - return 0x0014046cU; -} -static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) -{ - return 0x00140518U; -} -static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) -{ - return 0x0017e318U; -} -static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void) -{ - return 0x1U << 15U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) -{ - return 0x00140494U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) -{ - return (r >> 16U) & 0x3U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) -{ - return 0x00000000U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) -{ - return 0x00000002U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) -{ - return 0x0017e26cU; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) -{ - return 0x2U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) -{ - return 0x4U; -} -static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) -{ - return 0x0014046cU; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) -{ - return 0x0017e270U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) -{ - return 0x0017e274U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) -{ - return 0x0001ffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_base_r(void) -{ - return 0x0017e278U; -} -static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) -{ - return 0x0000000bU; -} -static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) -{ - return (r >> 0U) & 0x3ffffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) -{ - return 0x0017e27cU; -} -static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) -{ - return 0x0017e000U; -} -static inline u32 ltc_ltcs_ltss_cbc_param_r(void) -{ - return 0x0017e280U; -} -static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r) -{ - return (r >> 24U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r) -{ - return (r >> 28U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) -{ - return 0x0017e2acU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) -{ - return 0x0017e338U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) -{ - return 0x0017e33cU + i*4U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) -{ - return 0x0017e34cU; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) -{ - return 32U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) -{ - return 0x0017e2b0U; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_r(void) -{ - return 0x0017e214U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_r(void) -{ - return 0x00140214U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc1_ltss_g_elpg_r(void) -{ - return 0x00142214U; -} -static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_intr_r(void) -{ - return 0x0017e20cU; -} -static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) -{ - return 0x1U << 20U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) -{ - return 0x1U << 30U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_m(void) -{ - return 0x1U << 21U; -} -static inline u32 ltc_ltc0_lts0_intr_r(void) -{ - return 0x0014040cU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) -{ - return 0x0017e2a0U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) -{ - return 0x300U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) -{ - return 0x20000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) -{ - return 0x40000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) -{ - return 0x0017e2a4U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) -{ - return 0x300U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) -{ - return 0x10000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) -{ - return 0x20000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) -{ - return 0x40000000U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) -{ - return 0x001402a0U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) -{ - return 0x001402a4U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void) -{ - return 0x001422a0U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void) -{ - return 0x001422a4U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} -#endif diff --git a/include/nvgpu/hw/gm20b/hw_mc_gm20b.h b/include/nvgpu/hw/gm20b/hw_mc_gm20b.h deleted file mode 100644 index 0264803..0000000 --- a/include/nvgpu/hw/gm20b/hw_mc_gm20b.h +++ /dev/null @@ -1,287 +0,0 @@ -/* - * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_mc_gm20b_h_ -#define _hw_mc_gm20b_h_ - -static inline u32 mc_boot_0_r(void) -{ - return 0x00000000U; -} -static inline u32 mc_boot_0_architecture_v(u32 r) -{ - return (r >> 24U) & 0x1fU; -} -static inline u32 mc_boot_0_implementation_v(u32 r) -{ - return (r >> 20U) & 0xfU; -} -static inline u32 mc_boot_0_major_revision_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 mc_boot_0_minor_revision_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 mc_intr_r(u32 i) -{ - return 0x00000100U + i*4U; -} -static inline u32 mc_intr_pfifo_pending_f(void) -{ - return 0x100U; -} -static inline u32 mc_intr_pmu_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 mc_intr_ltc_pending_f(void) -{ - return 0x2000000U; -} -static inline u32 mc_intr_priv_ring_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 mc_intr_pbus_pending_f(void) -{ - return 0x10000000U; -} -static inline u32 mc_intr_mask_0_r(void) -{ - return 0x00000640U; -} -static inline u32 mc_intr_mask_0_pmu_enabled_f(void) -{ - return 0x1000000U; -} -static inline u32 mc_intr_en_0_r(void) -{ - return 0x00000140U; -} -static inline u32 mc_intr_en_0_inta_disabled_f(void) -{ - return 0x0U; -} -static inline u32 mc_intr_en_0_inta_hardware_f(void) -{ - return 0x1U; -} -static inline u32 mc_intr_mask_1_r(void) -{ - return 0x00000644U; -} -static inline u32 mc_intr_mask_1_pmu_s(void) -{ - return 1U; -} -static inline u32 mc_intr_mask_1_pmu_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 mc_intr_mask_1_pmu_m(void) -{ - return 0x1U << 24U; -} -static inline u32 mc_intr_mask_1_pmu_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 mc_intr_mask_1_pmu_enabled_f(void) -{ - return 0x1000000U; -} -static inline u32 mc_intr_en_1_r(void) -{ - return 0x00000144U; -} -static inline u32 mc_intr_en_1_inta_disabled_f(void) -{ - return 0x0U; -} -static inline u32 mc_intr_en_1_inta_hardware_f(void) -{ - return 0x1U; -} -static inline u32 mc_enable_r(void) -{ - return 0x00000200U; -} -static inline u32 mc_enable_xbar_enabled_f(void) -{ - return 0x4U; -} -static inline u32 mc_enable_l2_enabled_f(void) -{ - return 0x8U; -} -static inline u32 mc_enable_pmedia_s(void) -{ - return 1U; -} -static inline u32 mc_enable_pmedia_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 mc_enable_pmedia_m(void) -{ - return 0x1U << 4U; -} -static inline u32 mc_enable_pmedia_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 mc_enable_priv_ring_enabled_f(void) -{ - return 0x20U; -} -static inline u32 mc_enable_ce0_m(void) -{ - return 0x1U << 6U; -} -static inline u32 mc_enable_pfifo_enabled_f(void) -{ - return 0x100U; -} -static inline u32 mc_enable_pgraph_enabled_f(void) -{ - return 0x1000U; -} -static inline u32 mc_enable_pwr_v(u32 r) -{ - return (r >> 13U) & 0x1U; -} -static inline u32 mc_enable_pwr_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 mc_enable_pwr_enabled_f(void) -{ - return 0x2000U; -} -static inline u32 mc_enable_pfb_enabled_f(void) -{ - return 0x100000U; -} -static inline u32 mc_enable_ce2_m(void) -{ - return 0x1U << 21U; -} -static inline u32 mc_enable_ce2_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 mc_enable_blg_enabled_f(void) -{ - return 0x8000000U; -} -static inline u32 mc_enable_perfmon_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 mc_enable_hub_enabled_f(void) -{ - return 0x20000000U; -} -static inline u32 mc_intr_ltc_r(void) -{ - return 0x0000017cU; -} -static inline u32 mc_enable_pb_r(void) -{ - return 0x00000204U; -} -static inline u32 mc_enable_pb_0_s(void) -{ - return 1U; -} -static inline u32 mc_enable_pb_0_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 mc_enable_pb_0_m(void) -{ - return 0x1U << 0U; -} -static inline u32 mc_enable_pb_0_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 mc_enable_pb_0_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 mc_enable_pb_sel_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 mc_elpg_enable_r(void) -{ - return 0x0000020cU; -} -static inline u32 mc_elpg_enable_xbar_enabled_f(void) -{ - return 0x4U; -} -static inline u32 mc_elpg_enable_pfb_enabled_f(void) -{ - return 0x100000U; -} -static inline u32 mc_elpg_enable_hub_enabled_f(void) -{ - return 0x20000000U; -} -#endif diff --git a/include/nvgpu/hw/gm20b/hw_pbdma_gm20b.h b/include/nvgpu/hw/gm20b/hw_pbdma_gm20b.h deleted file mode 100644 index 10ed9ec..0000000 --- a/include/nvgpu/hw/gm20b/hw_pbdma_gm20b.h +++ /dev/null @@ -1,579 +0,0 @@ -/* - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pbdma_gm20b_h_ -#define _hw_pbdma_gm20b_h_ - -static inline u32 pbdma_gp_entry1_r(void) -{ - return 0x10000004U; -} -static inline u32 pbdma_gp_entry1_get_hi_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pbdma_gp_entry1_length_f(u32 v) -{ - return (v & 0x1fffffU) << 10U; -} -static inline u32 pbdma_gp_entry1_length_v(u32 r) -{ - return (r >> 10U) & 0x1fffffU; -} -static inline u32 pbdma_gp_base_r(u32 i) -{ - return 0x00040048U + i*8192U; -} -static inline u32 pbdma_gp_base__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 pbdma_gp_base_offset_f(u32 v) -{ - return (v & 0x1fffffffU) << 3U; -} -static inline u32 pbdma_gp_base_rsvd_s(void) -{ - return 3U; -} -static inline u32 pbdma_gp_base_hi_r(u32 i) -{ - return 0x0004004cU + i*8192U; -} -static inline u32 pbdma_gp_base_hi_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pbdma_gp_base_hi_limit2_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 pbdma_gp_fetch_r(u32 i) -{ - return 0x00040050U + i*8192U; -} -static inline u32 pbdma_gp_get_r(u32 i) -{ - return 0x00040014U + i*8192U; -} -static inline u32 pbdma_gp_put_r(u32 i) -{ - return 0x00040000U + i*8192U; -} -static inline u32 pbdma_pb_fetch_r(u32 i) -{ - return 0x00040054U + i*8192U; -} -static inline u32 pbdma_pb_fetch_hi_r(u32 i) -{ - return 0x00040058U + i*8192U; -} -static inline u32 pbdma_get_r(u32 i) -{ - return 0x00040018U + i*8192U; -} -static inline u32 pbdma_get_hi_r(u32 i) -{ - return 0x0004001cU + i*8192U; -} -static inline u32 pbdma_put_r(u32 i) -{ - return 0x0004005cU + i*8192U; -} -static inline u32 pbdma_put_hi_r(u32 i) -{ - return 0x00040060U + i*8192U; -} -static inline u32 pbdma_formats_r(u32 i) -{ - return 0x0004009cU + i*8192U; -} -static inline u32 pbdma_formats_gp_fermi0_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_formats_pb_fermi1_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_formats_mp_fermi0_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_r(u32 i) -{ - return 0x00040084U + i*8192U; -} -static inline u32 pbdma_pb_header_priv_user_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_method_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_subchannel_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_level_main_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_first_true_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_pb_header_type_inc_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_pb_header_type_non_inc_f(void) -{ - return 0x60000000U; -} -static inline u32 pbdma_hdr_shadow_r(u32 i) -{ - return 0x00040118U + i*8192U; -} -static inline u32 pbdma_gp_shadow_0_r(u32 i) -{ - return 0x00040110U + i*8192U; -} -static inline u32 pbdma_gp_shadow_1_r(u32 i) -{ - return 0x00040114U + i*8192U; -} -static inline u32 pbdma_subdevice_r(u32 i) -{ - return 0x00040094U + i*8192U; -} -static inline u32 pbdma_subdevice_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 pbdma_subdevice_status_active_f(void) -{ - return 0x10000000U; -} -static inline u32 pbdma_subdevice_channel_dma_enable_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_method0_r(u32 i) -{ - return 0x000400c0U + i*8192U; -} -static inline u32 pbdma_method0_fifo_size_v(void) -{ - return 0x00000004U; -} -static inline u32 pbdma_method0_addr_f(u32 v) -{ - return (v & 0xfffU) << 2U; -} -static inline u32 pbdma_method0_addr_v(u32 r) -{ - return (r >> 2U) & 0xfffU; -} -static inline u32 pbdma_method0_subch_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 pbdma_method0_first_true_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_method0_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_method1_r(u32 i) -{ - return 0x000400c8U + i*8192U; -} -static inline u32 pbdma_method2_r(u32 i) -{ - return 0x000400d0U + i*8192U; -} -static inline u32 pbdma_method3_r(u32 i) -{ - return 0x000400d8U + i*8192U; -} -static inline u32 pbdma_data0_r(u32 i) -{ - return 0x000400c4U + i*8192U; -} -static inline u32 pbdma_target_r(u32 i) -{ - return 0x000400acU + i*8192U; -} -static inline u32 pbdma_target_engine_sw_f(void) -{ - return 0x1fU; -} -static inline u32 pbdma_acquire_r(u32 i) -{ - return 0x00040030U + i*8192U; -} -static inline u32 pbdma_acquire_retry_man_2_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_acquire_retry_exp_2_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_acquire_timeout_exp_f(u32 v) -{ - return (v & 0xfU) << 11U; -} -static inline u32 pbdma_acquire_timeout_exp_max_v(void) -{ - return 0x0000000fU; -} -static inline u32 pbdma_acquire_timeout_exp_max_f(void) -{ - return 0x7800U; -} -static inline u32 pbdma_acquire_timeout_man_f(u32 v) -{ - return (v & 0xffffU) << 15U; -} -static inline u32 pbdma_acquire_timeout_man_max_v(void) -{ - return 0x0000ffffU; -} -static inline u32 pbdma_acquire_timeout_man_max_f(void) -{ - return 0x7fff8000U; -} -static inline u32 pbdma_acquire_timeout_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_acquire_timeout_en_disable_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_status_r(u32 i) -{ - return 0x00040100U + i*8192U; -} -static inline u32 pbdma_channel_r(u32 i) -{ - return 0x00040120U + i*8192U; -} -static inline u32 pbdma_signature_r(u32 i) -{ - return 0x00040010U + i*8192U; -} -static inline u32 pbdma_signature_hw_valid_f(void) -{ - return 0xfaceU; -} -static inline u32 pbdma_signature_sw_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_userd_r(u32 i) -{ - return 0x00040008U + i*8192U; -} -static inline u32 pbdma_userd_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_userd_target_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 pbdma_userd_addr_f(u32 v) -{ - return (v & 0x7fffffU) << 9U; -} -static inline u32 pbdma_userd_hi_r(u32 i) -{ - return 0x0004000cU + i*8192U; -} -static inline u32 pbdma_userd_hi_addr_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pbdma_hce_ctrl_r(u32 i) -{ - return 0x000400e4U + i*8192U; -} -static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void) -{ - return 0x20U; -} -static inline u32 pbdma_intr_0_r(u32 i) -{ - return 0x00040108U + i*8192U; -} -static inline u32 pbdma_intr_0_memreq_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pbdma_intr_0_memreq_pending_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_intr_0_memack_timeout_pending_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_intr_0_memack_extra_pending_f(void) -{ - return 0x4U; -} -static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void) -{ - return 0x8U; -} -static inline u32 pbdma_intr_0_memdat_extra_pending_f(void) -{ - return 0x10U; -} -static inline u32 pbdma_intr_0_memflush_pending_f(void) -{ - return 0x20U; -} -static inline u32 pbdma_intr_0_memop_pending_f(void) -{ - return 0x40U; -} -static inline u32 pbdma_intr_0_lbconnect_pending_f(void) -{ - return 0x80U; -} -static inline u32 pbdma_intr_0_lbreq_pending_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_0_lback_timeout_pending_f(void) -{ - return 0x200U; -} -static inline u32 pbdma_intr_0_lback_extra_pending_f(void) -{ - return 0x400U; -} -static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void) -{ - return 0x800U; -} -static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void) -{ - return 0x1000U; -} -static inline u32 pbdma_intr_0_gpfifo_pending_f(void) -{ - return 0x2000U; -} -static inline u32 pbdma_intr_0_gpptr_pending_f(void) -{ - return 0x4000U; -} -static inline u32 pbdma_intr_0_gpentry_pending_f(void) -{ - return 0x8000U; -} -static inline u32 pbdma_intr_0_gpcrc_pending_f(void) -{ - return 0x10000U; -} -static inline u32 pbdma_intr_0_pbptr_pending_f(void) -{ - return 0x20000U; -} -static inline u32 pbdma_intr_0_pbentry_pending_f(void) -{ - return 0x40000U; -} -static inline u32 pbdma_intr_0_pbcrc_pending_f(void) -{ - return 0x80000U; -} -static inline u32 pbdma_intr_0_xbarconnect_pending_f(void) -{ - return 0x100000U; -} -static inline u32 pbdma_intr_0_method_pending_f(void) -{ - return 0x200000U; -} -static inline u32 pbdma_intr_0_methodcrc_pending_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_intr_0_device_pending_f(void) -{ - return 0x800000U; -} -static inline u32 pbdma_intr_0_semaphore_pending_f(void) -{ - return 0x2000000U; -} -static inline u32 pbdma_intr_0_acquire_pending_f(void) -{ - return 0x4000000U; -} -static inline u32 pbdma_intr_0_pri_pending_f(void) -{ - return 0x8000000U; -} -static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_intr_0_pbseg_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 pbdma_intr_0_signature_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_intr_1_r(u32 i) -{ - return 0x00040148U + i*8192U; -} -static inline u32 pbdma_intr_en_0_r(u32 i) -{ - return 0x0004010cU + i*8192U; -} -static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_en_1_r(u32 i) -{ - return 0x0004014cU + i*8192U; -} -static inline u32 pbdma_intr_stall_r(u32 i) -{ - return 0x0004013cU + i*8192U; -} -static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_stall_1_r(u32 i) -{ - return 0x00040140U + i*8192U; -} -static inline u32 pbdma_intr_stall_1_hce_illegal_op_enabled_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_udma_nop_r(void) -{ - return 0x00000008U; -} -static inline u32 pbdma_syncpointa_r(u32 i) -{ - return 0x000400a4U + i*8192U; -} -static inline u32 pbdma_syncpointa_payload_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pbdma_syncpointb_r(u32 i) -{ - return 0x000400a8U + i*8192U; -} -static inline u32 pbdma_syncpointb_op_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 pbdma_syncpointb_op_wait_v(void) -{ - return 0x00000000U; -} -static inline u32 pbdma_syncpointb_wait_switch_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 pbdma_syncpointb_wait_switch_en_v(void) -{ - return 0x00000001U; -} -static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} -static inline u32 pbdma_runlist_timeslice_r(u32 i) -{ - return 0x000400f8U + i*8192U; -} -static inline u32 pbdma_runlist_timeslice_timeout_128_f(void) -{ - return 0x80U; -} -static inline u32 pbdma_runlist_timeslice_timescale_3_f(void) -{ - return 0x3000U; -} -static inline u32 pbdma_runlist_timeslice_enable_true_f(void) -{ - return 0x10000000U; -} -#endif diff --git a/include/nvgpu/hw/gm20b/hw_perf_gm20b.h b/include/nvgpu/hw/gm20b/hw_perf_gm20b.h deleted file mode 100644 index a94ba30..0000000 --- a/include/nvgpu/hw/gm20b/hw_perf_gm20b.h +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_perf_gm20b_h_ -#define _hw_perf_gm20b_h_ - -static inline u32 perf_pmmsys_base_v(void) -{ - return 0x001b0000U; -} -static inline u32 perf_pmmsys_extent_v(void) -{ - return 0x001b0fffU; -} -static inline u32 perf_pmasys_control_r(void) -{ - return 0x001b4000U; -} -static inline u32 perf_pmasys_control_membuf_status_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void) -{ - return 0x10U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) -{ - return 0x20U; -} -static inline u32 perf_pmasys_mem_block_r(void) -{ - return 0x001b4070U; -} -static inline u32 perf_pmasys_mem_block_base_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 perf_pmasys_mem_block_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 perf_pmasys_mem_block_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 perf_pmasys_mem_block_target_lfb_v(void) -{ - return 0x00000000U; -} -static inline u32 perf_pmasys_mem_block_target_lfb_f(void) -{ - return 0x0U; -} -static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 perf_pmasys_mem_block_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 perf_pmasys_mem_block_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 perf_pmasys_mem_block_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_mem_block_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 perf_pmasys_mem_block_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 perf_pmasys_mem_block_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 perf_pmasys_outbase_r(void) -{ - return 0x001b4074U; -} -static inline u32 perf_pmasys_outbase_ptr_f(u32 v) -{ - return (v & 0x7ffffffU) << 5U; -} -static inline u32 perf_pmasys_outbaseupper_r(void) -{ - return 0x001b4078U; -} -static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 perf_pmasys_outsize_r(void) -{ - return 0x001b407cU; -} -static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) -{ - return (v & 0x7ffffffU) << 5U; -} -static inline u32 perf_pmasys_mem_bytes_r(void) -{ - return 0x001b4084U; -} -static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 perf_pmasys_mem_bump_r(void) -{ - return 0x001b4088U; -} -static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 perf_pmasys_enginestatus_r(void) -{ - return 0x001b40a4U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void) -{ - return 0x10U; -} -#endif diff --git a/include/nvgpu/hw/gm20b/hw_pram_gm20b.h b/include/nvgpu/hw/gm20b/hw_pram_gm20b.h deleted file mode 100644 index 47a6bfa..0000000 --- a/include/nvgpu/hw/gm20b/hw_pram_gm20b.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pram_gm20b_h_ -#define _hw_pram_gm20b_h_ - -static inline u32 pram_data032_r(u32 i) -{ - return 0x00700000U + i*4U; -} -#endif diff --git a/include/nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h b/include/nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h deleted file mode 100644 index c6f08ed..0000000 --- a/include/nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pri_ringmaster_gm20b_h_ -#define _hw_pri_ringmaster_gm20b_h_ - -static inline u32 pri_ringmaster_command_r(void) -{ - return 0x0012004cU; -} -static inline u32 pri_ringmaster_command_cmd_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 pri_ringmaster_command_cmd_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void) -{ - return 0x00000000U; -} -static inline u32 pri_ringmaster_command_cmd_start_ring_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void) -{ - return 0x2U; -} -static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void) -{ - return 0x3U; -} -static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void) -{ - return 0x0U; -} -static inline u32 pri_ringmaster_command_data_r(void) -{ - return 0x00120048U; -} -static inline u32 pri_ringmaster_start_results_r(void) -{ - return 0x00120050U; -} -static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void) -{ - return 0x00000001U; -} -static inline u32 pri_ringmaster_intr_status0_r(void) -{ - return 0x00120058U; -} -static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status1_r(void) -{ - return 0x0012005cU; -} -static inline u32 pri_ringmaster_global_ctl_r(void) -{ - return 0x00120060U; -} -static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void) -{ - return 0x0U; -} -static inline u32 pri_ringmaster_enum_fbp_r(void) -{ - return 0x00120074U; -} -static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 pri_ringmaster_enum_gpc_r(void) -{ - return 0x00120078U; -} -static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 pri_ringmaster_enum_ltc_r(void) -{ - return 0x0012006cU; -} -static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -#endif diff --git a/include/nvgpu/hw/gm20b/hw_pri_ringstation_gpc_gm20b.h b/include/nvgpu/hw/gm20b/hw_pri_ringstation_gpc_gm20b.h deleted file mode 100644 index 8d1ffb2..0000000 --- a/include/nvgpu/hw/gm20b/hw_pri_ringstation_gpc_gm20b.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pri_ringstation_gpc_gm20b_h_ -#define _hw_pri_ringstation_gpc_gm20b_h_ - -static inline u32 pri_ringstation_gpc_master_config_r(u32 i) -{ - return 0x00128300U + i*4U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void) -{ - return 0x00128120U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void) -{ - return 0x00128124U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void) -{ - return 0x00128128U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void) -{ - return 0x0012812cU; -} -#endif diff --git a/include/nvgpu/hw/gm20b/hw_pri_ringstation_sys_gm20b.h b/include/nvgpu/hw/gm20b/hw_pri_ringstation_sys_gm20b.h deleted file mode 100644 index ac1d245..0000000 --- a/include/nvgpu/hw/gm20b/hw_pri_ringstation_sys_gm20b.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pri_ringstation_sys_gm20b_h_ -#define _hw_pri_ringstation_sys_gm20b_h_ - -static inline u32 pri_ringstation_sys_master_config_r(u32 i) -{ - return 0x00122300U + i*4U; -} -static inline u32 pri_ringstation_sys_decode_config_r(void) -{ - return 0x00122204U; -} -static inline u32 pri_ringstation_sys_decode_config_ring_m(void) -{ - return 0x7U << 0U; -} -static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringstation_sys_priv_error_adr_r(void) -{ - return 0x00122120U; -} -static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void) -{ - return 0x00122124U; -} -static inline u32 pri_ringstation_sys_priv_error_info_r(void) -{ - return 0x00122128U; -} -static inline u32 pri_ringstation_sys_priv_error_code_r(void) -{ - return 0x0012212cU; -} -#endif diff --git a/include/nvgpu/hw/gm20b/hw_proj_gm20b.h b/include/nvgpu/hw/gm20b/hw_proj_gm20b.h deleted file mode 100644 index 8129ea6..0000000 --- a/include/nvgpu/hw/gm20b/hw_proj_gm20b.h +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_proj_gm20b_h_ -#define _hw_proj_gm20b_h_ - -static inline u32 proj_gpc_base_v(void) -{ - return 0x00500000U; -} -static inline u32 proj_gpc_shared_base_v(void) -{ - return 0x00418000U; -} -static inline u32 proj_gpc_stride_v(void) -{ - return 0x00008000U; -} -static inline u32 proj_gpc_priv_stride_v(void) -{ - return 0x00000800U; -} -static inline u32 proj_ltc_stride_v(void) -{ - return 0x00002000U; -} -static inline u32 proj_lts_stride_v(void) -{ - return 0x00000200U; -} -static inline u32 proj_fbpa_stride_v(void) -{ - return 0x00001000U; -} -static inline u32 proj_ppc_in_gpc_base_v(void) -{ - return 0x00003000U; -} -static inline u32 proj_ppc_in_gpc_shared_base_v(void) -{ - return 0x00003e00U; -} -static inline u32 proj_ppc_in_gpc_stride_v(void) -{ - return 0x00000200U; -} -static inline u32 proj_rop_base_v(void) -{ - return 0x00410000U; -} -static inline u32 proj_rop_shared_base_v(void) -{ - return 0x00408800U; -} -static inline u32 proj_rop_stride_v(void) -{ - return 0x00000400U; -} -static inline u32 proj_tpc_in_gpc_base_v(void) -{ - return 0x00004000U; -} -static inline u32 proj_tpc_in_gpc_stride_v(void) -{ - return 0x00000800U; -} -static inline u32 proj_tpc_in_gpc_shared_base_v(void) -{ - return 0x00001800U; -} -static inline u32 proj_host_num_engines_v(void) -{ - return 0x00000002U; -} -static inline u32 proj_host_num_pbdma_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) -{ - return 0x00000002U; -} -static inline u32 proj_scal_litter_num_sm_per_tpc_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_fbps_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_fbpas_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_gpcs_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) -{ - return 0x00000002U; -} -static inline u32 proj_scal_litter_num_zcull_banks_v(void) -{ - return 0x00000004U; -} -static inline u32 proj_scal_max_gpcs_v(void) -{ - return 0x00000020U; -} -static inline u32 proj_scal_max_tpc_per_gpc_v(void) -{ - return 0x00000008U; -} -#endif diff --git a/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h b/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h deleted file mode 100644 index a7c409d..0000000 --- a/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h +++ /dev/null @@ -1,879 +0,0 @@ -/* - * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pwr_gm20b_h_ -#define _hw_pwr_gm20b_h_ - -static inline u32 pwr_falcon_irqsset_r(void) -{ - return 0x0010a000U; -} -static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 pwr_falcon_irqsclr_r(void) -{ - return 0x0010a004U; -} -static inline u32 pwr_falcon_irqstat_r(void) -{ - return 0x0010a008U; -} -static inline u32 pwr_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 pwr_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 pwr_falcon_irqmode_r(void) -{ - return 0x0010a00cU; -} -static inline u32 pwr_falcon_irqmset_r(void) -{ - return 0x0010a010U; -} -static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqmclr_r(void) -{ - return 0x0010a014U; -} -static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqmask_r(void) -{ - return 0x0010a018U; -} -static inline u32 pwr_falcon_irqdest_r(void) -{ - return 0x0010a01cU; -} -static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 pwr_falcon_curctx_r(void) -{ - return 0x0010a050U; -} -static inline u32 pwr_falcon_nxtctx_r(void) -{ - return 0x0010a054U; -} -static inline u32 pwr_falcon_mailbox0_r(void) -{ - return 0x0010a040U; -} -static inline u32 pwr_falcon_mailbox1_r(void) -{ - return 0x0010a044U; -} -static inline u32 pwr_falcon_itfen_r(void) -{ - return 0x0010a048U; -} -static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 pwr_falcon_idlestate_r(void) -{ - return 0x0010a04cU; -} -static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 pwr_falcon_os_r(void) -{ - return 0x0010a080U; -} -static inline u32 pwr_falcon_engctl_r(void) -{ - return 0x0010a0a4U; -} -static inline u32 pwr_falcon_cpuctl_r(void) -{ - return 0x0010a100U; -} -static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) -{ - return 0x1U << 4U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void) -{ - return 0x1U << 6U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 pwr_falcon_cpuctl_alias_r(void) -{ - return 0x0010a130U; -} -static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_pmu_scpctl_stat_r(void) -{ - return 0x0010ac08U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void) -{ - return 0x1U << 20U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 pwr_falcon_imemc_r(u32 i) -{ - return 0x0010a180U + i*16U; -} -static inline u32 pwr_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pwr_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_imemd_r(u32 i) -{ - return 0x0010a184U + i*16U; -} -static inline u32 pwr_falcon_imemt_r(u32 i) -{ - return 0x0010a188U + i*16U; -} -static inline u32 pwr_falcon_sctl_r(void) -{ - return 0x0010a240U; -} -static inline u32 pwr_falcon_mmu_phys_sec_r(void) -{ - return 0x00100ce4U; -} -static inline u32 pwr_falcon_bootvec_r(void) -{ - return 0x0010a104U; -} -static inline u32 pwr_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_falcon_dmactl_r(void) -{ - return 0x0010a10cU; -} -static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) -{ - return 0x1U << 1U; -} -static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) -{ - return 0x1U << 2U; -} -static inline u32 pwr_falcon_hwcfg_r(void) -{ - return 0x0010a108U; -} -static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 pwr_falcon_dmatrfbase_r(void) -{ - return 0x0010a110U; -} -static inline u32 pwr_falcon_dmatrfmoffs_r(void) -{ - return 0x0010a114U; -} -static inline u32 pwr_falcon_dmatrfcmd_r(void) -{ - return 0x0010a118U; -} -static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 pwr_falcon_dmatrffboffs_r(void) -{ - return 0x0010a11cU; -} -static inline u32 pwr_falcon_exterraddr_r(void) -{ - return 0x0010a168U; -} -static inline u32 pwr_falcon_exterrstat_r(void) -{ - return 0x0010a16cU; -} -static inline u32 pwr_falcon_exterrstat_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 pwr_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_r(void) -{ - return 0x0010a200U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) -{ - return 0xfU << 0U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 pwr_pmu_falcon_icd_rdata_r(void) -{ - return 0x0010a20cU; -} -static inline u32 pwr_falcon_dmemc_r(u32 i) -{ - return 0x0010a1c0U + i*8U; -} -static inline u32 pwr_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pwr_falcon_dmemc_offs_m(void) -{ - return 0x3fU << 2U; -} -static inline u32 pwr_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_dmemc_blk_m(void) -{ - return 0xffU << 8U; -} -static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 pwr_falcon_dmemd_r(u32 i) -{ - return 0x0010a1c4U + i*8U; -} -static inline u32 pwr_pmu_new_instblk_r(void) -{ - return 0x0010a480U; -} -static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 pwr_pmu_new_instblk_target_fb_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 pwr_pmu_mutex_id_r(void) -{ - return 0x0010a488U; -} -static inline u32 pwr_pmu_mutex_id_value_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pwr_pmu_mutex_id_value_init_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) -{ - return 0x000000ffU; -} -static inline u32 pwr_pmu_mutex_id_release_r(void) -{ - return 0x0010a48cU; -} -static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_id_release_value_m(void) -{ - return 0xffU << 0U; -} -static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_mutex_r(u32 i) -{ - return 0x0010a580U + i*4U; -} -static inline u32 pwr_pmu_mutex__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 pwr_pmu_mutex_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_value_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_queue_head_r(u32 i) -{ - return 0x0010a4a0U + i*4U; -} -static inline u32 pwr_pmu_queue_head__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 pwr_pmu_queue_head_address_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_queue_head_address_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_queue_tail_r(u32 i) -{ - return 0x0010a4b0U + i*4U; -} -static inline u32 pwr_pmu_queue_tail__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 pwr_pmu_queue_tail_address_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_queue_tail_address_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_msgq_head_r(void) -{ - return 0x0010a4c8U; -} -static inline u32 pwr_pmu_msgq_head_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_msgq_head_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_msgq_tail_r(void) -{ - return 0x0010a4ccU; -} -static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_idle_mask_r(u32 i) -{ - return 0x0010a504U + i*16U; -} -static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) -{ - return 0x1U; -} -static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 pwr_pmu_idle_mask_1_r(u32 i) -{ - return 0x0010aa34U + i*8U; -} -static inline u32 pwr_pmu_idle_count_r(u32 i) -{ - return 0x0010a508U + i*16U; -} -static inline u32 pwr_pmu_idle_count_value_f(u32 v) -{ - return (v & 0x7fffffffU) << 0U; -} -static inline u32 pwr_pmu_idle_count_value_v(u32 r) -{ - return (r >> 0U) & 0x7fffffffU; -} -static inline u32 pwr_pmu_idle_count_reset_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 pwr_pmu_idle_ctrl_r(u32 i) -{ - return 0x0010a50cU + i*16U; -} -static inline u32 pwr_pmu_idle_ctrl_value_m(void) -{ - return 0x3U << 0U; -} -static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) -{ - return 0x2U; -} -static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) -{ - return 0x3U; -} -static inline u32 pwr_pmu_idle_ctrl_filter_m(void) -{ - return 0x1U << 2U; -} -static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_idle_threshold_r(u32 i) -{ - return 0x0010a8a0U + i*4U; -} -static inline u32 pwr_pmu_idle_threshold_value_f(u32 v) -{ - return (v & 0x7fffffffU) << 0U; -} -static inline u32 pwr_pmu_idle_intr_r(void) -{ - return 0x0010a9e8U; -} -static inline u32 pwr_pmu_idle_intr_en_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_en_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_idle_intr_en_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_intr_status_r(void) -{ - return 0x0010a9ecU; -} -static inline u32 pwr_pmu_idle_intr_status_intr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_m(void) -{ - return 0x1U << 0U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) -{ - return 0x0010a9f0U + i*8U; -} -static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) -{ - return 0x0010a9f4U + i*8U; -} -static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) -{ - return 0x0010aa30U + i*8U; -} -static inline u32 pwr_pmu_debug_r(u32 i) -{ - return 0x0010a5c0U + i*4U; -} -static inline u32 pwr_pmu_debug__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 pwr_pmu_mailbox_r(u32 i) -{ - return 0x0010a450U + i*4U; -} -static inline u32 pwr_pmu_mailbox__size_1_v(void) -{ - return 0x0000000cU; -} -static inline u32 pwr_pmu_bar0_addr_r(void) -{ - return 0x0010a7a0U; -} -static inline u32 pwr_pmu_bar0_data_r(void) -{ - return 0x0010a7a4U; -} -static inline u32 pwr_pmu_bar0_ctl_r(void) -{ - return 0x0010a7acU; -} -static inline u32 pwr_pmu_bar0_timeout_r(void) -{ - return 0x0010a7a8U; -} -static inline u32 pwr_pmu_bar0_fecs_error_r(void) -{ - return 0x0010a988U; -} -static inline u32 pwr_pmu_bar0_error_status_r(void) -{ - return 0x0010a7b0U; -} -static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) -{ - return 0x0010a6c0U + i*4U; -} -static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) -{ - return 0x0010a6e8U + i*4U; -} -static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) -{ - return 0x0010a710U + i*4U; -} -static inline u32 pwr_pmu_pg_intren_r(u32 i) -{ - return 0x0010a760U + i*4U; -} -static inline u32 pwr_fbif_transcfg_r(u32 i) -{ - return 0x0010ae00U + i*4U; -} -static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) -{ - return 0x0U; -} -static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) -{ - return 0x1U; -} -static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) -{ - return 0x2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_s(void) -{ - return 1U; -} -static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_m(void) -{ - return 0x1U << 2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) -{ - return 0x0U; -} -static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) -{ - return 0x4U; -} -#endif diff --git a/include/nvgpu/hw/gm20b/hw_ram_gm20b.h b/include/nvgpu/hw/gm20b/hw_ram_gm20b.h deleted file mode 100644 index 2414abf..0000000 --- a/include/nvgpu/hw/gm20b/hw_ram_gm20b.h +++ /dev/null @@ -1,459 +0,0 @@ -/* - * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ram_gm20b_h_ -#define _hw_ram_gm20b_h_ - -static inline u32 ram_in_ramfc_s(void) -{ - return 4096U; -} -static inline u32 ram_in_ramfc_w(void) -{ - return 0U; -} -static inline u32 ram_in_page_dir_base_target_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ram_in_page_dir_base_target_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 ram_in_page_dir_base_vol_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_vol_true_f(void) -{ - return 0x4U; -} -static inline u32 ram_in_big_page_size_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 ram_in_big_page_size_m(void) -{ - return 0x1U << 11U; -} -static inline u32 ram_in_big_page_size_w(void) -{ - return 128U; -} -static inline u32 ram_in_big_page_size_128kb_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_big_page_size_64kb_f(void) -{ - return 0x800U; -} -static inline u32 ram_in_page_dir_base_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_page_dir_base_lo_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_hi_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ram_in_page_dir_base_hi_w(void) -{ - return 129U; -} -static inline u32 ram_in_adr_limit_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_adr_limit_lo_w(void) -{ - return 130U; -} -static inline u32 ram_in_adr_limit_hi_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ram_in_adr_limit_hi_w(void) -{ - return 131U; -} -static inline u32 ram_in_engine_cs_w(void) -{ - return 132U; -} -static inline u32 ram_in_engine_cs_wfi_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_engine_cs_wfi_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_engine_cs_fg_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_engine_cs_fg_f(void) -{ - return 0x8U; -} -static inline u32 ram_in_gr_cs_w(void) -{ - return 132U; -} -static inline u32 ram_in_gr_cs_wfi_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_gr_wfi_target_w(void) -{ - return 132U; -} -static inline u32 ram_in_gr_wfi_mode_w(void) -{ - return 132U; -} -static inline u32 ram_in_gr_wfi_mode_physical_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_gr_wfi_mode_physical_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_gr_wfi_mode_virtual_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_gr_wfi_mode_virtual_f(void) -{ - return 0x4U; -} -static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_gr_wfi_ptr_lo_w(void) -{ - return 132U; -} -static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ram_in_gr_wfi_ptr_hi_w(void) -{ - return 133U; -} -static inline u32 ram_in_base_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 ram_in_alloc_size_v(void) -{ - return 0x00001000U; -} -static inline u32 ram_fc_size_val_v(void) -{ - return 0x00000200U; -} -static inline u32 ram_fc_gp_put_w(void) -{ - return 0U; -} -static inline u32 ram_fc_userd_w(void) -{ - return 2U; -} -static inline u32 ram_fc_userd_hi_w(void) -{ - return 3U; -} -static inline u32 ram_fc_signature_w(void) -{ - return 4U; -} -static inline u32 ram_fc_gp_get_w(void) -{ - return 5U; -} -static inline u32 ram_fc_pb_get_w(void) -{ - return 6U; -} -static inline u32 ram_fc_pb_get_hi_w(void) -{ - return 7U; -} -static inline u32 ram_fc_pb_top_level_get_w(void) -{ - return 8U; -} -static inline u32 ram_fc_pb_top_level_get_hi_w(void) -{ - return 9U; -} -static inline u32 ram_fc_acquire_w(void) -{ - return 12U; -} -static inline u32 ram_fc_semaphorea_w(void) -{ - return 14U; -} -static inline u32 ram_fc_semaphoreb_w(void) -{ - return 15U; -} -static inline u32 ram_fc_semaphorec_w(void) -{ - return 16U; -} -static inline u32 ram_fc_semaphored_w(void) -{ - return 17U; -} -static inline u32 ram_fc_gp_base_w(void) -{ - return 18U; -} -static inline u32 ram_fc_gp_base_hi_w(void) -{ - return 19U; -} -static inline u32 ram_fc_gp_fetch_w(void) -{ - return 20U; -} -static inline u32 ram_fc_pb_fetch_w(void) -{ - return 21U; -} -static inline u32 ram_fc_pb_fetch_hi_w(void) -{ - return 22U; -} -static inline u32 ram_fc_pb_put_w(void) -{ - return 23U; -} -static inline u32 ram_fc_pb_put_hi_w(void) -{ - return 24U; -} -static inline u32 ram_fc_pb_header_w(void) -{ - return 33U; -} -static inline u32 ram_fc_pb_count_w(void) -{ - return 34U; -} -static inline u32 ram_fc_subdevice_w(void) -{ - return 37U; -} -static inline u32 ram_fc_formats_w(void) -{ - return 39U; -} -static inline u32 ram_fc_syncpointa_w(void) -{ - return 41U; -} -static inline u32 ram_fc_syncpointb_w(void) -{ - return 42U; -} -static inline u32 ram_fc_target_w(void) -{ - return 43U; -} -static inline u32 ram_fc_hce_ctrl_w(void) -{ - return 57U; -} -static inline u32 ram_fc_chid_w(void) -{ - return 58U; -} -static inline u32 ram_fc_chid_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_fc_chid_id_w(void) -{ - return 0U; -} -static inline u32 ram_fc_runlist_timeslice_w(void) -{ - return 62U; -} -static inline u32 ram_userd_base_shift_v(void) -{ - return 0x00000009U; -} -static inline u32 ram_userd_chan_size_v(void) -{ - return 0x00000200U; -} -static inline u32 ram_userd_put_w(void) -{ - return 16U; -} -static inline u32 ram_userd_get_w(void) -{ - return 17U; -} -static inline u32 ram_userd_ref_w(void) -{ - return 18U; -} -static inline u32 ram_userd_put_hi_w(void) -{ - return 19U; -} -static inline u32 ram_userd_ref_threshold_w(void) -{ - return 20U; -} -static inline u32 ram_userd_top_level_get_w(void) -{ - return 22U; -} -static inline u32 ram_userd_top_level_get_hi_w(void) -{ - return 23U; -} -static inline u32 ram_userd_get_hi_w(void) -{ - return 24U; -} -static inline u32 ram_userd_gp_get_w(void) -{ - return 34U; -} -static inline u32 ram_userd_gp_put_w(void) -{ - return 35U; -} -static inline u32 ram_userd_gp_top_level_get_w(void) -{ - return 22U; -} -static inline u32 ram_userd_gp_top_level_get_hi_w(void) -{ - return 23U; -} -static inline u32 ram_rl_entry_size_v(void) -{ - return 0x00000008U; -} -static inline u32 ram_rl_entry_chid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_type_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 ram_rl_entry_type_chid_f(void) -{ - return 0x0U; -} -static inline u32 ram_rl_entry_type_tsg_f(void) -{ - return 0x2000U; -} -static inline u32 ram_rl_entry_timeslice_scale_f(u32 v) -{ - return (v & 0xfU) << 14U; -} -static inline u32 ram_rl_entry_timeslice_scale_3_f(void) -{ - return 0xc000U; -} -static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v) -{ - return (v & 0xffU) << 18U; -} -static inline u32 ram_rl_entry_timeslice_timeout_128_f(void) -{ - return 0x2000000U; -} -static inline u32 ram_rl_entry_tsg_length_f(u32 v) -{ - return (v & 0x3fU) << 26U; -} -#endif diff --git a/include/nvgpu/hw/gm20b/hw_therm_gm20b.h b/include/nvgpu/hw/gm20b/hw_therm_gm20b.h deleted file mode 100644 index fc1cd51..0000000 --- a/include/nvgpu/hw/gm20b/hw_therm_gm20b.h +++ /dev/null @@ -1,355 +0,0 @@ -/* - * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_therm_gm20b_h_ -#define _hw_therm_gm20b_h_ - -static inline u32 therm_use_a_r(void) -{ - return 0x00020798U; -} -static inline u32 therm_use_a_ext_therm_0_enable_f(void) -{ - return 0x1U; -} -static inline u32 therm_use_a_ext_therm_1_enable_f(void) -{ - return 0x2U; -} -static inline u32 therm_use_a_ext_therm_2_enable_f(void) -{ - return 0x4U; -} -static inline u32 therm_evt_ext_therm_0_r(void) -{ - return 0x00020700U; -} -static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v) -{ - return (v & 0x3fU) << 8U; -} -static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void) -{ - return 0x00000000U; -} -static inline u32 therm_evt_ext_therm_1_r(void) -{ - return 0x00020704U; -} -static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v) -{ - return (v & 0x3fU) << 8U; -} -static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void) -{ - return 0x00000000U; -} -static inline u32 therm_evt_ext_therm_2_r(void) -{ - return 0x00020708U; -} -static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v) -{ - return (v & 0x3fU) << 8U; -} -static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void) -{ - return 0x00000000U; -} -static inline u32 therm_weight_1_r(void) -{ - return 0x00020024U; -} -static inline u32 therm_config1_r(void) -{ - return 0x00020050U; -} -static inline u32 therm_config2_r(void) -{ - return 0x00020130U; -} -static inline u32 therm_config2_slowdown_factor_extended_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 therm_config2_grad_enable_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 therm_gate_ctrl_r(u32 i) -{ - return 0x00020200U + i*4U; -} -static inline u32 therm_gate_ctrl_eng_clk_m(void) -{ - return 0x3U << 0U; -} -static inline u32 therm_gate_ctrl_eng_clk_run_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) -{ - return 0x1U; -} -static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) -{ - return 0x2U; -} -static inline u32 therm_gate_ctrl_blk_clk_m(void) -{ - return 0x3U << 2U; -} -static inline u32 therm_gate_ctrl_blk_clk_run_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) -{ - return 0x4U; -} -static inline u32 therm_gate_ctrl_eng_pwr_m(void) -{ - return 0x3U << 4U; -} -static inline u32 therm_gate_ctrl_eng_pwr_auto_f(void) -{ - return 0x10U; -} -static inline u32 therm_gate_ctrl_eng_pwr_off_v(void) -{ - return 0x00000002U; -} -static inline u32 therm_gate_ctrl_eng_pwr_off_f(void) -{ - return 0x20U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) -{ - return 0x1fU << 8U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) -{ - return (v & 0x7U) << 13U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) -{ - return 0x7U << 13U; -} -static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 therm_gate_ctrl_eng_delay_before_m(void) -{ - return 0xfU << 16U; -} -static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 therm_gate_ctrl_eng_delay_after_m(void) -{ - return 0xfU << 20U; -} -static inline u32 therm_fecs_idle_filter_r(void) -{ - return 0x00020288U; -} -static inline u32 therm_fecs_idle_filter_value_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 therm_hubmmu_idle_filter_r(void) -{ - return 0x0002028cU; -} -static inline u32 therm_hubmmu_idle_filter_value_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 therm_clk_slowdown_r(u32 i) -{ - return 0x00020160U + i*4U; -} -static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) -{ - return (v & 0x3fU) << 16U; -} -static inline u32 therm_clk_slowdown_idle_factor_m(void) -{ - return 0x3fU << 16U; -} -static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) -{ - return (r >> 16U) & 0x3fU; -} -static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) -{ - return 0x0U; -} -static inline u32 therm_grad_stepping_table_r(u32 i) -{ - return 0x000202c8U + i*4U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void) -{ - return 0x1U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void) -{ - return 0x2U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void) -{ - return 0x6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void) -{ - return 0xeU; -} -static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v) -{ - return (v & 0x3fU) << 6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void) -{ - return 0x3fU << 6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) -{ - return (v & 0x3fU) << 12U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void) -{ - return 0x3fU << 12U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) -{ - return (v & 0x3fU) << 18U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void) -{ - return 0x3fU << 18U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) -{ - return (v & 0x3fU) << 24U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void) -{ - return 0x3fU << 24U; -} -static inline u32 therm_grad_stepping0_r(void) -{ - return 0x000202c0U; -} -static inline u32 therm_grad_stepping0_feature_s(void) -{ - return 1U; -} -static inline u32 therm_grad_stepping0_feature_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 therm_grad_stepping0_feature_m(void) -{ - return 0x1U << 0U; -} -static inline u32 therm_grad_stepping0_feature_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 therm_grad_stepping0_feature_enable_f(void) -{ - return 0x1U; -} -static inline u32 therm_grad_stepping1_r(void) -{ - return 0x000202c4U; -} -static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 therm_clk_timing_r(u32 i) -{ - return 0x000203c0U + i*4U; -} -static inline u32 therm_clk_timing_grad_slowdown_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 therm_clk_timing_grad_slowdown_m(void) -{ - return 0x1U << 16U; -} -static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void) -{ - return 0x10000U; -} -#endif diff --git a/include/nvgpu/hw/gm20b/hw_timer_gm20b.h b/include/nvgpu/hw/gm20b/hw_timer_gm20b.h deleted file mode 100644 index f409367..0000000 --- a/include/nvgpu/hw/gm20b/hw_timer_gm20b.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_timer_gm20b_h_ -#define _hw_timer_gm20b_h_ - -static inline u32 timer_pri_timeout_r(void) -{ - return 0x00009080U; -} -static inline u32 timer_pri_timeout_period_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 timer_pri_timeout_period_m(void) -{ - return 0xffffffU << 0U; -} -static inline u32 timer_pri_timeout_period_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 timer_pri_timeout_en_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 timer_pri_timeout_en_m(void) -{ - return 0x1U << 31U; -} -static inline u32 timer_pri_timeout_en_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 timer_pri_timeout_en_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 timer_pri_timeout_en_en_disabled_f(void) -{ - return 0x0U; -} -static inline u32 timer_pri_timeout_save_0_r(void) -{ - return 0x00009084U; -} -static inline u32 timer_pri_timeout_save_0_fecs_tgt_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 timer_pri_timeout_save_0_addr_v(u32 r) -{ - return (r >> 2U) & 0x3fffffU; -} -static inline u32 timer_pri_timeout_save_0_write_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 timer_pri_timeout_save_1_r(void) -{ - return 0x00009088U; -} -static inline u32 timer_pri_timeout_fecs_errcode_r(void) -{ - return 0x0000908cU; -} -static inline u32 timer_time_0_r(void) -{ - return 0x00009400U; -} -static inline u32 timer_time_1_r(void) -{ - return 0x00009410U; -} -#endif diff --git a/include/nvgpu/hw/gm20b/hw_top_gm20b.h b/include/nvgpu/hw/gm20b/hw_top_gm20b.h deleted file mode 100644 index 6d48839..0000000 --- a/include/nvgpu/hw/gm20b/hw_top_gm20b.h +++ /dev/null @@ -1,235 +0,0 @@ -/* - * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_top_gm20b_h_ -#define _hw_top_gm20b_h_ - -static inline u32 top_num_gpcs_r(void) -{ - return 0x00022430U; -} -static inline u32 top_num_gpcs_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_tpc_per_gpc_r(void) -{ - return 0x00022434U; -} -static inline u32 top_tpc_per_gpc_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_num_fbps_r(void) -{ - return 0x00022438U; -} -static inline u32 top_num_fbps_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_ltc_per_fbp_r(void) -{ - return 0x00022450U; -} -static inline u32 top_ltc_per_fbp_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_slices_per_ltc_r(void) -{ - return 0x0002245cU; -} -static inline u32 top_slices_per_ltc_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_num_ltcs_r(void) -{ - return 0x00022454U; -} -static inline u32 top_device_info_r(u32 i) -{ - return 0x00022700U + i*4U; -} -static inline u32 top_device_info__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 top_device_info_chain_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 top_device_info_chain_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_engine_enum_v(u32 r) -{ - return (r >> 26U) & 0xfU; -} -static inline u32 top_device_info_runlist_enum_v(u32 r) -{ - return (r >> 21U) & 0xfU; -} -static inline u32 top_device_info_intr_enum_v(u32 r) -{ - return (r >> 15U) & 0x1fU; -} -static inline u32 top_device_info_reset_enum_v(u32 r) -{ - return (r >> 9U) & 0x1fU; -} -static inline u32 top_device_info_type_enum_v(u32 r) -{ - return (r >> 2U) & 0x1fffffffU; -} -static inline u32 top_device_info_type_enum_graphics_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_type_enum_graphics_f(void) -{ - return 0x0U; -} -static inline u32 top_device_info_type_enum_copy0_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_type_enum_copy0_f(void) -{ - return 0x4U; -} -static inline u32 top_device_info_type_enum_copy1_v(void) -{ - return 0x00000002U; -} -static inline u32 top_device_info_type_enum_copy1_f(void) -{ - return 0x8U; -} -static inline u32 top_device_info_type_enum_copy2_v(void) -{ - return 0x00000003U; -} -static inline u32 top_device_info_type_enum_copy2_f(void) -{ - return 0xcU; -} -static inline u32 top_device_info_engine_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 top_device_info_runlist_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 top_device_info_intr_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 top_device_info_reset_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 top_device_info_entry_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 top_device_info_entry_not_valid_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_entry_enum_v(void) -{ - return 0x00000002U; -} -static inline u32 top_device_info_entry_engine_type_v(void) -{ - return 0x00000003U; -} -static inline u32 top_device_info_entry_data_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_data_type_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 top_device_info_data_type_enum2_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_data_pri_base_v(u32 r) -{ - return (r >> 12U) & 0x7ffU; -} -static inline u32 top_device_info_data_pri_base_align_v(void) -{ - return 0x0000000cU; -} -static inline u32 top_device_info_data_fault_id_enum_v(u32 r) -{ - return (r >> 3U) & 0x1fU; -} -static inline u32 top_device_info_data_fault_id_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 top_device_info_data_fault_id_valid_v(void) -{ - return 0x00000001U; -} -#endif diff --git a/include/nvgpu/hw/gm20b/hw_trim_gm20b.h b/include/nvgpu/hw/gm20b/hw_trim_gm20b.h deleted file mode 100644 index 8f0a77a..0000000 --- a/include/nvgpu/hw/gm20b/hw_trim_gm20b.h +++ /dev/null @@ -1,503 +0,0 @@ -/* - * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_trim_gm20b_h_ -#define _hw_trim_gm20b_h_ - -static inline u32 trim_sys_gpcpll_cfg_r(void) -{ - return 0x00137000U; -} -static inline u32 trim_sys_gpcpll_cfg_enable_m(void) -{ - return 0x1U << 0U; -} -static inline u32 trim_sys_gpcpll_cfg_enable_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 trim_sys_gpcpll_cfg_enable_no_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_gpcpll_cfg_enable_yes_f(void) -{ - return 0x1U; -} -static inline u32 trim_sys_gpcpll_cfg_iddq_m(void) -{ - return 0x1U << 1U; -} -static inline u32 trim_sys_gpcpll_cfg_iddq_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 trim_sys_gpcpll_cfg_iddq_power_on_v(void) -{ - return 0x00000000U; -} -static inline u32 trim_sys_gpcpll_cfg_sync_mode_m(void) -{ - return 0x1U << 2U; -} -static inline u32 trim_sys_gpcpll_cfg_sync_mode_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 trim_sys_gpcpll_cfg_sync_mode_enable_f(void) -{ - return 0x4U; -} -static inline u32 trim_sys_gpcpll_cfg_sync_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_m(void) -{ - return 0x1U << 4U; -} -static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_on_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_off_f(void) -{ - return 0x10U; -} -static inline u32 trim_sys_gpcpll_cfg_pll_lock_v(u32 r) -{ - return (r >> 17U) & 0x1U; -} -static inline u32 trim_sys_gpcpll_cfg_pll_lock_true_f(void) -{ - return 0x20000U; -} -static inline u32 trim_sys_gpcpll_coeff_r(void) -{ - return 0x00137004U; -} -static inline u32 trim_sys_gpcpll_coeff_mdiv_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 trim_sys_gpcpll_coeff_mdiv_m(void) -{ - return 0xffU << 0U; -} -static inline u32 trim_sys_gpcpll_coeff_mdiv_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 trim_sys_gpcpll_coeff_ndiv_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 trim_sys_gpcpll_coeff_ndiv_m(void) -{ - return 0xffU << 8U; -} -static inline u32 trim_sys_gpcpll_coeff_ndiv_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} -static inline u32 trim_sys_gpcpll_coeff_pldiv_f(u32 v) -{ - return (v & 0x3fU) << 16U; -} -static inline u32 trim_sys_gpcpll_coeff_pldiv_m(void) -{ - return 0x3fU << 16U; -} -static inline u32 trim_sys_gpcpll_coeff_pldiv_v(u32 r) -{ - return (r >> 16U) & 0x3fU; -} -static inline u32 trim_sys_sel_vco_r(void) -{ - return 0x00137100U; -} -static inline u32 trim_sys_sel_vco_gpc2clk_out_m(void) -{ - return 0x1U << 0U; -} -static inline u32 trim_sys_sel_vco_gpc2clk_out_init_v(void) -{ - return 0x00000000U; -} -static inline u32 trim_sys_sel_vco_gpc2clk_out_init_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_sel_vco_gpc2clk_out_bypass_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_sel_vco_gpc2clk_out_vco_f(void) -{ - return 0x1U; -} -static inline u32 trim_sys_gpc2clk_out_r(void) -{ - return 0x00137250U; -} -static inline u32 trim_sys_gpc2clk_out_bypdiv_s(void) -{ - return 6U; -} -static inline u32 trim_sys_gpc2clk_out_bypdiv_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 trim_sys_gpc2clk_out_bypdiv_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 trim_sys_gpc2clk_out_bypdiv_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 trim_sys_gpc2clk_out_bypdiv_by31_f(void) -{ - return 0x3cU; -} -static inline u32 trim_sys_gpc2clk_out_vcodiv_s(void) -{ - return 6U; -} -static inline u32 trim_sys_gpc2clk_out_vcodiv_f(u32 v) -{ - return (v & 0x3fU) << 8U; -} -static inline u32 trim_sys_gpc2clk_out_vcodiv_m(void) -{ - return 0x3fU << 8U; -} -static inline u32 trim_sys_gpc2clk_out_vcodiv_v(u32 r) -{ - return (r >> 8U) & 0x3fU; -} -static inline u32 trim_sys_gpc2clk_out_vcodiv_by1_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_gpc2clk_out_sdiv14_m(void) -{ - return 0x1U << 31U; -} -static inline u32 trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f(void) -{ - return 0x80000000U; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_r(u32 i) -{ - return 0x00134124U + i*512U; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(u32 v) -{ - return (v & 0x3fffU) << 0U; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void) -{ - return 0x10000U; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f(void) -{ - return 0x100000U; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f(void) -{ - return 0x1000000U; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_r(u32 i) -{ - return 0x00134128U + i*512U; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(u32 r) -{ - return (r >> 0U) & 0xfffffU; -} -static inline u32 trim_sys_gpcpll_cfg2_r(void) -{ - return 0x0013700cU; -} -static inline u32 trim_sys_gpcpll_cfg2_sdm_din_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 trim_sys_gpcpll_cfg2_sdm_din_m(void) -{ - return 0xffU << 0U; -} -static inline u32 trim_sys_gpcpll_cfg2_sdm_din_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 trim_sys_gpcpll_cfg2_sdm_din_new_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 trim_sys_gpcpll_cfg2_sdm_din_new_m(void) -{ - return 0xffU << 8U; -} -static inline u32 trim_sys_gpcpll_cfg2_sdm_din_new_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} -static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_m(void) -{ - return 0xffU << 24U; -} -static inline u32 trim_sys_gpcpll_cfg3_r(void) -{ - return 0x00137018U; -} -static inline u32 trim_sys_gpcpll_cfg3_vco_ctrl_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 trim_sys_gpcpll_cfg3_vco_ctrl_m(void) -{ - return 0x1ffU << 0U; -} -static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_m(void) -{ - return 0xffU << 16U; -} -static inline u32 trim_sys_gpcpll_cfg3_dfs_testout_v(u32 r) -{ - return (r >> 24U) & 0x7fU; -} -static inline u32 trim_sys_gpcpll_dvfs0_r(void) -{ - return 0x00137010U; -} -static inline u32 trim_sys_gpcpll_dvfs0_dfs_coeff_f(u32 v) -{ - return (v & 0x7fU) << 0U; -} -static inline u32 trim_sys_gpcpll_dvfs0_dfs_coeff_m(void) -{ - return 0x7fU << 0U; -} -static inline u32 trim_sys_gpcpll_dvfs0_dfs_coeff_v(u32 r) -{ - return (r >> 0U) & 0x7fU; -} -static inline u32 trim_sys_gpcpll_dvfs0_dfs_det_max_f(u32 v) -{ - return (v & 0x7fU) << 8U; -} -static inline u32 trim_sys_gpcpll_dvfs0_dfs_det_max_m(void) -{ - return 0x7fU << 8U; -} -static inline u32 trim_sys_gpcpll_dvfs0_dfs_det_max_v(u32 r) -{ - return (r >> 8U) & 0x7fU; -} -static inline u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset_f(u32 v) -{ - return (v & 0x3fU) << 16U; -} -static inline u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset_m(void) -{ - return 0x3fU << 16U; -} -static inline u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset_v(u32 r) -{ - return (r >> 16U) & 0x3fU; -} -static inline u32 trim_sys_gpcpll_dvfs0_mode_m(void) -{ - return 0x1U << 28U; -} -static inline u32 trim_sys_gpcpll_dvfs0_mode_dvfspll_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_gpcpll_dvfs1_r(void) -{ - return 0x00137014U; -} -static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_det_f(u32 v) -{ - return (v & 0x7fU) << 0U; -} -static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_det_m(void) -{ - return 0x7fU << 0U; -} -static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_det_v(u32 r) -{ - return (r >> 0U) & 0x7fU; -} -static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_strb_m(void) -{ - return 0x1U << 7U; -} -static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_cal_f(u32 v) -{ - return (v & 0x7fU) << 8U; -} -static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_cal_m(void) -{ - return 0x7fU << 8U; -} -static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_cal_v(u32 r) -{ - return (r >> 8U) & 0x7fU; -} -static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_sel_m(void) -{ - return 0x1U << 15U; -} -static inline u32 trim_sys_gpcpll_dvfs1_dfs_ctrl_f(u32 v) -{ - return (v & 0xfffU) << 16U; -} -static inline u32 trim_sys_gpcpll_dvfs1_dfs_ctrl_m(void) -{ - return 0xfffU << 16U; -} -static inline u32 trim_sys_gpcpll_dvfs1_dfs_ctrl_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 trim_sys_gpcpll_dvfs1_en_sdm_m(void) -{ - return 0x1U << 28U; -} -static inline u32 trim_sys_gpcpll_dvfs1_en_dfs_m(void) -{ - return 0x1U << 29U; -} -static inline u32 trim_sys_gpcpll_dvfs1_en_dfs_cal_m(void) -{ - return 0x1U << 30U; -} -static inline u32 trim_sys_gpcpll_dvfs1_dfs_cal_done_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 trim_sys_gpcpll_dvfs2_r(void) -{ - return 0x00137020U; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_r(void) -{ - return 0x0013701cU; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m(void) -{ - return 0x1U << 22U; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_yes_f(void) -{ - return 0x400000U; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_no_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(void) -{ - return 0x1U << 31U; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f(void) -{ - return 0x80000000U; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_no_f(void) -{ - return 0x0U; -} -static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r(void) -{ - return 0x001328a0U; -} -static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_synced_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 trim_gpc_bcast_gpcpll_dvfs2_r(void) -{ - return 0x00132820U; -} -static inline u32 trim_sys_bypassctrl_r(void) -{ - return 0x00137340U; -} -static inline u32 trim_sys_bypassctrl_gpcpll_m(void) -{ - return 0x1U << 0U; -} -static inline u32 trim_sys_bypassctrl_gpcpll_bypassclk_f(void) -{ - return 0x1U; -} -static inline u32 trim_sys_bypassctrl_gpcpll_vco_f(void) -{ - return 0x0U; -} -#endif diff --git a/include/nvgpu/hw/gp106/hw_bus_gp106.h b/include/nvgpu/hw/gp106/hw_bus_gp106.h deleted file mode 100644 index ce3aafd..0000000 --- a/include/nvgpu/hw/gp106/hw_bus_gp106.h +++ /dev/null @@ -1,223 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_bus_gp106_h_ -#define _hw_bus_gp106_h_ - -static inline u32 bus_bar0_window_r(void) -{ - return 0x00001700U; -} -static inline u32 bus_bar0_window_base_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 bus_bar0_window_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) -{ - return 0x2000000U; -} -static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) -{ - return 0x3000000U; -} -static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) -{ - return 0x00000010U; -} -static inline u32 bus_bar1_block_r(void) -{ - return 0x00001704U; -} -static inline u32 bus_bar1_block_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 bus_bar1_block_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar1_block_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 bus_bar1_block_mode_virtual_f(void) -{ - return 0x80000000U; -} -static inline u32 bus_bar2_block_r(void) -{ - return 0x00001714U; -} -static inline u32 bus_bar2_block_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 bus_bar2_block_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar2_block_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 bus_bar2_block_mode_virtual_f(void) -{ - return 0x80000000U; -} -static inline u32 bus_bar1_block_ptr_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 bus_bar2_block_ptr_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 bus_bind_status_r(void) -{ - return 0x00001710U; -} -static inline u32 bus_bind_status_bar1_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 bus_bind_status_bar1_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar1_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 bus_bind_status_bar1_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 bus_bind_status_bar1_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar1_outstanding_true_f(void) -{ - return 0x2U; -} -static inline u32 bus_bind_status_bar2_pending_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 bus_bind_status_bar2_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar2_pending_busy_f(void) -{ - return 0x4U; -} -static inline u32 bus_bind_status_bar2_outstanding_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 bus_bind_status_bar2_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar2_outstanding_true_f(void) -{ - return 0x8U; -} -static inline u32 bus_intr_0_r(void) -{ - return 0x00001100U; -} -static inline u32 bus_intr_0_pri_squash_m(void) -{ - return 0x1U << 1U; -} -static inline u32 bus_intr_0_pri_fecserr_m(void) -{ - return 0x1U << 2U; -} -static inline u32 bus_intr_0_pri_timeout_m(void) -{ - return 0x1U << 3U; -} -static inline u32 bus_intr_en_0_r(void) -{ - return 0x00001140U; -} -static inline u32 bus_intr_en_0_pri_squash_m(void) -{ - return 0x1U << 1U; -} -static inline u32 bus_intr_en_0_pri_fecserr_m(void) -{ - return 0x1U << 2U; -} -static inline u32 bus_intr_en_0_pri_timeout_m(void) -{ - return 0x1U << 3U; -} -#endif diff --git a/include/nvgpu/hw/gp106/hw_ccsr_gp106.h b/include/nvgpu/hw/gp106/hw_ccsr_gp106.h deleted file mode 100644 index cd63777..0000000 --- a/include/nvgpu/hw/gp106/hw_ccsr_gp106.h +++ /dev/null @@ -1,163 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ccsr_gp106_h_ -#define _hw_ccsr_gp106_h_ - -static inline u32 ccsr_channel_inst_r(u32 i) -{ - return 0x00800000U + i*8U; -} -static inline u32 ccsr_channel_inst__size_1_v(void) -{ - return 0x00001000U; -} -static inline u32 ccsr_channel_inst_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 ccsr_channel_inst_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 ccsr_channel_inst_bind_false_f(void) -{ - return 0x0U; -} -static inline u32 ccsr_channel_inst_bind_true_f(void) -{ - return 0x80000000U; -} -static inline u32 ccsr_channel_r(u32 i) -{ - return 0x00800004U + i*8U; -} -static inline u32 ccsr_channel__size_1_v(void) -{ - return 0x00001000U; -} -static inline u32 ccsr_channel_enable_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ccsr_channel_enable_set_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 ccsr_channel_enable_set_true_f(void) -{ - return 0x400U; -} -static inline u32 ccsr_channel_enable_clr_true_f(void) -{ - return 0x800U; -} -static inline u32 ccsr_channel_status_v(u32 r) -{ - return (r >> 24U) & 0xfU; -} -static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) -{ - return 0x00000002U; -} -static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) -{ - return 0x00000004U; -} -static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) -{ - return 0x0000000aU; -} -static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) -{ - return 0x0000000bU; -} -static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) -{ - return 0x0000000cU; -} -static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) -{ - return 0x0000000dU; -} -static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) -{ - return 0x0000000eU; -} -static inline u32 ccsr_channel_next_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ccsr_channel_next_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_force_ctx_reload_true_f(void) -{ - return 0x100U; -} -static inline u32 ccsr_channel_busy_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -#endif diff --git a/include/nvgpu/hw/gp106/hw_ce_gp106.h b/include/nvgpu/hw/gp106/hw_ce_gp106.h deleted file mode 100644 index 8892f42..0000000 --- a/include/nvgpu/hw/gp106/hw_ce_gp106.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ce_gp106_h_ -#define _hw_ce_gp106_h_ - -static inline u32 ce_intr_status_r(u32 i) -{ - return 0x00104410U + i*128U; -} -static inline u32 ce_intr_status_blockpipe_pending_f(void) -{ - return 0x1U; -} -static inline u32 ce_intr_status_blockpipe_reset_f(void) -{ - return 0x1U; -} -static inline u32 ce_intr_status_nonblockpipe_pending_f(void) -{ - return 0x2U; -} -static inline u32 ce_intr_status_nonblockpipe_reset_f(void) -{ - return 0x2U; -} -static inline u32 ce_intr_status_launcherr_pending_f(void) -{ - return 0x4U; -} -static inline u32 ce_intr_status_launcherr_reset_f(void) -{ - return 0x4U; -} -#endif diff --git a/include/nvgpu/hw/gp106/hw_ctxsw_prog_gp106.h b/include/nvgpu/hw/gp106/hw_ctxsw_prog_gp106.h deleted file mode 100644 index 3387d23..0000000 --- a/include/nvgpu/hw/gp106/hw_ctxsw_prog_gp106.h +++ /dev/null @@ -1,295 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ctxsw_prog_gp106_h_ -#define _hw_ctxsw_prog_gp106_h_ - -static inline u32 ctxsw_prog_fecs_header_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) -{ - return 0x00000008U; -} -static inline u32 ctxsw_prog_main_image_patch_count_o(void) -{ - return 0x00000010U; -} -static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) -{ - return 0x00000014U; -} -static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) -{ - return 0x00000018U; -} -static inline u32 ctxsw_prog_main_image_zcull_o(void) -{ - return 0x0000001cU; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) -{ - return 0x00000001U; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) -{ - return 0x00000020U; -} -static inline u32 ctxsw_prog_main_image_pm_o(void) -{ - return 0x00000028U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_m(void) -{ - return 0x7U << 0U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) -{ - return 0x7U << 3U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) -{ - return 0x8U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) -{ - return 0x0000002cU; -} -static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) -{ - return 0x000000f4U; -} -static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void) -{ - return 0x000000d0U; -} -static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void) -{ - return 0x000000d4U; -} -static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void) -{ - return 0x000000d8U; -} -static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void) -{ - return 0x000000dcU; -} -static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) -{ - return 0x000000f8U; -} -static inline u32 ctxsw_prog_main_image_magic_value_o(void) -{ - return 0x000000fcU; -} -static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) -{ - return 0x600dc0deU; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_ppc_info_o(void) -{ - return 0x000000f4U; -} -static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) -{ - return 0x000000f8U; -} -static inline u32 ctxsw_prog_local_magic_value_o(void) -{ - return 0x000000fcU; -} -static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) -{ - return 0xad0becabU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) -{ - return 0x000000ecU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) -{ - return 0x00000000U; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) -{ - return 0x000000a0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) -{ - return 2U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) -{ - return 0x3U << 0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) -{ - return 0x2U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) -{ - return 0x000000a4U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) -{ - return 0x000000a8U; -} -static inline u32 ctxsw_prog_main_image_misc_options_o(void) -{ - return 0x0000003cU; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) -{ - return 0x1U << 3U; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void) -{ - return 0x00000080U; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void) -{ - return 0x1U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void) -{ - return 0x00000068U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void) -{ - return 0x00000084U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void) -{ - return 0x1U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void) -{ - return 0x2U; -} -#endif diff --git a/include/nvgpu/hw/gp106/hw_falcon_gp106.h b/include/nvgpu/hw/gp106/hw_falcon_gp106.h deleted file mode 100644 index d899e3f..0000000 --- a/include/nvgpu/hw/gp106/hw_falcon_gp106.h +++ /dev/null @@ -1,603 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_falcon_gp106_h_ -#define _hw_falcon_gp106_h_ - -static inline u32 falcon_falcon_irqsset_r(void) -{ - return 0x00000000U; -} -static inline u32 falcon_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 falcon_falcon_irqsclr_r(void) -{ - return 0x00000004U; -} -static inline u32 falcon_falcon_irqstat_r(void) -{ - return 0x00000008U; -} -static inline u32 falcon_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 falcon_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 falcon_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 falcon_falcon_irqmode_r(void) -{ - return 0x0000000cU; -} -static inline u32 falcon_falcon_irqmset_r(void) -{ - return 0x00000010U; -} -static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqmclr_r(void) -{ - return 0x00000014U; -} -static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_irqmask_r(void) -{ - return 0x00000018U; -} -static inline u32 falcon_falcon_irqdest_r(void) -{ - return 0x0000001cU; -} -static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 falcon_falcon_curctx_r(void) -{ - return 0x00000050U; -} -static inline u32 falcon_falcon_nxtctx_r(void) -{ - return 0x00000054U; -} -static inline u32 falcon_falcon_mailbox0_r(void) -{ - return 0x00000040U; -} -static inline u32 falcon_falcon_mailbox1_r(void) -{ - return 0x00000044U; -} -static inline u32 falcon_falcon_itfen_r(void) -{ - return 0x00000048U; -} -static inline u32 falcon_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 falcon_falcon_idlestate_r(void) -{ - return 0x0000004cU; -} -static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 falcon_falcon_os_r(void) -{ - return 0x00000080U; -} -static inline u32 falcon_falcon_engctl_r(void) -{ - return 0x000000a4U; -} -static inline u32 falcon_falcon_cpuctl_r(void) -{ - return 0x00000100U; -} -static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_m(void) -{ - return 0x1U << 4U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 falcon_falcon_cpuctl_stopped_m(void) -{ - return 0x1U << 5U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void) -{ - return 0x1U << 6U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 falcon_falcon_cpuctl_alias_r(void) -{ - return 0x00000130U; -} -static inline u32 falcon_falcon_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_imemc_r(u32 i) -{ - return 0x00000180U + i*16U; -} -static inline u32 falcon_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 falcon_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 falcon_falcon_imemc_secure_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 falcon_falcon_imemd_r(u32 i) -{ - return 0x00000184U + i*16U; -} -static inline u32 falcon_falcon_imemt_r(u32 i) -{ - return 0x00000188U + i*16U; -} -static inline u32 falcon_falcon_sctl_r(void) -{ - return 0x00000240U; -} -static inline u32 falcon_falcon_mmu_phys_sec_r(void) -{ - return 0x00100ce4U; -} -static inline u32 falcon_falcon_bootvec_r(void) -{ - return 0x00000104U; -} -static inline u32 falcon_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 falcon_falcon_dmactl_r(void) -{ - return 0x0000010cU; -} -static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void) -{ - return 0x1U << 1U; -} -static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void) -{ - return 0x1U << 2U; -} -static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_hwcfg_r(void) -{ - return 0x00000108U; -} -static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 falcon_falcon_dmatrfbase_r(void) -{ - return 0x00000110U; -} -static inline u32 falcon_falcon_dmatrfbase1_r(void) -{ - return 0x00000128U; -} -static inline u32 falcon_falcon_dmatrfmoffs_r(void) -{ - return 0x00000114U; -} -static inline u32 falcon_falcon_dmatrfcmd_r(void) -{ - return 0x00000118U; -} -static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 falcon_falcon_dmatrffboffs_r(void) -{ - return 0x0000011cU; -} -static inline u32 falcon_falcon_imctl_debug_r(void) -{ - return 0x0000015cU; -} -static inline u32 falcon_falcon_imctl_debug_addr_blk_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 falcon_falcon_imctl_debug_cmd_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 falcon_falcon_imstat_r(void) -{ - return 0x00000144U; -} -static inline u32 falcon_falcon_traceidx_r(void) -{ - return 0x00000148U; -} -static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 falcon_falcon_traceidx_idx_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 falcon_falcon_tracepc_r(void) -{ - return 0x0000014cU; -} -static inline u32 falcon_falcon_tracepc_pc_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 falcon_falcon_exterraddr_r(void) -{ - return 0x00000168U; -} -static inline u32 falcon_falcon_exterrstat_r(void) -{ - return 0x0000016cU; -} -static inline u32 falcon_falcon_exterrstat_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 falcon_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 falcon_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 falcon_falcon_icd_cmd_r(void) -{ - return 0x00000200U; -} -static inline u32 falcon_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 falcon_falcon_icd_cmd_opc_m(void) -{ - return 0xfU << 0U; -} -static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 falcon_falcon_icd_rdata_r(void) -{ - return 0x0000020cU; -} -static inline u32 falcon_falcon_dmemc_r(u32 i) -{ - return 0x000001c0U + i*8U; -} -static inline u32 falcon_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 falcon_falcon_dmemc_offs_m(void) -{ - return 0x3fU << 2U; -} -static inline u32 falcon_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_dmemc_blk_m(void) -{ - return 0xffU << 8U; -} -static inline u32 falcon_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 falcon_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 falcon_falcon_dmemd_r(u32 i) -{ - return 0x000001c4U + i*8U; -} -static inline u32 falcon_falcon_debug1_r(void) -{ - return 0x00000090U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void) -{ - return 1U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void) -{ - return 0x1U << 16U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void) -{ - return 0x0U; -} -static inline u32 falcon_falcon_debuginfo_r(void) -{ - return 0x00000094U; -} -#endif diff --git a/include/nvgpu/hw/gp106/hw_fb_gp106.h b/include/nvgpu/hw/gp106/hw_fb_gp106.h deleted file mode 100644 index 1c2a1ac..0000000 --- a/include/nvgpu/hw/gp106/hw_fb_gp106.h +++ /dev/null @@ -1,563 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_fb_gp106_h_ -#define _hw_fb_gp106_h_ - -static inline u32 fb_fbhub_num_active_ltcs_r(void) -{ - return 0x00100800U; -} -static inline u32 fb_mmu_ctrl_r(void) -{ - return 0x00100c80U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 fb_priv_mmu_phy_secure_r(void) -{ - return 0x00100ce4U; -} -static inline u32 fb_mmu_invalidate_pdb_r(void) -{ - return 0x00100cb8U; -} -static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_invalidate_r(void) -{ - return 0x00100cbcU; -} -static inline u32 fb_mmu_invalidate_all_va_true_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_m(void) -{ - return 0x1U << 2U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_invalidate_replay_s(void) -{ - return 3U; -} -static inline u32 fb_mmu_invalidate_replay_f(u32 v) -{ - return (v & 0x7U) << 3U; -} -static inline u32 fb_mmu_invalidate_replay_m(void) -{ - return 0x7U << 3U; -} -static inline u32 fb_mmu_invalidate_replay_v(u32 r) -{ - return (r >> 3U) & 0x7U; -} -static inline u32 fb_mmu_invalidate_replay_none_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_replay_start_f(void) -{ - return 0x8U; -} -static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void) -{ - return 0x10U; -} -static inline u32 fb_mmu_invalidate_replay_cancel_targeted_f(void) -{ - return 0x18U; -} -static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void) -{ - return 0x20U; -} -static inline u32 fb_mmu_invalidate_replay_cancel_f(void) -{ - return 0x20U; -} -static inline u32 fb_mmu_invalidate_sys_membar_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 fb_mmu_invalidate_sys_membar_m(void) -{ - return 0x1U << 6U; -} -static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_sys_membar_true_f(void) -{ - return 0x40U; -} -static inline u32 fb_mmu_invalidate_ack_s(void) -{ - return 2U; -} -static inline u32 fb_mmu_invalidate_ack_f(u32 v) -{ - return (v & 0x3U) << 7U; -} -static inline u32 fb_mmu_invalidate_ack_m(void) -{ - return 0x3U << 7U; -} -static inline u32 fb_mmu_invalidate_ack_v(u32 r) -{ - return (r >> 7U) & 0x3U; -} -static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void) -{ - return 0x100U; -} -static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void) -{ - return 0x80U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_s(void) -{ - return 6U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v) -{ - return (v & 0x3fU) << 9U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_m(void) -{ - return 0x3fU << 9U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r) -{ - return (r >> 9U) & 0x3fU; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void) -{ - return 5U; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v) -{ - return (v & 0x1fU) << 15U; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void) -{ - return 0x1fU << 15U; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r) -{ - return (r >> 15U) & 0x1fU; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_m(void) -{ - return 0x1U << 20U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void) -{ - return 0x100000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void) -{ - return 3U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void) -{ - return 0x7U << 24U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r) -{ - return (r >> 24U) & 0x7U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void) -{ - return 0x1000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void) -{ - return 0x2000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void) -{ - return 0x3000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void) -{ - return 0x4000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void) -{ - return 0x5000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void) -{ - return 0x6000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void) -{ - return 0x7000000U; -} -static inline u32 fb_mmu_invalidate_trigger_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_trigger_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_invalidate_trigger_m(void) -{ - return 0x1U << 31U; -} -static inline u32 fb_mmu_invalidate_trigger_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_trigger_true_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_debug_wr_r(void) -{ - return 0x00100cc8U; -} -static inline u32 fb_mmu_debug_wr_aperture_s(void) -{ - return 2U; -} -static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 fb_mmu_debug_wr_aperture_m(void) -{ - return 0x3U << 0U; -} -static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_debug_wr_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_wr_vol_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_debug_wr_vol_true_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_debug_wr_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) -{ - return 0x0000000cU; -} -static inline u32 fb_mmu_debug_rd_r(void) -{ - return 0x00100cccU; -} -static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_debug_rd_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_rd_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) -{ - return 0x0000000cU; -} -static inline u32 fb_mmu_debug_ctrl_r(void) -{ - return 0x00100cc4U; -} -static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 fb_mmu_debug_ctrl_debug_m(void) -{ - return 0x1U << 16U; -} -static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_debug_ctrl_debug_enabled_f(void) -{ - return 0x10000U; -} -static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_debug_ctrl_debug_disabled_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_priv_level_mask_r(void) -{ - return 0x00100cdcU; -} -static inline u32 fb_mmu_priv_level_mask_write_violation_m(void) -{ - return 0x1U << 7U; -} -static inline u32 fb_niso_flush_sysmem_addr_r(void) -{ - return 0x00100c10U; -} -static inline u32 fb_mmu_local_memory_range_r(void) -{ - return 0x00100ce0U; -} -static inline u32 fb_mmu_local_memory_range_lower_scale_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 fb_mmu_local_memory_range_lower_mag_v(u32 r) -{ - return (r >> 4U) & 0x3fU; -} -static inline u32 fb_mmu_local_memory_range_ecc_mode_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fb_fbpa_fbio_delay_r(void) -{ - return 0x009a065cU; -} -static inline u32 fb_fbpa_fbio_delay_src_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 fb_fbpa_fbio_delay_src_m(void) -{ - return 0xfU << 0U; -} -static inline u32 fb_fbpa_fbio_delay_src_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 fb_fbpa_fbio_delay_src_max_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_fbpa_fbio_delay_priv_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 fb_fbpa_fbio_delay_priv_m(void) -{ - return 0xfU << 4U; -} -static inline u32 fb_fbpa_fbio_delay_priv_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 fb_fbpa_fbio_delay_priv_max_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_fbpa_fbio_cmd_delay_r(void) -{ - return 0x009a08e0U; -} -static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_m(void) -{ - return 0xfU << 0U; -} -static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_max_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_m(void) -{ - return 0xfU << 4U; -} -static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_max_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_niso_scrub_status_r(void) -{ - return 0x00100b20U; -} -static inline u32 fb_niso_scrub_status_flag_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 fb_fbpa_fbio_iref_byte_rx_ctrl_r(void) -{ - return 0x009a0eb0U; -} -#endif diff --git a/include/nvgpu/hw/gp106/hw_fbpa_gp106.h b/include/nvgpu/hw/gp106/hw_fbpa_gp106.h deleted file mode 100644 index 797a40c..0000000 --- a/include/nvgpu/hw/gp106/hw_fbpa_gp106.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_fbpa_gp106_h_ -#define _hw_fbpa_gp106_h_ - -static inline u32 fbpa_cstatus_r(void) -{ - return 0x009a020cU; -} -static inline u32 fbpa_cstatus_ramamount_v(u32 r) -{ - return (r >> 0U) & 0x1ffffU; -} -#endif diff --git a/include/nvgpu/hw/gp106/hw_fifo_gp106.h b/include/nvgpu/hw/gp106/hw_fifo_gp106.h deleted file mode 100644 index 804e9e4..0000000 --- a/include/nvgpu/hw/gp106/hw_fifo_gp106.h +++ /dev/null @@ -1,695 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_fifo_gp106_h_ -#define _hw_fifo_gp106_h_ - -static inline u32 fifo_bar1_base_r(void) -{ - return 0x00002254U; -} -static inline u32 fifo_bar1_base_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 fifo_bar1_base_ptr_align_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 fifo_bar1_base_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 fifo_bar1_base_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 fifo_runlist_base_r(void) -{ - return 0x00002270U; -} -static inline u32 fifo_runlist_base_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 fifo_runlist_base_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 fifo_runlist_r(void) -{ - return 0x00002274U; -} -static inline u32 fifo_runlist_engine_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 fifo_eng_runlist_base_r(u32 i) -{ - return 0x00002280U + i*8U; -} -static inline u32 fifo_eng_runlist_base__size_1_v(void) -{ - return 0x00000007U; -} -static inline u32 fifo_eng_runlist_r(u32 i) -{ - return 0x00002284U + i*8U; -} -static inline u32 fifo_eng_runlist__size_1_v(void) -{ - return 0x00000007U; -} -static inline u32 fifo_eng_runlist_length_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fifo_eng_runlist_length_max_v(void) -{ - return 0x0000ffffU; -} -static inline u32 fifo_eng_runlist_pending_true_f(void) -{ - return 0x100000U; -} -static inline u32 fifo_pb_timeslice_r(u32 i) -{ - return 0x00002350U + i*4U; -} -static inline u32 fifo_pb_timeslice_timeout_16_f(void) -{ - return 0x10U; -} -static inline u32 fifo_pb_timeslice_timescale_0_f(void) -{ - return 0x0U; -} -static inline u32 fifo_pb_timeslice_enable_true_f(void) -{ - return 0x10000000U; -} -static inline u32 fifo_pbdma_map_r(u32 i) -{ - return 0x00002390U + i*4U; -} -static inline u32 fifo_intr_0_r(void) -{ - return 0x00002100U; -} -static inline u32 fifo_intr_0_bind_error_pending_f(void) -{ - return 0x1U; -} -static inline u32 fifo_intr_0_bind_error_reset_f(void) -{ - return 0x1U; -} -static inline u32 fifo_intr_0_sched_error_pending_f(void) -{ - return 0x100U; -} -static inline u32 fifo_intr_0_sched_error_reset_f(void) -{ - return 0x100U; -} -static inline u32 fifo_intr_0_chsw_error_pending_f(void) -{ - return 0x10000U; -} -static inline u32 fifo_intr_0_chsw_error_reset_f(void) -{ - return 0x10000U; -} -static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void) -{ - return 0x800000U; -} -static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void) -{ - return 0x800000U; -} -static inline u32 fifo_intr_0_lb_error_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_intr_0_lb_error_reset_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_intr_0_replayable_fault_error_pending_f(void) -{ - return 0x2000000U; -} -static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void) -{ - return 0x8000000U; -} -static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void) -{ - return 0x8000000U; -} -static inline u32 fifo_intr_0_mmu_fault_pending_f(void) -{ - return 0x10000000U; -} -static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 fifo_intr_0_runlist_event_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 fifo_intr_0_channel_intr_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 fifo_intr_en_0_r(void) -{ - return 0x00002140U; -} -static inline u32 fifo_intr_en_0_sched_error_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 fifo_intr_en_0_sched_error_m(void) -{ - return 0x1U << 8U; -} -static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 fifo_intr_en_0_mmu_fault_m(void) -{ - return 0x1U << 28U; -} -static inline u32 fifo_intr_en_1_r(void) -{ - return 0x00002528U; -} -static inline u32 fifo_intr_bind_error_r(void) -{ - return 0x0000252cU; -} -static inline u32 fifo_intr_sched_error_r(void) -{ - return 0x0000254cU; -} -static inline u32 fifo_intr_sched_error_code_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void) -{ - return 0x0000000aU; -} -static inline u32 fifo_intr_chsw_error_r(void) -{ - return 0x0000256cU; -} -static inline u32 fifo_intr_mmu_fault_id_r(void) -{ - return 0x0000259cU; -} -static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void) -{ - return 0x0U; -} -static inline u32 fifo_intr_mmu_fault_inst_r(u32 i) -{ - return 0x00002800U + i*16U; -} -static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 fifo_intr_mmu_fault_lo_r(u32 i) -{ - return 0x00002804U + i*16U; -} -static inline u32 fifo_intr_mmu_fault_hi_r(u32 i) -{ - return 0x00002808U + i*16U; -} -static inline u32 fifo_intr_mmu_fault_info_r(u32 i) -{ - return 0x0000280cU + i*16U; -} -static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 fifo_intr_mmu_fault_info_client_type_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 fifo_intr_mmu_fault_info_client_type_gpc_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_intr_mmu_fault_info_client_type_hub_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r) -{ - return (r >> 8U) & 0x7fU; -} -static inline u32 fifo_intr_pbdma_id_r(void) -{ - return 0x000025a0U; -} -static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) -{ - return (r >> (0U + i*1U)) & 0x1U; -} -static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 fifo_intr_runlist_r(void) -{ - return 0x00002a00U; -} -static inline u32 fifo_fb_timeout_r(void) -{ - return 0x00002a04U; -} -static inline u32 fifo_fb_timeout_period_m(void) -{ - return 0x3fffffffU << 0U; -} -static inline u32 fifo_fb_timeout_period_max_f(void) -{ - return 0x3fffffffU; -} -static inline u32 fifo_error_sched_disable_r(void) -{ - return 0x0000262cU; -} -static inline u32 fifo_sched_disable_r(void) -{ - return 0x00002630U; -} -static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_sched_disable_runlist_m(u32 i) -{ - return 0x1U << (0U + i*1U); -} -static inline u32 fifo_sched_disable_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_preempt_r(void) -{ - return 0x00002634U; -} -static inline u32 fifo_preempt_pending_true_f(void) -{ - return 0x100000U; -} -static inline u32 fifo_preempt_type_channel_f(void) -{ - return 0x0U; -} -static inline u32 fifo_preempt_type_tsg_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_preempt_chid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 fifo_preempt_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 fifo_trigger_mmu_fault_r(u32 i) -{ - return 0x00002a30U + i*4U; -} -static inline u32 fifo_trigger_mmu_fault_id_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 fifo_engine_status_r(u32 i) -{ - return 0x00002640U + i*8U; -} -static inline u32 fifo_engine_status__size_1_v(void) -{ - return 0x00000009U; -} -static inline u32 fifo_engine_status_id_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 fifo_engine_status_id_type_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 fifo_engine_status_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctx_status_v(u32 r) -{ - return (r >> 13U) & 0x7U; -} -static inline u32 fifo_engine_status_ctx_status_invalid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_ctx_status_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void) -{ - return 0x00000005U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void) -{ - return 0x00000006U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void) -{ - return 0x00000007U; -} -static inline u32 fifo_engine_status_next_id_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 fifo_engine_status_next_id_type_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 fifo_engine_status_next_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_faulted_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fifo_engine_status_faulted_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_engine_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fifo_engine_status_engine_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_engine_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctxsw_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fifo_engine_status_ctxsw_in_progress_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) -{ - return 0x8000U; -} -static inline u32 fifo_pbdma_status_r(u32 i) -{ - return 0x00003080U + i*4U; -} -static inline u32 fifo_pbdma_status__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 fifo_pbdma_status_id_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 fifo_pbdma_status_id_type_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 fifo_pbdma_status_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chan_status_v(u32 r) -{ - return (r >> 13U) & 0x7U; -} -static inline u32 fifo_pbdma_status_chan_status_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void) -{ - return 0x00000005U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void) -{ - return 0x00000006U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void) -{ - return 0x00000007U; -} -static inline u32 fifo_pbdma_status_next_id_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 fifo_pbdma_status_next_id_type_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 fifo_pbdma_status_next_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_pbdma_status_chsw_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_replay_fault_buffer_lo_r(void) -{ - return 0x00002a70U; -} -static inline u32 fifo_replay_fault_buffer_lo_enable_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 fifo_replay_fault_buffer_lo_enable_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_replay_fault_buffer_lo_enable_false_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_replay_fault_buffer_lo_base_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 fifo_replay_fault_buffer_lo_base_reset_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_replay_fault_buffer_hi_r(void) -{ - return 0x00002a74U; -} -static inline u32 fifo_replay_fault_buffer_hi_base_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fifo_replay_fault_buffer_hi_base_reset_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_replay_fault_buffer_size_r(void) -{ - return 0x00002a78U; -} -static inline u32 fifo_replay_fault_buffer_size_hw_f(u32 v) -{ - return (v & 0x3fffU) << 0U; -} -static inline u32 fifo_replay_fault_buffer_size_hw_entries_v(void) -{ - return 0x00001200U; -} -static inline u32 fifo_replay_fault_buffer_get_r(void) -{ - return 0x00002a7cU; -} -static inline u32 fifo_replay_fault_buffer_get_offset_hw_f(u32 v) -{ - return (v & 0x3fffU) << 0U; -} -static inline u32 fifo_replay_fault_buffer_get_offset_hw_init_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_replay_fault_buffer_put_r(void) -{ - return 0x00002a80U; -} -static inline u32 fifo_replay_fault_buffer_put_offset_hw_f(u32 v) -{ - return (v & 0x3fffU) << 0U; -} -static inline u32 fifo_replay_fault_buffer_put_offset_hw_init_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_replay_fault_buffer_info_r(void) -{ - return 0x00002a84U; -} -static inline u32 fifo_replay_fault_buffer_info_overflow_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 fifo_replay_fault_buffer_info_overflow_false_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_replay_fault_buffer_info_overflow_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_replay_fault_buffer_info_overflow_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_replay_fault_buffer_info_write_nack_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 fifo_replay_fault_buffer_info_write_nack_false_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_replay_fault_buffer_info_write_nack_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_replay_fault_buffer_info_write_nack_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_false_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_clear_v(void) -{ - return 0x00000001U; -} -#endif diff --git a/include/nvgpu/hw/gp106/hw_flush_gp106.h b/include/nvgpu/hw/gp106/hw_flush_gp106.h deleted file mode 100644 index c4e1c32..0000000 --- a/include/nvgpu/hw/gp106/hw_flush_gp106.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_flush_gp106_h_ -#define _hw_flush_gp106_h_ - -static inline u32 flush_l2_system_invalidate_r(void) -{ - return 0x00070004U; -} -static inline u32 flush_l2_system_invalidate_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_system_invalidate_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_system_invalidate_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_system_invalidate_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_flush_dirty_r(void) -{ - return 0x00070010U; -} -static inline u32 flush_l2_flush_dirty_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_flush_dirty_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_flush_dirty_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_flush_dirty_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_flush_dirty_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_flush_dirty_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_flush_dirty_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_clean_comptags_r(void) -{ - return 0x0007000cU; -} -static inline u32 flush_l2_clean_comptags_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_clean_comptags_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_clean_comptags_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_clean_comptags_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_clean_comptags_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_clean_comptags_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_clean_comptags_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_clean_comptags_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_fb_flush_r(void) -{ - return 0x00070000U; -} -static inline u32 flush_fb_flush_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_fb_flush_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_fb_flush_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_fb_flush_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_fb_flush_outstanding_true_v(void) -{ - return 0x00000001U; -} -#endif diff --git a/include/nvgpu/hw/gp106/hw_fuse_gp106.h b/include/nvgpu/hw/gp106/hw_fuse_gp106.h deleted file mode 100644 index bfb19b9..0000000 --- a/include/nvgpu/hw/gp106/hw_fuse_gp106.h +++ /dev/null @@ -1,275 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_fuse_gp106_h_ -#define _hw_fuse_gp106_h_ - -static inline u32 fuse_status_opt_gpc_r(void) -{ - return 0x00021c1cU; -} -static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) -{ - return 0x00021c38U + i*4U; -} -static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i) -{ - return 0x00021838U + i*4U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void) -{ - return 0x00021944U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void) -{ - return 0x3U << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void) -{ - return 0x00021948U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void) -{ - return 0x1U << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void) -{ - return 0x1U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void) -{ - return 0x0U; -} -static inline u32 fuse_status_opt_fbio_r(void) -{ - return 0x00021c14U; -} -static inline u32 fuse_status_opt_fbio_data_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fuse_status_opt_fbio_data_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 fuse_status_opt_fbio_data_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i) -{ - return 0x00021d70U + i*4U; -} -static inline u32 fuse_status_opt_fbp_r(void) -{ - return 0x00021d38U; -} -static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) -{ - return (r >> (0U + i*1U)) & 0x1U; -} -static inline u32 fuse_vin_cal_fuse_rev_r(void) -{ - return 0x0002164cU; -} -static inline u32 fuse_vin_cal_fuse_rev_data_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 fuse_vin_cal_gpc0_r(void) -{ - return 0x00021650U; -} -static inline u32 fuse_vin_cal_gpc0_icpt_int_data_s(void) -{ - return 12U; -} -static inline u32 fuse_vin_cal_gpc0_icpt_int_data_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 fuse_vin_cal_gpc0_icpt_frac_data_s(void) -{ - return 2U; -} -static inline u32 fuse_vin_cal_gpc0_icpt_frac_data_v(u32 r) -{ - return (r >> 14U) & 0x3U; -} -static inline u32 fuse_vin_cal_gpc0_slope_int_data_s(void) -{ - return 4U; -} -static inline u32 fuse_vin_cal_gpc0_slope_int_data_v(u32 r) -{ - return (r >> 10U) & 0xfU; -} -static inline u32 fuse_vin_cal_gpc0_slope_frac_data_s(void) -{ - return 10U; -} -static inline u32 fuse_vin_cal_gpc0_slope_frac_data_v(u32 r) -{ - return (r >> 0U) & 0x3ffU; -} -static inline u32 fuse_vin_cal_gpc1_delta_r(void) -{ - return 0x00021654U; -} -static inline u32 fuse_vin_cal_gpc1_delta_icpt_int_data_s(void) -{ - return 8U; -} -static inline u32 fuse_vin_cal_gpc1_delta_icpt_int_data_v(u32 r) -{ - return (r >> 14U) & 0xffU; -} -static inline u32 fuse_vin_cal_gpc1_delta_icpt_frac_data_s(void) -{ - return 2U; -} -static inline u32 fuse_vin_cal_gpc1_delta_icpt_frac_data_v(u32 r) -{ - return (r >> 12U) & 0x3U; -} -static inline u32 fuse_vin_cal_gpc1_delta_icpt_sign_data_s(void) -{ - return 1U; -} -static inline u32 fuse_vin_cal_gpc1_delta_icpt_sign_data_v(u32 r) -{ - return (r >> 22U) & 0x1U; -} -static inline u32 fuse_vin_cal_gpc1_delta_slope_int_data_s(void) -{ - return 1U; -} -static inline u32 fuse_vin_cal_gpc1_delta_slope_int_data_v(u32 r) -{ - return (r >> 10U) & 0x1U; -} -static inline u32 fuse_vin_cal_gpc1_delta_slope_frac_data_s(void) -{ - return 10U; -} -static inline u32 fuse_vin_cal_gpc1_delta_slope_frac_data_v(u32 r) -{ - return (r >> 0U) & 0x3ffU; -} -static inline u32 fuse_vin_cal_gpc1_delta_slope_sign_data_s(void) -{ - return 1U; -} -static inline u32 fuse_vin_cal_gpc1_delta_slope_sign_data_v(u32 r) -{ - return (r >> 11U) & 0x1U; -} -static inline u32 fuse_vin_cal_gpc2_delta_r(void) -{ - return 0x00021658U; -} -static inline u32 fuse_vin_cal_gpc3_delta_r(void) -{ - return 0x0002165cU; -} -static inline u32 fuse_vin_cal_gpc4_delta_r(void) -{ - return 0x00021660U; -} -static inline u32 fuse_vin_cal_gpc5_delta_r(void) -{ - return 0x00021664U; -} -static inline u32 fuse_vin_cal_shared_delta_r(void) -{ - return 0x00021668U; -} -static inline u32 fuse_vin_cal_sram_delta_r(void) -{ - return 0x0002166cU; -} -static inline u32 fuse_vin_cal_sram_delta_icpt_int_data_s(void) -{ - return 9U; -} -static inline u32 fuse_vin_cal_sram_delta_icpt_int_data_v(u32 r) -{ - return (r >> 13U) & 0x1ffU; -} -static inline u32 fuse_vin_cal_sram_delta_icpt_frac_data_s(void) -{ - return 1U; -} -static inline u32 fuse_vin_cal_sram_delta_icpt_frac_data_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -#endif diff --git a/include/nvgpu/hw/gp106/hw_gc6_gp106.h b/include/nvgpu/hw/gp106/hw_gc6_gp106.h deleted file mode 100644 index 91e9d7b..0000000 --- a/include/nvgpu/hw/gp106/hw_gc6_gp106.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_gc6_gp106_h_ -#define _hw_gc6_gp106_h_ -static inline u32 gc6_sci_strap_r(void) -{ - return 0x00010ebb0; -} -#endif diff --git a/include/nvgpu/hw/gp106/hw_gmmu_gp106.h b/include/nvgpu/hw/gp106/hw_gmmu_gp106.h deleted file mode 100644 index 8369001..0000000 --- a/include/nvgpu/hw/gp106/hw_gmmu_gp106.h +++ /dev/null @@ -1,331 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_gmmu_gp106_h_ -#define _hw_gmmu_gp106_h_ - -static inline u32 gmmu_new_pde_is_pte_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_is_pte_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pde_aperture_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_aperture_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pde_aperture_video_memory_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_pde_address_sys_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_pde_address_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_vol_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_vol_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_pde_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pde_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_new_pde__size_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_new_dual_pde_is_pte_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_is_pte_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 gmmu_new_dual_pde_address_big_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_w(void) -{ - return 2U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_dual_pde_vol_small_w(void) -{ - return 2U; -} -static inline u32 gmmu_new_dual_pde_vol_small_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_dual_pde_vol_small_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_vol_big_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_vol_big_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_dual_pde_vol_big_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) -{ - return 2U; -} -static inline u32 gmmu_new_dual_pde_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_new_dual_pde_address_big_shift_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_new_dual_pde__size_v(void) -{ - return 0x00000010U; -} -static inline u32 gmmu_new_pte__size_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_new_pte_valid_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_valid_true_f(void) -{ - return 0x1U; -} -static inline u32 gmmu_new_pte_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_privilege_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_privilege_true_f(void) -{ - return 0x20U; -} -static inline u32 gmmu_new_pte_privilege_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_address_sys_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_pte_address_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_address_vid_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_pte_address_vid_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_vol_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_vol_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_pte_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_aperture_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_aperture_video_memory_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_pte_read_only_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_read_only_true_f(void) -{ - return 0x40U; -} -static inline u32 gmmu_new_pte_comptagline_f(u32 v) -{ - return (v & 0x3ffffU) << 4U; -} -static inline u32 gmmu_new_pte_comptagline_w(void) -{ - return 1U; -} -static inline u32 gmmu_new_pte_kind_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gmmu_new_pte_kind_w(void) -{ - return 1U; -} -static inline u32 gmmu_new_pte_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_pte_kind_f(u32 v) -{ - return (v & 0xffU) << 4U; -} -static inline u32 gmmu_pte_kind_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_kind_invalid_v(void) -{ - return 0x000000ffU; -} -static inline u32 gmmu_pte_kind_pitch_v(void) -{ - return 0x00000000U; -} -#endif diff --git a/include/nvgpu/hw/gp106/hw_gr_gp106.h b/include/nvgpu/hw/gp106/hw_gr_gp106.h deleted file mode 100644 index ac82901..0000000 --- a/include/nvgpu/hw/gp106/hw_gr_gp106.h +++ /dev/null @@ -1,4167 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_gr_gp106_h_ -#define _hw_gr_gp106_h_ - -static inline u32 gr_intr_r(void) -{ - return 0x00400100U; -} -static inline u32 gr_intr_notify_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_intr_notify_reset_f(void) -{ - return 0x1U; -} -static inline u32 gr_intr_semaphore_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_semaphore_reset_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_illegal_method_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_intr_illegal_method_reset_f(void) -{ - return 0x10U; -} -static inline u32 gr_intr_illegal_notify_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_intr_illegal_notify_reset_f(void) -{ - return 0x40U; -} -static inline u32 gr_intr_firmware_method_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 gr_intr_firmware_method_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_intr_firmware_method_reset_f(void) -{ - return 0x100U; -} -static inline u32 gr_intr_illegal_class_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_intr_illegal_class_reset_f(void) -{ - return 0x20U; -} -static inline u32 gr_intr_fecs_error_pending_f(void) -{ - return 0x80000U; -} -static inline u32 gr_intr_fecs_error_reset_f(void) -{ - return 0x80000U; -} -static inline u32 gr_intr_class_error_pending_f(void) -{ - return 0x100000U; -} -static inline u32 gr_intr_class_error_reset_f(void) -{ - return 0x100000U; -} -static inline u32 gr_intr_exception_pending_f(void) -{ - return 0x200000U; -} -static inline u32 gr_intr_exception_reset_f(void) -{ - return 0x200000U; -} -static inline u32 gr_fecs_intr_r(void) -{ - return 0x00400144U; -} -static inline u32 gr_class_error_r(void) -{ - return 0x00400110U; -} -static inline u32 gr_class_error_code_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_intr_nonstall_r(void) -{ - return 0x00400120U; -} -static inline u32 gr_intr_nonstall_trap_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_en_r(void) -{ - return 0x0040013cU; -} -static inline u32 gr_exception_r(void) -{ - return 0x00400108U; -} -static inline u32 gr_exception_fe_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_exception_gpc_m(void) -{ - return 0x1U << 24U; -} -static inline u32 gr_exception_memfmt_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_exception_ds_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_exception_sked_m(void) -{ - return 0x1U << 8U; -} -static inline u32 gr_exception_pd_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_exception_scc_m(void) -{ - return 0x1U << 3U; -} -static inline u32 gr_exception_ssync_m(void) -{ - return 0x1U << 5U; -} -static inline u32 gr_exception_mme_m(void) -{ - return 0x1U << 7U; -} -static inline u32 gr_exception1_r(void) -{ - return 0x00400118U; -} -static inline u32 gr_exception1_gpc_0_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_exception2_r(void) -{ - return 0x0040011cU; -} -static inline u32 gr_exception_en_r(void) -{ - return 0x00400138U; -} -static inline u32 gr_exception_en_fe_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_exception1_en_r(void) -{ - return 0x00400130U; -} -static inline u32 gr_exception2_en_r(void) -{ - return 0x00400134U; -} -static inline u32 gr_gpfifo_ctl_r(void) -{ - return 0x00400500U; -} -static inline u32 gr_gpfifo_ctl_access_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpfifo_ctl_access_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpfifo_ctl_access_enabled_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void) -{ - return 0x10000U; -} -static inline u32 gr_gpfifo_status_r(void) -{ - return 0x00400504U; -} -static inline u32 gr_trapped_addr_r(void) -{ - return 0x00400704U; -} -static inline u32 gr_trapped_addr_mthd_v(u32 r) -{ - return (r >> 2U) & 0xfffU; -} -static inline u32 gr_trapped_addr_subch_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 gr_trapped_addr_mme_generated_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 gr_trapped_addr_datahigh_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 gr_trapped_addr_priv_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 gr_trapped_addr_status_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_trapped_data_lo_r(void) -{ - return 0x00400708U; -} -static inline u32 gr_trapped_data_hi_r(void) -{ - return 0x0040070cU; -} -static inline u32 gr_trapped_data_mme_r(void) -{ - return 0x00400710U; -} -static inline u32 gr_trapped_data_mme_pc_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 gr_status_r(void) -{ - return 0x00400700U; -} -static inline u32 gr_status_fe_method_upper_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_status_fe_method_lower_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_status_fe_method_lower_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_status_fe_gi_v(u32 r) -{ - return (r >> 21U) & 0x1U; -} -static inline u32 gr_status_mask_r(void) -{ - return 0x00400610U; -} -static inline u32 gr_status_1_r(void) -{ - return 0x00400604U; -} -static inline u32 gr_status_2_r(void) -{ - return 0x00400608U; -} -static inline u32 gr_engine_status_r(void) -{ - return 0x0040060cU; -} -static inline u32 gr_engine_status_value_busy_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_be0_becs_be_exception_r(void) -{ - return 0x00410204U; -} -static inline u32 gr_pri_be0_becs_be_exception_en_r(void) -{ - return 0x00410208U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void) -{ - return 0x00502c90U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void) -{ - return 0x00502c94U; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void) -{ - return 0x00504508U; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void) -{ - return 0x0050450cU; -} -static inline u32 gr_activity_0_r(void) -{ - return 0x00400380U; -} -static inline u32 gr_activity_1_r(void) -{ - return 0x00400384U; -} -static inline u32 gr_activity_2_r(void) -{ - return 0x00400388U; -} -static inline u32 gr_activity_4_r(void) -{ - return 0x00400390U; -} -static inline u32 gr_activity_4_gpc0_s(void) -{ - return 3U; -} -static inline u32 gr_activity_4_gpc0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_activity_4_gpc0_m(void) -{ - return 0x7U << 0U; -} -static inline u32 gr_activity_4_gpc0_v(u32 r) -{ - return (r >> 0U) & 0x7U; -} -static inline u32 gr_activity_4_gpc0_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_activity_4_gpc0_preempted_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_pri_gpc0_gcc_dbg_r(void) -{ - return 0x00501000U; -} -static inline u32 gr_pri_gpcs_gcc_dbg_r(void) -{ - return 0x00419000U; -} -static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) -{ - return 0x005046a4U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) -{ - return 0x00419ea4U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_pri_sked_activity_r(void) -{ - return 0x00407054U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void) -{ - return 0x00502c80U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void) -{ - return 0x00502c84U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void) -{ - return 0x00502c88U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void) -{ - return 0x00502c8cU; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void) -{ - return 0x00504500U; -} -static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void) -{ - return 0x00504d00U; -} -static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void) -{ - return 0x00501d00U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void) -{ - return 0x0041ac80U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void) -{ - return 0x0041ac84U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void) -{ - return 0x0041ac88U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void) -{ - return 0x0041ac8cU; -} -static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void) -{ - return 0x0041c500U; -} -static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void) -{ - return 0x0041cd00U; -} -static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void) -{ - return 0x00419d00U; -} -static inline u32 gr_pri_be0_becs_be_activity0_r(void) -{ - return 0x00410200U; -} -static inline u32 gr_pri_be1_becs_be_activity0_r(void) -{ - return 0x00410600U; -} -static inline u32 gr_pri_bes_becs_be_activity0_r(void) -{ - return 0x00408a00U; -} -static inline u32 gr_pri_ds_mpipe_status_r(void) -{ - return 0x00405858U; -} -static inline u32 gr_pri_fe_go_idle_info_r(void) -{ - return 0x00404194U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) -{ - return 0x00504238U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) -{ - return 0x005046b8U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp1_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp2_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f(void) -{ - return 0x80U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp1_pending_f(void) -{ - return 0x200U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp2_pending_f(void) -{ - return 0x400U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f(void) -{ - return 0x800U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_r(void) -{ - return 0x005044a0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm1_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f(void) -{ - return 0x200U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r(void) -{ - return 0x005046bcU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r(void) -{ - return 0x005046c0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r(void) -{ - return 0x005044a4U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m(void) -{ - return 0xffU << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m(void) -{ - return 0xffU << 8U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m(void) -{ - return 0xffU << 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) -{ - return 0x005042c4U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void) -{ - return 0x2U; -} -static inline u32 gr_pri_be0_crop_status1_r(void) -{ - return 0x00410134U; -} -static inline u32 gr_pri_bes_crop_status1_r(void) -{ - return 0x00408934U; -} -static inline u32 gr_pri_be0_zrop_status_r(void) -{ - return 0x00410048U; -} -static inline u32 gr_pri_be0_zrop_status2_r(void) -{ - return 0x0041004cU; -} -static inline u32 gr_pri_bes_zrop_status_r(void) -{ - return 0x00408848U; -} -static inline u32 gr_pri_bes_zrop_status2_r(void) -{ - return 0x0040884cU; -} -static inline u32 gr_pipe_bundle_address_r(void) -{ - return 0x00400200U; -} -static inline u32 gr_pipe_bundle_address_value_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pipe_bundle_data_r(void) -{ - return 0x00400204U; -} -static inline u32 gr_pipe_bundle_config_r(void) -{ - return 0x00400208U; -} -static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fe_hww_esr_r(void) -{ - return 0x00404000U; -} -static inline u32 gr_fe_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_fe_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fe_hww_esr_info_r(void) -{ - return 0x004041b0U; -} -static inline u32 gr_fe_go_idle_timeout_r(void) -{ - return 0x00404154U; -} -static inline u32 gr_fe_go_idle_timeout_count_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) -{ - return 0x1800U; -} -static inline u32 gr_fe_object_table_r(u32 i) -{ - return 0x00404200U + i*4U; -} -static inline u32 gr_fe_object_table_nvclass_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_fe_tpc_fs_r(void) -{ - return 0x004041c4U; -} -static inline u32 gr_pri_mme_shadow_raw_index_r(void) -{ - return 0x00404488U; -} -static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pri_mme_shadow_raw_data_r(void) -{ - return 0x0040448cU; -} -static inline u32 gr_mme_hww_esr_r(void) -{ - return 0x00404490U; -} -static inline u32 gr_mme_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_mme_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_mme_hww_esr_info_r(void) -{ - return 0x00404494U; -} -static inline u32 gr_memfmt_hww_esr_r(void) -{ - return 0x00404600U; -} -static inline u32 gr_memfmt_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_memfmt_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fecs_cpuctl_r(void) -{ - return 0x00409100U; -} -static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_cpuctl_alias_r(void) -{ - return 0x00409130U; -} -static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_dmactl_r(void) -{ - return 0x0040910cU; -} -static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_fecs_os_r(void) -{ - return 0x00409080U; -} -static inline u32 gr_fecs_idlestate_r(void) -{ - return 0x0040904cU; -} -static inline u32 gr_fecs_mailbox0_r(void) -{ - return 0x00409040U; -} -static inline u32 gr_fecs_mailbox1_r(void) -{ - return 0x00409044U; -} -static inline u32 gr_fecs_irqstat_r(void) -{ - return 0x00409008U; -} -static inline u32 gr_fecs_irqmode_r(void) -{ - return 0x0040900cU; -} -static inline u32 gr_fecs_irqmask_r(void) -{ - return 0x00409018U; -} -static inline u32 gr_fecs_irqdest_r(void) -{ - return 0x0040901cU; -} -static inline u32 gr_fecs_curctx_r(void) -{ - return 0x00409050U; -} -static inline u32 gr_fecs_nxtctx_r(void) -{ - return 0x00409054U; -} -static inline u32 gr_fecs_engctl_r(void) -{ - return 0x004090a4U; -} -static inline u32 gr_fecs_debug1_r(void) -{ - return 0x00409090U; -} -static inline u32 gr_fecs_debuginfo_r(void) -{ - return 0x00409094U; -} -static inline u32 gr_fecs_icd_cmd_r(void) -{ - return 0x00409200U; -} -static inline u32 gr_fecs_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 gr_fecs_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_fecs_icd_cmd_opc_m(void) -{ - return 0xfU << 0U; -} -static inline u32 gr_fecs_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 gr_fecs_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 gr_fecs_icd_rdata_r(void) -{ - return 0x0040920cU; -} -static inline u32 gr_fecs_imemc_r(u32 i) -{ - return 0x00409180U + i*16U; -} -static inline u32 gr_fecs_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_fecs_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_fecs_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_fecs_imemd_r(u32 i) -{ - return 0x00409184U + i*16U; -} -static inline u32 gr_fecs_imemt_r(u32 i) -{ - return 0x00409188U + i*16U; -} -static inline u32 gr_fecs_imemt_tag_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_fecs_dmemc_r(u32 i) -{ - return 0x004091c0U + i*8U; -} -static inline u32 gr_fecs_dmemc_offs_s(void) -{ - return 6U; -} -static inline u32 gr_fecs_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_fecs_dmemc_offs_m(void) -{ - return 0x3fU << 2U; -} -static inline u32 gr_fecs_dmemc_offs_v(u32 r) -{ - return (r >> 2U) & 0x3fU; -} -static inline u32 gr_fecs_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_fecs_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_fecs_dmemd_r(u32 i) -{ - return 0x004091c4U + i*8U; -} -static inline u32 gr_fecs_dmatrfbase_r(void) -{ - return 0x00409110U; -} -static inline u32 gr_fecs_dmatrfmoffs_r(void) -{ - return 0x00409114U; -} -static inline u32 gr_fecs_dmatrffboffs_r(void) -{ - return 0x0040911cU; -} -static inline u32 gr_fecs_dmatrfcmd_r(void) -{ - return 0x00409118U; -} -static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_fecs_bootvec_r(void) -{ - return 0x00409104U; -} -static inline u32 gr_fecs_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_falcon_hwcfg_r(void) -{ - return 0x00409108U; -} -static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void) -{ - return 0x0041a108U; -} -static inline u32 gr_fecs_falcon_rm_r(void) -{ - return 0x00409084U; -} -static inline u32 gr_fecs_current_ctx_r(void) -{ - return 0x00409b00U; -} -static inline u32 gr_fecs_current_ctx_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_current_ctx_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_current_ctx_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_current_ctx_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_current_ctx_target_m(void) -{ - return 0x3U << 28U; -} -static inline u32 gr_fecs_current_ctx_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 gr_fecs_current_ctx_valid_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_current_ctx_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_fecs_current_ctx_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_fecs_current_ctx_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_fecs_current_ctx_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_method_data_r(void) -{ - return 0x00409500U; -} -static inline u32 gr_fecs_method_push_r(void) -{ - return 0x00409504U; -} -static inline u32 gr_fecs_method_push_adr_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void) -{ - return 0x00000003U; -} -static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void) -{ - return 0x3U; -} -static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void) -{ - return 0x00000009U; -} -static inline u32 gr_fecs_method_push_adr_restore_golden_v(void) -{ - return 0x00000015U; -} -static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void) -{ - return 0x00000016U; -} -static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void) -{ - return 0x00000025U; -} -static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void) -{ - return 0x00000030U; -} -static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void) -{ - return 0x00000031U; -} -static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void) -{ - return 0x00000032U; -} -static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void) -{ - return 0x00000038U; -} -static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void) -{ - return 0x00000039U; -} -static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) -{ - return 0x21U; -} -static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void) -{ - return 0x0000001aU; -} -static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_fecs_host_int_status_r(void) -{ - return 0x00409c18U; -} -static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 gr_fecs_host_int_clear_r(void) -{ - return 0x00409c20U; -} -static inline u32 gr_fecs_host_int_enable_r(void) -{ - return 0x00409c24U; -} -static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void) -{ - return 0x10000U; -} -static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void) -{ - return 0x20000U; -} -static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void) -{ - return 0x40000U; -} -static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void) -{ - return 0x80000U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) -{ - return 0x00409614U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void) -{ - return 0x10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void) -{ - return 0x20U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void) -{ - return 0x40U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void) -{ - return 0x100U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void) -{ - return 0x200U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void) -{ - return 0x1U << 10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r) -{ - return (r >> 10U) & 0x1U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void) -{ - return 0x400U; -} -static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void) -{ - return 0x0040960cU; -} -static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i) -{ - return 0x00409800U + i*4U; -} -static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void) -{ - return 0x00000002U; -} -static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i) -{ - return 0x004098c0U + i*4U; -} -static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i) -{ - return 0x00409840U + i*4U; -} -static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_fs_r(void) -{ - return 0x00409604U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_m(void) -{ - return 0x1fU << 0U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_fecs_fs_num_available_fbps_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 gr_fecs_fs_num_available_fbps_m(void) -{ - return 0x1fU << 16U; -} -static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -static inline u32 gr_fecs_cfg_r(void) -{ - return 0x00409620U; -} -static inline u32 gr_fecs_cfg_imem_sz_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_fecs_rc_lanes_r(void) -{ - return 0x00409880U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_s(void) -{ - return 6U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_fecs_ctxsw_status_1_r(void) -{ - return 0x00409400U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void) -{ - return 0x1U << 12U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 gr_fecs_arb_ctx_adr_r(void) -{ - return 0x00409a24U; -} -static inline u32 gr_fecs_new_ctx_r(void) -{ - return 0x00409b04U; -} -static inline u32 gr_fecs_new_ctx_ptr_s(void) -{ - return 28U; -} -static inline u32 gr_fecs_new_ctx_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_new_ctx_ptr_m(void) -{ - return 0xfffffffU << 0U; -} -static inline u32 gr_fecs_new_ctx_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_new_ctx_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_new_ctx_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_new_ctx_target_m(void) -{ - return 0x3U << 28U; -} -static inline u32 gr_fecs_new_ctx_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_new_ctx_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_new_ctx_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 gr_fecs_new_ctx_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_fecs_new_ctx_valid_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_new_ctx_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_fecs_new_ctx_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_fecs_new_ctx_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_fecs_arb_ctx_ptr_r(void) -{ - return 0x00409a0cU; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void) -{ - return 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void) -{ - return 0xfffffffU << 0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_m(void) -{ - return 0x3U << 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_fecs_arb_ctx_cmd_r(void) -{ - return 0x00409a10U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void) -{ - return 0x1fU << 0U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_fecs_ctxsw_status_fe_0_r(void) -{ - return 0x00409c00U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void) -{ - return 0x00502c04U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) -{ - return 0x00502400U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_mailbox__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_fecs_ctxsw_idlestate_r(void) -{ - return 0x00409420U; -} -static inline u32 gr_fecs_feature_override_ecc_r(void) -{ - return 0x00409658U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) -{ - return 0x00502420U; -} -static inline u32 gr_rstr2d_gpc_map0_r(void) -{ - return 0x0040780cU; -} -static inline u32 gr_rstr2d_gpc_map1_r(void) -{ - return 0x00407810U; -} -static inline u32 gr_rstr2d_gpc_map2_r(void) -{ - return 0x00407814U; -} -static inline u32 gr_rstr2d_gpc_map3_r(void) -{ - return 0x00407818U; -} -static inline u32 gr_rstr2d_gpc_map4_r(void) -{ - return 0x0040781cU; -} -static inline u32 gr_rstr2d_gpc_map5_r(void) -{ - return 0x00407820U; -} -static inline u32 gr_rstr2d_map_table_cfg_r(void) -{ - return 0x004078bcU; -} -static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_pd_hww_esr_r(void) -{ - return 0x00406018U; -} -static inline u32 gr_pd_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pd_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i) -{ - return 0x00406028U + i*4U; -} -static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v) -{ - return (v & 0xfU) << 12U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v) -{ - return (v & 0xfU) << 24U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v) -{ - return (v & 0xfU) << 28U; -} -static inline u32 gr_pd_ab_dist_cfg0_r(void) -{ - return 0x004064c0U; -} -static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void) -{ - return 0x0U; -} -static inline u32 gr_pd_ab_dist_cfg1_r(void) -{ - return 0x004064c4U; -} -static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void) -{ - return 0xffffU; -} -static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void) -{ - return 0x00000080U; -} -static inline u32 gr_pd_ab_dist_cfg2_r(void) -{ - return 0x004064c8U; -} -static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) -{ - return (v & 0x1fffU) << 0U; -} -static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) -{ - return 0x00000900U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) -{ - return (v & 0x1fffU) << 16U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) -{ - return 0x00000900U; -} -static inline u32 gr_pd_dist_skip_table_r(u32 i) -{ - return 0x004064d0U + i*4U; -} -static inline u32 gr_pd_dist_skip_table__size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gr_ds_debug_r(void) -{ - return 0x00405800U; -} -static inline u32 gr_ds_debug_timeslice_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_debug_timeslice_mode_enable_f(void) -{ - return 0x8000000U; -} -static inline u32 gr_ds_zbc_color_r_r(void) -{ - return 0x00405804U; -} -static inline u32 gr_ds_zbc_color_r_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_g_r(void) -{ - return 0x00405808U; -} -static inline u32 gr_ds_zbc_color_g_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_b_r(void) -{ - return 0x0040580cU; -} -static inline u32 gr_ds_zbc_color_b_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_a_r(void) -{ - return 0x00405810U; -} -static inline u32 gr_ds_zbc_color_a_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_fmt_r(void) -{ - return 0x00405814U; -} -static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v) -{ - return (v & 0x7fU) << 0U; -} -static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void) -{ - return 0x00000002U; -} -static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) -{ - return 0x00000028U; -} -static inline u32 gr_ds_zbc_z_r(void) -{ - return 0x00405818U; -} -static inline u32 gr_ds_zbc_z_val_s(void) -{ - return 32U; -} -static inline u32 gr_ds_zbc_z_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_z_val_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 gr_ds_zbc_z_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gr_ds_zbc_z_val__init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_ds_zbc_z_val__init_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_z_fmt_r(void) -{ - return 0x0040581cU; -} -static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_zbc_tbl_index_r(void) -{ - return 0x00405820U; -} -static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_ds_zbc_tbl_ld_r(void) -{ - return 0x00405824U; -} -static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) -{ - return 0x4U; -} -static inline u32 gr_ds_tga_constraintlogic_beta_r(void) -{ - return 0x00405830U; -} -static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_ds_tga_constraintlogic_alpha_r(void) -{ - return 0x0040585cU; -} -static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_ds_hww_esr_r(void) -{ - return 0x00405840U; -} -static inline u32 gr_ds_hww_esr_reset_s(void) -{ - return 1U; -} -static inline u32 gr_ds_hww_esr_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_reset_m(void) -{ - return 0x1U << 30U; -} -static inline u32 gr_ds_hww_esr_reset_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_ds_hww_esr_reset_task_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_hww_esr_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_ds_hww_esr_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_ds_hww_esr_2_r(void) -{ - return 0x00405848U; -} -static inline u32 gr_ds_hww_esr_2_reset_s(void) -{ - return 1U; -} -static inline u32 gr_ds_hww_esr_2_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_2_reset_m(void) -{ - return 0x1U << 30U; -} -static inline u32 gr_ds_hww_esr_2_reset_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_ds_hww_esr_2_reset_task_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_hww_esr_2_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_ds_hww_esr_2_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_ds_hww_report_mask_r(void) -{ - return 0x00405844U; -} -static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void) -{ - return 0x8U; -} -static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void) -{ - return 0x80U; -} -static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void) -{ - return 0x200U; -} -static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void) -{ - return 0x400U; -} -static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void) -{ - return 0x800U; -} -static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void) -{ - return 0x1000U; -} -static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void) -{ - return 0x2000U; -} -static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void) -{ - return 0x4000U; -} -static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void) -{ - return 0x8000U; -} -static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void) -{ - return 0x10000U; -} -static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void) -{ - return 0x20000U; -} -static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void) -{ - return 0x40000U; -} -static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void) -{ - return 0x80000U; -} -static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void) -{ - return 0x100000U; -} -static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void) -{ - return 0x200000U; -} -static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void) -{ - return 0x400000U; -} -static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void) -{ - return 0x800000U; -} -static inline u32 gr_ds_hww_report_mask_2_r(void) -{ - return 0x0040584cU; -} -static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i) -{ - return 0x00405870U + i*4U; -} -static inline u32 gr_scc_bundle_cb_base_r(void) -{ - return 0x00408004U; -} -static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_scc_bundle_cb_size_r(void) -{ - return 0x00408008U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7ffU) << 0U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) -{ - return 0x00000030U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_scc_bundle_cb_size_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_scc_bundle_cb_size_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_scc_bundle_cb_size_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_scc_pagepool_base_r(void) -{ - return 0x0040800cU; -} -static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_scc_pagepool_r(void) -{ - return 0x00408010U; -} -static inline u32 gr_scc_pagepool_total_pages_f(u32 v) -{ - return (v & 0x3ffU) << 0U; -} -static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void) -{ - return 0x00000200U; -} -static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_s(void) -{ - return 10U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) -{ - return (v & 0x3ffU) << 10U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_m(void) -{ - return 0x3ffU << 10U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) -{ - return (r >> 10U) & 0x3ffU; -} -static inline u32 gr_scc_pagepool_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_scc_init_r(void) -{ - return 0x0040802cU; -} -static inline u32 gr_scc_init_ram_trigger_f(void) -{ - return 0x1U; -} -static inline u32 gr_scc_hww_esr_r(void) -{ - return 0x00408030U; -} -static inline u32 gr_scc_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_scc_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_sked_hww_esr_r(void) -{ - return 0x00407020U; -} -static inline u32 gr_sked_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_cwd_fs_r(void) -{ - return 0x00405b00U; -} -static inline u32 gr_cwd_fs_num_gpcs_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_cwd_fs_num_tpcs_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_cwd_gpc_tpc_id_r(u32 i) -{ - return 0x00405b60U + i*4U; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void) -{ - return 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void) -{ - return 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_cwd_sm_id_r(u32 i) -{ - return 0x00405ba0U + i*4U; -} -static inline u32 gr_cwd_sm_id__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_cwd_sm_id_tpc1_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpc0_fs_gpc_r(void) -{ - return 0x00502608U; -} -static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -static inline u32 gr_gpc0_cfg_r(void) -{ - return 0x00502620U; -} -static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpccs_rc_lanes_r(void) -{ - return 0x00502880U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_gpccs_rc_lane_size_r(void) -{ - return 0x00502910U; -} -static inline u32 gr_gpccs_rc_lane_size_v_s(void) -{ - return 24U; -} -static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_gpccs_rc_lane_size_v_m(void) -{ - return 0xffffffU << 0U; -} -static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_zcull_fs_r(void) -{ - return 0x00500910U; -} -static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 gr_gpc0_zcull_ram_addr_r(void) -{ - return 0x00500914U; -} -static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void) -{ - return 0x00500918U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void) -{ - return 0x00800000U; -} -static inline u32 gr_gpc0_zcull_total_ram_size_r(void) -{ - return 0x00500920U; -} -static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_zcull_zcsize_r(u32 i) -{ - return 0x00500a04U + i*32U; -} -static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void) -{ - return 0x00000040U; -} -static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i) -{ - return 0x00500c10U + i*4U; -} -static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i) -{ - return 0x00500c30U + i*4U; -} -static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void) -{ - return 0x00504088U; -} -static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) -{ - return 0x00504698U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_arch_r(void) -{ - return 0x0050469cU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r) -{ - return (r >> 8U) & 0xfffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r) -{ - return (r >> 20U) & 0xfffU; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) -{ - return 0x00503018U; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void) -{ - return 0x005030c0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) -{ - return 0x3fffffU << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) -{ - return 0x00000320U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) -{ - return 0x00000ba8U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void) -{ - return 0x005030f4U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void) -{ - return 0x005030e4U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void) -{ - return 0x00000800U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) -{ - return 0x005030f8U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void) -{ - return 0x005030f0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) -{ - return 0x00000320U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) -{ - return 0x00419b00U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void) -{ - return 0x00419b04U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void) -{ - return 21U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v) -{ - return (v & 0x1fffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void) -{ - return 0x1fffffU << 0U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r) -{ - return (r >> 0U) & 0x1fffffU; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void) -{ - return 0x80U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void) -{ - return 1U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpccs_falcon_addr_r(void) -{ - return 0x0041a0acU; -} -static inline u32 gr_gpccs_falcon_addr_lsb_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpccs_falcon_addr_msb_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v) -{ - return (v & 0x3fU) << 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_m(void) -{ - return 0x3fU << 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r) -{ - return (r >> 6U) & 0x3fU; -} -static inline u32 gr_gpccs_falcon_addr_msb_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_falcon_addr_msb_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_s(void) -{ - return 12U; -} -static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_m(void) -{ - return 0xfffU << 0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 gr_gpccs_cpuctl_r(void) -{ - return 0x0041a100U; -} -static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_gpccs_dmactl_r(void) -{ - return 0x0041a10cU; -} -static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_gpccs_imemc_r(u32 i) -{ - return 0x0041a180U + i*16U; -} -static inline u32 gr_gpccs_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_gpccs_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpccs_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_gpccs_imemd_r(u32 i) -{ - return 0x0041a184U + i*16U; -} -static inline u32 gr_gpccs_imemt_r(u32 i) -{ - return 0x0041a188U + i*16U; -} -static inline u32 gr_gpccs_imemt__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_gpccs_imemt_tag_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpccs_dmemc_r(u32 i) -{ - return 0x0041a1c0U + i*8U; -} -static inline u32 gr_gpccs_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_gpccs_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpccs_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_gpccs_dmemd_r(u32 i) -{ - return 0x0041a1c4U + i*8U; -} -static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i) -{ - return 0x0041a800U + i*4U; -} -static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void) -{ - return 0x00418e24U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void) -{ - return 32U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void) -{ - return 0x00418e28U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void) -{ - return 11U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7ffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void) -{ - return 0x7ffU << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) -{ - return (r >> 0U) & 0x7ffU; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) -{ - return 0x00000030U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) -{ - return 0x30U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) -{ - return 1U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void) -{ - return 0x005001dcU; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void) -{ - return 0x00000de0U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void) -{ - return 0x005001d8U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void) -{ - return 0x004181e4U; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void) -{ - return 0x0041befcU; -} -static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) -{ - return 0x00418ea0U + i*4U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) -{ - return 0x3fffffU << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i) -{ - return 0x00418010U + i*4U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i) -{ - return 0x0041804cU + i*4U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i) -{ - return 0x00418088U + i*4U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i) -{ - return 0x004180c4U + i*4U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void) -{ - return 0x00500100U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i) -{ - return 0x00418110U + i*4U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void) -{ - return 0x0050014cU; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) -{ - return 0x00418810U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void) -{ - return 0x0000000cU; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_crstr_gpc_map0_r(void) -{ - return 0x00418b08U; -} -static inline u32 gr_crstr_gpc_map0_tile0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map0_tile1_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map0_tile2_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map0_tile3_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map0_tile4_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map0_tile5_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map1_r(void) -{ - return 0x00418b0cU; -} -static inline u32 gr_crstr_gpc_map1_tile6_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map1_tile7_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map1_tile8_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map1_tile9_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map1_tile10_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map1_tile11_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map2_r(void) -{ - return 0x00418b10U; -} -static inline u32 gr_crstr_gpc_map2_tile12_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map2_tile13_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map2_tile14_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map2_tile15_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map2_tile16_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map2_tile17_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map3_r(void) -{ - return 0x00418b14U; -} -static inline u32 gr_crstr_gpc_map3_tile18_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map3_tile19_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map3_tile20_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map3_tile21_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map3_tile22_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map3_tile23_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map4_r(void) -{ - return 0x00418b18U; -} -static inline u32 gr_crstr_gpc_map4_tile24_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map4_tile25_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map4_tile26_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map4_tile27_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map4_tile28_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map4_tile29_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map5_r(void) -{ - return 0x00418b1cU; -} -static inline u32 gr_crstr_gpc_map5_tile30_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map5_tile31_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map5_tile32_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map5_tile33_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map5_tile34_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map5_tile35_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_map_table_cfg_r(void) -{ - return 0x00418bb8U; -} -static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_r(void) -{ - return 0x00418980U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_r(void) -{ - return 0x00418984U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_r(void) -{ - return 0x00418988U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s(void) -{ - return 3U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void) -{ - return 0x7U << 28U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r) -{ - return (r >> 28U) & 0x7U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_r(void) -{ - return 0x0041898cU; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_gpm_pd_cfg_r(void) -{ - return 0x00418c6cU; -} -static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpcs_gcc_pagepool_base_r(void) -{ - return 0x00419004U; -} -static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_gcc_pagepool_r(void) -{ - return 0x00419008U; -} -static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v) -{ - return (v & 0x3ffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_pe_vaf_r(void) -{ - return 0x0041980cU; -} -static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void) -{ - return 0x00419848U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) -{ - return 0x00419c00U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void) -{ - return 0x00419c2cU; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void) -{ - return 0x00419e44U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f(void) -{ - return 0x80U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) -{ - return 0x200U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f(void) -{ - return 0x400U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) -{ - return 0x800U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f(void) -{ - return 0x1000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f(void) -{ - return 0x2000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f(void) -{ - return 0x4000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f(void) -{ - return 0x8000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) -{ - return 0x10000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f(void) -{ - return 0x20000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) -{ - return 0x40000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_mmu_fault_report_f(void) -{ - return 0x800000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_overflow_report_f(void) -{ - return 0x400000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f(void) -{ - return 0x80000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(void) -{ - return 0x100000U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_report_mask_r(void) -{ - return 0x00504644U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void) -{ - return 0x00419e4cU; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_sec_error_report_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_ded_error_report_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_report_mask_r(void) -{ - return 0x0050464cU; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) -{ - return 0x00419d0cU; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) -{ - return 0x0050450cU; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) -{ - return 0x0041ac94U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) -{ - return 0x00502c90U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) -{ - return 0x00504508U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void) -{ - return 0x00504610U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void) -{ - return 0x00504614U; -} -static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_1_r(void) -{ - return 0x00504618U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void) -{ - return 0x00504624U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_1_r(void) -{ - return 0x00504628U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void) -{ - return 0x00504634U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_1_r(void) -{ - return 0x00504638U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void) -{ - return 0x00419e24U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_stop_on_any_warp_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_stop_on_any_sm_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) -{ - return 0x0050460cU; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void) -{ - return 0x00419e50U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void) -{ - return 0x00504650U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_sec_error_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_ded_error_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void) -{ - return 0x00504224U; -} -static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void) -{ - return 0x00504648U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) -{ - return 0x00504770U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) -{ - return 0x00419f70U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) -{ - return 0x0050477cU; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) -{ - return 0x00419f7cU; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) -{ - return 0x0041be08U; -} -static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) -{ - return 0x4U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map0_r(void) -{ - return 0x0041bf00U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map1_r(void) -{ - return 0x0041bf04U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map2_r(void) -{ - return 0x0041bf08U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map3_r(void) -{ - return 0x0041bf0cU; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map4_r(void) -{ - return 0x0041bf10U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map5_r(void) -{ - return 0x0041bf14U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) -{ - return 0x0041bfd0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) -{ - return (v & 0x7U) << 21U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 24U; -} -static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) -{ - return 0x0041bfd4U; -} -static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_r(void) -{ - return 0x0041bfe4U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 5U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 10U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 15U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 20U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 25U; -} -static inline u32 gr_bes_zrop_settings_r(void) -{ - return 0x00408850U; -} -static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_be0_crop_debug3_r(void) -{ - return 0x00410108U; -} -static inline u32 gr_bes_crop_debug3_r(void) -{ - return 0x00408908U; -} -static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_bes_crop_debug3_blendopt_fill_override_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_bes_crop_debug3_blendopt_fill_override_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_bes_crop_debug3_blendopt_fill_override_enabled_f(void) -{ - return 0x4U; -} -static inline u32 gr_bes_crop_debug4_r(void) -{ - return 0x0040894cU; -} -static inline u32 gr_bes_crop_debug4_clamp_fp_blend_m(void) -{ - return 0x1U << 18U; -} -static inline u32 gr_bes_crop_debug4_clamp_fp_blend_to_inf_f(void) -{ - return 0x0U; -} -static inline u32 gr_bes_crop_debug4_clamp_fp_blend_to_maxval_f(void) -{ - return 0x40000U; -} -static inline u32 gr_bes_crop_settings_r(void) -{ - return 0x00408958U; -} -static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void) -{ - return 0x000000c0U; -} -static inline u32 gr_zcull_subregion_qty_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void) -{ - return 0x00504604U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void) -{ - return 0x00504608U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void) -{ - return 0x0050465cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void) -{ - return 0x00504660U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void) -{ - return 0x00504664U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void) -{ - return 0x00504668U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void) -{ - return 0x0050466cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void) -{ - return 0x00504658U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void) -{ - return 0x00504730U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void) -{ - return 0x00504734U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void) -{ - return 0x00504738U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void) -{ - return 0x0050473cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void) -{ - return 0x00504740U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void) -{ - return 0x00504744U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void) -{ - return 0x00504748U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void) -{ - return 0x0050474cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_s1_r(void) -{ - return 0x00504678U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r(void) -{ - return 0x00504694U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s0_r(void) -{ - return 0x005046f0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s1_r(void) -{ - return 0x00504700U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s0_r(void) -{ - return 0x005046f4U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s1_r(void) -{ - return 0x00504704U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s0_r(void) -{ - return 0x005046f8U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s1_r(void) -{ - return 0x00504708U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s0_r(void) -{ - return 0x005046fcU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s1_r(void) -{ - return 0x0050470cU; -} -static inline u32 gr_fe_pwr_mode_r(void) -{ - return 0x00404170U; -} -static inline u32 gr_fe_pwr_mode_mode_auto_f(void) -{ - return 0x0U; -} -static inline u32 gr_fe_pwr_mode_mode_force_on_f(void) -{ - return 0x2U; -} -static inline u32 gr_fe_pwr_mode_req_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 gr_fe_pwr_mode_req_send_f(void) -{ - return 0x10U; -} -static inline u32 gr_fe_pwr_mode_req_done_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) -{ - return 0x00418880U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void) -{ - return 0x1U << 11U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void) -{ - return 0x3U << 3U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void) -{ - return 0x3U << 5U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void) -{ - return 0x3U << 28U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void) -{ - return 0x1U << 30U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) -{ - return 0x00418890U; -} -static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void) -{ - return 0x00418894U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) -{ - return 0x004188b0U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) -{ - return 0x004188b4U; -} -static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void) -{ - return 0x004188b8U; -} -static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) -{ - return 0x004188acU; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void) -{ - return 0x00419e10U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) -{ - return 0x1U << 30U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_fe_gfxp_wfi_timeout_r(void) -{ - return 0x004041c0U; -} -static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void) -{ - return 0x00419c84U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void) -{ - return 0x7U << 8U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void) -{ - return 0x00419f78U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void) -{ - return 0x3U << 11U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void) -{ - return 0x1000U; -} -static inline u32 gr_gpcs_tc_debug0_r(void) -{ - return 0x00418708U; -} -static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) -{ - return 0x1ffU << 0U; -} -#endif diff --git a/include/nvgpu/hw/gp106/hw_ltc_gp106.h b/include/nvgpu/hw/gp106/hw_ltc_gp106.h deleted file mode 100644 index e4e87aa..0000000 --- a/include/nvgpu/hw/gp106/hw_ltc_gp106.h +++ /dev/null @@ -1,559 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ltc_gp106_h_ -#define _hw_ltc_gp106_h_ - -static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) -{ - return 0x0014046cU; -} -static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) -{ - return 0x00140518U; -} -static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) -{ - return 0x0017e318U; -} -static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void) -{ - return 0x1U << 15U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) -{ - return 0x00140494U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) -{ - return (r >> 16U) & 0x3U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) -{ - return 0x00000000U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) -{ - return 0x00000002U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) -{ - return 0x0017e26cU; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) -{ - return 0x2U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) -{ - return 0x4U; -} -static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) -{ - return 0x0014046cU; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) -{ - return 0x0017e270U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) -{ - return (v & 0x3ffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) -{ - return 0x0017e274U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) -{ - return (v & 0x3ffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) -{ - return 0x0003ffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_base_r(void) -{ - return 0x0017e278U; -} -static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) -{ - return 0x0000000bU; -} -static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) -{ - return (r >> 0U) & 0x3ffffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) -{ - return 0x0017e27cU; -} -static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) -{ - return 0x0017e000U; -} -static inline u32 ltc_ltcs_ltss_cbc_param_r(void) -{ - return 0x0017e280U; -} -static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r) -{ - return (r >> 24U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r) -{ - return (r >> 28U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_cbc_param2_r(void) -{ - return 0x0017e3f4U; -} -static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) -{ - return 0x0017e2acU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) -{ - return 0x0017e338U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) -{ - return 0x0017e33cU + i*4U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) -{ - return 0x0017e34cU; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) -{ - return 32U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) -{ - return 0x0017e2b0U; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_r(void) -{ - return 0x0017e214U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_r(void) -{ - return 0x00140214U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc1_ltss_g_elpg_r(void) -{ - return 0x00142214U; -} -static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_intr_r(void) -{ - return 0x0017e20cU; -} -static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void) -{ - return 0x100U; -} -static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void) -{ - return 0x200U; -} -static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) -{ - return 0x1U << 20U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) -{ - return 0x1U << 30U; -} -static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void) -{ - return 0x1000000U; -} -static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void) -{ - return 0x2000000U; -} -static inline u32 ltc_ltc0_lts0_intr_r(void) -{ - return 0x0014040cU; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void) -{ - return 0x0014051cU; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void) -{ - return 0xffU << 0U; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void) -{ - return 0xffU << 16U; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) -{ - return 0x0017e2a0U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) -{ - return 0x300U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) -{ - return 0x20000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) -{ - return 0x40000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) -{ - return 0x0017e2a4U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) -{ - return 0x300U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) -{ - return 0x10000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) -{ - return 0x20000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) -{ - return 0x40000000U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) -{ - return 0x001402a0U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) -{ - return 0x001402a4U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void) -{ - return 0x001422a0U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void) -{ - return 0x001422a4U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void) -{ - return 0x0014058cU; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -#endif diff --git a/include/nvgpu/hw/gp106/hw_mc_gp106.h b/include/nvgpu/hw/gp106/hw_mc_gp106.h deleted file mode 100644 index 349e2d7..0000000 --- a/include/nvgpu/hw/gp106/hw_mc_gp106.h +++ /dev/null @@ -1,251 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_mc_gp106_h_ -#define _hw_mc_gp106_h_ - -static inline u32 mc_boot_0_r(void) -{ - return 0x00000000U; -} -static inline u32 mc_boot_0_architecture_v(u32 r) -{ - return (r >> 24U) & 0x1fU; -} -static inline u32 mc_boot_0_implementation_v(u32 r) -{ - return (r >> 20U) & 0xfU; -} -static inline u32 mc_boot_0_major_revision_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 mc_boot_0_minor_revision_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 mc_intr_r(u32 i) -{ - return 0x00000100U + i*4U; -} -static inline u32 mc_intr_pfifo_pending_f(void) -{ - return 0x100U; -} -static inline u32 mc_intr_replayable_fault_pending_f(void) -{ - return 0x200U; -} -static inline u32 mc_intr_pgraph_pending_f(void) -{ - return 0x1000U; -} -static inline u32 mc_intr_pmu_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 mc_intr_ltc_pending_f(void) -{ - return 0x2000000U; -} -static inline u32 mc_intr_priv_ring_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 mc_intr_pbus_pending_f(void) -{ - return 0x10000000U; -} -static inline u32 mc_intr_en_r(u32 i) -{ - return 0x00000140U + i*4U; -} -static inline u32 mc_intr_en_set_r(u32 i) -{ - return 0x00000160U + i*4U; -} -static inline u32 mc_intr_en_clear_r(u32 i) -{ - return 0x00000180U + i*4U; -} -static inline u32 mc_enable_r(void) -{ - return 0x00000200U; -} -static inline u32 mc_enable_xbar_enabled_f(void) -{ - return 0x4U; -} -static inline u32 mc_enable_l2_enabled_f(void) -{ - return 0x8U; -} -static inline u32 mc_enable_pmedia_s(void) -{ - return 1U; -} -static inline u32 mc_enable_pmedia_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 mc_enable_pmedia_m(void) -{ - return 0x1U << 4U; -} -static inline u32 mc_enable_pmedia_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 mc_enable_priv_ring_enabled_f(void) -{ - return 0x20U; -} -static inline u32 mc_enable_ce0_m(void) -{ - return 0x1U << 6U; -} -static inline u32 mc_enable_pfifo_enabled_f(void) -{ - return 0x100U; -} -static inline u32 mc_enable_pgraph_enabled_f(void) -{ - return 0x1000U; -} -static inline u32 mc_enable_pwr_v(u32 r) -{ - return (r >> 13U) & 0x1U; -} -static inline u32 mc_enable_pwr_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 mc_enable_pwr_enabled_f(void) -{ - return 0x2000U; -} -static inline u32 mc_enable_pfb_enabled_f(void) -{ - return 0x100000U; -} -static inline u32 mc_enable_ce2_m(void) -{ - return 0x1U << 21U; -} -static inline u32 mc_enable_ce2_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 mc_enable_blg_enabled_f(void) -{ - return 0x8000000U; -} -static inline u32 mc_enable_perfmon_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 mc_enable_hub_enabled_f(void) -{ - return 0x20000000U; -} -static inline u32 mc_intr_ltc_r(void) -{ - return 0x000001c0U; -} -static inline u32 mc_enable_pb_r(void) -{ - return 0x00000204U; -} -static inline u32 mc_enable_pb_0_s(void) -{ - return 1U; -} -static inline u32 mc_enable_pb_0_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 mc_enable_pb_0_m(void) -{ - return 0x1U << 0U; -} -static inline u32 mc_enable_pb_0_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 mc_enable_pb_0_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 mc_enable_pb_sel_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 mc_elpg_enable_r(void) -{ - return 0x0000020cU; -} -static inline u32 mc_elpg_enable_xbar_enabled_f(void) -{ - return 0x4U; -} -static inline u32 mc_elpg_enable_pfb_enabled_f(void) -{ - return 0x100000U; -} -static inline u32 mc_elpg_enable_hub_enabled_f(void) -{ - return 0x20000000U; -} -#endif diff --git a/include/nvgpu/hw/gp106/hw_pbdma_gp106.h b/include/nvgpu/hw/gp106/hw_pbdma_gp106.h deleted file mode 100644 index 1005c5a..0000000 --- a/include/nvgpu/hw/gp106/hw_pbdma_gp106.h +++ /dev/null @@ -1,535 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pbdma_gp106_h_ -#define _hw_pbdma_gp106_h_ - -static inline u32 pbdma_gp_entry1_r(void) -{ - return 0x10000004U; -} -static inline u32 pbdma_gp_entry1_get_hi_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pbdma_gp_entry1_length_f(u32 v) -{ - return (v & 0x1fffffU) << 10U; -} -static inline u32 pbdma_gp_entry1_length_v(u32 r) -{ - return (r >> 10U) & 0x1fffffU; -} -static inline u32 pbdma_gp_base_r(u32 i) -{ - return 0x00040048U + i*8192U; -} -static inline u32 pbdma_gp_base__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 pbdma_gp_base_offset_f(u32 v) -{ - return (v & 0x1fffffffU) << 3U; -} -static inline u32 pbdma_gp_base_rsvd_s(void) -{ - return 3U; -} -static inline u32 pbdma_gp_base_hi_r(u32 i) -{ - return 0x0004004cU + i*8192U; -} -static inline u32 pbdma_gp_base_hi_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pbdma_gp_base_hi_limit2_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 pbdma_gp_fetch_r(u32 i) -{ - return 0x00040050U + i*8192U; -} -static inline u32 pbdma_gp_get_r(u32 i) -{ - return 0x00040014U + i*8192U; -} -static inline u32 pbdma_gp_put_r(u32 i) -{ - return 0x00040000U + i*8192U; -} -static inline u32 pbdma_pb_fetch_r(u32 i) -{ - return 0x00040054U + i*8192U; -} -static inline u32 pbdma_pb_fetch_hi_r(u32 i) -{ - return 0x00040058U + i*8192U; -} -static inline u32 pbdma_get_r(u32 i) -{ - return 0x00040018U + i*8192U; -} -static inline u32 pbdma_get_hi_r(u32 i) -{ - return 0x0004001cU + i*8192U; -} -static inline u32 pbdma_put_r(u32 i) -{ - return 0x0004005cU + i*8192U; -} -static inline u32 pbdma_put_hi_r(u32 i) -{ - return 0x00040060U + i*8192U; -} -static inline u32 pbdma_formats_r(u32 i) -{ - return 0x0004009cU + i*8192U; -} -static inline u32 pbdma_formats_gp_fermi0_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_formats_pb_fermi1_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_formats_mp_fermi0_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_r(u32 i) -{ - return 0x00040084U + i*8192U; -} -static inline u32 pbdma_pb_header_priv_user_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_method_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_subchannel_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_level_main_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_first_true_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_pb_header_type_inc_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_pb_header_type_non_inc_f(void) -{ - return 0x60000000U; -} -static inline u32 pbdma_hdr_shadow_r(u32 i) -{ - return 0x00040118U + i*8192U; -} -static inline u32 pbdma_gp_shadow_0_r(u32 i) -{ - return 0x00040110U + i*8192U; -} -static inline u32 pbdma_gp_shadow_1_r(u32 i) -{ - return 0x00040114U + i*8192U; -} -static inline u32 pbdma_subdevice_r(u32 i) -{ - return 0x00040094U + i*8192U; -} -static inline u32 pbdma_subdevice_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 pbdma_subdevice_status_active_f(void) -{ - return 0x10000000U; -} -static inline u32 pbdma_subdevice_channel_dma_enable_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_method0_r(u32 i) -{ - return 0x000400c0U + i*8192U; -} -static inline u32 pbdma_method0_fifo_size_v(void) -{ - return 0x00000004U; -} -static inline u32 pbdma_method0_addr_f(u32 v) -{ - return (v & 0xfffU) << 2U; -} -static inline u32 pbdma_method0_addr_v(u32 r) -{ - return (r >> 2U) & 0xfffU; -} -static inline u32 pbdma_method0_subch_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 pbdma_method0_first_true_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_method0_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_method1_r(u32 i) -{ - return 0x000400c8U + i*8192U; -} -static inline u32 pbdma_method2_r(u32 i) -{ - return 0x000400d0U + i*8192U; -} -static inline u32 pbdma_method3_r(u32 i) -{ - return 0x000400d8U + i*8192U; -} -static inline u32 pbdma_data0_r(u32 i) -{ - return 0x000400c4U + i*8192U; -} -static inline u32 pbdma_target_r(u32 i) -{ - return 0x000400acU + i*8192U; -} -static inline u32 pbdma_target_engine_sw_f(void) -{ - return 0x1fU; -} -static inline u32 pbdma_acquire_r(u32 i) -{ - return 0x00040030U + i*8192U; -} -static inline u32 pbdma_acquire_retry_man_2_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_acquire_retry_exp_2_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_acquire_timeout_exp_max_f(void) -{ - return 0x7800U; -} -static inline u32 pbdma_acquire_timeout_man_max_f(void) -{ - return 0x7fff8000U; -} -static inline u32 pbdma_acquire_timeout_en_disable_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_status_r(u32 i) -{ - return 0x00040100U + i*8192U; -} -static inline u32 pbdma_channel_r(u32 i) -{ - return 0x00040120U + i*8192U; -} -static inline u32 pbdma_signature_r(u32 i) -{ - return 0x00040010U + i*8192U; -} -static inline u32 pbdma_signature_hw_valid_f(void) -{ - return 0xfaceU; -} -static inline u32 pbdma_signature_sw_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_userd_r(u32 i) -{ - return 0x00040008U + i*8192U; -} -static inline u32 pbdma_userd_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_userd_target_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 pbdma_userd_addr_f(u32 v) -{ - return (v & 0x7fffffU) << 9U; -} -static inline u32 pbdma_userd_hi_r(u32 i) -{ - return 0x0004000cU + i*8192U; -} -static inline u32 pbdma_userd_hi_addr_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pbdma_config_r(u32 i) -{ - return 0x000400f4U + i*8192U; -} -static inline u32 pbdma_config_auth_level_privileged_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_hce_ctrl_r(u32 i) -{ - return 0x000400e4U + i*8192U; -} -static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void) -{ - return 0x20U; -} -static inline u32 pbdma_intr_0_r(u32 i) -{ - return 0x00040108U + i*8192U; -} -static inline u32 pbdma_intr_0_memreq_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pbdma_intr_0_memreq_pending_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_intr_0_memack_timeout_pending_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_intr_0_memack_extra_pending_f(void) -{ - return 0x4U; -} -static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void) -{ - return 0x8U; -} -static inline u32 pbdma_intr_0_memdat_extra_pending_f(void) -{ - return 0x10U; -} -static inline u32 pbdma_intr_0_memflush_pending_f(void) -{ - return 0x20U; -} -static inline u32 pbdma_intr_0_memop_pending_f(void) -{ - return 0x40U; -} -static inline u32 pbdma_intr_0_lbconnect_pending_f(void) -{ - return 0x80U; -} -static inline u32 pbdma_intr_0_lbreq_pending_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_0_lback_timeout_pending_f(void) -{ - return 0x200U; -} -static inline u32 pbdma_intr_0_lback_extra_pending_f(void) -{ - return 0x400U; -} -static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void) -{ - return 0x800U; -} -static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void) -{ - return 0x1000U; -} -static inline u32 pbdma_intr_0_gpfifo_pending_f(void) -{ - return 0x2000U; -} -static inline u32 pbdma_intr_0_gpptr_pending_f(void) -{ - return 0x4000U; -} -static inline u32 pbdma_intr_0_gpentry_pending_f(void) -{ - return 0x8000U; -} -static inline u32 pbdma_intr_0_gpcrc_pending_f(void) -{ - return 0x10000U; -} -static inline u32 pbdma_intr_0_pbptr_pending_f(void) -{ - return 0x20000U; -} -static inline u32 pbdma_intr_0_pbentry_pending_f(void) -{ - return 0x40000U; -} -static inline u32 pbdma_intr_0_pbcrc_pending_f(void) -{ - return 0x80000U; -} -static inline u32 pbdma_intr_0_xbarconnect_pending_f(void) -{ - return 0x100000U; -} -static inline u32 pbdma_intr_0_method_pending_f(void) -{ - return 0x200000U; -} -static inline u32 pbdma_intr_0_methodcrc_pending_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_intr_0_device_pending_f(void) -{ - return 0x800000U; -} -static inline u32 pbdma_intr_0_semaphore_pending_f(void) -{ - return 0x2000000U; -} -static inline u32 pbdma_intr_0_acquire_pending_f(void) -{ - return 0x4000000U; -} -static inline u32 pbdma_intr_0_pri_pending_f(void) -{ - return 0x8000000U; -} -static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_intr_0_pbseg_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 pbdma_intr_0_signature_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_intr_1_r(u32 i) -{ - return 0x00040148U + i*8192U; -} -static inline u32 pbdma_intr_en_0_r(u32 i) -{ - return 0x0004010cU + i*8192U; -} -static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_en_1_r(u32 i) -{ - return 0x0004014cU + i*8192U; -} -static inline u32 pbdma_intr_stall_r(u32 i) -{ - return 0x0004013cU + i*8192U; -} -static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_stall_1_r(u32 i) -{ - return 0x00040140U + i*8192U; -} -static inline u32 pbdma_intr_stall_1_hce_illegal_op_enabled_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_udma_nop_r(void) -{ - return 0x00000008U; -} -static inline u32 pbdma_runlist_timeslice_r(u32 i) -{ - return 0x000400f8U + i*8192U; -} -static inline u32 pbdma_runlist_timeslice_timeout_128_f(void) -{ - return 0x80U; -} -static inline u32 pbdma_runlist_timeslice_timescale_3_f(void) -{ - return 0x3000U; -} -static inline u32 pbdma_runlist_timeslice_enable_true_f(void) -{ - return 0x10000000U; -} -#endif diff --git a/include/nvgpu/hw/gp106/hw_perf_gp106.h b/include/nvgpu/hw/gp106/hw_perf_gp106.h deleted file mode 100644 index 334cd20..0000000 --- a/include/nvgpu/hw/gp106/hw_perf_gp106.h +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_perf_gp106_h_ -#define _hw_perf_gp106_h_ - -static inline u32 perf_pmmsys_base_v(void) -{ - return 0x001b0000U; -} -static inline u32 perf_pmmsys_extent_v(void) -{ - return 0x001b0fffU; -} -static inline u32 perf_pmasys_control_r(void) -{ - return 0x001b4000U; -} -static inline u32 perf_pmasys_control_membuf_status_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void) -{ - return 0x10U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) -{ - return 0x20U; -} -static inline u32 perf_pmasys_mem_block_r(void) -{ - return 0x001b4070U; -} -static inline u32 perf_pmasys_mem_block_base_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 perf_pmasys_mem_block_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 perf_pmasys_mem_block_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 perf_pmasys_mem_block_target_lfb_v(void) -{ - return 0x00000000U; -} -static inline u32 perf_pmasys_mem_block_target_lfb_f(void) -{ - return 0x0U; -} -static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 perf_pmasys_mem_block_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 perf_pmasys_mem_block_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 perf_pmasys_mem_block_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_mem_block_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 perf_pmasys_mem_block_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 perf_pmasys_mem_block_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 perf_pmasys_outbase_r(void) -{ - return 0x001b4074U; -} -static inline u32 perf_pmasys_outbase_ptr_f(u32 v) -{ - return (v & 0x7ffffffU) << 5U; -} -static inline u32 perf_pmasys_outbaseupper_r(void) -{ - return 0x001b4078U; -} -static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 perf_pmasys_outsize_r(void) -{ - return 0x001b407cU; -} -static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) -{ - return (v & 0x7ffffffU) << 5U; -} -static inline u32 perf_pmasys_mem_bytes_r(void) -{ - return 0x001b4084U; -} -static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 perf_pmasys_mem_bump_r(void) -{ - return 0x001b4088U; -} -static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 perf_pmasys_enginestatus_r(void) -{ - return 0x001b40a4U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void) -{ - return 0x10U; -} -#endif diff --git a/include/nvgpu/hw/gp106/hw_pram_gp106.h b/include/nvgpu/hw/gp106/hw_pram_gp106.h deleted file mode 100644 index 7e33e71..0000000 --- a/include/nvgpu/hw/gp106/hw_pram_gp106.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pram_gp106_h_ -#define _hw_pram_gp106_h_ - -static inline u32 pram_data032_r(u32 i) -{ - return 0x00700000U + i*4U; -} -#endif diff --git a/include/nvgpu/hw/gp106/hw_pri_ringmaster_gp106.h b/include/nvgpu/hw/gp106/hw_pri_ringmaster_gp106.h deleted file mode 100644 index efdedc3..0000000 --- a/include/nvgpu/hw/gp106/hw_pri_ringmaster_gp106.h +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pri_ringmaster_gp106_h_ -#define _hw_pri_ringmaster_gp106_h_ - -static inline u32 pri_ringmaster_command_r(void) -{ - return 0x0012004cU; -} -static inline u32 pri_ringmaster_command_cmd_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 pri_ringmaster_command_cmd_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void) -{ - return 0x00000000U; -} -static inline u32 pri_ringmaster_command_cmd_start_ring_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void) -{ - return 0x2U; -} -static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void) -{ - return 0x3U; -} -static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void) -{ - return 0x0U; -} -static inline u32 pri_ringmaster_command_data_r(void) -{ - return 0x00120048U; -} -static inline u32 pri_ringmaster_start_results_r(void) -{ - return 0x00120050U; -} -static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void) -{ - return 0x00000001U; -} -static inline u32 pri_ringmaster_intr_status0_r(void) -{ - return 0x00120058U; -} -static inline u32 pri_ringmaster_intr_status1_r(void) -{ - return 0x0012005cU; -} -static inline u32 pri_ringmaster_global_ctl_r(void) -{ - return 0x00120060U; -} -static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void) -{ - return 0x0U; -} -static inline u32 pri_ringmaster_enum_fbp_r(void) -{ - return 0x00120074U; -} -static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 pri_ringmaster_enum_gpc_r(void) -{ - return 0x00120078U; -} -static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 pri_ringmaster_enum_ltc_r(void) -{ - return 0x0012006cU; -} -static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -#endif diff --git a/include/nvgpu/hw/gp106/hw_pri_ringstation_gpc_gp106.h b/include/nvgpu/hw/gp106/hw_pri_ringstation_gpc_gp106.h deleted file mode 100644 index 711938d..0000000 --- a/include/nvgpu/hw/gp106/hw_pri_ringstation_gpc_gp106.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pri_ringstation_gpc_gp106_h_ -#define _hw_pri_ringstation_gpc_gp106_h_ - -static inline u32 pri_ringstation_gpc_master_config_r(u32 i) -{ - return 0x00128300U + i*4U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void) -{ - return 0x00128120U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void) -{ - return 0x00128124U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void) -{ - return 0x00128128U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void) -{ - return 0x0012812cU; -} -#endif diff --git a/include/nvgpu/hw/gp106/hw_pri_ringstation_sys_gp106.h b/include/nvgpu/hw/gp106/hw_pri_ringstation_sys_gp106.h deleted file mode 100644 index a3a1447..0000000 --- a/include/nvgpu/hw/gp106/hw_pri_ringstation_sys_gp106.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pri_ringstation_sys_gp106_h_ -#define _hw_pri_ringstation_sys_gp106_h_ - -static inline u32 pri_ringstation_sys_master_config_r(u32 i) -{ - return 0x00122300U + i*4U; -} -static inline u32 pri_ringstation_sys_decode_config_r(void) -{ - return 0x00122204U; -} -static inline u32 pri_ringstation_sys_decode_config_ring_m(void) -{ - return 0x7U << 0U; -} -static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringstation_sys_priv_error_adr_r(void) -{ - return 0x00122120U; -} -static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void) -{ - return 0x00122124U; -} -static inline u32 pri_ringstation_sys_priv_error_info_r(void) -{ - return 0x00122128U; -} -static inline u32 pri_ringstation_sys_priv_error_code_r(void) -{ - return 0x0012212cU; -} -#endif diff --git a/include/nvgpu/hw/gp106/hw_proj_gp106.h b/include/nvgpu/hw/gp106/hw_proj_gp106.h deleted file mode 100644 index 866bc7b..0000000 --- a/include/nvgpu/hw/gp106/hw_proj_gp106.h +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_proj_gp106_h_ -#define _hw_proj_gp106_h_ - -static inline u32 proj_gpc_base_v(void) -{ - return 0x00500000U; -} -static inline u32 proj_gpc_shared_base_v(void) -{ - return 0x00418000U; -} -static inline u32 proj_gpc_stride_v(void) -{ - return 0x00008000U; -} -static inline u32 proj_gpc_priv_stride_v(void) -{ - return 0x00000800U; -} -static inline u32 proj_ltc_stride_v(void) -{ - return 0x00002000U; -} -static inline u32 proj_lts_stride_v(void) -{ - return 0x00000200U; -} -static inline u32 proj_fbpa_base_v(void) -{ - return 0x00900000U; -} -static inline u32 proj_fbpa_shared_base_v(void) -{ - return 0x009a0000U; -} -static inline u32 proj_fbpa_stride_v(void) -{ - return 0x00004000U; -} -static inline u32 proj_ppc_in_gpc_base_v(void) -{ - return 0x00003000U; -} -static inline u32 proj_ppc_in_gpc_shared_base_v(void) -{ - return 0x00003e00U; -} -static inline u32 proj_ppc_in_gpc_stride_v(void) -{ - return 0x00000200U; -} -static inline u32 proj_rop_base_v(void) -{ - return 0x00410000U; -} -static inline u32 proj_rop_shared_base_v(void) -{ - return 0x00408800U; -} -static inline u32 proj_rop_stride_v(void) -{ - return 0x00000400U; -} -static inline u32 proj_tpc_in_gpc_base_v(void) -{ - return 0x00004000U; -} -static inline u32 proj_tpc_in_gpc_stride_v(void) -{ - return 0x00000800U; -} -static inline u32 proj_tpc_in_gpc_shared_base_v(void) -{ - return 0x00001800U; -} -static inline u32 proj_host_num_engines_v(void) -{ - return 0x00000009U; -} -static inline u32 proj_host_num_pbdma_v(void) -{ - return 0x00000004U; -} -static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) -{ - return 0x00000005U; -} -static inline u32 proj_scal_litter_num_sm_per_tpc_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_fbps_v(void) -{ - return 0x00000006U; -} -static inline u32 proj_scal_litter_num_fbpas_v(void) -{ - return 0x00000006U; -} -static inline u32 proj_scal_litter_num_gpcs_v(void) -{ - return 0x00000006U; -} -static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) -{ - return 0x00000003U; -} -static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) -{ - return 0x00000002U; -} -static inline u32 proj_scal_litter_num_zcull_banks_v(void) -{ - return 0x00000004U; -} -static inline u32 proj_scal_max_gpcs_v(void) -{ - return 0x00000020U; -} -static inline u32 proj_scal_max_tpc_per_gpc_v(void) -{ - return 0x00000008U; -} -#endif diff --git a/include/nvgpu/hw/gp106/hw_psec_gp106.h b/include/nvgpu/hw/gp106/hw_psec_gp106.h deleted file mode 100644 index b91c09b..0000000 --- a/include/nvgpu/hw/gp106/hw_psec_gp106.h +++ /dev/null @@ -1,615 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_psec_gp106_h_ -#define _hw_psec_gp106_h_ - -static inline u32 psec_falcon_irqsset_r(void) -{ - return 0x00087000U; -} -static inline u32 psec_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 psec_falcon_irqsclr_r(void) -{ - return 0x00087004U; -} -static inline u32 psec_falcon_irqstat_r(void) -{ - return 0x00087008U; -} -static inline u32 psec_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 psec_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 psec_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 psec_falcon_irqmode_r(void) -{ - return 0x0008700cU; -} -static inline u32 psec_falcon_irqmset_r(void) -{ - return 0x00087010U; -} -static inline u32 psec_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 psec_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 psec_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 psec_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 psec_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 psec_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 psec_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 psec_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 psec_falcon_irqmclr_r(void) -{ - return 0x00087014U; -} -static inline u32 psec_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 psec_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 psec_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 psec_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 psec_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 psec_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 psec_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 psec_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 psec_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 psec_falcon_irqmask_r(void) -{ - return 0x00087018U; -} -static inline u32 psec_falcon_irqdest_r(void) -{ - return 0x0008701cU; -} -static inline u32 psec_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 psec_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 psec_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 psec_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 psec_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 psec_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 psec_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 psec_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 psec_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 psec_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 psec_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 psec_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 psec_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 psec_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 psec_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 psec_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 psec_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 psec_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 psec_falcon_curctx_r(void) -{ - return 0x00087050U; -} -static inline u32 psec_falcon_nxtctx_r(void) -{ - return 0x00087054U; -} -static inline u32 psec_falcon_mailbox0_r(void) -{ - return 0x00087040U; -} -static inline u32 psec_falcon_mailbox1_r(void) -{ - return 0x00087044U; -} -static inline u32 psec_falcon_itfen_r(void) -{ - return 0x00087048U; -} -static inline u32 psec_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 psec_falcon_idlestate_r(void) -{ - return 0x0008704cU; -} -static inline u32 psec_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 psec_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 psec_falcon_os_r(void) -{ - return 0x00087080U; -} -static inline u32 psec_falcon_engctl_r(void) -{ - return 0x000870a4U; -} -static inline u32 psec_falcon_cpuctl_r(void) -{ - return 0x00087100U; -} -static inline u32 psec_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 psec_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 psec_falcon_cpuctl_halt_intr_m(void) -{ - return 0x1U << 4U; -} -static inline u32 psec_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 psec_falcon_cpuctl_cpuctl_alias_en_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 psec_falcon_cpuctl_cpuctl_alias_en_m(void) -{ - return 0x1U << 6U; -} -static inline u32 psec_falcon_cpuctl_cpuctl_alias_en_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 psec_falcon_cpuctl_alias_r(void) -{ - return 0x00087130U; -} -static inline u32 psec_falcon_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 psec_falcon_imemc_r(u32 i) -{ - return 0x00087180U + i*16U; -} -static inline u32 psec_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 psec_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 psec_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 psec_falcon_imemd_r(u32 i) -{ - return 0x00087184U + i*16U; -} -static inline u32 psec_falcon_imemt_r(u32 i) -{ - return 0x00087188U + i*16U; -} -static inline u32 psec_falcon_sctl_r(void) -{ - return 0x00087240U; -} -static inline u32 psec_falcon_mmu_phys_sec_r(void) -{ - return 0x00100ce4U; -} -static inline u32 psec_falcon_bootvec_r(void) -{ - return 0x00087104U; -} -static inline u32 psec_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 psec_falcon_dmactl_r(void) -{ - return 0x0008710cU; -} -static inline u32 psec_falcon_dmactl_dmem_scrubbing_m(void) -{ - return 0x1U << 1U; -} -static inline u32 psec_falcon_dmactl_imem_scrubbing_m(void) -{ - return 0x1U << 2U; -} -static inline u32 psec_falcon_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 psec_falcon_hwcfg_r(void) -{ - return 0x00087108U; -} -static inline u32 psec_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 psec_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 psec_falcon_dmatrfbase_r(void) -{ - return 0x00087110U; -} -static inline u32 psec_falcon_dmatrfbase1_r(void) -{ - return 0x00087128U; -} -static inline u32 psec_falcon_dmatrfmoffs_r(void) -{ - return 0x00087114U; -} -static inline u32 psec_falcon_dmatrfcmd_r(void) -{ - return 0x00087118U; -} -static inline u32 psec_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 psec_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 psec_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 psec_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 psec_falcon_dmatrffboffs_r(void) -{ - return 0x0008711cU; -} -static inline u32 psec_falcon_exterraddr_r(void) -{ - return 0x00087168U; -} -static inline u32 psec_falcon_exterrstat_r(void) -{ - return 0x0008716cU; -} -static inline u32 psec_falcon_exterrstat_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 psec_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 psec_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 psec_sec2_falcon_icd_cmd_r(void) -{ - return 0x00087200U; -} -static inline u32 psec_sec2_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 psec_sec2_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 psec_sec2_falcon_icd_cmd_opc_m(void) -{ - return 0xfU << 0U; -} -static inline u32 psec_sec2_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 psec_sec2_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 psec_sec2_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 psec_sec2_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 psec_sec2_falcon_icd_rdata_r(void) -{ - return 0x0008720cU; -} -static inline u32 psec_falcon_dmemc_r(u32 i) -{ - return 0x000871c0U + i*8U; -} -static inline u32 psec_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 psec_falcon_dmemc_offs_m(void) -{ - return 0x3fU << 2U; -} -static inline u32 psec_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 psec_falcon_dmemc_blk_m(void) -{ - return 0xffU << 8U; -} -static inline u32 psec_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 psec_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 psec_falcon_dmemd_r(u32 i) -{ - return 0x000871c4U + i*8U; -} -static inline u32 psec_falcon_debug1_r(void) -{ - return 0x00087090U; -} -static inline u32 psec_falcon_debug1_ctxsw_mode_s(void) -{ - return 1U; -} -static inline u32 psec_falcon_debug1_ctxsw_mode_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 psec_falcon_debug1_ctxsw_mode_m(void) -{ - return 0x1U << 16U; -} -static inline u32 psec_falcon_debug1_ctxsw_mode_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 psec_falcon_debug1_ctxsw_mode_init_f(void) -{ - return 0x0U; -} -static inline u32 psec_fbif_transcfg_r(u32 i) -{ - return 0x00087600U + i*4U; -} -static inline u32 psec_fbif_transcfg_target_local_fb_f(void) -{ - return 0x0U; -} -static inline u32 psec_fbif_transcfg_target_coherent_sysmem_f(void) -{ - return 0x1U; -} -static inline u32 psec_fbif_transcfg_target_noncoherent_sysmem_f(void) -{ - return 0x2U; -} -static inline u32 psec_fbif_transcfg_mem_type_s(void) -{ - return 1U; -} -static inline u32 psec_fbif_transcfg_mem_type_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 psec_fbif_transcfg_mem_type_m(void) -{ - return 0x1U << 2U; -} -static inline u32 psec_fbif_transcfg_mem_type_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 psec_fbif_transcfg_mem_type_virtual_f(void) -{ - return 0x0U; -} -static inline u32 psec_fbif_transcfg_mem_type_physical_f(void) -{ - return 0x4U; -} -static inline u32 psec_falcon_engine_r(void) -{ - return 0x000873c0U; -} -static inline u32 psec_falcon_engine_reset_true_f(void) -{ - return 0x1U; -} -static inline u32 psec_falcon_engine_reset_false_f(void) -{ - return 0x0U; -} -static inline u32 psec_fbif_ctl_r(void) -{ - return 0x00087624U; -} -static inline u32 psec_fbif_ctl_allow_phys_no_ctx_init_f(void) -{ - return 0x0U; -} -static inline u32 psec_fbif_ctl_allow_phys_no_ctx_disallow_f(void) -{ - return 0x0U; -} -static inline u32 psec_fbif_ctl_allow_phys_no_ctx_allow_f(void) -{ - return 0x80U; -} -#endif diff --git a/include/nvgpu/hw/gp106/hw_pwr_gp106.h b/include/nvgpu/hw/gp106/hw_pwr_gp106.h deleted file mode 100644 index 2e75fa6..0000000 --- a/include/nvgpu/hw/gp106/hw_pwr_gp106.h +++ /dev/null @@ -1,895 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pwr_gp106_h_ -#define _hw_pwr_gp106_h_ - -static inline u32 pwr_falcon_irqsset_r(void) -{ - return 0x0010a000U; -} -static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 pwr_falcon_irqsclr_r(void) -{ - return 0x0010a004U; -} -static inline u32 pwr_falcon_irqstat_r(void) -{ - return 0x0010a008U; -} -static inline u32 pwr_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 pwr_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 pwr_falcon_irqmode_r(void) -{ - return 0x0010a00cU; -} -static inline u32 pwr_falcon_irqmset_r(void) -{ - return 0x0010a010U; -} -static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqmclr_r(void) -{ - return 0x0010a014U; -} -static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqmask_r(void) -{ - return 0x0010a018U; -} -static inline u32 pwr_falcon_irqdest_r(void) -{ - return 0x0010a01cU; -} -static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 pwr_falcon_curctx_r(void) -{ - return 0x0010a050U; -} -static inline u32 pwr_falcon_nxtctx_r(void) -{ - return 0x0010a054U; -} -static inline u32 pwr_falcon_mailbox0_r(void) -{ - return 0x0010a040U; -} -static inline u32 pwr_falcon_mailbox1_r(void) -{ - return 0x0010a044U; -} -static inline u32 pwr_falcon_itfen_r(void) -{ - return 0x0010a048U; -} -static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 pwr_falcon_idlestate_r(void) -{ - return 0x0010a04cU; -} -static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 pwr_falcon_os_r(void) -{ - return 0x0010a080U; -} -static inline u32 pwr_falcon_engctl_r(void) -{ - return 0x0010a0a4U; -} -static inline u32 pwr_falcon_cpuctl_r(void) -{ - return 0x0010a100U; -} -static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) -{ - return 0x1U << 4U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void) -{ - return 0x1U << 6U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 pwr_falcon_cpuctl_alias_r(void) -{ - return 0x0010a130U; -} -static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_pmu_scpctl_stat_r(void) -{ - return 0x0010ac08U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void) -{ - return 0x1U << 20U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 pwr_falcon_imemc_r(u32 i) -{ - return 0x0010a180U + i*16U; -} -static inline u32 pwr_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pwr_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_imemd_r(u32 i) -{ - return 0x0010a184U + i*16U; -} -static inline u32 pwr_falcon_imemt_r(u32 i) -{ - return 0x0010a188U + i*16U; -} -static inline u32 pwr_falcon_sctl_r(void) -{ - return 0x0010a240U; -} -static inline u32 pwr_falcon_mmu_phys_sec_r(void) -{ - return 0x00100ce4U; -} -static inline u32 pwr_falcon_bootvec_r(void) -{ - return 0x0010a104U; -} -static inline u32 pwr_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_falcon_dmactl_r(void) -{ - return 0x0010a10cU; -} -static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) -{ - return 0x1U << 1U; -} -static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) -{ - return 0x1U << 2U; -} -static inline u32 pwr_falcon_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_hwcfg_r(void) -{ - return 0x0010a108U; -} -static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 pwr_falcon_dmatrfbase_r(void) -{ - return 0x0010a110U; -} -static inline u32 pwr_falcon_dmatrfbase1_r(void) -{ - return 0x0010a128U; -} -static inline u32 pwr_falcon_dmatrfmoffs_r(void) -{ - return 0x0010a114U; -} -static inline u32 pwr_falcon_dmatrfcmd_r(void) -{ - return 0x0010a118U; -} -static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 pwr_falcon_dmatrffboffs_r(void) -{ - return 0x0010a11cU; -} -static inline u32 pwr_falcon_exterraddr_r(void) -{ - return 0x0010a168U; -} -static inline u32 pwr_falcon_exterrstat_r(void) -{ - return 0x0010a16cU; -} -static inline u32 pwr_falcon_exterrstat_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 pwr_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_r(void) -{ - return 0x0010a200U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) -{ - return 0xfU << 0U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 pwr_pmu_falcon_icd_rdata_r(void) -{ - return 0x0010a20cU; -} -static inline u32 pwr_falcon_dmemc_r(u32 i) -{ - return 0x0010a1c0U + i*8U; -} -static inline u32 pwr_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pwr_falcon_dmemc_offs_m(void) -{ - return 0x3fU << 2U; -} -static inline u32 pwr_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_dmemc_blk_m(void) -{ - return 0xffU << 8U; -} -static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 pwr_falcon_dmemd_r(u32 i) -{ - return 0x0010a1c4U + i*8U; -} -static inline u32 pwr_pmu_new_instblk_r(void) -{ - return 0x0010a480U; -} -static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 pwr_pmu_new_instblk_target_fb_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 pwr_pmu_mutex_id_r(void) -{ - return 0x0010a488U; -} -static inline u32 pwr_pmu_mutex_id_value_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pwr_pmu_mutex_id_value_init_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) -{ - return 0x000000ffU; -} -static inline u32 pwr_pmu_mutex_id_release_r(void) -{ - return 0x0010a48cU; -} -static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_id_release_value_m(void) -{ - return 0xffU << 0U; -} -static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_mutex_r(u32 i) -{ - return 0x0010a580U + i*4U; -} -static inline u32 pwr_pmu_mutex__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 pwr_pmu_mutex_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_value_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_queue_head_r(u32 i) -{ - return 0x0010a4a0U + i*4U; -} -static inline u32 pwr_pmu_queue_head__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 pwr_pmu_queue_head_address_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_queue_head_address_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_queue_tail_r(u32 i) -{ - return 0x0010a4b0U + i*4U; -} -static inline u32 pwr_pmu_queue_tail__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 pwr_pmu_queue_tail_address_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_queue_tail_address_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_msgq_head_r(void) -{ - return 0x0010a4c8U; -} -static inline u32 pwr_pmu_msgq_head_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_msgq_head_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_msgq_tail_r(void) -{ - return 0x0010a4ccU; -} -static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_idle_mask_r(u32 i) -{ - return 0x0010a504U + i*16U; -} -static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) -{ - return 0x1U; -} -static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 pwr_pmu_idle_count_r(u32 i) -{ - return 0x0010a508U + i*16U; -} -static inline u32 pwr_pmu_idle_count_value_f(u32 v) -{ - return (v & 0x7fffffffU) << 0U; -} -static inline u32 pwr_pmu_idle_count_value_v(u32 r) -{ - return (r >> 0U) & 0x7fffffffU; -} -static inline u32 pwr_pmu_idle_count_reset_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 pwr_pmu_idle_ctrl_r(u32 i) -{ - return 0x0010a50cU + i*16U; -} -static inline u32 pwr_pmu_idle_ctrl_value_m(void) -{ - return 0x3U << 0U; -} -static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) -{ - return 0x2U; -} -static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) -{ - return 0x3U; -} -static inline u32 pwr_pmu_idle_ctrl_filter_m(void) -{ - return 0x1U << 2U; -} -static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_idle_threshold_r(u32 i) -{ - return 0x0010a8a0U + i*4U; -} -static inline u32 pwr_pmu_idle_threshold_value_f(u32 v) -{ - return (v & 0x7fffffffU) << 0U; -} -static inline u32 pwr_pmu_idle_intr_r(void) -{ - return 0x0010a9e8U; -} -static inline u32 pwr_pmu_idle_intr_en_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_en_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_idle_intr_en_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_intr_status_r(void) -{ - return 0x0010a9ecU; -} -static inline u32 pwr_pmu_idle_intr_status_intr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) -{ - return 0x0010a9f0U + i*8U; -} -static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) -{ - return 0x0010a9f4U + i*8U; -} -static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) -{ - return 0x0010aa30U + i*8U; -} -static inline u32 pwr_pmu_debug_r(u32 i) -{ - return 0x0010a5c0U + i*4U; -} -static inline u32 pwr_pmu_debug__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 pwr_pmu_mailbox_r(u32 i) -{ - return 0x0010a450U + i*4U; -} -static inline u32 pwr_pmu_mailbox__size_1_v(void) -{ - return 0x0000000cU; -} -static inline u32 pwr_pmu_bar0_addr_r(void) -{ - return 0x0010a7a0U; -} -static inline u32 pwr_pmu_bar0_data_r(void) -{ - return 0x0010a7a4U; -} -static inline u32 pwr_pmu_bar0_ctl_r(void) -{ - return 0x0010a7acU; -} -static inline u32 pwr_pmu_bar0_timeout_r(void) -{ - return 0x0010a7a8U; -} -static inline u32 pwr_pmu_bar0_fecs_error_r(void) -{ - return 0x0010a988U; -} -static inline u32 pwr_pmu_bar0_error_status_r(void) -{ - return 0x0010a7b0U; -} -static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) -{ - return 0x0010a6c0U + i*4U; -} -static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) -{ - return 0x0010a6e8U + i*4U; -} -static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) -{ - return 0x0010a710U + i*4U; -} -static inline u32 pwr_pmu_pg_intren_r(u32 i) -{ - return 0x0010a760U + i*4U; -} -static inline u32 pwr_fbif_transcfg_r(u32 i) -{ - return 0x0010ae00U + i*4U; -} -static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) -{ - return 0x0U; -} -static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) -{ - return 0x1U; -} -static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) -{ - return 0x2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_s(void) -{ - return 1U; -} -static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_m(void) -{ - return 0x1U << 2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) -{ - return 0x0U; -} -static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) -{ - return 0x4U; -} -static inline u32 pwr_falcon_engine_r(void) -{ - return 0x0010a3c0U; -} -static inline u32 pwr_falcon_engine_reset_true_f(void) -{ - return 0x1U; -} -static inline u32 pwr_falcon_engine_reset_false_f(void) -{ - return 0x0U; -} -#endif diff --git a/include/nvgpu/hw/gp106/hw_ram_gp106.h b/include/nvgpu/hw/gp106/hw_ram_gp106.h deleted file mode 100644 index 1de8aa2..0000000 --- a/include/nvgpu/hw/gp106/hw_ram_gp106.h +++ /dev/null @@ -1,507 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ram_gp106_h_ -#define _hw_ram_gp106_h_ - -static inline u32 ram_in_ramfc_s(void) -{ - return 4096U; -} -static inline u32 ram_in_ramfc_w(void) -{ - return 0U; -} -static inline u32 ram_in_page_dir_base_target_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ram_in_page_dir_base_target_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 ram_in_page_dir_base_vol_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_vol_true_f(void) -{ - return 0x4U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) -{ - return 0x1U << 4U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) -{ - return 0x10U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) -{ - return 0x1U << 5U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void) -{ - return 0x20U; -} -static inline u32 ram_in_use_ver2_pt_format_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 ram_in_use_ver2_pt_format_m(void) -{ - return 0x1U << 10U; -} -static inline u32 ram_in_use_ver2_pt_format_w(void) -{ - return 128U; -} -static inline u32 ram_in_use_ver2_pt_format_true_f(void) -{ - return 0x400U; -} -static inline u32 ram_in_use_ver2_pt_format_false_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_big_page_size_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 ram_in_big_page_size_m(void) -{ - return 0x1U << 11U; -} -static inline u32 ram_in_big_page_size_w(void) -{ - return 128U; -} -static inline u32 ram_in_big_page_size_128kb_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_big_page_size_64kb_f(void) -{ - return 0x800U; -} -static inline u32 ram_in_page_dir_base_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_page_dir_base_lo_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_hi_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_in_page_dir_base_hi_w(void) -{ - return 129U; -} -static inline u32 ram_in_adr_limit_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_adr_limit_lo_w(void) -{ - return 130U; -} -static inline u32 ram_in_adr_limit_hi_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_in_adr_limit_hi_w(void) -{ - return 131U; -} -static inline u32 ram_in_engine_cs_w(void) -{ - return 132U; -} -static inline u32 ram_in_engine_cs_wfi_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_engine_cs_wfi_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_engine_cs_fg_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_engine_cs_fg_f(void) -{ - return 0x8U; -} -static inline u32 ram_in_gr_cs_w(void) -{ - return 132U; -} -static inline u32 ram_in_gr_cs_wfi_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_gr_wfi_target_w(void) -{ - return 132U; -} -static inline u32 ram_in_gr_wfi_mode_w(void) -{ - return 132U; -} -static inline u32 ram_in_gr_wfi_mode_physical_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_gr_wfi_mode_physical_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_gr_wfi_mode_virtual_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_gr_wfi_mode_virtual_f(void) -{ - return 0x4U; -} -static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_gr_wfi_ptr_lo_w(void) -{ - return 132U; -} -static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ram_in_gr_wfi_ptr_hi_w(void) -{ - return 133U; -} -static inline u32 ram_in_base_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 ram_in_alloc_size_v(void) -{ - return 0x00001000U; -} -static inline u32 ram_fc_size_val_v(void) -{ - return 0x00000200U; -} -static inline u32 ram_fc_gp_put_w(void) -{ - return 0U; -} -static inline u32 ram_fc_userd_w(void) -{ - return 2U; -} -static inline u32 ram_fc_userd_hi_w(void) -{ - return 3U; -} -static inline u32 ram_fc_signature_w(void) -{ - return 4U; -} -static inline u32 ram_fc_gp_get_w(void) -{ - return 5U; -} -static inline u32 ram_fc_pb_get_w(void) -{ - return 6U; -} -static inline u32 ram_fc_pb_get_hi_w(void) -{ - return 7U; -} -static inline u32 ram_fc_pb_top_level_get_w(void) -{ - return 8U; -} -static inline u32 ram_fc_pb_top_level_get_hi_w(void) -{ - return 9U; -} -static inline u32 ram_fc_acquire_w(void) -{ - return 12U; -} -static inline u32 ram_fc_semaphorea_w(void) -{ - return 14U; -} -static inline u32 ram_fc_semaphoreb_w(void) -{ - return 15U; -} -static inline u32 ram_fc_semaphorec_w(void) -{ - return 16U; -} -static inline u32 ram_fc_semaphored_w(void) -{ - return 17U; -} -static inline u32 ram_fc_gp_base_w(void) -{ - return 18U; -} -static inline u32 ram_fc_gp_base_hi_w(void) -{ - return 19U; -} -static inline u32 ram_fc_gp_fetch_w(void) -{ - return 20U; -} -static inline u32 ram_fc_pb_fetch_w(void) -{ - return 21U; -} -static inline u32 ram_fc_pb_fetch_hi_w(void) -{ - return 22U; -} -static inline u32 ram_fc_pb_put_w(void) -{ - return 23U; -} -static inline u32 ram_fc_pb_put_hi_w(void) -{ - return 24U; -} -static inline u32 ram_fc_pb_header_w(void) -{ - return 33U; -} -static inline u32 ram_fc_pb_count_w(void) -{ - return 34U; -} -static inline u32 ram_fc_subdevice_w(void) -{ - return 37U; -} -static inline u32 ram_fc_formats_w(void) -{ - return 39U; -} -static inline u32 ram_fc_target_w(void) -{ - return 43U; -} -static inline u32 ram_fc_hce_ctrl_w(void) -{ - return 57U; -} -static inline u32 ram_fc_chid_w(void) -{ - return 58U; -} -static inline u32 ram_fc_chid_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_fc_chid_id_w(void) -{ - return 0U; -} -static inline u32 ram_fc_config_w(void) -{ - return 61U; -} -static inline u32 ram_fc_runlist_timeslice_w(void) -{ - return 62U; -} -static inline u32 ram_userd_base_shift_v(void) -{ - return 0x00000009U; -} -static inline u32 ram_userd_chan_size_v(void) -{ - return 0x00000200U; -} -static inline u32 ram_userd_put_w(void) -{ - return 16U; -} -static inline u32 ram_userd_get_w(void) -{ - return 17U; -} -static inline u32 ram_userd_ref_w(void) -{ - return 18U; -} -static inline u32 ram_userd_put_hi_w(void) -{ - return 19U; -} -static inline u32 ram_userd_ref_threshold_w(void) -{ - return 20U; -} -static inline u32 ram_userd_top_level_get_w(void) -{ - return 22U; -} -static inline u32 ram_userd_top_level_get_hi_w(void) -{ - return 23U; -} -static inline u32 ram_userd_get_hi_w(void) -{ - return 24U; -} -static inline u32 ram_userd_gp_get_w(void) -{ - return 34U; -} -static inline u32 ram_userd_gp_put_w(void) -{ - return 35U; -} -static inline u32 ram_userd_gp_top_level_get_w(void) -{ - return 22U; -} -static inline u32 ram_userd_gp_top_level_get_hi_w(void) -{ - return 23U; -} -static inline u32 ram_rl_entry_size_v(void) -{ - return 0x00000008U; -} -static inline u32 ram_rl_entry_chid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_type_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 ram_rl_entry_type_chid_f(void) -{ - return 0x0U; -} -static inline u32 ram_rl_entry_type_tsg_f(void) -{ - return 0x2000U; -} -static inline u32 ram_rl_entry_timeslice_scale_f(u32 v) -{ - return (v & 0xfU) << 14U; -} -static inline u32 ram_rl_entry_timeslice_scale_3_f(void) -{ - return 0xc000U; -} -static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v) -{ - return (v & 0xffU) << 18U; -} -static inline u32 ram_rl_entry_timeslice_timeout_128_f(void) -{ - return 0x2000000U; -} -static inline u32 ram_rl_entry_tsg_length_f(u32 v) -{ - return (v & 0x3fU) << 26U; -} -#endif diff --git a/include/nvgpu/hw/gp106/hw_therm_gp106.h b/include/nvgpu/hw/gp106/hw_therm_gp106.h deleted file mode 100644 index ee58032..0000000 --- a/include/nvgpu/hw/gp106/hw_therm_gp106.h +++ /dev/null @@ -1,183 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_therm_gp106_h_ -#define _hw_therm_gp106_h_ - -static inline u32 therm_temp_sensor_tsense_r(void) -{ - return 0x00020460U; -} -static inline u32 therm_temp_sensor_tsense_fixed_point_f(u32 v) -{ - return (v & 0x3fffU) << 3U; -} -static inline u32 therm_temp_sensor_tsense_fixed_point_m(void) -{ - return 0x3fffU << 3U; -} -static inline u32 therm_temp_sensor_tsense_fixed_point_v(u32 r) -{ - return (r >> 3U) & 0x3fffU; -} -static inline u32 therm_temp_sensor_tsense_fixed_point_min_v(void) -{ - return 0x00003b00U; -} -static inline u32 therm_temp_sensor_tsense_fixed_point_max_v(void) -{ - return 0x000010e0U; -} -static inline u32 therm_temp_sensor_tsense_state_f(u32 v) -{ - return (v & 0x3U) << 29U; -} -static inline u32 therm_temp_sensor_tsense_state_m(void) -{ - return 0x3U << 29U; -} -static inline u32 therm_temp_sensor_tsense_state_v(u32 r) -{ - return (r >> 29U) & 0x3U; -} -static inline u32 therm_temp_sensor_tsense_state_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 therm_temp_sensor_tsense_state_shadow_v(void) -{ - return 0x00000002U; -} -static inline u32 therm_gate_ctrl_r(u32 i) -{ - return 0x00020200U + i*4U; -} -static inline u32 therm_gate_ctrl_eng_clk_m(void) -{ - return 0x3U << 0U; -} -static inline u32 therm_gate_ctrl_eng_clk_run_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) -{ - return 0x1U; -} -static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) -{ - return 0x2U; -} -static inline u32 therm_gate_ctrl_blk_clk_m(void) -{ - return 0x3U << 2U; -} -static inline u32 therm_gate_ctrl_blk_clk_run_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) -{ - return 0x4U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) -{ - return 0x1fU << 8U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) -{ - return (v & 0x7U) << 13U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) -{ - return 0x7U << 13U; -} -static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 therm_gate_ctrl_eng_delay_before_m(void) -{ - return 0xfU << 16U; -} -static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 therm_gate_ctrl_eng_delay_after_m(void) -{ - return 0xfU << 20U; -} -static inline u32 therm_fecs_idle_filter_r(void) -{ - return 0x00020288U; -} -static inline u32 therm_fecs_idle_filter_value_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 therm_hubmmu_idle_filter_r(void) -{ - return 0x0002028cU; -} -static inline u32 therm_hubmmu_idle_filter_value_m(void) -{ - return 0xffffffffU << 0U; -} -#endif diff --git a/include/nvgpu/hw/gp106/hw_timer_gp106.h b/include/nvgpu/hw/gp106/hw_timer_gp106.h deleted file mode 100644 index 7fd722f..0000000 --- a/include/nvgpu/hw/gp106/hw_timer_gp106.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_timer_gp106_h_ -#define _hw_timer_gp106_h_ - -static inline u32 timer_pri_timeout_r(void) -{ - return 0x00009080U; -} -static inline u32 timer_pri_timeout_period_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 timer_pri_timeout_period_m(void) -{ - return 0xffffffU << 0U; -} -static inline u32 timer_pri_timeout_period_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 timer_pri_timeout_en_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 timer_pri_timeout_en_m(void) -{ - return 0x1U << 31U; -} -static inline u32 timer_pri_timeout_en_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 timer_pri_timeout_en_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 timer_pri_timeout_en_en_disabled_f(void) -{ - return 0x0U; -} -static inline u32 timer_pri_timeout_save_0_r(void) -{ - return 0x00009084U; -} -static inline u32 timer_pri_timeout_save_1_r(void) -{ - return 0x00009088U; -} -static inline u32 timer_pri_timeout_fecs_errcode_r(void) -{ - return 0x0000908cU; -} -static inline u32 timer_time_0_r(void) -{ - return 0x00009400U; -} -static inline u32 timer_time_1_r(void) -{ - return 0x00009410U; -} -#endif diff --git a/include/nvgpu/hw/gp106/hw_top_gp106.h b/include/nvgpu/hw/gp106/hw_top_gp106.h deleted file mode 100644 index 749f66e..0000000 --- a/include/nvgpu/hw/gp106/hw_top_gp106.h +++ /dev/null @@ -1,255 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_top_gp106_h_ -#define _hw_top_gp106_h_ - -static inline u32 top_num_gpcs_r(void) -{ - return 0x00022430U; -} -static inline u32 top_num_gpcs_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_tpc_per_gpc_r(void) -{ - return 0x00022434U; -} -static inline u32 top_tpc_per_gpc_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_num_fbps_r(void) -{ - return 0x00022438U; -} -static inline u32 top_num_fbps_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_num_fbpas_r(void) -{ - return 0x0002243cU; -} -static inline u32 top_num_fbpas_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_ltc_per_fbp_r(void) -{ - return 0x00022450U; -} -static inline u32 top_ltc_per_fbp_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_slices_per_ltc_r(void) -{ - return 0x0002245cU; -} -static inline u32 top_slices_per_ltc_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_num_ltcs_r(void) -{ - return 0x00022454U; -} -static inline u32 top_device_info_r(u32 i) -{ - return 0x00022700U + i*4U; -} -static inline u32 top_device_info__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 top_device_info_chain_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 top_device_info_chain_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_engine_enum_v(u32 r) -{ - return (r >> 26U) & 0xfU; -} -static inline u32 top_device_info_runlist_enum_v(u32 r) -{ - return (r >> 21U) & 0xfU; -} -static inline u32 top_device_info_intr_enum_v(u32 r) -{ - return (r >> 15U) & 0x1fU; -} -static inline u32 top_device_info_reset_enum_v(u32 r) -{ - return (r >> 9U) & 0x1fU; -} -static inline u32 top_device_info_type_enum_v(u32 r) -{ - return (r >> 2U) & 0x1fffffffU; -} -static inline u32 top_device_info_type_enum_graphics_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_type_enum_graphics_f(void) -{ - return 0x0U; -} -static inline u32 top_device_info_type_enum_copy0_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_type_enum_copy0_f(void) -{ - return 0x4U; -} -static inline u32 top_device_info_type_enum_copy2_v(void) -{ - return 0x00000003U; -} -static inline u32 top_device_info_type_enum_copy2_f(void) -{ - return 0xcU; -} -static inline u32 top_device_info_type_enum_lce_v(void) -{ - return 0x00000013U; -} -static inline u32 top_device_info_type_enum_lce_f(void) -{ - return 0x4cU; -} -static inline u32 top_device_info_engine_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 top_device_info_runlist_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 top_device_info_intr_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 top_device_info_reset_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 top_device_info_entry_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 top_device_info_entry_not_valid_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_entry_enum_v(void) -{ - return 0x00000002U; -} -static inline u32 top_device_info_entry_engine_type_v(void) -{ - return 0x00000003U; -} -static inline u32 top_device_info_entry_data_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_data_type_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 top_device_info_data_type_enum2_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_data_inst_id_v(u32 r) -{ - return (r >> 26U) & 0xfU; -} -static inline u32 top_device_info_data_pri_base_v(u32 r) -{ - return (r >> 12U) & 0xfffU; -} -static inline u32 top_device_info_data_pri_base_align_v(void) -{ - return 0x0000000cU; -} -static inline u32 top_device_info_data_fault_id_enum_v(u32 r) -{ - return (r >> 3U) & 0x1fU; -} -static inline u32 top_device_info_data_fault_id_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 top_device_info_data_fault_id_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 top_scratch1_r(void) -{ - return 0x0002240cU; -} -static inline u32 top_scratch1_devinit_completed_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -#endif diff --git a/include/nvgpu/hw/gp106/hw_trim_gp106.h b/include/nvgpu/hw/gp106/hw_trim_gp106.h deleted file mode 100644 index cebb6d4..0000000 --- a/include/nvgpu/hw/gp106/hw_trim_gp106.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_trim_gp106_h_ -#define _hw_trim_gp106_h_ - -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_r(void) -{ - return 0x00132924U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_s(void) -{ - return 16U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_s(void) -{ - return 1U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_m(void) -{ - return 0x1U << 16U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_deasserted_f(void) -{ - return 0x0U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void) -{ - return 0x10000U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_s(void) -{ - return 1U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_m(void) -{ - return 0x1U << 20U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f(void) -{ - return 0x0U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_asserted_f(void) -{ - return 0x100000U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_s(void) -{ - return 1U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_m(void) -{ - return 0x1U << 24U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_deasserted_f(void) -{ - return 0x0U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_asserted_f(void) -{ - return 0x1000000U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_source_gpc2clk_f(void) -{ - return 0x70000000U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cnt_r(void) -{ - return 0x00132928U; -} -static inline u32 trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_r(void) -{ - return 0x00132128U; -} -static inline u32 trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_source_dramdiv4_rec_clk1_f(void) -{ - return 0x30000000U; -} -static inline u32 trim_fbpa_bcast_clk_cntr_ncltcclk_cnt_r(void) -{ - return 0x0013212cU; -} -static inline u32 trim_sys_clk_cntr_ncltcpll_cfg_r(void) -{ - return 0x001373c0U; -} -static inline u32 trim_sys_clk_cntr_ncltcpll_cfg_source_xbar2clk_f(void) -{ - return 0x20000000U; -} -static inline u32 trim_sys_clk_cntr_ncltcpll_cnt_r(void) -{ - return 0x001373c4U; -} -static inline u32 trim_sys_clk_cntr_ncsyspll_cfg_r(void) -{ - return 0x001373b0U; -} -static inline u32 trim_sys_clk_cntr_ncsyspll_cfg_source_sys2clk_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_clk_cntr_ncsyspll_cnt_r(void) -{ - return 0x001373b4U; -} -#endif diff --git a/include/nvgpu/hw/gp106/hw_xp_gp106.h b/include/nvgpu/hw/gp106/hw_xp_gp106.h deleted file mode 100644 index f6c843c..0000000 --- a/include/nvgpu/hw/gp106/hw_xp_gp106.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_xp_gp106_h_ -#define _hw_xp_gp106_h_ - -static inline u32 xp_dl_mgr_r(u32 i) -{ - return 0x0008b8c0U + i*4U; -} -static inline u32 xp_dl_mgr_safe_timing_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 xp_pl_link_config_r(u32 i) -{ - return 0x0008c040U + i*4U; -} -static inline u32 xp_pl_link_config_ltssm_status_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 xp_pl_link_config_ltssm_status_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 xp_pl_link_config_ltssm_directive_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 xp_pl_link_config_ltssm_directive_m(void) -{ - return 0xfU << 0U; -} -static inline u32 xp_pl_link_config_ltssm_directive_normal_operations_v(void) -{ - return 0x00000000U; -} -static inline u32 xp_pl_link_config_ltssm_directive_change_speed_v(void) -{ - return 0x00000001U; -} -static inline u32 xp_pl_link_config_max_link_rate_f(u32 v) -{ - return (v & 0x3U) << 18U; -} -static inline u32 xp_pl_link_config_max_link_rate_m(void) -{ - return 0x3U << 18U; -} -static inline u32 xp_pl_link_config_max_link_rate_2500_mtps_v(void) -{ - return 0x00000002U; -} -static inline u32 xp_pl_link_config_max_link_rate_5000_mtps_v(void) -{ - return 0x00000001U; -} -static inline u32 xp_pl_link_config_max_link_rate_8000_mtps_v(void) -{ - return 0x00000000U; -} -static inline u32 xp_pl_link_config_target_tx_width_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 xp_pl_link_config_target_tx_width_m(void) -{ - return 0x7U << 20U; -} -static inline u32 xp_pl_link_config_target_tx_width_x1_v(void) -{ - return 0x00000007U; -} -static inline u32 xp_pl_link_config_target_tx_width_x2_v(void) -{ - return 0x00000006U; -} -static inline u32 xp_pl_link_config_target_tx_width_x4_v(void) -{ - return 0x00000005U; -} -static inline u32 xp_pl_link_config_target_tx_width_x8_v(void) -{ - return 0x00000004U; -} -static inline u32 xp_pl_link_config_target_tx_width_x16_v(void) -{ - return 0x00000000U; -} -#endif diff --git a/include/nvgpu/hw/gp106/hw_xve_gp106.h b/include/nvgpu/hw/gp106/hw_xve_gp106.h deleted file mode 100644 index e61d13f..0000000 --- a/include/nvgpu/hw/gp106/hw_xve_gp106.h +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_xve_gp106_h_ -#define _hw_xve_gp106_h_ - -static inline u32 xve_rom_ctrl_r(void) -{ - return 0x00000050U; -} -static inline u32 xve_rom_ctrl_rom_shadow_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 xve_rom_ctrl_rom_shadow_disabled_f(void) -{ - return 0x0U; -} -static inline u32 xve_rom_ctrl_rom_shadow_enabled_f(void) -{ - return 0x1U; -} -static inline u32 xve_link_control_status_r(void) -{ - return 0x00000088U; -} -static inline u32 xve_link_control_status_link_speed_m(void) -{ - return 0xfU << 16U; -} -static inline u32 xve_link_control_status_link_speed_v(u32 r) -{ - return (r >> 16U) & 0xfU; -} -static inline u32 xve_link_control_status_link_speed_link_speed_2p5_v(void) -{ - return 0x00000001U; -} -static inline u32 xve_link_control_status_link_speed_link_speed_5p0_v(void) -{ - return 0x00000002U; -} -static inline u32 xve_link_control_status_link_speed_link_speed_8p0_v(void) -{ - return 0x00000003U; -} -static inline u32 xve_link_control_status_link_width_m(void) -{ - return 0x3fU << 20U; -} -static inline u32 xve_link_control_status_link_width_v(u32 r) -{ - return (r >> 20U) & 0x3fU; -} -static inline u32 xve_link_control_status_link_width_x1_v(void) -{ - return 0x00000001U; -} -static inline u32 xve_link_control_status_link_width_x2_v(void) -{ - return 0x00000002U; -} -static inline u32 xve_link_control_status_link_width_x4_v(void) -{ - return 0x00000004U; -} -static inline u32 xve_link_control_status_link_width_x8_v(void) -{ - return 0x00000008U; -} -static inline u32 xve_link_control_status_link_width_x16_v(void) -{ - return 0x00000010U; -} -static inline u32 xve_priv_xv_r(void) -{ - return 0x00000150U; -} -static inline u32 xve_priv_xv_cya_l0s_enable_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 xve_priv_xv_cya_l0s_enable_m(void) -{ - return 0x1U << 7U; -} -static inline u32 xve_priv_xv_cya_l0s_enable_v(u32 r) -{ - return (r >> 7U) & 0x1U; -} -static inline u32 xve_priv_xv_cya_l1_enable_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 xve_priv_xv_cya_l1_enable_m(void) -{ - return 0x1U << 8U; -} -static inline u32 xve_priv_xv_cya_l1_enable_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 xve_cya_2_r(void) -{ - return 0x00000704U; -} -static inline u32 xve_reset_r(void) -{ - return 0x00000718U; -} -static inline u32 xve_reset_reset_m(void) -{ - return 0x1U << 0U; -} -static inline u32 xve_reset_gpu_on_sw_reset_m(void) -{ - return 0x1U << 1U; -} -static inline u32 xve_reset_counter_en_m(void) -{ - return 0x1U << 2U; -} -static inline u32 xve_reset_counter_val_f(u32 v) -{ - return (v & 0x7ffU) << 4U; -} -static inline u32 xve_reset_counter_val_m(void) -{ - return 0x7ffU << 4U; -} -static inline u32 xve_reset_counter_val_v(u32 r) -{ - return (r >> 4U) & 0x7ffU; -} -static inline u32 xve_reset_clock_on_sw_reset_m(void) -{ - return 0x1U << 15U; -} -static inline u32 xve_reset_clock_counter_en_m(void) -{ - return 0x1U << 16U; -} -static inline u32 xve_reset_clock_counter_val_f(u32 v) -{ - return (v & 0x7ffU) << 17U; -} -static inline u32 xve_reset_clock_counter_val_m(void) -{ - return 0x7ffU << 17U; -} -static inline u32 xve_reset_clock_counter_val_v(u32 r) -{ - return (r >> 17U) & 0x7ffU; -} -#endif diff --git a/include/nvgpu/hw/gp10b/hw_bus_gp10b.h b/include/nvgpu/hw/gp10b/hw_bus_gp10b.h deleted file mode 100644 index b06ea66..0000000 --- a/include/nvgpu/hw/gp10b/hw_bus_gp10b.h +++ /dev/null @@ -1,223 +0,0 @@ -/* - * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_bus_gp10b_h_ -#define _hw_bus_gp10b_h_ - -static inline u32 bus_bar0_window_r(void) -{ - return 0x00001700U; -} -static inline u32 bus_bar0_window_base_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 bus_bar0_window_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) -{ - return 0x2000000U; -} -static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) -{ - return 0x3000000U; -} -static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) -{ - return 0x00000010U; -} -static inline u32 bus_bar1_block_r(void) -{ - return 0x00001704U; -} -static inline u32 bus_bar1_block_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 bus_bar1_block_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar1_block_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 bus_bar1_block_mode_virtual_f(void) -{ - return 0x80000000U; -} -static inline u32 bus_bar2_block_r(void) -{ - return 0x00001714U; -} -static inline u32 bus_bar2_block_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 bus_bar2_block_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar2_block_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 bus_bar2_block_mode_virtual_f(void) -{ - return 0x80000000U; -} -static inline u32 bus_bar1_block_ptr_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 bus_bar2_block_ptr_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 bus_bind_status_r(void) -{ - return 0x00001710U; -} -static inline u32 bus_bind_status_bar1_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 bus_bind_status_bar1_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar1_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 bus_bind_status_bar1_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 bus_bind_status_bar1_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar1_outstanding_true_f(void) -{ - return 0x2U; -} -static inline u32 bus_bind_status_bar2_pending_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 bus_bind_status_bar2_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar2_pending_busy_f(void) -{ - return 0x4U; -} -static inline u32 bus_bind_status_bar2_outstanding_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 bus_bind_status_bar2_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar2_outstanding_true_f(void) -{ - return 0x8U; -} -static inline u32 bus_intr_0_r(void) -{ - return 0x00001100U; -} -static inline u32 bus_intr_0_pri_squash_m(void) -{ - return 0x1U << 1U; -} -static inline u32 bus_intr_0_pri_fecserr_m(void) -{ - return 0x1U << 2U; -} -static inline u32 bus_intr_0_pri_timeout_m(void) -{ - return 0x1U << 3U; -} -static inline u32 bus_intr_en_0_r(void) -{ - return 0x00001140U; -} -static inline u32 bus_intr_en_0_pri_squash_m(void) -{ - return 0x1U << 1U; -} -static inline u32 bus_intr_en_0_pri_fecserr_m(void) -{ - return 0x1U << 2U; -} -static inline u32 bus_intr_en_0_pri_timeout_m(void) -{ - return 0x1U << 3U; -} -#endif diff --git a/include/nvgpu/hw/gp10b/hw_ccsr_gp10b.h b/include/nvgpu/hw/gp10b/hw_ccsr_gp10b.h deleted file mode 100644 index 00879c1..0000000 --- a/include/nvgpu/hw/gp10b/hw_ccsr_gp10b.h +++ /dev/null @@ -1,163 +0,0 @@ -/* - * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ccsr_gp10b_h_ -#define _hw_ccsr_gp10b_h_ - -static inline u32 ccsr_channel_inst_r(u32 i) -{ - return 0x00800000U + i*8U; -} -static inline u32 ccsr_channel_inst__size_1_v(void) -{ - return 0x00000200U; -} -static inline u32 ccsr_channel_inst_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 ccsr_channel_inst_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 ccsr_channel_inst_bind_false_f(void) -{ - return 0x0U; -} -static inline u32 ccsr_channel_inst_bind_true_f(void) -{ - return 0x80000000U; -} -static inline u32 ccsr_channel_r(u32 i) -{ - return 0x00800004U + i*8U; -} -static inline u32 ccsr_channel__size_1_v(void) -{ - return 0x00000200U; -} -static inline u32 ccsr_channel_enable_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ccsr_channel_enable_set_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 ccsr_channel_enable_set_true_f(void) -{ - return 0x400U; -} -static inline u32 ccsr_channel_enable_clr_true_f(void) -{ - return 0x800U; -} -static inline u32 ccsr_channel_status_v(u32 r) -{ - return (r >> 24U) & 0xfU; -} -static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) -{ - return 0x00000002U; -} -static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) -{ - return 0x00000004U; -} -static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) -{ - return 0x0000000aU; -} -static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) -{ - return 0x0000000bU; -} -static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) -{ - return 0x0000000cU; -} -static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) -{ - return 0x0000000dU; -} -static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) -{ - return 0x0000000eU; -} -static inline u32 ccsr_channel_next_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ccsr_channel_next_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_force_ctx_reload_true_f(void) -{ - return 0x100U; -} -static inline u32 ccsr_channel_busy_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -#endif diff --git a/include/nvgpu/hw/gp10b/hw_ce_gp10b.h b/include/nvgpu/hw/gp10b/hw_ce_gp10b.h deleted file mode 100644 index c293771..0000000 --- a/include/nvgpu/hw/gp10b/hw_ce_gp10b.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ce_gp10b_h_ -#define _hw_ce_gp10b_h_ - -static inline u32 ce_intr_status_r(u32 i) -{ - return 0x00104410U + i*128U; -} -static inline u32 ce_intr_status_blockpipe_pending_f(void) -{ - return 0x1U; -} -static inline u32 ce_intr_status_blockpipe_reset_f(void) -{ - return 0x1U; -} -static inline u32 ce_intr_status_nonblockpipe_pending_f(void) -{ - return 0x2U; -} -static inline u32 ce_intr_status_nonblockpipe_reset_f(void) -{ - return 0x2U; -} -static inline u32 ce_intr_status_launcherr_pending_f(void) -{ - return 0x4U; -} -static inline u32 ce_intr_status_launcherr_reset_f(void) -{ - return 0x4U; -} -#endif diff --git a/include/nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h b/include/nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h deleted file mode 100644 index d83320f..0000000 --- a/include/nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h +++ /dev/null @@ -1,491 +0,0 @@ -/* - * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ctxsw_prog_gp10b_h_ -#define _hw_ctxsw_prog_gp10b_h_ - -static inline u32 ctxsw_prog_fecs_header_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) -{ - return 0x00000008U; -} -static inline u32 ctxsw_prog_main_image_patch_count_o(void) -{ - return 0x00000010U; -} -static inline u32 ctxsw_prog_main_image_context_id_o(void) -{ - return 0x000000f0U; -} -static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) -{ - return 0x00000014U; -} -static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) -{ - return 0x00000018U; -} -static inline u32 ctxsw_prog_main_image_zcull_o(void) -{ - return 0x0000001cU; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) -{ - return 0x00000001U; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) -{ - return 0x00000020U; -} -static inline u32 ctxsw_prog_main_image_pm_o(void) -{ - return 0x00000028U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_m(void) -{ - return 0x7U << 0U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_ctxsw_f(void) -{ - return 0x1U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) -{ - return 0x7U << 3U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) -{ - return 0x8U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) -{ - return 0x0000002cU; -} -static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) -{ - return 0x000000f4U; -} -static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void) -{ - return 0x000000d0U; -} -static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void) -{ - return 0x000000d4U; -} -static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void) -{ - return 0x000000d8U; -} -static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void) -{ - return 0x000000dcU; -} -static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) -{ - return 0x000000f8U; -} -static inline u32 ctxsw_prog_main_image_magic_value_o(void) -{ - return 0x000000fcU; -} -static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) -{ - return 0x600dc0deU; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_ppc_info_o(void) -{ - return 0x000000f4U; -} -static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) -{ - return 0x000000f8U; -} -static inline u32 ctxsw_prog_local_magic_value_o(void) -{ - return 0x000000fcU; -} -static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) -{ - return 0xad0becabU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) -{ - return 0x000000ecU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) -{ - return 0x00000000U; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) -{ - return 0x000000a0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) -{ - return 2U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) -{ - return 0x3U << 0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) -{ - return 0x2U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) -{ - return 0x000000a4U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) -{ - return 0x000000a8U; -} -static inline u32 ctxsw_prog_main_image_misc_options_o(void) -{ - return 0x0000003cU; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) -{ - return 0x1U << 3U; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_pmu_options_o(void) -{ - return 0x00000070U; -} -static inline u32 ctxsw_prog_main_image_pmu_options_boost_clock_frequencies_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void) -{ - return 0x00000080U; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void) -{ - return 0x1U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void) -{ - return 0x00000068U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void) -{ - return 0x00000084U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void) -{ - return 0x1U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void) -{ - return 0x2U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_o(void) -{ - return 0x000000acU; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(void) -{ - return 0x000000b0U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m(void) -{ - return 0xfffffffU << 0U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_m(void) -{ - return 0x3U << 28U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_coherent_f(void) -{ - return 0x20000000U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_noncoherent_f(void) -{ - return 0x30000000U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(void) -{ - return 0x000000b4U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_record_timestamp_record_size_in_bytes_v(void) -{ - return 0x00000080U; -} -static inline u32 ctxsw_prog_record_timestamp_record_size_in_words_v(void) -{ - return 0x00000020U; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_o(void) -{ - return 0x00000000U; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_v_value_v(void) -{ - return 0x00000000U; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_o(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_v_value_v(void) -{ - return 0x600dbeefU; -} -static inline u32 ctxsw_prog_record_timestamp_context_id_o(void) -{ - return 0x00000008U; -} -static inline u32 ctxsw_prog_record_timestamp_context_ptr_o(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_lo_o(void) -{ - return 0x00000018U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_o(void) -{ - return 0x0000001cU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_m(void) -{ - return 0xffU << 24U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_v(u32 r) -{ - return (r >> 24U) & 0xffU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v(void) -{ - return 0x00000001U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_f(void) -{ - return 0x1000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_f(void) -{ - return 0x2000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_v(void) -{ - return 0x0000000aU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_f(void) -{ - return 0xa000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_v(void) -{ - return 0x0000000bU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_f(void) -{ - return 0xb000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_v(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_f(void) -{ - return 0xc000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_v(void) -{ - return 0x0000000dU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_f(void) -{ - return 0xd000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_v(void) -{ - return 0x00000003U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_f(void) -{ - return 0x3000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_v(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_f(void) -{ - return 0x4000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_v(void) -{ - return 0x00000005U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_f(void) -{ - return 0x5000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v(void) -{ - return 0x000000ffU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f(void) -{ - return 0xff000000U; -} -#endif diff --git a/include/nvgpu/hw/gp10b/hw_falcon_gp10b.h b/include/nvgpu/hw/gp10b/hw_falcon_gp10b.h deleted file mode 100644 index 6dc401d..0000000 --- a/include/nvgpu/hw/gp10b/hw_falcon_gp10b.h +++ /dev/null @@ -1,603 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_falcon_gp10b_h_ -#define _hw_falcon_gp10b_h_ - -static inline u32 falcon_falcon_irqsset_r(void) -{ - return 0x00000000U; -} -static inline u32 falcon_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 falcon_falcon_irqsclr_r(void) -{ - return 0x00000004U; -} -static inline u32 falcon_falcon_irqstat_r(void) -{ - return 0x00000008U; -} -static inline u32 falcon_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 falcon_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 falcon_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 falcon_falcon_irqmode_r(void) -{ - return 0x0000000cU; -} -static inline u32 falcon_falcon_irqmset_r(void) -{ - return 0x00000010U; -} -static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqmclr_r(void) -{ - return 0x00000014U; -} -static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_irqmask_r(void) -{ - return 0x00000018U; -} -static inline u32 falcon_falcon_irqdest_r(void) -{ - return 0x0000001cU; -} -static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 falcon_falcon_curctx_r(void) -{ - return 0x00000050U; -} -static inline u32 falcon_falcon_nxtctx_r(void) -{ - return 0x00000054U; -} -static inline u32 falcon_falcon_mailbox0_r(void) -{ - return 0x00000040U; -} -static inline u32 falcon_falcon_mailbox1_r(void) -{ - return 0x00000044U; -} -static inline u32 falcon_falcon_itfen_r(void) -{ - return 0x00000048U; -} -static inline u32 falcon_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 falcon_falcon_idlestate_r(void) -{ - return 0x0000004cU; -} -static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 falcon_falcon_os_r(void) -{ - return 0x00000080U; -} -static inline u32 falcon_falcon_engctl_r(void) -{ - return 0x000000a4U; -} -static inline u32 falcon_falcon_cpuctl_r(void) -{ - return 0x00000100U; -} -static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_m(void) -{ - return 0x1U << 4U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 falcon_falcon_cpuctl_stopped_m(void) -{ - return 0x1U << 5U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void) -{ - return 0x1U << 6U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 falcon_falcon_cpuctl_alias_r(void) -{ - return 0x00000130U; -} -static inline u32 falcon_falcon_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_imemc_r(u32 i) -{ - return 0x00000180U + i*16U; -} -static inline u32 falcon_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 falcon_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 falcon_falcon_imemc_secure_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 falcon_falcon_imemd_r(u32 i) -{ - return 0x00000184U + i*16U; -} -static inline u32 falcon_falcon_imemt_r(u32 i) -{ - return 0x00000188U + i*16U; -} -static inline u32 falcon_falcon_sctl_r(void) -{ - return 0x00000240U; -} -static inline u32 falcon_falcon_mmu_phys_sec_r(void) -{ - return 0x00100ce4U; -} -static inline u32 falcon_falcon_bootvec_r(void) -{ - return 0x00000104U; -} -static inline u32 falcon_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 falcon_falcon_dmactl_r(void) -{ - return 0x0000010cU; -} -static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void) -{ - return 0x1U << 1U; -} -static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void) -{ - return 0x1U << 2U; -} -static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_hwcfg_r(void) -{ - return 0x00000108U; -} -static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 falcon_falcon_dmatrfbase_r(void) -{ - return 0x00000110U; -} -static inline u32 falcon_falcon_dmatrfbase1_r(void) -{ - return 0x00000128U; -} -static inline u32 falcon_falcon_dmatrfmoffs_r(void) -{ - return 0x00000114U; -} -static inline u32 falcon_falcon_imctl_debug_r(void) -{ - return 0x0000015cU; -} -static inline u32 falcon_falcon_imctl_debug_addr_blk_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 falcon_falcon_imctl_debug_cmd_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 falcon_falcon_imstat_r(void) -{ - return 0x00000144U; -} -static inline u32 falcon_falcon_traceidx_r(void) -{ - return 0x00000148U; -} -static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 falcon_falcon_traceidx_idx_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 falcon_falcon_tracepc_r(void) -{ - return 0x0000014cU; -} -static inline u32 falcon_falcon_tracepc_pc_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 falcon_falcon_dmatrfcmd_r(void) -{ - return 0x00000118U; -} -static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 falcon_falcon_dmatrffboffs_r(void) -{ - return 0x0000011cU; -} -static inline u32 falcon_falcon_exterraddr_r(void) -{ - return 0x00000168U; -} -static inline u32 falcon_falcon_exterrstat_r(void) -{ - return 0x0000016cU; -} -static inline u32 falcon_falcon_exterrstat_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 falcon_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 falcon_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 falcon_falcon_icd_cmd_r(void) -{ - return 0x00000200U; -} -static inline u32 falcon_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 falcon_falcon_icd_cmd_opc_m(void) -{ - return 0xfU << 0U; -} -static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 falcon_falcon_icd_rdata_r(void) -{ - return 0x0000020cU; -} -static inline u32 falcon_falcon_dmemc_r(u32 i) -{ - return 0x000001c0U + i*8U; -} -static inline u32 falcon_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 falcon_falcon_dmemc_offs_m(void) -{ - return 0x3fU << 2U; -} -static inline u32 falcon_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_dmemc_blk_m(void) -{ - return 0xffU << 8U; -} -static inline u32 falcon_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 falcon_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 falcon_falcon_dmemd_r(u32 i) -{ - return 0x000001c4U + i*8U; -} -static inline u32 falcon_falcon_debug1_r(void) -{ - return 0x00000090U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void) -{ - return 1U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void) -{ - return 0x1U << 16U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void) -{ - return 0x0U; -} -static inline u32 falcon_falcon_debuginfo_r(void) -{ - return 0x00000094U; -} -#endif diff --git a/include/nvgpu/hw/gp10b/hw_fb_gp10b.h b/include/nvgpu/hw/gp10b/hw_fb_gp10b.h deleted file mode 100644 index c1ef471..0000000 --- a/include/nvgpu/hw/gp10b/hw_fb_gp10b.h +++ /dev/null @@ -1,463 +0,0 @@ -/* - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_fb_gp10b_h_ -#define _hw_fb_gp10b_h_ - -static inline u32 fb_fbhub_num_active_ltcs_r(void) -{ - return 0x00100800U; -} -static inline u32 fb_mmu_ctrl_r(void) -{ - return 0x00100c80U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 fb_priv_mmu_phy_secure_r(void) -{ - return 0x00100ce4U; -} -static inline u32 fb_mmu_invalidate_pdb_r(void) -{ - return 0x00100cb8U; -} -static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_invalidate_r(void) -{ - return 0x00100cbcU; -} -static inline u32 fb_mmu_invalidate_all_va_true_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_m(void) -{ - return 0x1U << 2U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_invalidate_replay_s(void) -{ - return 3U; -} -static inline u32 fb_mmu_invalidate_replay_f(u32 v) -{ - return (v & 0x7U) << 3U; -} -static inline u32 fb_mmu_invalidate_replay_m(void) -{ - return 0x7U << 3U; -} -static inline u32 fb_mmu_invalidate_replay_v(u32 r) -{ - return (r >> 3U) & 0x7U; -} -static inline u32 fb_mmu_invalidate_replay_none_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_replay_start_f(void) -{ - return 0x8U; -} -static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void) -{ - return 0x10U; -} -static inline u32 fb_mmu_invalidate_replay_cancel_targeted_f(void) -{ - return 0x18U; -} -static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void) -{ - return 0x20U; -} -static inline u32 fb_mmu_invalidate_replay_cancel_f(void) -{ - return 0x20U; -} -static inline u32 fb_mmu_invalidate_sys_membar_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 fb_mmu_invalidate_sys_membar_m(void) -{ - return 0x1U << 6U; -} -static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_sys_membar_true_f(void) -{ - return 0x40U; -} -static inline u32 fb_mmu_invalidate_ack_s(void) -{ - return 2U; -} -static inline u32 fb_mmu_invalidate_ack_f(u32 v) -{ - return (v & 0x3U) << 7U; -} -static inline u32 fb_mmu_invalidate_ack_m(void) -{ - return 0x3U << 7U; -} -static inline u32 fb_mmu_invalidate_ack_v(u32 r) -{ - return (r >> 7U) & 0x3U; -} -static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void) -{ - return 0x100U; -} -static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void) -{ - return 0x80U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_s(void) -{ - return 6U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v) -{ - return (v & 0x3fU) << 9U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_m(void) -{ - return 0x3fU << 9U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r) -{ - return (r >> 9U) & 0x3fU; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void) -{ - return 5U; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v) -{ - return (v & 0x1fU) << 15U; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void) -{ - return 0x1fU << 15U; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r) -{ - return (r >> 15U) & 0x1fU; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_m(void) -{ - return 0x1U << 20U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void) -{ - return 0x100000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void) -{ - return 3U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void) -{ - return 0x7U << 24U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r) -{ - return (r >> 24U) & 0x7U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void) -{ - return 0x1000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void) -{ - return 0x2000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void) -{ - return 0x3000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void) -{ - return 0x4000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void) -{ - return 0x5000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void) -{ - return 0x6000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void) -{ - return 0x7000000U; -} -static inline u32 fb_mmu_invalidate_trigger_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_trigger_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_invalidate_trigger_m(void) -{ - return 0x1U << 31U; -} -static inline u32 fb_mmu_invalidate_trigger_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_trigger_true_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_debug_wr_r(void) -{ - return 0x00100cc8U; -} -static inline u32 fb_mmu_debug_wr_aperture_s(void) -{ - return 2U; -} -static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 fb_mmu_debug_wr_aperture_m(void) -{ - return 0x3U << 0U; -} -static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_debug_wr_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_wr_vol_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_debug_wr_vol_true_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_debug_wr_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) -{ - return 0x0000000cU; -} -static inline u32 fb_mmu_debug_rd_r(void) -{ - return 0x00100cccU; -} -static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_debug_rd_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_rd_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) -{ - return 0x0000000cU; -} -static inline u32 fb_mmu_debug_ctrl_r(void) -{ - return 0x00100cc4U; -} -static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 fb_mmu_debug_ctrl_debug_m(void) -{ - return 0x1U << 16U; -} -static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_vpr_info_r(void) -{ - return 0x00100cd0U; -} -static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 fb_mmu_vpr_info_fetch_false_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_vpr_info_fetch_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_niso_flush_sysmem_addr_r(void) -{ - return 0x00100c10U; -} -#endif diff --git a/include/nvgpu/hw/gp10b/hw_fifo_gp10b.h b/include/nvgpu/hw/gp10b/hw_fifo_gp10b.h deleted file mode 100644 index 7170162..0000000 --- a/include/nvgpu/hw/gp10b/hw_fifo_gp10b.h +++ /dev/null @@ -1,699 +0,0 @@ -/* - * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_fifo_gp10b_h_ -#define _hw_fifo_gp10b_h_ - -static inline u32 fifo_bar1_base_r(void) -{ - return 0x00002254U; -} -static inline u32 fifo_bar1_base_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 fifo_bar1_base_ptr_align_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 fifo_bar1_base_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 fifo_bar1_base_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 fifo_runlist_base_r(void) -{ - return 0x00002270U; -} -static inline u32 fifo_runlist_base_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 fifo_runlist_base_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 fifo_runlist_r(void) -{ - return 0x00002274U; -} -static inline u32 fifo_runlist_engine_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 fifo_eng_runlist_base_r(u32 i) -{ - return 0x00002280U + i*8U; -} -static inline u32 fifo_eng_runlist_base__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_eng_runlist_r(u32 i) -{ - return 0x00002284U + i*8U; -} -static inline u32 fifo_eng_runlist__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_eng_runlist_length_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fifo_eng_runlist_length_max_v(void) -{ - return 0x0000ffffU; -} -static inline u32 fifo_eng_runlist_pending_true_f(void) -{ - return 0x100000U; -} -static inline u32 fifo_pb_timeslice_r(u32 i) -{ - return 0x00002350U + i*4U; -} -static inline u32 fifo_pb_timeslice_timeout_16_f(void) -{ - return 0x10U; -} -static inline u32 fifo_pb_timeslice_timescale_0_f(void) -{ - return 0x0U; -} -static inline u32 fifo_pb_timeslice_enable_true_f(void) -{ - return 0x10000000U; -} -static inline u32 fifo_pbdma_map_r(u32 i) -{ - return 0x00002390U + i*4U; -} -static inline u32 fifo_intr_0_r(void) -{ - return 0x00002100U; -} -static inline u32 fifo_intr_0_bind_error_pending_f(void) -{ - return 0x1U; -} -static inline u32 fifo_intr_0_bind_error_reset_f(void) -{ - return 0x1U; -} -static inline u32 fifo_intr_0_sched_error_pending_f(void) -{ - return 0x100U; -} -static inline u32 fifo_intr_0_sched_error_reset_f(void) -{ - return 0x100U; -} -static inline u32 fifo_intr_0_chsw_error_pending_f(void) -{ - return 0x10000U; -} -static inline u32 fifo_intr_0_chsw_error_reset_f(void) -{ - return 0x10000U; -} -static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void) -{ - return 0x800000U; -} -static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void) -{ - return 0x800000U; -} -static inline u32 fifo_intr_0_lb_error_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_intr_0_lb_error_reset_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_intr_0_replayable_fault_error_pending_f(void) -{ - return 0x2000000U; -} -static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void) -{ - return 0x8000000U; -} -static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void) -{ - return 0x8000000U; -} -static inline u32 fifo_intr_0_mmu_fault_pending_f(void) -{ - return 0x10000000U; -} -static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 fifo_intr_0_runlist_event_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 fifo_intr_0_channel_intr_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 fifo_intr_en_0_r(void) -{ - return 0x00002140U; -} -static inline u32 fifo_intr_en_0_sched_error_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 fifo_intr_en_0_sched_error_m(void) -{ - return 0x1U << 8U; -} -static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 fifo_intr_en_0_mmu_fault_m(void) -{ - return 0x1U << 28U; -} -static inline u32 fifo_intr_en_1_r(void) -{ - return 0x00002528U; -} -static inline u32 fifo_intr_bind_error_r(void) -{ - return 0x0000252cU; -} -static inline u32 fifo_intr_sched_error_r(void) -{ - return 0x0000254cU; -} -static inline u32 fifo_intr_sched_error_code_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void) -{ - return 0x0000000aU; -} -static inline u32 fifo_intr_chsw_error_r(void) -{ - return 0x0000256cU; -} -static inline u32 fifo_intr_mmu_fault_id_r(void) -{ - return 0x0000259cU; -} -static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void) -{ - return 0x0U; -} -static inline u32 fifo_intr_mmu_fault_inst_r(u32 i) -{ - return 0x00002800U + i*16U; -} -static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 fifo_intr_mmu_fault_lo_r(u32 i) -{ - return 0x00002804U + i*16U; -} -static inline u32 fifo_intr_mmu_fault_hi_r(u32 i) -{ - return 0x00002808U + i*16U; -} -static inline u32 fifo_intr_mmu_fault_info_r(u32 i) -{ - return 0x0000280cU + i*16U; -} -static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 fifo_intr_mmu_fault_info_access_type_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 fifo_intr_mmu_fault_info_client_type_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 fifo_intr_mmu_fault_info_client_type_gpc_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_intr_mmu_fault_info_client_type_hub_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r) -{ - return (r >> 8U) & 0x7fU; -} -static inline u32 fifo_intr_pbdma_id_r(void) -{ - return 0x000025a0U; -} -static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) -{ - return (r >> (0U + i*1U)) & 0x1U; -} -static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_intr_runlist_r(void) -{ - return 0x00002a00U; -} -static inline u32 fifo_fb_timeout_r(void) -{ - return 0x00002a04U; -} -static inline u32 fifo_fb_timeout_period_m(void) -{ - return 0x3fffffffU << 0U; -} -static inline u32 fifo_fb_timeout_period_max_f(void) -{ - return 0x3fffffffU; -} -static inline u32 fifo_error_sched_disable_r(void) -{ - return 0x0000262cU; -} -static inline u32 fifo_sched_disable_r(void) -{ - return 0x00002630U; -} -static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_sched_disable_runlist_m(u32 i) -{ - return 0x1U << (0U + i*1U); -} -static inline u32 fifo_sched_disable_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_preempt_r(void) -{ - return 0x00002634U; -} -static inline u32 fifo_preempt_pending_true_f(void) -{ - return 0x100000U; -} -static inline u32 fifo_preempt_type_channel_f(void) -{ - return 0x0U; -} -static inline u32 fifo_preempt_type_tsg_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_preempt_chid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 fifo_preempt_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 fifo_trigger_mmu_fault_r(u32 i) -{ - return 0x00002a30U + i*4U; -} -static inline u32 fifo_trigger_mmu_fault_id_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 fifo_engine_status_r(u32 i) -{ - return 0x00002640U + i*8U; -} -static inline u32 fifo_engine_status__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fifo_engine_status_id_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 fifo_engine_status_id_type_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 fifo_engine_status_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctx_status_v(u32 r) -{ - return (r >> 13U) & 0x7U; -} -static inline u32 fifo_engine_status_ctx_status_invalid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_ctx_status_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void) -{ - return 0x00000005U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void) -{ - return 0x00000006U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void) -{ - return 0x00000007U; -} -static inline u32 fifo_engine_status_next_id_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 fifo_engine_status_next_id_type_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 fifo_engine_status_next_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_faulted_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fifo_engine_status_faulted_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_engine_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fifo_engine_status_engine_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_engine_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctxsw_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fifo_engine_status_ctxsw_in_progress_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) -{ - return 0x8000U; -} -static inline u32 fifo_pbdma_status_r(u32 i) -{ - return 0x00003080U + i*4U; -} -static inline u32 fifo_pbdma_status__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_id_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 fifo_pbdma_status_id_type_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 fifo_pbdma_status_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chan_status_v(u32 r) -{ - return (r >> 13U) & 0x7U; -} -static inline u32 fifo_pbdma_status_chan_status_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void) -{ - return 0x00000005U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void) -{ - return 0x00000006U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void) -{ - return 0x00000007U; -} -static inline u32 fifo_pbdma_status_next_id_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 fifo_pbdma_status_next_id_type_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 fifo_pbdma_status_next_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_pbdma_status_chsw_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_replay_fault_buffer_lo_r(void) -{ - return 0x00002a70U; -} -static inline u32 fifo_replay_fault_buffer_lo_enable_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 fifo_replay_fault_buffer_lo_enable_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_replay_fault_buffer_lo_enable_false_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_replay_fault_buffer_lo_base_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 fifo_replay_fault_buffer_lo_base_reset_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_replay_fault_buffer_hi_r(void) -{ - return 0x00002a74U; -} -static inline u32 fifo_replay_fault_buffer_hi_base_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fifo_replay_fault_buffer_hi_base_reset_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_replay_fault_buffer_size_r(void) -{ - return 0x00002a78U; -} -static inline u32 fifo_replay_fault_buffer_size_hw_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 fifo_replay_fault_buffer_size_hw_entries_v(void) -{ - return 0x000000c0U; -} -static inline u32 fifo_replay_fault_buffer_get_r(void) -{ - return 0x00002a7cU; -} -static inline u32 fifo_replay_fault_buffer_get_offset_hw_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 fifo_replay_fault_buffer_get_offset_hw_init_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_replay_fault_buffer_put_r(void) -{ - return 0x00002a80U; -} -static inline u32 fifo_replay_fault_buffer_put_offset_hw_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 fifo_replay_fault_buffer_put_offset_hw_init_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_replay_fault_buffer_info_r(void) -{ - return 0x00002a84U; -} -static inline u32 fifo_replay_fault_buffer_info_overflow_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 fifo_replay_fault_buffer_info_overflow_false_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_replay_fault_buffer_info_overflow_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_replay_fault_buffer_info_overflow_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_replay_fault_buffer_info_write_nack_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 fifo_replay_fault_buffer_info_write_nack_false_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_replay_fault_buffer_info_write_nack_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_replay_fault_buffer_info_write_nack_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_false_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_clear_v(void) -{ - return 0x00000001U; -} -#endif diff --git a/include/nvgpu/hw/gp10b/hw_flush_gp10b.h b/include/nvgpu/hw/gp10b/hw_flush_gp10b.h deleted file mode 100644 index ae6eabf..0000000 --- a/include/nvgpu/hw/gp10b/hw_flush_gp10b.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_flush_gp10b_h_ -#define _hw_flush_gp10b_h_ - -static inline u32 flush_l2_system_invalidate_r(void) -{ - return 0x00070004U; -} -static inline u32 flush_l2_system_invalidate_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_system_invalidate_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_system_invalidate_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_system_invalidate_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_flush_dirty_r(void) -{ - return 0x00070010U; -} -static inline u32 flush_l2_flush_dirty_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_flush_dirty_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_flush_dirty_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_flush_dirty_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_flush_dirty_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_flush_dirty_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_flush_dirty_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_clean_comptags_r(void) -{ - return 0x0007000cU; -} -static inline u32 flush_l2_clean_comptags_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_clean_comptags_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_clean_comptags_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_clean_comptags_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_clean_comptags_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_clean_comptags_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_clean_comptags_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_clean_comptags_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_fb_flush_r(void) -{ - return 0x00070000U; -} -static inline u32 flush_fb_flush_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_fb_flush_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_fb_flush_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_fb_flush_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_fb_flush_outstanding_true_v(void) -{ - return 0x00000001U; -} -#endif diff --git a/include/nvgpu/hw/gp10b/hw_fuse_gp10b.h b/include/nvgpu/hw/gp10b/hw_fuse_gp10b.h deleted file mode 100644 index 521dcfe..0000000 --- a/include/nvgpu/hw/gp10b/hw_fuse_gp10b.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_fuse_gp10b_h_ -#define _hw_fuse_gp10b_h_ - -static inline u32 fuse_status_opt_gpc_r(void) -{ - return 0x00021c1cU; -} -static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) -{ - return 0x00021c38U + i*4U; -} -static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i) -{ - return 0x00021838U + i*4U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void) -{ - return 0x00021944U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void) -{ - return 0xffU << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void) -{ - return 0x00021948U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void) -{ - return 0x1U << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void) -{ - return 0x1U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void) -{ - return 0x0U; -} -static inline u32 fuse_status_opt_fbio_r(void) -{ - return 0x00021c14U; -} -static inline u32 fuse_status_opt_fbio_data_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fuse_status_opt_fbio_data_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 fuse_status_opt_fbio_data_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i) -{ - return 0x00021d70U + i*4U; -} -static inline u32 fuse_status_opt_fbp_r(void) -{ - return 0x00021d38U; -} -static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) -{ - return (r >> (0U + i*1U)) & 0x1U; -} -static inline u32 fuse_opt_ecc_en_r(void) -{ - return 0x00021228U; -} -static inline u32 fuse_opt_feature_fuses_override_disable_r(void) -{ - return 0x000213f0U; -} -static inline u32 fuse_opt_sec_debug_en_r(void) -{ - return 0x00021218U; -} -static inline u32 fuse_opt_priv_sec_en_r(void) -{ - return 0x00021434U; -} -#endif diff --git a/include/nvgpu/hw/gp10b/hw_gmmu_gp10b.h b/include/nvgpu/hw/gp10b/hw_gmmu_gp10b.h deleted file mode 100644 index 6aeb435..0000000 --- a/include/nvgpu/hw/gp10b/hw_gmmu_gp10b.h +++ /dev/null @@ -1,331 +0,0 @@ -/* - * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_gmmu_gp10b_h_ -#define _hw_gmmu_gp10b_h_ - -static inline u32 gmmu_new_pde_is_pte_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_is_pte_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pde_aperture_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_aperture_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pde_aperture_video_memory_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_pde_address_sys_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_pde_address_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_vol_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_vol_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_pde_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pde_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_new_pde__size_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_new_dual_pde_is_pte_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_is_pte_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 gmmu_new_dual_pde_address_big_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_w(void) -{ - return 2U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_dual_pde_vol_small_w(void) -{ - return 2U; -} -static inline u32 gmmu_new_dual_pde_vol_small_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_dual_pde_vol_small_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_vol_big_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_vol_big_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_dual_pde_vol_big_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) -{ - return 2U; -} -static inline u32 gmmu_new_dual_pde_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_new_dual_pde_address_big_shift_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_new_dual_pde__size_v(void) -{ - return 0x00000010U; -} -static inline u32 gmmu_new_pte__size_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_new_pte_valid_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_valid_true_f(void) -{ - return 0x1U; -} -static inline u32 gmmu_new_pte_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_privilege_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_privilege_true_f(void) -{ - return 0x20U; -} -static inline u32 gmmu_new_pte_privilege_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_address_sys_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_pte_address_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_address_vid_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_pte_address_vid_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_vol_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_vol_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_pte_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_aperture_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_aperture_video_memory_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_pte_read_only_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_read_only_true_f(void) -{ - return 0x40U; -} -static inline u32 gmmu_new_pte_comptagline_f(u32 v) -{ - return (v & 0x3ffffU) << 4U; -} -static inline u32 gmmu_new_pte_comptagline_w(void) -{ - return 1U; -} -static inline u32 gmmu_new_pte_kind_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gmmu_new_pte_kind_w(void) -{ - return 1U; -} -static inline u32 gmmu_new_pte_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_pte_kind_f(u32 v) -{ - return (v & 0xffU) << 4U; -} -static inline u32 gmmu_pte_kind_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_kind_invalid_v(void) -{ - return 0x000000ffU; -} -static inline u32 gmmu_pte_kind_pitch_v(void) -{ - return 0x00000000U; -} -#endif diff --git a/include/nvgpu/hw/gp10b/hw_gr_gp10b.h b/include/nvgpu/hw/gp10b/hw_gr_gp10b.h deleted file mode 100644 index 89c6bba..0000000 --- a/include/nvgpu/hw/gp10b/hw_gr_gp10b.h +++ /dev/null @@ -1,4419 +0,0 @@ -/* - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_gr_gp10b_h_ -#define _hw_gr_gp10b_h_ - -static inline u32 gr_intr_r(void) -{ - return 0x00400100U; -} -static inline u32 gr_intr_notify_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_intr_notify_reset_f(void) -{ - return 0x1U; -} -static inline u32 gr_intr_semaphore_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_semaphore_reset_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_illegal_method_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_intr_illegal_method_reset_f(void) -{ - return 0x10U; -} -static inline u32 gr_intr_illegal_notify_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_intr_illegal_notify_reset_f(void) -{ - return 0x40U; -} -static inline u32 gr_intr_firmware_method_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 gr_intr_firmware_method_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_intr_firmware_method_reset_f(void) -{ - return 0x100U; -} -static inline u32 gr_intr_illegal_class_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_intr_illegal_class_reset_f(void) -{ - return 0x20U; -} -static inline u32 gr_intr_fecs_error_pending_f(void) -{ - return 0x80000U; -} -static inline u32 gr_intr_fecs_error_reset_f(void) -{ - return 0x80000U; -} -static inline u32 gr_intr_class_error_pending_f(void) -{ - return 0x100000U; -} -static inline u32 gr_intr_class_error_reset_f(void) -{ - return 0x100000U; -} -static inline u32 gr_intr_exception_pending_f(void) -{ - return 0x200000U; -} -static inline u32 gr_intr_exception_reset_f(void) -{ - return 0x200000U; -} -static inline u32 gr_fecs_intr_r(void) -{ - return 0x00400144U; -} -static inline u32 gr_class_error_r(void) -{ - return 0x00400110U; -} -static inline u32 gr_class_error_code_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_intr_nonstall_r(void) -{ - return 0x00400120U; -} -static inline u32 gr_intr_nonstall_trap_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_en_r(void) -{ - return 0x0040013cU; -} -static inline u32 gr_exception_r(void) -{ - return 0x00400108U; -} -static inline u32 gr_exception_fe_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_exception_gpc_m(void) -{ - return 0x1U << 24U; -} -static inline u32 gr_exception_memfmt_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_exception_ds_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_exception_sked_m(void) -{ - return 0x1U << 8U; -} -static inline u32 gr_exception_pd_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_exception_scc_m(void) -{ - return 0x1U << 3U; -} -static inline u32 gr_exception_ssync_m(void) -{ - return 0x1U << 5U; -} -static inline u32 gr_exception_mme_m(void) -{ - return 0x1U << 7U; -} -static inline u32 gr_exception1_r(void) -{ - return 0x00400118U; -} -static inline u32 gr_exception1_gpc_0_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_exception2_r(void) -{ - return 0x0040011cU; -} -static inline u32 gr_exception_en_r(void) -{ - return 0x00400138U; -} -static inline u32 gr_exception_en_fe_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_exception1_en_r(void) -{ - return 0x00400130U; -} -static inline u32 gr_exception2_en_r(void) -{ - return 0x00400134U; -} -static inline u32 gr_gpfifo_ctl_r(void) -{ - return 0x00400500U; -} -static inline u32 gr_gpfifo_ctl_access_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpfifo_ctl_access_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpfifo_ctl_access_enabled_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void) -{ - return 0x10000U; -} -static inline u32 gr_gpfifo_status_r(void) -{ - return 0x00400504U; -} -static inline u32 gr_trapped_addr_r(void) -{ - return 0x00400704U; -} -static inline u32 gr_trapped_addr_mthd_v(u32 r) -{ - return (r >> 2U) & 0xfffU; -} -static inline u32 gr_trapped_addr_subch_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 gr_trapped_addr_mme_generated_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 gr_trapped_addr_datahigh_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 gr_trapped_addr_priv_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 gr_trapped_addr_status_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_trapped_data_lo_r(void) -{ - return 0x00400708U; -} -static inline u32 gr_trapped_data_hi_r(void) -{ - return 0x0040070cU; -} -static inline u32 gr_trapped_data_mme_r(void) -{ - return 0x00400710U; -} -static inline u32 gr_trapped_data_mme_pc_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 gr_status_r(void) -{ - return 0x00400700U; -} -static inline u32 gr_status_fe_method_upper_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_status_fe_method_lower_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_status_fe_method_lower_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_status_fe_gi_v(u32 r) -{ - return (r >> 21U) & 0x1U; -} -static inline u32 gr_status_mask_r(void) -{ - return 0x00400610U; -} -static inline u32 gr_status_1_r(void) -{ - return 0x00400604U; -} -static inline u32 gr_status_2_r(void) -{ - return 0x00400608U; -} -static inline u32 gr_engine_status_r(void) -{ - return 0x0040060cU; -} -static inline u32 gr_engine_status_value_busy_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_be0_becs_be_exception_r(void) -{ - return 0x00410204U; -} -static inline u32 gr_pri_be0_becs_be_exception_en_r(void) -{ - return 0x00410208U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void) -{ - return 0x00502c90U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void) -{ - return 0x00502c94U; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void) -{ - return 0x00504508U; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void) -{ - return 0x0050450cU; -} -static inline u32 gr_activity_0_r(void) -{ - return 0x00400380U; -} -static inline u32 gr_activity_1_r(void) -{ - return 0x00400384U; -} -static inline u32 gr_activity_2_r(void) -{ - return 0x00400388U; -} -static inline u32 gr_activity_4_r(void) -{ - return 0x00400390U; -} -static inline u32 gr_activity_4_gpc0_s(void) -{ - return 3U; -} -static inline u32 gr_activity_4_gpc0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_activity_4_gpc0_m(void) -{ - return 0x7U << 0U; -} -static inline u32 gr_activity_4_gpc0_v(u32 r) -{ - return (r >> 0U) & 0x7U; -} -static inline u32 gr_activity_4_gpc0_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_activity_4_gpc0_preempted_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_pri_gpc0_gcc_dbg_r(void) -{ - return 0x00501000U; -} -static inline u32 gr_pri_gpcs_gcc_dbg_r(void) -{ - return 0x00419000U; -} -static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) -{ - return 0x005046a4U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) -{ - return 0x00419ea4U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_pri_sked_activity_r(void) -{ - return 0x00407054U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void) -{ - return 0x00502c80U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void) -{ - return 0x00502c84U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void) -{ - return 0x00502c88U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void) -{ - return 0x00502c8cU; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void) -{ - return 0x00504500U; -} -static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void) -{ - return 0x00504d00U; -} -static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void) -{ - return 0x00501d00U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void) -{ - return 0x0041ac80U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void) -{ - return 0x0041ac84U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void) -{ - return 0x0041ac88U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void) -{ - return 0x0041ac8cU; -} -static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void) -{ - return 0x0041c500U; -} -static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void) -{ - return 0x0041cd00U; -} -static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void) -{ - return 0x00419d00U; -} -static inline u32 gr_pri_be0_becs_be_activity0_r(void) -{ - return 0x00410200U; -} -static inline u32 gr_pri_be1_becs_be_activity0_r(void) -{ - return 0x00410600U; -} -static inline u32 gr_pri_bes_becs_be_activity0_r(void) -{ - return 0x00408a00U; -} -static inline u32 gr_pri_ds_mpipe_status_r(void) -{ - return 0x00405858U; -} -static inline u32 gr_pri_fe_go_idle_info_r(void) -{ - return 0x00404194U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) -{ - return 0x00504238U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) -{ - return 0x005046b8U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_b(void) -{ - return 4U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp1_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp2_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f(void) -{ - return 0x80U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_b(void) -{ - return 8U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp1_pending_f(void) -{ - return 0x200U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp2_pending_f(void) -{ - return 0x400U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f(void) -{ - return 0x800U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_r(void) -{ - return 0x005044a0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm1_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f(void) -{ - return 0x200U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r(void) -{ - return 0x005046bcU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r(void) -{ - return 0x005046c0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r(void) -{ - return 0x005044a4U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m(void) -{ - return 0xffU << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m(void) -{ - return 0xffU << 8U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m(void) -{ - return 0xffU << 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) -{ - return 0x005042c4U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void) -{ - return 0x2U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r(void) -{ - return 0x00504218U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(void) -{ - return 0xffffU << 16U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r(void) -{ - return 0x005042ecU; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(void) -{ - return 0xffffU << 16U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 gr_pri_be0_crop_status1_r(void) -{ - return 0x00410134U; -} -static inline u32 gr_pri_bes_crop_status1_r(void) -{ - return 0x00408934U; -} -static inline u32 gr_pri_be0_zrop_status_r(void) -{ - return 0x00410048U; -} -static inline u32 gr_pri_be0_zrop_status2_r(void) -{ - return 0x0041004cU; -} -static inline u32 gr_pri_bes_zrop_status_r(void) -{ - return 0x00408848U; -} -static inline u32 gr_pri_bes_zrop_status2_r(void) -{ - return 0x0040884cU; -} -static inline u32 gr_pipe_bundle_address_r(void) -{ - return 0x00400200U; -} -static inline u32 gr_pipe_bundle_address_value_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pipe_bundle_data_r(void) -{ - return 0x00400204U; -} -static inline u32 gr_pipe_bundle_config_r(void) -{ - return 0x00400208U; -} -static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fe_hww_esr_r(void) -{ - return 0x00404000U; -} -static inline u32 gr_fe_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_fe_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fe_hww_esr_info_r(void) -{ - return 0x004041b0U; -} -static inline u32 gr_fe_go_idle_timeout_r(void) -{ - return 0x00404154U; -} -static inline u32 gr_fe_go_idle_timeout_count_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) -{ - return 0x7fffffffU; -} -static inline u32 gr_fe_object_table_r(u32 i) -{ - return 0x00404200U + i*4U; -} -static inline u32 gr_fe_object_table_nvclass_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_fe_tpc_fs_r(void) -{ - return 0x004041c4U; -} -static inline u32 gr_pri_mme_shadow_raw_index_r(void) -{ - return 0x00404488U; -} -static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pri_mme_shadow_raw_data_r(void) -{ - return 0x0040448cU; -} -static inline u32 gr_mme_hww_esr_r(void) -{ - return 0x00404490U; -} -static inline u32 gr_mme_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_mme_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_mme_hww_esr_info_r(void) -{ - return 0x00404494U; -} -static inline u32 gr_memfmt_hww_esr_r(void) -{ - return 0x00404600U; -} -static inline u32 gr_memfmt_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_memfmt_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fecs_cpuctl_r(void) -{ - return 0x00409100U; -} -static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_cpuctl_alias_r(void) -{ - return 0x00409130U; -} -static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_dmactl_r(void) -{ - return 0x0040910cU; -} -static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_fecs_os_r(void) -{ - return 0x00409080U; -} -static inline u32 gr_fecs_idlestate_r(void) -{ - return 0x0040904cU; -} -static inline u32 gr_fecs_mailbox0_r(void) -{ - return 0x00409040U; -} -static inline u32 gr_fecs_mailbox1_r(void) -{ - return 0x00409044U; -} -static inline u32 gr_fecs_irqstat_r(void) -{ - return 0x00409008U; -} -static inline u32 gr_fecs_irqmode_r(void) -{ - return 0x0040900cU; -} -static inline u32 gr_fecs_irqmask_r(void) -{ - return 0x00409018U; -} -static inline u32 gr_fecs_irqdest_r(void) -{ - return 0x0040901cU; -} -static inline u32 gr_fecs_curctx_r(void) -{ - return 0x00409050U; -} -static inline u32 gr_fecs_nxtctx_r(void) -{ - return 0x00409054U; -} -static inline u32 gr_fecs_engctl_r(void) -{ - return 0x004090a4U; -} -static inline u32 gr_fecs_debug1_r(void) -{ - return 0x00409090U; -} -static inline u32 gr_fecs_debuginfo_r(void) -{ - return 0x00409094U; -} -static inline u32 gr_fecs_icd_cmd_r(void) -{ - return 0x00409200U; -} -static inline u32 gr_fecs_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 gr_fecs_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_fecs_icd_cmd_opc_m(void) -{ - return 0xfU << 0U; -} -static inline u32 gr_fecs_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 gr_fecs_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 gr_fecs_icd_rdata_r(void) -{ - return 0x0040920cU; -} -static inline u32 gr_fecs_imemc_r(u32 i) -{ - return 0x00409180U + i*16U; -} -static inline u32 gr_fecs_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_fecs_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_fecs_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_fecs_imemd_r(u32 i) -{ - return 0x00409184U + i*16U; -} -static inline u32 gr_fecs_imemt_r(u32 i) -{ - return 0x00409188U + i*16U; -} -static inline u32 gr_fecs_imemt_tag_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_fecs_dmemc_r(u32 i) -{ - return 0x004091c0U + i*8U; -} -static inline u32 gr_fecs_dmemc_offs_s(void) -{ - return 6U; -} -static inline u32 gr_fecs_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_fecs_dmemc_offs_m(void) -{ - return 0x3fU << 2U; -} -static inline u32 gr_fecs_dmemc_offs_v(u32 r) -{ - return (r >> 2U) & 0x3fU; -} -static inline u32 gr_fecs_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_fecs_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_fecs_dmemd_r(u32 i) -{ - return 0x004091c4U + i*8U; -} -static inline u32 gr_fecs_dmatrfbase_r(void) -{ - return 0x00409110U; -} -static inline u32 gr_fecs_dmatrfmoffs_r(void) -{ - return 0x00409114U; -} -static inline u32 gr_fecs_dmatrffboffs_r(void) -{ - return 0x0040911cU; -} -static inline u32 gr_fecs_dmatrfcmd_r(void) -{ - return 0x00409118U; -} -static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_fecs_bootvec_r(void) -{ - return 0x00409104U; -} -static inline u32 gr_fecs_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_falcon_hwcfg_r(void) -{ - return 0x00409108U; -} -static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void) -{ - return 0x0041a108U; -} -static inline u32 gr_fecs_falcon_rm_r(void) -{ - return 0x00409084U; -} -static inline u32 gr_fecs_current_ctx_r(void) -{ - return 0x00409b00U; -} -static inline u32 gr_fecs_current_ctx_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_current_ctx_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_current_ctx_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_current_ctx_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_current_ctx_target_m(void) -{ - return 0x3U << 28U; -} -static inline u32 gr_fecs_current_ctx_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 gr_fecs_current_ctx_valid_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_current_ctx_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_fecs_current_ctx_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_fecs_current_ctx_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_fecs_current_ctx_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_method_data_r(void) -{ - return 0x00409500U; -} -static inline u32 gr_fecs_method_push_r(void) -{ - return 0x00409504U; -} -static inline u32 gr_fecs_method_push_adr_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void) -{ - return 0x00000003U; -} -static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void) -{ - return 0x3U; -} -static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void) -{ - return 0x00000009U; -} -static inline u32 gr_fecs_method_push_adr_restore_golden_v(void) -{ - return 0x00000015U; -} -static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void) -{ - return 0x00000016U; -} -static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void) -{ - return 0x00000025U; -} -static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void) -{ - return 0x00000030U; -} -static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void) -{ - return 0x00000031U; -} -static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void) -{ - return 0x00000032U; -} -static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void) -{ - return 0x00000038U; -} -static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void) -{ - return 0x00000039U; -} -static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) -{ - return 0x21U; -} -static inline u32 gr_fecs_method_push_adr_write_timestamp_record_v(void) -{ - return 0x0000003dU; -} -static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void) -{ - return 0x0000001aU; -} -static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(void) -{ - return 0x0000003aU; -} -static inline u32 gr_fecs_host_int_status_r(void) -{ - return 0x00409c18U; -} -static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 gr_fecs_host_int_status_watchdog_active_f(void) -{ - return 0x80000U; -} -static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_fecs_host_int_clear_r(void) -{ - return 0x00409c20U; -} -static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void) -{ - return 0x2U; -} -static inline u32 gr_fecs_host_int_enable_r(void) -{ - return 0x00409c24U; -} -static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void) -{ - return 0x2U; -} -static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void) -{ - return 0x10000U; -} -static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void) -{ - return 0x20000U; -} -static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void) -{ - return 0x40000U; -} -static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void) -{ - return 0x80000U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) -{ - return 0x00409614U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void) -{ - return 0x10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void) -{ - return 0x20U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void) -{ - return 0x40U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void) -{ - return 0x100U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void) -{ - return 0x200U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void) -{ - return 0x1U << 10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r) -{ - return (r >> 10U) & 0x1U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void) -{ - return 0x400U; -} -static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void) -{ - return 0x0040960cU; -} -static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i) -{ - return 0x00409800U + i*4U; -} -static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void) -{ - return 0x00000002U; -} -static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i) -{ - return 0x004098c0U + i*4U; -} -static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i) -{ - return 0x00409840U + i*4U; -} -static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_fs_r(void) -{ - return 0x00409604U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_m(void) -{ - return 0x1fU << 0U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_fecs_fs_num_available_fbps_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 gr_fecs_fs_num_available_fbps_m(void) -{ - return 0x1fU << 16U; -} -static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -static inline u32 gr_fecs_cfg_r(void) -{ - return 0x00409620U; -} -static inline u32 gr_fecs_cfg_imem_sz_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_fecs_rc_lanes_r(void) -{ - return 0x00409880U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_s(void) -{ - return 6U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_fecs_ctxsw_status_1_r(void) -{ - return 0x00409400U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void) -{ - return 0x1U << 12U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 gr_fecs_arb_ctx_adr_r(void) -{ - return 0x00409a24U; -} -static inline u32 gr_fecs_new_ctx_r(void) -{ - return 0x00409b04U; -} -static inline u32 gr_fecs_new_ctx_ptr_s(void) -{ - return 28U; -} -static inline u32 gr_fecs_new_ctx_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_new_ctx_ptr_m(void) -{ - return 0xfffffffU << 0U; -} -static inline u32 gr_fecs_new_ctx_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_new_ctx_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_new_ctx_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_new_ctx_target_m(void) -{ - return 0x3U << 28U; -} -static inline u32 gr_fecs_new_ctx_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_new_ctx_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_new_ctx_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 gr_fecs_new_ctx_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_fecs_new_ctx_valid_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_new_ctx_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_fecs_new_ctx_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_fecs_new_ctx_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_fecs_arb_ctx_ptr_r(void) -{ - return 0x00409a0cU; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void) -{ - return 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void) -{ - return 0xfffffffU << 0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_m(void) -{ - return 0x3U << 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_fecs_arb_ctx_cmd_r(void) -{ - return 0x00409a10U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void) -{ - return 0x1fU << 0U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_fecs_ctxsw_status_fe_0_r(void) -{ - return 0x00409c00U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void) -{ - return 0x00502c04U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) -{ - return 0x00502400U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_mailbox__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_fecs_ctxsw_idlestate_r(void) -{ - return 0x00409420U; -} -static inline u32 gr_fecs_feature_override_ecc_r(void) -{ - return 0x00409658U; -} -static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_sm_shm_override_v(u32 r) -{ - return (r >> 7U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_tex_override_v(u32 r) -{ - return (r >> 11U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_sm_shm_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_tex_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) -{ - return 0x00502420U; -} -static inline u32 gr_rstr2d_gpc_map0_r(void) -{ - return 0x0040780cU; -} -static inline u32 gr_rstr2d_gpc_map1_r(void) -{ - return 0x00407810U; -} -static inline u32 gr_rstr2d_gpc_map2_r(void) -{ - return 0x00407814U; -} -static inline u32 gr_rstr2d_gpc_map3_r(void) -{ - return 0x00407818U; -} -static inline u32 gr_rstr2d_gpc_map4_r(void) -{ - return 0x0040781cU; -} -static inline u32 gr_rstr2d_gpc_map5_r(void) -{ - return 0x00407820U; -} -static inline u32 gr_rstr2d_map_table_cfg_r(void) -{ - return 0x004078bcU; -} -static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_pd_hww_esr_r(void) -{ - return 0x00406018U; -} -static inline u32 gr_pd_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pd_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i) -{ - return 0x00406028U + i*4U; -} -static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v) -{ - return (v & 0xfU) << 12U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v) -{ - return (v & 0xfU) << 24U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v) -{ - return (v & 0xfU) << 28U; -} -static inline u32 gr_pd_ab_dist_cfg0_r(void) -{ - return 0x004064c0U; -} -static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void) -{ - return 0x0U; -} -static inline u32 gr_pd_ab_dist_cfg1_r(void) -{ - return 0x004064c4U; -} -static inline u32 gr_pd_ab_dist_cfg1_max_batches_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void) -{ - return 0xffffU; -} -static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void) -{ - return 0x00000080U; -} -static inline u32 gr_pd_ab_dist_cfg2_r(void) -{ - return 0x004064c8U; -} -static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) -{ - return (v & 0x1fffU) << 0U; -} -static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) -{ - return 0x000001c0U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) -{ - return (v & 0x1fffU) << 16U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) -{ - return 0x00000182U; -} -static inline u32 gr_pd_dist_skip_table_r(u32 i) -{ - return 0x004064d0U + i*4U; -} -static inline u32 gr_pd_dist_skip_table__size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gr_ds_debug_r(void) -{ - return 0x00405800U; -} -static inline u32 gr_ds_debug_timeslice_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_debug_timeslice_mode_enable_f(void) -{ - return 0x8000000U; -} -static inline u32 gr_ds_zbc_color_r_r(void) -{ - return 0x00405804U; -} -static inline u32 gr_ds_zbc_color_r_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_g_r(void) -{ - return 0x00405808U; -} -static inline u32 gr_ds_zbc_color_g_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_b_r(void) -{ - return 0x0040580cU; -} -static inline u32 gr_ds_zbc_color_b_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_a_r(void) -{ - return 0x00405810U; -} -static inline u32 gr_ds_zbc_color_a_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_fmt_r(void) -{ - return 0x00405814U; -} -static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v) -{ - return (v & 0x7fU) << 0U; -} -static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void) -{ - return 0x00000002U; -} -static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) -{ - return 0x00000028U; -} -static inline u32 gr_ds_zbc_z_r(void) -{ - return 0x00405818U; -} -static inline u32 gr_ds_zbc_z_val_s(void) -{ - return 32U; -} -static inline u32 gr_ds_zbc_z_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_z_val_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 gr_ds_zbc_z_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gr_ds_zbc_z_val__init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_ds_zbc_z_val__init_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_z_fmt_r(void) -{ - return 0x0040581cU; -} -static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_zbc_tbl_index_r(void) -{ - return 0x00405820U; -} -static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_ds_zbc_tbl_ld_r(void) -{ - return 0x00405824U; -} -static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) -{ - return 0x4U; -} -static inline u32 gr_ds_tga_constraintlogic_beta_r(void) -{ - return 0x00405830U; -} -static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_ds_tga_constraintlogic_alpha_r(void) -{ - return 0x0040585cU; -} -static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_ds_hww_esr_r(void) -{ - return 0x00405840U; -} -static inline u32 gr_ds_hww_esr_reset_s(void) -{ - return 1U; -} -static inline u32 gr_ds_hww_esr_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_reset_m(void) -{ - return 0x1U << 30U; -} -static inline u32 gr_ds_hww_esr_reset_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_ds_hww_esr_reset_task_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_hww_esr_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_ds_hww_esr_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_ds_hww_esr_2_r(void) -{ - return 0x00405848U; -} -static inline u32 gr_ds_hww_esr_2_reset_s(void) -{ - return 1U; -} -static inline u32 gr_ds_hww_esr_2_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_2_reset_m(void) -{ - return 0x1U << 30U; -} -static inline u32 gr_ds_hww_esr_2_reset_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_ds_hww_esr_2_reset_task_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_hww_esr_2_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_ds_hww_esr_2_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_ds_hww_report_mask_r(void) -{ - return 0x00405844U; -} -static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void) -{ - return 0x8U; -} -static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void) -{ - return 0x80U; -} -static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void) -{ - return 0x200U; -} -static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void) -{ - return 0x400U; -} -static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void) -{ - return 0x800U; -} -static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void) -{ - return 0x1000U; -} -static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void) -{ - return 0x2000U; -} -static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void) -{ - return 0x4000U; -} -static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void) -{ - return 0x8000U; -} -static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void) -{ - return 0x10000U; -} -static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void) -{ - return 0x20000U; -} -static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void) -{ - return 0x40000U; -} -static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void) -{ - return 0x80000U; -} -static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void) -{ - return 0x100000U; -} -static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void) -{ - return 0x200000U; -} -static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void) -{ - return 0x400000U; -} -static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void) -{ - return 0x800000U; -} -static inline u32 gr_ds_hww_report_mask_2_r(void) -{ - return 0x0040584cU; -} -static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i) -{ - return 0x00405870U + i*4U; -} -static inline u32 gr_scc_bundle_cb_base_r(void) -{ - return 0x00408004U; -} -static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_scc_bundle_cb_size_r(void) -{ - return 0x00408008U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7ffU) << 0U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) -{ - return 0x00000018U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_scc_bundle_cb_size_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_scc_bundle_cb_size_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_scc_bundle_cb_size_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_scc_pagepool_base_r(void) -{ - return 0x0040800cU; -} -static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_scc_pagepool_r(void) -{ - return 0x00408010U; -} -static inline u32 gr_scc_pagepool_total_pages_f(u32 v) -{ - return (v & 0x3ffU) << 0U; -} -static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void) -{ - return 0x00000200U; -} -static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_s(void) -{ - return 10U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) -{ - return (v & 0x3ffU) << 10U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_m(void) -{ - return 0x3ffU << 10U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) -{ - return (r >> 10U) & 0x3ffU; -} -static inline u32 gr_scc_pagepool_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_scc_init_r(void) -{ - return 0x0040802cU; -} -static inline u32 gr_scc_init_ram_trigger_f(void) -{ - return 0x1U; -} -static inline u32 gr_scc_hww_esr_r(void) -{ - return 0x00408030U; -} -static inline u32 gr_scc_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_scc_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_sked_hww_esr_r(void) -{ - return 0x00407020U; -} -static inline u32 gr_sked_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_cwd_fs_r(void) -{ - return 0x00405b00U; -} -static inline u32 gr_cwd_fs_num_gpcs_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_cwd_fs_num_tpcs_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_cwd_gpc_tpc_id_r(u32 i) -{ - return 0x00405b60U + i*4U; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void) -{ - return 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void) -{ - return 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_cwd_sm_id_r(u32 i) -{ - return 0x00405ba0U + i*4U; -} -static inline u32 gr_cwd_sm_id__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_cwd_sm_id_tpc1_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpc0_fs_gpc_r(void) -{ - return 0x00502608U; -} -static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -static inline u32 gr_gpc0_cfg_r(void) -{ - return 0x00502620U; -} -static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpccs_rc_lanes_r(void) -{ - return 0x00502880U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_gpccs_rc_lane_size_r(void) -{ - return 0x00502910U; -} -static inline u32 gr_gpccs_rc_lane_size_v_s(void) -{ - return 24U; -} -static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_gpccs_rc_lane_size_v_m(void) -{ - return 0xffffffU << 0U; -} -static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_zcull_fs_r(void) -{ - return 0x00500910U; -} -static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 gr_gpc0_zcull_ram_addr_r(void) -{ - return 0x00500914U; -} -static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void) -{ - return 0x00500918U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void) -{ - return 0x00800000U; -} -static inline u32 gr_gpc0_zcull_total_ram_size_r(void) -{ - return 0x00500920U; -} -static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_zcull_zcsize_r(u32 i) -{ - return 0x00500a04U + i*32U; -} -static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void) -{ - return 0x00000040U; -} -static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i) -{ - return 0x00500c10U + i*4U; -} -static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i) -{ - return 0x00500c30U + i*4U; -} -static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void) -{ - return 0x00504088U; -} -static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) -{ - return 0x00504698U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_r(void) -{ - return 0x0050469cU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r) -{ - return (r >> 8U) & 0xfffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r) -{ - return (r >> 20U) & 0xfffU; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) -{ - return 0x00503018U; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void) -{ - return 0x005030c0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) -{ - return 0x3fffffU << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) -{ - return 0x00030000U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) -{ - return 0x00030a00U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void) -{ - return 0x005030f4U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void) -{ - return 0x005030e4U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void) -{ - return 0x00000800U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) -{ - return 0x005030f8U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void) -{ - return 0x005030f0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) -{ - return 0x00030000U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) -{ - return 0x00419b00U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void) -{ - return 0x00419b04U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void) -{ - return 21U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v) -{ - return (v & 0x1fffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void) -{ - return 0x1fffffU << 0U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r) -{ - return (r >> 0U) & 0x1fffffU; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void) -{ - return 0x80U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void) -{ - return 1U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpcs_tpcs_tex_m_dbg2_r(void) -{ - return 0x00419a3cU; -} -static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_gpccs_falcon_addr_r(void) -{ - return 0x0041a0acU; -} -static inline u32 gr_gpccs_falcon_addr_lsb_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpccs_falcon_addr_msb_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v) -{ - return (v & 0x3fU) << 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_m(void) -{ - return 0x3fU << 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r) -{ - return (r >> 6U) & 0x3fU; -} -static inline u32 gr_gpccs_falcon_addr_msb_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_falcon_addr_msb_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_s(void) -{ - return 12U; -} -static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_m(void) -{ - return 0xfffU << 0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 gr_gpccs_cpuctl_r(void) -{ - return 0x0041a100U; -} -static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_gpccs_dmactl_r(void) -{ - return 0x0041a10cU; -} -static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_gpccs_imemc_r(u32 i) -{ - return 0x0041a180U + i*16U; -} -static inline u32 gr_gpccs_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_gpccs_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpccs_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_gpccs_imemd_r(u32 i) -{ - return 0x0041a184U + i*16U; -} -static inline u32 gr_gpccs_imemt_r(u32 i) -{ - return 0x0041a188U + i*16U; -} -static inline u32 gr_gpccs_imemt__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_gpccs_imemt_tag_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpccs_dmemc_r(u32 i) -{ - return 0x0041a1c0U + i*8U; -} -static inline u32 gr_gpccs_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_gpccs_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpccs_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_gpccs_dmemd_r(u32 i) -{ - return 0x0041a1c4U + i*8U; -} -static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i) -{ - return 0x0041a800U + i*4U; -} -static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void) -{ - return 0x00418e24U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void) -{ - return 32U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void) -{ - return 0x00418e28U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void) -{ - return 11U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7ffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void) -{ - return 0x7ffU << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) -{ - return (r >> 0U) & 0x7ffU; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) -{ - return 0x00000018U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) -{ - return 0x18U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) -{ - return 1U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void) -{ - return 0x00500ee4U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void) -{ - return 0x00000250U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void) -{ - return 0x00500ee0U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void) -{ - return 0x00418eecU; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void) -{ - return 0x0041befcU; -} -static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) -{ - return 0x00418ea0U + i*4U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) -{ - return 0x3fffffU << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i) -{ - return 0x00418010U + i*4U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i) -{ - return 0x0041804cU + i*4U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i) -{ - return 0x00418088U + i*4U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i) -{ - return 0x004180c4U + i*4U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void) -{ - return 0x00500100U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i) -{ - return 0x00418110U + i*4U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void) -{ - return 0x0050014cU; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) -{ - return 0x00418810U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void) -{ - return 0x0000000cU; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_crstr_gpc_map0_r(void) -{ - return 0x00418b08U; -} -static inline u32 gr_crstr_gpc_map0_tile0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map0_tile1_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map0_tile2_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map0_tile3_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map0_tile4_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map0_tile5_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map1_r(void) -{ - return 0x00418b0cU; -} -static inline u32 gr_crstr_gpc_map1_tile6_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map1_tile7_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map1_tile8_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map1_tile9_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map1_tile10_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map1_tile11_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map2_r(void) -{ - return 0x00418b10U; -} -static inline u32 gr_crstr_gpc_map2_tile12_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map2_tile13_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map2_tile14_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map2_tile15_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map2_tile16_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map2_tile17_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map3_r(void) -{ - return 0x00418b14U; -} -static inline u32 gr_crstr_gpc_map3_tile18_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map3_tile19_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map3_tile20_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map3_tile21_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map3_tile22_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map3_tile23_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map4_r(void) -{ - return 0x00418b18U; -} -static inline u32 gr_crstr_gpc_map4_tile24_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map4_tile25_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map4_tile26_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map4_tile27_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map4_tile28_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map4_tile29_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map5_r(void) -{ - return 0x00418b1cU; -} -static inline u32 gr_crstr_gpc_map5_tile30_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map5_tile31_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map5_tile32_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map5_tile33_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map5_tile34_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map5_tile35_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_map_table_cfg_r(void) -{ - return 0x00418bb8U; -} -static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_r(void) -{ - return 0x00418980U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_r(void) -{ - return 0x00418984U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_r(void) -{ - return 0x00418988U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s(void) -{ - return 3U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void) -{ - return 0x7U << 28U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r) -{ - return (r >> 28U) & 0x7U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_r(void) -{ - return 0x0041898cU; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_gpm_pd_cfg_r(void) -{ - return 0x00418c6cU; -} -static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpcs_gcc_pagepool_base_r(void) -{ - return 0x00419004U; -} -static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_gcc_pagepool_r(void) -{ - return 0x00419008U; -} -static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v) -{ - return (v & 0x3ffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_pe_vaf_r(void) -{ - return 0x0041980cU; -} -static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void) -{ - return 0x00419848U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) -{ - return 0x00419c00U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void) -{ - return 0x00419c2cU; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void) -{ - return 0x00419e44U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f(void) -{ - return 0x80U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) -{ - return 0x200U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f(void) -{ - return 0x400U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) -{ - return 0x800U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f(void) -{ - return 0x1000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f(void) -{ - return 0x2000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f(void) -{ - return 0x4000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f(void) -{ - return 0x8000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) -{ - return 0x10000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f(void) -{ - return 0x20000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) -{ - return 0x40000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_mmu_fault_report_f(void) -{ - return 0x800000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_overflow_report_f(void) -{ - return 0x400000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f(void) -{ - return 0x80000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(void) -{ - return 0x100000U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_report_mask_r(void) -{ - return 0x00504644U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void) -{ - return 0x00419e4cU; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_sec_error_report_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_ded_error_report_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_report_mask_r(void) -{ - return 0x0050464cU; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) -{ - return 0x00419d0cU; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) -{ - return 0x0050450cU; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) -{ - return 0x0041ac94U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) -{ - return 0x00502c90U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) -{ - return 0x00504508U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void) -{ - return 0x00504610U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_warp_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_sm_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void) -{ - return 0x00504614U; -} -static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_1_r(void) -{ - return 0x00504618U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void) -{ - return 0x00504624U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_1_r(void) -{ - return 0x00504628U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void) -{ - return 0x00504634U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_1_r(void) -{ - return 0x00504638U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void) -{ - return 0x00419e24U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) -{ - return 0x0050460cU; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void) -{ - return 0x00419e50U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void) -{ - return 0x00504650U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_sec_error_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_ded_error_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void) -{ - return 0x00504224U; -} -static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_sec_pending_f(void) -{ - return 0x80U; -} -static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void) -{ - return 0x00504648U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m(void) -{ - return 0x1U << 24U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(void) -{ - return 0x7U << 25U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_none_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_pc_r(void) -{ - return 0x00504654U; -} -static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) -{ - return 0x00504770U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) -{ - return 0x00419f70U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) -{ - return 0x0050477cU; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) -{ - return 0x00419f7cU; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) -{ - return 0x0041be08U; -} -static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) -{ - return 0x4U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map0_r(void) -{ - return 0x0041bf00U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map1_r(void) -{ - return 0x0041bf04U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map2_r(void) -{ - return 0x0041bf08U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map3_r(void) -{ - return 0x0041bf0cU; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map4_r(void) -{ - return 0x0041bf10U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map5_r(void) -{ - return 0x0041bf14U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) -{ - return 0x0041bfd0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) -{ - return (v & 0x7U) << 21U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 24U; -} -static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) -{ - return 0x0041bfd4U; -} -static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_r(void) -{ - return 0x0041bfe4U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 5U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 10U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 15U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 20U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 25U; -} -static inline u32 gr_bes_zrop_settings_r(void) -{ - return 0x00408850U; -} -static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_be0_crop_debug3_r(void) -{ - return 0x00410108U; -} -static inline u32 gr_bes_crop_debug3_r(void) -{ - return 0x00408908U; -} -static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_bes_crop_debug3_blendopt_fill_override_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_bes_crop_debug3_blendopt_fill_override_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_bes_crop_debug3_blendopt_fill_override_enabled_f(void) -{ - return 0x4U; -} -static inline u32 gr_bes_crop_debug4_r(void) -{ - return 0x0040894cU; -} -static inline u32 gr_bes_crop_debug4_clamp_fp_blend_m(void) -{ - return 0x1U << 18U; -} -static inline u32 gr_bes_crop_debug4_clamp_fp_blend_to_inf_f(void) -{ - return 0x0U; -} -static inline u32 gr_bes_crop_debug4_clamp_fp_blend_to_maxval_f(void) -{ - return 0x40000U; -} -static inline u32 gr_bes_crop_settings_r(void) -{ - return 0x00408958U; -} -static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void) -{ - return 0x000000c0U; -} -static inline u32 gr_zcull_subregion_qty_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void) -{ - return 0x00504604U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void) -{ - return 0x00504608U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void) -{ - return 0x0050465cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void) -{ - return 0x00504660U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void) -{ - return 0x00504664U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void) -{ - return 0x00504668U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void) -{ - return 0x0050466cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void) -{ - return 0x00504658U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void) -{ - return 0x00504730U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void) -{ - return 0x00504734U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void) -{ - return 0x00504738U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void) -{ - return 0x0050473cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void) -{ - return 0x00504740U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void) -{ - return 0x00504744U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void) -{ - return 0x00504748U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void) -{ - return 0x0050474cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_s1_r(void) -{ - return 0x00504678U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r(void) -{ - return 0x00504694U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s0_r(void) -{ - return 0x005046f0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s1_r(void) -{ - return 0x00504700U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s0_r(void) -{ - return 0x005046f4U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s1_r(void) -{ - return 0x00504704U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s0_r(void) -{ - return 0x005046f8U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s1_r(void) -{ - return 0x00504708U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s0_r(void) -{ - return 0x005046fcU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s1_r(void) -{ - return 0x0050470cU; -} -static inline u32 gr_fe_pwr_mode_r(void) -{ - return 0x00404170U; -} -static inline u32 gr_fe_pwr_mode_mode_auto_f(void) -{ - return 0x0U; -} -static inline u32 gr_fe_pwr_mode_mode_force_on_f(void) -{ - return 0x2U; -} -static inline u32 gr_fe_pwr_mode_req_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 gr_fe_pwr_mode_req_send_f(void) -{ - return 0x10U; -} -static inline u32 gr_fe_pwr_mode_req_done_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) -{ - return 0x00418880U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void) -{ - return 0x1U << 11U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void) -{ - return 0x3U << 3U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void) -{ - return 0x3U << 5U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void) -{ - return 0x3U << 28U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void) -{ - return 0x1U << 30U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) -{ - return 0x00418890U; -} -static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void) -{ - return 0x00418894U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) -{ - return 0x004188b0U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) -{ - return 0x004188b4U; -} -static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void) -{ - return 0x004188b8U; -} -static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) -{ - return 0x004188acU; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void) -{ - return 0x00419e10U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(void) -{ - return 0x1U << 3U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) -{ - return 0x1U << 30U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_fe_gfxp_wfi_timeout_r(void) -{ - return 0x004041c0U; -} -static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_debug_2_r(void) -{ - return 0x00400088U; -} -static inline u32 gr_debug_2_gfxp_wfi_always_injects_wfi_m(void) -{ - return 0x1U << 23U; -} -static inline u32 gr_debug_2_gfxp_wfi_always_injects_wfi_v(u32 r) -{ - return (r >> 23U) & 0x1U; -} -static inline u32 gr_debug_2_gfxp_wfi_always_injects_wfi_enabled_f(void) -{ - return 0x800000U; -} -static inline u32 gr_debug_2_gfxp_wfi_always_injects_wfi_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void) -{ - return 0x00419c84U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void) -{ - return 0x7U << 8U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void) -{ - return 0x00419f78U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void) -{ - return 0x3U << 11U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void) -{ - return 0x1000U; -} -static inline u32 gr_gpcs_tc_debug0_r(void) -{ - return 0x00418708U; -} -static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) -{ - return 0xffU << 0U; -} -static inline u32 gr_gpc0_prop_debug1_r(void) -{ - return 0x00500400U; -} -static inline u32 gr_gpc0_prop_debug1_czf_bypass_f(u32 v) -{ - return (v & 0x3U) << 14U; -} -static inline u32 gr_gpc0_prop_debug1_czf_bypass_m(void) -{ - return 0x3U << 14U; -} -static inline u32 gr_gpc0_prop_debug1_czf_bypass_init_v(void) -{ - return 0x00000001U; -} -#endif diff --git a/include/nvgpu/hw/gp10b/hw_ltc_gp10b.h b/include/nvgpu/hw/gp10b/hw_ltc_gp10b.h deleted file mode 100644 index 721a48a..0000000 --- a/include/nvgpu/hw/gp10b/hw_ltc_gp10b.h +++ /dev/null @@ -1,587 +0,0 @@ -/* - * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ltc_gp10b_h_ -#define _hw_ltc_gp10b_h_ - -static inline u32 ltc_pltcg_base_v(void) -{ - return 0x00140000U; -} -static inline u32 ltc_pltcg_extent_v(void) -{ - return 0x0017ffffU; -} -static inline u32 ltc_ltc0_ltss_v(void) -{ - return 0x00140200U; -} -static inline u32 ltc_ltc0_lts0_v(void) -{ - return 0x00140400U; -} -static inline u32 ltc_ltcs_ltss_v(void) -{ - return 0x0017e200U; -} -static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) -{ - return 0x0014046cU; -} -static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) -{ - return 0x00140518U; -} -static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) -{ - return 0x0017e318U; -} -static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void) -{ - return 0x1U << 15U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) -{ - return 0x00140494U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) -{ - return (r >> 16U) & 0x3U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) -{ - return 0x00000000U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) -{ - return 0x00000002U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) -{ - return 0x0017e26cU; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) -{ - return 0x2U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) -{ - return 0x4U; -} -static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) -{ - return 0x0014046cU; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) -{ - return 0x0017e270U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) -{ - return (v & 0x3ffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) -{ - return 0x0017e274U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) -{ - return (v & 0x3ffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) -{ - return 0x0003ffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_base_r(void) -{ - return 0x0017e278U; -} -static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) -{ - return 0x0000000bU; -} -static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) -{ - return (r >> 0U) & 0x3ffffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) -{ - return 0x0017e27cU; -} -static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) -{ - return 0x0017e000U; -} -static inline u32 ltc_ltcs_ltss_cbc_param_r(void) -{ - return 0x0017e280U; -} -static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r) -{ - return (r >> 24U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r) -{ - return (r >> 28U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_cbc_param2_r(void) -{ - return 0x0017e3f4U; -} -static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) -{ - return 0x0017e2acU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) -{ - return 0x0017e338U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) -{ - return 0x0017e33cU + i*4U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) -{ - return 0x0017e34cU; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) -{ - return 32U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) -{ - return 0x0017e2b0U; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_r(void) -{ - return 0x0017e214U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_r(void) -{ - return 0x00140214U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc1_ltss_g_elpg_r(void) -{ - return 0x00142214U; -} -static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_intr_r(void) -{ - return 0x0017e20cU; -} -static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void) -{ - return 0x100U; -} -static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void) -{ - return 0x200U; -} -static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) -{ - return 0x1U << 20U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) -{ - return 0x1U << 30U; -} -static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void) -{ - return 0x1000000U; -} -static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void) -{ - return 0x2000000U; -} -static inline u32 ltc_ltc0_lts0_intr_r(void) -{ - return 0x0014040cU; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void) -{ - return 0x0014051cU; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void) -{ - return 0xffU << 0U; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void) -{ - return 0xffU << 16U; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) -{ - return 0x0017e2a0U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) -{ - return 0x300U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) -{ - return 0x20000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) -{ - return 0x40000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) -{ - return 0x0017e2a4U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) -{ - return 0x300U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) -{ - return 0x10000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) -{ - return 0x20000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) -{ - return 0x40000000U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) -{ - return 0x001402a0U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) -{ - return 0x001402a4U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void) -{ - return 0x001422a0U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void) -{ - return 0x001422a4U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void) -{ - return 0x0014058cU; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -static inline u32 ltc_ltca_g_axi_pctrl_r(void) -{ - return 0x00160000U; -} -static inline u32 ltc_ltca_g_axi_pctrl_user_sid_f(u32 v) -{ - return (v & 0xffU) << 2U; -} -#endif diff --git a/include/nvgpu/hw/gp10b/hw_mc_gp10b.h b/include/nvgpu/hw/gp10b/hw_mc_gp10b.h deleted file mode 100644 index 39c132a..0000000 --- a/include/nvgpu/hw/gp10b/hw_mc_gp10b.h +++ /dev/null @@ -1,255 +0,0 @@ -/* - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_mc_gp10b_h_ -#define _hw_mc_gp10b_h_ - -static inline u32 mc_boot_0_r(void) -{ - return 0x00000000U; -} -static inline u32 mc_boot_0_architecture_v(u32 r) -{ - return (r >> 24U) & 0x1fU; -} -static inline u32 mc_boot_0_implementation_v(u32 r) -{ - return (r >> 20U) & 0xfU; -} -static inline u32 mc_boot_0_major_revision_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 mc_boot_0_minor_revision_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 mc_intr_r(u32 i) -{ - return 0x00000100U + i*4U; -} -static inline u32 mc_intr_pfifo_pending_f(void) -{ - return 0x100U; -} -static inline u32 mc_intr_replayable_fault_pending_f(void) -{ - return 0x200U; -} -static inline u32 mc_intr_pfb_pending_f(void) -{ - return 0x2000U; -} -static inline u32 mc_intr_pgraph_pending_f(void) -{ - return 0x1000U; -} -static inline u32 mc_intr_pmu_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 mc_intr_ltc_pending_f(void) -{ - return 0x2000000U; -} -static inline u32 mc_intr_priv_ring_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 mc_intr_pbus_pending_f(void) -{ - return 0x10000000U; -} -static inline u32 mc_intr_en_r(u32 i) -{ - return 0x00000140U + i*4U; -} -static inline u32 mc_intr_en_set_r(u32 i) -{ - return 0x00000160U + i*4U; -} -static inline u32 mc_intr_en_clear_r(u32 i) -{ - return 0x00000180U + i*4U; -} -static inline u32 mc_enable_r(void) -{ - return 0x00000200U; -} -static inline u32 mc_enable_xbar_enabled_f(void) -{ - return 0x4U; -} -static inline u32 mc_enable_l2_enabled_f(void) -{ - return 0x8U; -} -static inline u32 mc_enable_pmedia_s(void) -{ - return 1U; -} -static inline u32 mc_enable_pmedia_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 mc_enable_pmedia_m(void) -{ - return 0x1U << 4U; -} -static inline u32 mc_enable_pmedia_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 mc_enable_priv_ring_enabled_f(void) -{ - return 0x20U; -} -static inline u32 mc_enable_ce0_m(void) -{ - return 0x1U << 6U; -} -static inline u32 mc_enable_pfifo_enabled_f(void) -{ - return 0x100U; -} -static inline u32 mc_enable_pgraph_enabled_f(void) -{ - return 0x1000U; -} -static inline u32 mc_enable_pwr_v(u32 r) -{ - return (r >> 13U) & 0x1U; -} -static inline u32 mc_enable_pwr_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 mc_enable_pwr_enabled_f(void) -{ - return 0x2000U; -} -static inline u32 mc_enable_pfb_enabled_f(void) -{ - return 0x100000U; -} -static inline u32 mc_enable_ce2_m(void) -{ - return 0x1U << 21U; -} -static inline u32 mc_enable_ce2_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 mc_enable_blg_enabled_f(void) -{ - return 0x8000000U; -} -static inline u32 mc_enable_perfmon_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 mc_enable_hub_enabled_f(void) -{ - return 0x20000000U; -} -static inline u32 mc_intr_ltc_r(void) -{ - return 0x000001c0U; -} -static inline u32 mc_enable_pb_r(void) -{ - return 0x00000204U; -} -static inline u32 mc_enable_pb_0_s(void) -{ - return 1U; -} -static inline u32 mc_enable_pb_0_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 mc_enable_pb_0_m(void) -{ - return 0x1U << 0U; -} -static inline u32 mc_enable_pb_0_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 mc_enable_pb_0_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 mc_enable_pb_sel_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 mc_elpg_enable_r(void) -{ - return 0x0000020cU; -} -static inline u32 mc_elpg_enable_xbar_enabled_f(void) -{ - return 0x4U; -} -static inline u32 mc_elpg_enable_pfb_enabled_f(void) -{ - return 0x100000U; -} -static inline u32 mc_elpg_enable_hub_enabled_f(void) -{ - return 0x20000000U; -} -#endif diff --git a/include/nvgpu/hw/gp10b/hw_pbdma_gp10b.h b/include/nvgpu/hw/gp10b/hw_pbdma_gp10b.h deleted file mode 100644 index 66e8ddb..0000000 --- a/include/nvgpu/hw/gp10b/hw_pbdma_gp10b.h +++ /dev/null @@ -1,615 +0,0 @@ -/* - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pbdma_gp10b_h_ -#define _hw_pbdma_gp10b_h_ - -static inline u32 pbdma_gp_entry1_r(void) -{ - return 0x10000004U; -} -static inline u32 pbdma_gp_entry1_get_hi_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pbdma_gp_entry1_length_f(u32 v) -{ - return (v & 0x1fffffU) << 10U; -} -static inline u32 pbdma_gp_entry1_length_v(u32 r) -{ - return (r >> 10U) & 0x1fffffU; -} -static inline u32 pbdma_gp_base_r(u32 i) -{ - return 0x00040048U + i*8192U; -} -static inline u32 pbdma_gp_base__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 pbdma_gp_base_offset_f(u32 v) -{ - return (v & 0x1fffffffU) << 3U; -} -static inline u32 pbdma_gp_base_rsvd_s(void) -{ - return 3U; -} -static inline u32 pbdma_gp_base_hi_r(u32 i) -{ - return 0x0004004cU + i*8192U; -} -static inline u32 pbdma_gp_base_hi_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pbdma_gp_base_hi_limit2_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 pbdma_gp_fetch_r(u32 i) -{ - return 0x00040050U + i*8192U; -} -static inline u32 pbdma_gp_get_r(u32 i) -{ - return 0x00040014U + i*8192U; -} -static inline u32 pbdma_gp_put_r(u32 i) -{ - return 0x00040000U + i*8192U; -} -static inline u32 pbdma_pb_fetch_r(u32 i) -{ - return 0x00040054U + i*8192U; -} -static inline u32 pbdma_pb_fetch_hi_r(u32 i) -{ - return 0x00040058U + i*8192U; -} -static inline u32 pbdma_get_r(u32 i) -{ - return 0x00040018U + i*8192U; -} -static inline u32 pbdma_get_hi_r(u32 i) -{ - return 0x0004001cU + i*8192U; -} -static inline u32 pbdma_put_r(u32 i) -{ - return 0x0004005cU + i*8192U; -} -static inline u32 pbdma_put_hi_r(u32 i) -{ - return 0x00040060U + i*8192U; -} -static inline u32 pbdma_formats_r(u32 i) -{ - return 0x0004009cU + i*8192U; -} -static inline u32 pbdma_formats_gp_fermi0_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_formats_pb_fermi1_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_formats_mp_fermi0_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_r(u32 i) -{ - return 0x00040084U + i*8192U; -} -static inline u32 pbdma_pb_header_priv_user_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_method_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_subchannel_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_level_main_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_first_true_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_pb_header_type_inc_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_pb_header_type_non_inc_f(void) -{ - return 0x60000000U; -} -static inline u32 pbdma_hdr_shadow_r(u32 i) -{ - return 0x00040118U + i*8192U; -} -static inline u32 pbdma_gp_shadow_0_r(u32 i) -{ - return 0x00040110U + i*8192U; -} -static inline u32 pbdma_gp_shadow_1_r(u32 i) -{ - return 0x00040114U + i*8192U; -} -static inline u32 pbdma_subdevice_r(u32 i) -{ - return 0x00040094U + i*8192U; -} -static inline u32 pbdma_subdevice_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 pbdma_subdevice_status_active_f(void) -{ - return 0x10000000U; -} -static inline u32 pbdma_subdevice_channel_dma_enable_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_method0_r(u32 i) -{ - return 0x000400c0U + i*8192U; -} -static inline u32 pbdma_method0_fifo_size_v(void) -{ - return 0x00000004U; -} -static inline u32 pbdma_method0_addr_f(u32 v) -{ - return (v & 0xfffU) << 2U; -} -static inline u32 pbdma_method0_addr_v(u32 r) -{ - return (r >> 2U) & 0xfffU; -} -static inline u32 pbdma_method0_subch_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 pbdma_method0_first_true_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_method0_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_method1_r(u32 i) -{ - return 0x000400c8U + i*8192U; -} -static inline u32 pbdma_method2_r(u32 i) -{ - return 0x000400d0U + i*8192U; -} -static inline u32 pbdma_method3_r(u32 i) -{ - return 0x000400d8U + i*8192U; -} -static inline u32 pbdma_data0_r(u32 i) -{ - return 0x000400c4U + i*8192U; -} -static inline u32 pbdma_target_r(u32 i) -{ - return 0x000400acU + i*8192U; -} -static inline u32 pbdma_target_engine_sw_f(void) -{ - return 0x1fU; -} -static inline u32 pbdma_acquire_r(u32 i) -{ - return 0x00040030U + i*8192U; -} -static inline u32 pbdma_acquire_retry_man_2_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_acquire_retry_exp_2_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_acquire_timeout_exp_f(u32 v) -{ - return (v & 0xfU) << 11U; -} -static inline u32 pbdma_acquire_timeout_exp_max_v(void) -{ - return 0x0000000fU; -} -static inline u32 pbdma_acquire_timeout_exp_max_f(void) -{ - return 0x7800U; -} -static inline u32 pbdma_acquire_timeout_man_f(u32 v) -{ - return (v & 0xffffU) << 15U; -} -static inline u32 pbdma_acquire_timeout_man_max_v(void) -{ - return 0x0000ffffU; -} -static inline u32 pbdma_acquire_timeout_man_max_f(void) -{ - return 0x7fff8000U; -} -static inline u32 pbdma_acquire_timeout_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_acquire_timeout_en_disable_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_status_r(u32 i) -{ - return 0x00040100U + i*8192U; -} -static inline u32 pbdma_channel_r(u32 i) -{ - return 0x00040120U + i*8192U; -} -static inline u32 pbdma_signature_r(u32 i) -{ - return 0x00040010U + i*8192U; -} -static inline u32 pbdma_signature_hw_valid_f(void) -{ - return 0xfaceU; -} -static inline u32 pbdma_signature_sw_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_userd_r(u32 i) -{ - return 0x00040008U + i*8192U; -} -static inline u32 pbdma_userd_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_userd_target_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 pbdma_userd_addr_f(u32 v) -{ - return (v & 0x7fffffU) << 9U; -} -static inline u32 pbdma_userd_hi_r(u32 i) -{ - return 0x0004000cU + i*8192U; -} -static inline u32 pbdma_userd_hi_addr_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pbdma_config_r(u32 i) -{ - return 0x000400f4U + i*8192U; -} -static inline u32 pbdma_config_auth_level_privileged_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_hce_ctrl_r(u32 i) -{ - return 0x000400e4U + i*8192U; -} -static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void) -{ - return 0x20U; -} -static inline u32 pbdma_intr_0_r(u32 i) -{ - return 0x00040108U + i*8192U; -} -static inline u32 pbdma_intr_0_memreq_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pbdma_intr_0_memreq_pending_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_intr_0_memack_timeout_pending_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_intr_0_memack_extra_pending_f(void) -{ - return 0x4U; -} -static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void) -{ - return 0x8U; -} -static inline u32 pbdma_intr_0_memdat_extra_pending_f(void) -{ - return 0x10U; -} -static inline u32 pbdma_intr_0_memflush_pending_f(void) -{ - return 0x20U; -} -static inline u32 pbdma_intr_0_memop_pending_f(void) -{ - return 0x40U; -} -static inline u32 pbdma_intr_0_lbconnect_pending_f(void) -{ - return 0x80U; -} -static inline u32 pbdma_intr_0_lbreq_pending_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_0_lback_timeout_pending_f(void) -{ - return 0x200U; -} -static inline u32 pbdma_intr_0_lback_extra_pending_f(void) -{ - return 0x400U; -} -static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void) -{ - return 0x800U; -} -static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void) -{ - return 0x1000U; -} -static inline u32 pbdma_intr_0_gpfifo_pending_f(void) -{ - return 0x2000U; -} -static inline u32 pbdma_intr_0_gpptr_pending_f(void) -{ - return 0x4000U; -} -static inline u32 pbdma_intr_0_gpentry_pending_f(void) -{ - return 0x8000U; -} -static inline u32 pbdma_intr_0_gpcrc_pending_f(void) -{ - return 0x10000U; -} -static inline u32 pbdma_intr_0_pbptr_pending_f(void) -{ - return 0x20000U; -} -static inline u32 pbdma_intr_0_pbentry_pending_f(void) -{ - return 0x40000U; -} -static inline u32 pbdma_intr_0_pbcrc_pending_f(void) -{ - return 0x80000U; -} -static inline u32 pbdma_intr_0_xbarconnect_pending_f(void) -{ - return 0x100000U; -} -static inline u32 pbdma_intr_0_method_pending_f(void) -{ - return 0x200000U; -} -static inline u32 pbdma_intr_0_methodcrc_pending_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_intr_0_device_pending_f(void) -{ - return 0x800000U; -} -static inline u32 pbdma_intr_0_semaphore_pending_f(void) -{ - return 0x2000000U; -} -static inline u32 pbdma_intr_0_acquire_pending_f(void) -{ - return 0x4000000U; -} -static inline u32 pbdma_intr_0_pri_pending_f(void) -{ - return 0x8000000U; -} -static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_intr_0_pbseg_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 pbdma_intr_0_signature_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_intr_0_syncpoint_illegal_pending_f(void) -{ - return 0x10000000U; -} -static inline u32 pbdma_intr_1_r(u32 i) -{ - return 0x00040148U + i*8192U; -} -static inline u32 pbdma_intr_en_0_r(u32 i) -{ - return 0x0004010cU + i*8192U; -} -static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_en_1_r(u32 i) -{ - return 0x0004014cU + i*8192U; -} -static inline u32 pbdma_intr_stall_r(u32 i) -{ - return 0x0004013cU + i*8192U; -} -static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_stall_1_r(u32 i) -{ - return 0x00040140U + i*8192U; -} -static inline u32 pbdma_intr_stall_1_hce_illegal_op_enabled_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_udma_nop_r(void) -{ - return 0x00000008U; -} -static inline u32 pbdma_allowed_syncpoints_r(u32 i) -{ - return 0x000400e8U + i*8192U; -} -static inline u32 pbdma_allowed_syncpoints_0_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 pbdma_allowed_syncpoints_0_index_f(u32 v) -{ - return (v & 0x7fffU) << 16U; -} -static inline u32 pbdma_allowed_syncpoints_0_index_v(u32 r) -{ - return (r >> 16U) & 0x7fffU; -} -static inline u32 pbdma_allowed_syncpoints_1_valid_f(u32 v) -{ - return (v & 0x1U) << 15U; -} -static inline u32 pbdma_allowed_syncpoints_1_index_f(u32 v) -{ - return (v & 0x7fffU) << 0U; -} -static inline u32 pbdma_syncpointa_r(u32 i) -{ - return 0x000400a4U + i*8192U; -} -static inline u32 pbdma_syncpointa_payload_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pbdma_syncpointb_r(u32 i) -{ - return 0x000400a8U + i*8192U; -} -static inline u32 pbdma_syncpointb_op_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pbdma_syncpointb_op_wait_v(void) -{ - return 0x00000000U; -} -static inline u32 pbdma_syncpointb_wait_switch_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 pbdma_syncpointb_wait_switch_en_v(void) -{ - return 0x00000001U; -} -static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r) -{ - return (r >> 8U) & 0xfffU; -} -static inline u32 pbdma_runlist_timeslice_r(u32 i) -{ - return 0x000400f8U + i*8192U; -} -static inline u32 pbdma_runlist_timeslice_timeout_128_f(void) -{ - return 0x80U; -} -static inline u32 pbdma_runlist_timeslice_timescale_3_f(void) -{ - return 0x3000U; -} -static inline u32 pbdma_runlist_timeslice_enable_true_f(void) -{ - return 0x10000000U; -} -#endif diff --git a/include/nvgpu/hw/gp10b/hw_perf_gp10b.h b/include/nvgpu/hw/gp10b/hw_perf_gp10b.h deleted file mode 100644 index 43424e1..0000000 --- a/include/nvgpu/hw/gp10b/hw_perf_gp10b.h +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_perf_gp10b_h_ -#define _hw_perf_gp10b_h_ - -static inline u32 perf_pmmsys_base_v(void) -{ - return 0x001b0000U; -} -static inline u32 perf_pmmsys_extent_v(void) -{ - return 0x001b0fffU; -} -static inline u32 perf_pmasys_control_r(void) -{ - return 0x001b4000U; -} -static inline u32 perf_pmasys_control_membuf_status_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void) -{ - return 0x10U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) -{ - return 0x20U; -} -static inline u32 perf_pmasys_mem_block_r(void) -{ - return 0x001b4070U; -} -static inline u32 perf_pmasys_mem_block_base_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 perf_pmasys_mem_block_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 perf_pmasys_mem_block_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 perf_pmasys_mem_block_target_lfb_v(void) -{ - return 0x00000000U; -} -static inline u32 perf_pmasys_mem_block_target_lfb_f(void) -{ - return 0x0U; -} -static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 perf_pmasys_mem_block_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 perf_pmasys_mem_block_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 perf_pmasys_mem_block_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_mem_block_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 perf_pmasys_mem_block_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 perf_pmasys_mem_block_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 perf_pmasys_outbase_r(void) -{ - return 0x001b4074U; -} -static inline u32 perf_pmasys_outbase_ptr_f(u32 v) -{ - return (v & 0x7ffffffU) << 5U; -} -static inline u32 perf_pmasys_outbaseupper_r(void) -{ - return 0x001b4078U; -} -static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 perf_pmasys_outsize_r(void) -{ - return 0x001b407cU; -} -static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) -{ - return (v & 0x7ffffffU) << 5U; -} -static inline u32 perf_pmasys_mem_bytes_r(void) -{ - return 0x001b4084U; -} -static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 perf_pmasys_mem_bump_r(void) -{ - return 0x001b4088U; -} -static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 perf_pmasys_enginestatus_r(void) -{ - return 0x001b40a4U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void) -{ - return 0x10U; -} -#endif diff --git a/include/nvgpu/hw/gp10b/hw_pram_gp10b.h b/include/nvgpu/hw/gp10b/hw_pram_gp10b.h deleted file mode 100644 index aef0e69..0000000 --- a/include/nvgpu/hw/gp10b/hw_pram_gp10b.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pram_gp10b_h_ -#define _hw_pram_gp10b_h_ - -static inline u32 pram_data032_r(u32 i) -{ - return 0x00700000U + i*4U; -} -#endif diff --git a/include/nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h b/include/nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h deleted file mode 100644 index 03a3854..0000000 --- a/include/nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pri_ringmaster_gp10b_h_ -#define _hw_pri_ringmaster_gp10b_h_ - -static inline u32 pri_ringmaster_command_r(void) -{ - return 0x0012004cU; -} -static inline u32 pri_ringmaster_command_cmd_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 pri_ringmaster_command_cmd_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void) -{ - return 0x00000000U; -} -static inline u32 pri_ringmaster_command_cmd_start_ring_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void) -{ - return 0x2U; -} -static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void) -{ - return 0x3U; -} -static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void) -{ - return 0x0U; -} -static inline u32 pri_ringmaster_command_data_r(void) -{ - return 0x00120048U; -} -static inline u32 pri_ringmaster_start_results_r(void) -{ - return 0x00120050U; -} -static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void) -{ - return 0x00000001U; -} -static inline u32 pri_ringmaster_intr_status0_r(void) -{ - return 0x00120058U; -} -static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status1_r(void) -{ - return 0x0012005cU; -} -static inline u32 pri_ringmaster_global_ctl_r(void) -{ - return 0x00120060U; -} -static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void) -{ - return 0x0U; -} -static inline u32 pri_ringmaster_enum_fbp_r(void) -{ - return 0x00120074U; -} -static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 pri_ringmaster_enum_gpc_r(void) -{ - return 0x00120078U; -} -static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 pri_ringmaster_enum_ltc_r(void) -{ - return 0x0012006cU; -} -static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -#endif diff --git a/include/nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h b/include/nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h deleted file mode 100644 index ba55658..0000000 --- a/include/nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pri_ringstation_gpc_gp10b_h_ -#define _hw_pri_ringstation_gpc_gp10b_h_ - -static inline u32 pri_ringstation_gpc_master_config_r(u32 i) -{ - return 0x00128300U + i*4U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void) -{ - return 0x00128120U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void) -{ - return 0x00128124U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void) -{ - return 0x00128128U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_subid_v(u32 r) -{ - return (r >> 24U) & 0x3fU; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_priv_level_v(u32 r) -{ - return (r >> 20U) & 0x3U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void) -{ - return 0x0012812cU; -} -#endif diff --git a/include/nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h b/include/nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h deleted file mode 100644 index 1dcb1a3..0000000 --- a/include/nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pri_ringstation_sys_gp10b_h_ -#define _hw_pri_ringstation_sys_gp10b_h_ - -static inline u32 pri_ringstation_sys_master_config_r(u32 i) -{ - return 0x00122300U + i*4U; -} -static inline u32 pri_ringstation_sys_decode_config_r(void) -{ - return 0x00122204U; -} -static inline u32 pri_ringstation_sys_decode_config_ring_m(void) -{ - return 0x7U << 0U; -} -static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringstation_sys_priv_error_adr_r(void) -{ - return 0x00122120U; -} -static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void) -{ - return 0x00122124U; -} -static inline u32 pri_ringstation_sys_priv_error_info_r(void) -{ - return 0x00122128U; -} -static inline u32 pri_ringstation_sys_priv_error_info_subid_v(u32 r) -{ - return (r >> 24U) & 0x3fU; -} -static inline u32 pri_ringstation_sys_priv_error_info_priv_level_v(u32 r) -{ - return (r >> 20U) & 0x3U; -} -static inline u32 pri_ringstation_sys_priv_error_code_r(void) -{ - return 0x0012212cU; -} -#endif diff --git a/include/nvgpu/hw/gp10b/hw_proj_gp10b.h b/include/nvgpu/hw/gp10b/hw_proj_gp10b.h deleted file mode 100644 index a885e93..0000000 --- a/include/nvgpu/hw/gp10b/hw_proj_gp10b.h +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_proj_gp10b_h_ -#define _hw_proj_gp10b_h_ - -static inline u32 proj_gpc_base_v(void) -{ - return 0x00500000U; -} -static inline u32 proj_gpc_shared_base_v(void) -{ - return 0x00418000U; -} -static inline u32 proj_gpc_stride_v(void) -{ - return 0x00008000U; -} -static inline u32 proj_gpc_priv_stride_v(void) -{ - return 0x00000800U; -} -static inline u32 proj_ltc_stride_v(void) -{ - return 0x00002000U; -} -static inline u32 proj_lts_stride_v(void) -{ - return 0x00000200U; -} -static inline u32 proj_fbpa_base_v(void) -{ - return 0x00900000U; -} -static inline u32 proj_fbpa_shared_base_v(void) -{ - return 0x009a0000U; -} -static inline u32 proj_fbpa_stride_v(void) -{ - return 0x00004000U; -} -static inline u32 proj_ppc_in_gpc_base_v(void) -{ - return 0x00003000U; -} -static inline u32 proj_ppc_in_gpc_shared_base_v(void) -{ - return 0x00003e00U; -} -static inline u32 proj_ppc_in_gpc_stride_v(void) -{ - return 0x00000200U; -} -static inline u32 proj_rop_base_v(void) -{ - return 0x00410000U; -} -static inline u32 proj_rop_shared_base_v(void) -{ - return 0x00408800U; -} -static inline u32 proj_rop_stride_v(void) -{ - return 0x00000400U; -} -static inline u32 proj_tpc_in_gpc_base_v(void) -{ - return 0x00004000U; -} -static inline u32 proj_tpc_in_gpc_stride_v(void) -{ - return 0x00000800U; -} -static inline u32 proj_tpc_in_gpc_shared_base_v(void) -{ - return 0x00001800U; -} -static inline u32 proj_host_num_engines_v(void) -{ - return 0x00000002U; -} -static inline u32 proj_host_num_pbdma_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) -{ - return 0x00000002U; -} -static inline u32 proj_scal_litter_num_sm_per_tpc_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_fbps_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_fbpas_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_gpcs_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) -{ - return 0x00000002U; -} -static inline u32 proj_scal_litter_num_zcull_banks_v(void) -{ - return 0x00000004U; -} -static inline u32 proj_scal_max_gpcs_v(void) -{ - return 0x00000020U; -} -static inline u32 proj_scal_max_tpc_per_gpc_v(void) -{ - return 0x00000008U; -} -#endif diff --git a/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h b/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h deleted file mode 100644 index f067be7..0000000 --- a/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h +++ /dev/null @@ -1,883 +0,0 @@ -/* - * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pwr_gp10b_h_ -#define _hw_pwr_gp10b_h_ - -static inline u32 pwr_falcon_irqsset_r(void) -{ - return 0x0010a000U; -} -static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 pwr_falcon_irqsclr_r(void) -{ - return 0x0010a004U; -} -static inline u32 pwr_falcon_irqstat_r(void) -{ - return 0x0010a008U; -} -static inline u32 pwr_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 pwr_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 pwr_falcon_irqmode_r(void) -{ - return 0x0010a00cU; -} -static inline u32 pwr_falcon_irqmset_r(void) -{ - return 0x0010a010U; -} -static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqmclr_r(void) -{ - return 0x0010a014U; -} -static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqmask_r(void) -{ - return 0x0010a018U; -} -static inline u32 pwr_falcon_irqdest_r(void) -{ - return 0x0010a01cU; -} -static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 pwr_falcon_curctx_r(void) -{ - return 0x0010a050U; -} -static inline u32 pwr_falcon_nxtctx_r(void) -{ - return 0x0010a054U; -} -static inline u32 pwr_falcon_mailbox0_r(void) -{ - return 0x0010a040U; -} -static inline u32 pwr_falcon_mailbox1_r(void) -{ - return 0x0010a044U; -} -static inline u32 pwr_falcon_itfen_r(void) -{ - return 0x0010a048U; -} -static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 pwr_falcon_idlestate_r(void) -{ - return 0x0010a04cU; -} -static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 pwr_falcon_os_r(void) -{ - return 0x0010a080U; -} -static inline u32 pwr_falcon_engctl_r(void) -{ - return 0x0010a0a4U; -} -static inline u32 pwr_falcon_cpuctl_r(void) -{ - return 0x0010a100U; -} -static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) -{ - return 0x1U << 4U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void) -{ - return 0x1U << 6U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 pwr_falcon_cpuctl_alias_r(void) -{ - return 0x0010a130U; -} -static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_pmu_scpctl_stat_r(void) -{ - return 0x0010ac08U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void) -{ - return 0x1U << 20U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 pwr_falcon_imemc_r(u32 i) -{ - return 0x0010a180U + i*16U; -} -static inline u32 pwr_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pwr_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_imemd_r(u32 i) -{ - return 0x0010a184U + i*16U; -} -static inline u32 pwr_falcon_imemt_r(u32 i) -{ - return 0x0010a188U + i*16U; -} -static inline u32 pwr_falcon_sctl_r(void) -{ - return 0x0010a240U; -} -static inline u32 pwr_falcon_mmu_phys_sec_r(void) -{ - return 0x00100ce4U; -} -static inline u32 pwr_falcon_bootvec_r(void) -{ - return 0x0010a104U; -} -static inline u32 pwr_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_falcon_dmactl_r(void) -{ - return 0x0010a10cU; -} -static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) -{ - return 0x1U << 1U; -} -static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) -{ - return 0x1U << 2U; -} -static inline u32 pwr_falcon_hwcfg_r(void) -{ - return 0x0010a108U; -} -static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 pwr_falcon_dmatrfbase_r(void) -{ - return 0x0010a110U; -} -static inline u32 pwr_falcon_dmatrfbase1_r(void) -{ - return 0x0010a128U; -} -static inline u32 pwr_falcon_dmatrfmoffs_r(void) -{ - return 0x0010a114U; -} -static inline u32 pwr_falcon_dmatrfcmd_r(void) -{ - return 0x0010a118U; -} -static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 pwr_falcon_dmatrffboffs_r(void) -{ - return 0x0010a11cU; -} -static inline u32 pwr_falcon_exterraddr_r(void) -{ - return 0x0010a168U; -} -static inline u32 pwr_falcon_exterrstat_r(void) -{ - return 0x0010a16cU; -} -static inline u32 pwr_falcon_exterrstat_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 pwr_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_r(void) -{ - return 0x0010a200U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) -{ - return 0xfU << 0U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 pwr_pmu_falcon_icd_rdata_r(void) -{ - return 0x0010a20cU; -} -static inline u32 pwr_falcon_dmemc_r(u32 i) -{ - return 0x0010a1c0U + i*8U; -} -static inline u32 pwr_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pwr_falcon_dmemc_offs_m(void) -{ - return 0x3fU << 2U; -} -static inline u32 pwr_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_dmemc_blk_m(void) -{ - return 0xffU << 8U; -} -static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 pwr_falcon_dmemd_r(u32 i) -{ - return 0x0010a1c4U + i*8U; -} -static inline u32 pwr_pmu_new_instblk_r(void) -{ - return 0x0010a480U; -} -static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 pwr_pmu_new_instblk_target_fb_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 pwr_pmu_mutex_id_r(void) -{ - return 0x0010a488U; -} -static inline u32 pwr_pmu_mutex_id_value_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pwr_pmu_mutex_id_value_init_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) -{ - return 0x000000ffU; -} -static inline u32 pwr_pmu_mutex_id_release_r(void) -{ - return 0x0010a48cU; -} -static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_id_release_value_m(void) -{ - return 0xffU << 0U; -} -static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_mutex_r(u32 i) -{ - return 0x0010a580U + i*4U; -} -static inline u32 pwr_pmu_mutex__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 pwr_pmu_mutex_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_value_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_queue_head_r(u32 i) -{ - return 0x0010a4a0U + i*4U; -} -static inline u32 pwr_pmu_queue_head__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 pwr_pmu_queue_head_address_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_queue_head_address_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_queue_tail_r(u32 i) -{ - return 0x0010a4b0U + i*4U; -} -static inline u32 pwr_pmu_queue_tail__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 pwr_pmu_queue_tail_address_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_queue_tail_address_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_msgq_head_r(void) -{ - return 0x0010a4c8U; -} -static inline u32 pwr_pmu_msgq_head_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_msgq_head_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_msgq_tail_r(void) -{ - return 0x0010a4ccU; -} -static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_idle_mask_r(u32 i) -{ - return 0x0010a504U + i*16U; -} -static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) -{ - return 0x1U; -} -static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 pwr_pmu_idle_mask_1_r(u32 i) -{ - return 0x0010aa34U + i*8U; -} -static inline u32 pwr_pmu_idle_count_r(u32 i) -{ - return 0x0010a508U + i*16U; -} -static inline u32 pwr_pmu_idle_count_value_f(u32 v) -{ - return (v & 0x7fffffffU) << 0U; -} -static inline u32 pwr_pmu_idle_count_value_v(u32 r) -{ - return (r >> 0U) & 0x7fffffffU; -} -static inline u32 pwr_pmu_idle_count_reset_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 pwr_pmu_idle_ctrl_r(u32 i) -{ - return 0x0010a50cU + i*16U; -} -static inline u32 pwr_pmu_idle_ctrl_value_m(void) -{ - return 0x3U << 0U; -} -static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) -{ - return 0x2U; -} -static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) -{ - return 0x3U; -} -static inline u32 pwr_pmu_idle_ctrl_filter_m(void) -{ - return 0x1U << 2U; -} -static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_idle_threshold_r(u32 i) -{ - return 0x0010a8a0U + i*4U; -} -static inline u32 pwr_pmu_idle_threshold_value_f(u32 v) -{ - return (v & 0x7fffffffU) << 0U; -} -static inline u32 pwr_pmu_idle_intr_r(void) -{ - return 0x0010a9e8U; -} -static inline u32 pwr_pmu_idle_intr_en_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_en_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_idle_intr_en_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_intr_status_r(void) -{ - return 0x0010a9ecU; -} -static inline u32 pwr_pmu_idle_intr_status_intr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_m(void) -{ - return 0x1U << 0U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) -{ - return 0x0010a9f0U + i*8U; -} -static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) -{ - return 0x0010a9f4U + i*8U; -} -static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) -{ - return 0x0010aa30U + i*8U; -} -static inline u32 pwr_pmu_debug_r(u32 i) -{ - return 0x0010a5c0U + i*4U; -} -static inline u32 pwr_pmu_debug__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 pwr_pmu_mailbox_r(u32 i) -{ - return 0x0010a450U + i*4U; -} -static inline u32 pwr_pmu_mailbox__size_1_v(void) -{ - return 0x0000000cU; -} -static inline u32 pwr_pmu_bar0_addr_r(void) -{ - return 0x0010a7a0U; -} -static inline u32 pwr_pmu_bar0_data_r(void) -{ - return 0x0010a7a4U; -} -static inline u32 pwr_pmu_bar0_ctl_r(void) -{ - return 0x0010a7acU; -} -static inline u32 pwr_pmu_bar0_timeout_r(void) -{ - return 0x0010a7a8U; -} -static inline u32 pwr_pmu_bar0_fecs_error_r(void) -{ - return 0x0010a988U; -} -static inline u32 pwr_pmu_bar0_error_status_r(void) -{ - return 0x0010a7b0U; -} -static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) -{ - return 0x0010a6c0U + i*4U; -} -static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) -{ - return 0x0010a6e8U + i*4U; -} -static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) -{ - return 0x0010a710U + i*4U; -} -static inline u32 pwr_pmu_pg_intren_r(u32 i) -{ - return 0x0010a760U + i*4U; -} -static inline u32 pwr_fbif_transcfg_r(u32 i) -{ - return 0x0010ae00U + i*4U; -} -static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) -{ - return 0x0U; -} -static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) -{ - return 0x1U; -} -static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) -{ - return 0x2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_s(void) -{ - return 1U; -} -static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_m(void) -{ - return 0x1U << 2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) -{ - return 0x0U; -} -static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) -{ - return 0x4U; -} -#endif diff --git a/include/nvgpu/hw/gp10b/hw_ram_gp10b.h b/include/nvgpu/hw/gp10b/hw_ram_gp10b.h deleted file mode 100644 index cc83f52..0000000 --- a/include/nvgpu/hw/gp10b/hw_ram_gp10b.h +++ /dev/null @@ -1,519 +0,0 @@ -/* - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ram_gp10b_h_ -#define _hw_ram_gp10b_h_ - -static inline u32 ram_in_ramfc_s(void) -{ - return 4096U; -} -static inline u32 ram_in_ramfc_w(void) -{ - return 0U; -} -static inline u32 ram_in_page_dir_base_target_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ram_in_page_dir_base_target_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 ram_in_page_dir_base_vol_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_vol_true_f(void) -{ - return 0x4U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) -{ - return 0x1U << 4U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) -{ - return 0x10U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) -{ - return 0x1U << 5U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void) -{ - return 0x20U; -} -static inline u32 ram_in_use_ver2_pt_format_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 ram_in_use_ver2_pt_format_m(void) -{ - return 0x1U << 10U; -} -static inline u32 ram_in_use_ver2_pt_format_w(void) -{ - return 128U; -} -static inline u32 ram_in_use_ver2_pt_format_true_f(void) -{ - return 0x400U; -} -static inline u32 ram_in_use_ver2_pt_format_false_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_big_page_size_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 ram_in_big_page_size_m(void) -{ - return 0x1U << 11U; -} -static inline u32 ram_in_big_page_size_w(void) -{ - return 128U; -} -static inline u32 ram_in_big_page_size_128kb_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_big_page_size_64kb_f(void) -{ - return 0x800U; -} -static inline u32 ram_in_page_dir_base_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_page_dir_base_lo_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_hi_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ram_in_page_dir_base_hi_w(void) -{ - return 129U; -} -static inline u32 ram_in_adr_limit_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_adr_limit_lo_w(void) -{ - return 130U; -} -static inline u32 ram_in_adr_limit_hi_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_in_adr_limit_hi_w(void) -{ - return 131U; -} -static inline u32 ram_in_engine_cs_w(void) -{ - return 132U; -} -static inline u32 ram_in_engine_cs_wfi_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_engine_cs_wfi_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_engine_cs_fg_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_engine_cs_fg_f(void) -{ - return 0x8U; -} -static inline u32 ram_in_gr_cs_w(void) -{ - return 132U; -} -static inline u32 ram_in_gr_cs_wfi_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_gr_wfi_target_w(void) -{ - return 132U; -} -static inline u32 ram_in_gr_wfi_mode_w(void) -{ - return 132U; -} -static inline u32 ram_in_gr_wfi_mode_physical_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_gr_wfi_mode_physical_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_gr_wfi_mode_virtual_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_gr_wfi_mode_virtual_f(void) -{ - return 0x4U; -} -static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_gr_wfi_ptr_lo_w(void) -{ - return 132U; -} -static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ram_in_gr_wfi_ptr_hi_w(void) -{ - return 133U; -} -static inline u32 ram_in_base_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 ram_in_alloc_size_v(void) -{ - return 0x00001000U; -} -static inline u32 ram_fc_size_val_v(void) -{ - return 0x00000200U; -} -static inline u32 ram_fc_gp_put_w(void) -{ - return 0U; -} -static inline u32 ram_fc_userd_w(void) -{ - return 2U; -} -static inline u32 ram_fc_userd_hi_w(void) -{ - return 3U; -} -static inline u32 ram_fc_signature_w(void) -{ - return 4U; -} -static inline u32 ram_fc_gp_get_w(void) -{ - return 5U; -} -static inline u32 ram_fc_pb_get_w(void) -{ - return 6U; -} -static inline u32 ram_fc_pb_get_hi_w(void) -{ - return 7U; -} -static inline u32 ram_fc_pb_top_level_get_w(void) -{ - return 8U; -} -static inline u32 ram_fc_pb_top_level_get_hi_w(void) -{ - return 9U; -} -static inline u32 ram_fc_acquire_w(void) -{ - return 12U; -} -static inline u32 ram_fc_semaphorea_w(void) -{ - return 14U; -} -static inline u32 ram_fc_semaphoreb_w(void) -{ - return 15U; -} -static inline u32 ram_fc_semaphorec_w(void) -{ - return 16U; -} -static inline u32 ram_fc_semaphored_w(void) -{ - return 17U; -} -static inline u32 ram_fc_gp_base_w(void) -{ - return 18U; -} -static inline u32 ram_fc_gp_base_hi_w(void) -{ - return 19U; -} -static inline u32 ram_fc_gp_fetch_w(void) -{ - return 20U; -} -static inline u32 ram_fc_pb_fetch_w(void) -{ - return 21U; -} -static inline u32 ram_fc_pb_fetch_hi_w(void) -{ - return 22U; -} -static inline u32 ram_fc_pb_put_w(void) -{ - return 23U; -} -static inline u32 ram_fc_pb_put_hi_w(void) -{ - return 24U; -} -static inline u32 ram_fc_pb_header_w(void) -{ - return 33U; -} -static inline u32 ram_fc_pb_count_w(void) -{ - return 34U; -} -static inline u32 ram_fc_subdevice_w(void) -{ - return 37U; -} -static inline u32 ram_fc_formats_w(void) -{ - return 39U; -} -static inline u32 ram_fc_allowed_syncpoints_w(void) -{ - return 58U; -} -static inline u32 ram_fc_syncpointa_w(void) -{ - return 41U; -} -static inline u32 ram_fc_syncpointb_w(void) -{ - return 42U; -} -static inline u32 ram_fc_target_w(void) -{ - return 43U; -} -static inline u32 ram_fc_hce_ctrl_w(void) -{ - return 57U; -} -static inline u32 ram_fc_chid_w(void) -{ - return 58U; -} -static inline u32 ram_fc_chid_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_fc_chid_id_w(void) -{ - return 0U; -} -static inline u32 ram_fc_config_w(void) -{ - return 61U; -} -static inline u32 ram_fc_runlist_timeslice_w(void) -{ - return 62U; -} -static inline u32 ram_userd_base_shift_v(void) -{ - return 0x00000009U; -} -static inline u32 ram_userd_chan_size_v(void) -{ - return 0x00000200U; -} -static inline u32 ram_userd_put_w(void) -{ - return 16U; -} -static inline u32 ram_userd_get_w(void) -{ - return 17U; -} -static inline u32 ram_userd_ref_w(void) -{ - return 18U; -} -static inline u32 ram_userd_put_hi_w(void) -{ - return 19U; -} -static inline u32 ram_userd_ref_threshold_w(void) -{ - return 20U; -} -static inline u32 ram_userd_top_level_get_w(void) -{ - return 22U; -} -static inline u32 ram_userd_top_level_get_hi_w(void) -{ - return 23U; -} -static inline u32 ram_userd_get_hi_w(void) -{ - return 24U; -} -static inline u32 ram_userd_gp_get_w(void) -{ - return 34U; -} -static inline u32 ram_userd_gp_put_w(void) -{ - return 35U; -} -static inline u32 ram_userd_gp_top_level_get_w(void) -{ - return 22U; -} -static inline u32 ram_userd_gp_top_level_get_hi_w(void) -{ - return 23U; -} -static inline u32 ram_rl_entry_size_v(void) -{ - return 0x00000008U; -} -static inline u32 ram_rl_entry_chid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_type_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 ram_rl_entry_type_chid_f(void) -{ - return 0x0U; -} -static inline u32 ram_rl_entry_type_tsg_f(void) -{ - return 0x2000U; -} -static inline u32 ram_rl_entry_timeslice_scale_f(u32 v) -{ - return (v & 0xfU) << 14U; -} -static inline u32 ram_rl_entry_timeslice_scale_3_f(void) -{ - return 0xc000U; -} -static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v) -{ - return (v & 0xffU) << 18U; -} -static inline u32 ram_rl_entry_timeslice_timeout_128_f(void) -{ - return 0x2000000U; -} -static inline u32 ram_rl_entry_tsg_length_f(u32 v) -{ - return (v & 0x3fU) << 26U; -} -#endif diff --git a/include/nvgpu/hw/gp10b/hw_therm_gp10b.h b/include/nvgpu/hw/gp10b/hw_therm_gp10b.h deleted file mode 100644 index 49fb718..0000000 --- a/include/nvgpu/hw/gp10b/hw_therm_gp10b.h +++ /dev/null @@ -1,415 +0,0 @@ -/* - * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_therm_gp10b_h_ -#define _hw_therm_gp10b_h_ - -static inline u32 therm_use_a_r(void) -{ - return 0x00020798U; -} -static inline u32 therm_use_a_ext_therm_0_enable_f(void) -{ - return 0x1U; -} -static inline u32 therm_use_a_ext_therm_1_enable_f(void) -{ - return 0x2U; -} -static inline u32 therm_use_a_ext_therm_2_enable_f(void) -{ - return 0x4U; -} -static inline u32 therm_evt_ext_therm_0_r(void) -{ - return 0x00020700U; -} -static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v) -{ - return (v & 0x3fU) << 24U; -} -static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void) -{ - return 0x00000001U; -} -static inline u32 therm_evt_ext_therm_0_mode_f(u32 v) -{ - return (v & 0x3U) << 30U; -} -static inline u32 therm_evt_ext_therm_0_mode_normal_v(void) -{ - return 0x00000000U; -} -static inline u32 therm_evt_ext_therm_0_mode_inverted_v(void) -{ - return 0x00000001U; -} -static inline u32 therm_evt_ext_therm_0_mode_forced_v(void) -{ - return 0x00000002U; -} -static inline u32 therm_evt_ext_therm_0_mode_cleared_v(void) -{ - return 0x00000003U; -} -static inline u32 therm_evt_ext_therm_1_r(void) -{ - return 0x00020704U; -} -static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v) -{ - return (v & 0x3fU) << 24U; -} -static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void) -{ - return 0x00000002U; -} -static inline u32 therm_evt_ext_therm_1_mode_f(u32 v) -{ - return (v & 0x3U) << 30U; -} -static inline u32 therm_evt_ext_therm_1_mode_normal_v(void) -{ - return 0x00000000U; -} -static inline u32 therm_evt_ext_therm_1_mode_inverted_v(void) -{ - return 0x00000001U; -} -static inline u32 therm_evt_ext_therm_1_mode_forced_v(void) -{ - return 0x00000002U; -} -static inline u32 therm_evt_ext_therm_1_mode_cleared_v(void) -{ - return 0x00000003U; -} -static inline u32 therm_evt_ext_therm_2_r(void) -{ - return 0x00020708U; -} -static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v) -{ - return (v & 0x3fU) << 24U; -} -static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void) -{ - return 0x00000003U; -} -static inline u32 therm_evt_ext_therm_2_mode_f(u32 v) -{ - return (v & 0x3U) << 30U; -} -static inline u32 therm_evt_ext_therm_2_mode_normal_v(void) -{ - return 0x00000000U; -} -static inline u32 therm_evt_ext_therm_2_mode_inverted_v(void) -{ - return 0x00000001U; -} -static inline u32 therm_evt_ext_therm_2_mode_forced_v(void) -{ - return 0x00000002U; -} -static inline u32 therm_evt_ext_therm_2_mode_cleared_v(void) -{ - return 0x00000003U; -} -static inline u32 therm_weight_1_r(void) -{ - return 0x00020024U; -} -static inline u32 therm_config1_r(void) -{ - return 0x00020050U; -} -static inline u32 therm_config2_r(void) -{ - return 0x00020130U; -} -static inline u32 therm_config2_slowdown_factor_extended_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 therm_config2_grad_enable_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 therm_gate_ctrl_r(u32 i) -{ - return 0x00020200U + i*4U; -} -static inline u32 therm_gate_ctrl_eng_clk_m(void) -{ - return 0x3U << 0U; -} -static inline u32 therm_gate_ctrl_eng_clk_run_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) -{ - return 0x1U; -} -static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) -{ - return 0x2U; -} -static inline u32 therm_gate_ctrl_blk_clk_m(void) -{ - return 0x3U << 2U; -} -static inline u32 therm_gate_ctrl_blk_clk_run_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) -{ - return 0x4U; -} -static inline u32 therm_gate_ctrl_eng_pwr_m(void) -{ - return 0x3U << 4U; -} -static inline u32 therm_gate_ctrl_eng_pwr_auto_f(void) -{ - return 0x10U; -} -static inline u32 therm_gate_ctrl_eng_pwr_off_v(void) -{ - return 0x00000002U; -} -static inline u32 therm_gate_ctrl_eng_pwr_off_f(void) -{ - return 0x20U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) -{ - return 0x1fU << 8U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) -{ - return (v & 0x7U) << 13U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) -{ - return 0x7U << 13U; -} -static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 therm_gate_ctrl_eng_delay_before_m(void) -{ - return 0xfU << 16U; -} -static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 therm_gate_ctrl_eng_delay_after_m(void) -{ - return 0xfU << 20U; -} -static inline u32 therm_fecs_idle_filter_r(void) -{ - return 0x00020288U; -} -static inline u32 therm_fecs_idle_filter_value_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 therm_hubmmu_idle_filter_r(void) -{ - return 0x0002028cU; -} -static inline u32 therm_hubmmu_idle_filter_value_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 therm_clk_slowdown_r(u32 i) -{ - return 0x00020160U + i*4U; -} -static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) -{ - return (v & 0x3fU) << 16U; -} -static inline u32 therm_clk_slowdown_idle_factor_m(void) -{ - return 0x3fU << 16U; -} -static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) -{ - return (r >> 16U) & 0x3fU; -} -static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) -{ - return 0x0U; -} -static inline u32 therm_grad_stepping_table_r(u32 i) -{ - return 0x000202c8U + i*4U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void) -{ - return 0x1U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void) -{ - return 0x2U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void) -{ - return 0x6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void) -{ - return 0xeU; -} -static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v) -{ - return (v & 0x3fU) << 6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void) -{ - return 0x3fU << 6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) -{ - return (v & 0x3fU) << 12U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void) -{ - return 0x3fU << 12U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) -{ - return (v & 0x3fU) << 18U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void) -{ - return 0x3fU << 18U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) -{ - return (v & 0x3fU) << 24U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void) -{ - return 0x3fU << 24U; -} -static inline u32 therm_grad_stepping0_r(void) -{ - return 0x000202c0U; -} -static inline u32 therm_grad_stepping0_feature_s(void) -{ - return 1U; -} -static inline u32 therm_grad_stepping0_feature_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 therm_grad_stepping0_feature_m(void) -{ - return 0x1U << 0U; -} -static inline u32 therm_grad_stepping0_feature_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 therm_grad_stepping0_feature_enable_f(void) -{ - return 0x1U; -} -static inline u32 therm_grad_stepping1_r(void) -{ - return 0x000202c4U; -} -static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 therm_clk_timing_r(u32 i) -{ - return 0x000203c0U + i*4U; -} -static inline u32 therm_clk_timing_grad_slowdown_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 therm_clk_timing_grad_slowdown_m(void) -{ - return 0x1U << 16U; -} -static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void) -{ - return 0x10000U; -} -#endif diff --git a/include/nvgpu/hw/gp10b/hw_timer_gp10b.h b/include/nvgpu/hw/gp10b/hw_timer_gp10b.h deleted file mode 100644 index 54facfc..0000000 --- a/include/nvgpu/hw/gp10b/hw_timer_gp10b.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_timer_gp10b_h_ -#define _hw_timer_gp10b_h_ - -static inline u32 timer_pri_timeout_r(void) -{ - return 0x00009080U; -} -static inline u32 timer_pri_timeout_period_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 timer_pri_timeout_period_m(void) -{ - return 0xffffffU << 0U; -} -static inline u32 timer_pri_timeout_period_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 timer_pri_timeout_en_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 timer_pri_timeout_en_m(void) -{ - return 0x1U << 31U; -} -static inline u32 timer_pri_timeout_en_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 timer_pri_timeout_en_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 timer_pri_timeout_en_en_disabled_f(void) -{ - return 0x0U; -} -static inline u32 timer_pri_timeout_save_0_r(void) -{ - return 0x00009084U; -} -static inline u32 timer_pri_timeout_save_0_fecs_tgt_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 timer_pri_timeout_save_0_addr_v(u32 r) -{ - return (r >> 2U) & 0x3fffffU; -} -static inline u32 timer_pri_timeout_save_0_write_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 timer_pri_timeout_save_1_r(void) -{ - return 0x00009088U; -} -static inline u32 timer_pri_timeout_fecs_errcode_r(void) -{ - return 0x0000908cU; -} -static inline u32 timer_time_0_r(void) -{ - return 0x00009400U; -} -static inline u32 timer_time_1_r(void) -{ - return 0x00009410U; -} -#endif diff --git a/include/nvgpu/hw/gp10b/hw_top_gp10b.h b/include/nvgpu/hw/gp10b/hw_top_gp10b.h deleted file mode 100644 index a7b7c2b..0000000 --- a/include/nvgpu/hw/gp10b/hw_top_gp10b.h +++ /dev/null @@ -1,231 +0,0 @@ -/* - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_top_gp10b_h_ -#define _hw_top_gp10b_h_ - -static inline u32 top_num_gpcs_r(void) -{ - return 0x00022430U; -} -static inline u32 top_num_gpcs_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_tpc_per_gpc_r(void) -{ - return 0x00022434U; -} -static inline u32 top_tpc_per_gpc_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_num_fbps_r(void) -{ - return 0x00022438U; -} -static inline u32 top_num_fbps_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_ltc_per_fbp_r(void) -{ - return 0x00022450U; -} -static inline u32 top_ltc_per_fbp_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_slices_per_ltc_r(void) -{ - return 0x0002245cU; -} -static inline u32 top_slices_per_ltc_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_num_ltcs_r(void) -{ - return 0x00022454U; -} -static inline u32 top_device_info_r(u32 i) -{ - return 0x00022700U + i*4U; -} -static inline u32 top_device_info__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 top_device_info_chain_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 top_device_info_chain_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_engine_enum_v(u32 r) -{ - return (r >> 26U) & 0xfU; -} -static inline u32 top_device_info_runlist_enum_v(u32 r) -{ - return (r >> 21U) & 0xfU; -} -static inline u32 top_device_info_intr_enum_v(u32 r) -{ - return (r >> 15U) & 0x1fU; -} -static inline u32 top_device_info_reset_enum_v(u32 r) -{ - return (r >> 9U) & 0x1fU; -} -static inline u32 top_device_info_type_enum_v(u32 r) -{ - return (r >> 2U) & 0x1fffffffU; -} -static inline u32 top_device_info_type_enum_graphics_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_type_enum_graphics_f(void) -{ - return 0x0U; -} -static inline u32 top_device_info_type_enum_copy2_v(void) -{ - return 0x00000003U; -} -static inline u32 top_device_info_type_enum_copy2_f(void) -{ - return 0xcU; -} -static inline u32 top_device_info_type_enum_lce_v(void) -{ - return 0x00000013U; -} -static inline u32 top_device_info_type_enum_lce_f(void) -{ - return 0x4cU; -} -static inline u32 top_device_info_engine_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 top_device_info_runlist_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 top_device_info_intr_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 top_device_info_reset_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 top_device_info_entry_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 top_device_info_entry_not_valid_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_entry_enum_v(void) -{ - return 0x00000002U; -} -static inline u32 top_device_info_entry_engine_type_v(void) -{ - return 0x00000003U; -} -static inline u32 top_device_info_entry_data_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_data_type_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 top_device_info_data_type_enum2_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_data_inst_id_v(u32 r) -{ - return (r >> 26U) & 0xfU; -} -static inline u32 top_device_info_data_pri_base_v(u32 r) -{ - return (r >> 12U) & 0xfffU; -} -static inline u32 top_device_info_data_pri_base_align_v(void) -{ - return 0x0000000cU; -} -static inline u32 top_device_info_data_fault_id_enum_v(u32 r) -{ - return (r >> 3U) & 0x1fU; -} -static inline u32 top_device_info_data_fault_id_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 top_device_info_data_fault_id_valid_v(void) -{ - return 0x00000001U; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_bus_gv100.h b/include/nvgpu/hw/gv100/hw_bus_gv100.h deleted file mode 100644 index 7771f1e..0000000 --- a/include/nvgpu/hw/gv100/hw_bus_gv100.h +++ /dev/null @@ -1,227 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_bus_gv100_h_ -#define _hw_bus_gv100_h_ - -static inline u32 bus_sw_scratch_r(u32 i) -{ - return 0x00001580U + i*4U; -} -static inline u32 bus_bar0_window_r(void) -{ - return 0x00001700U; -} -static inline u32 bus_bar0_window_base_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 bus_bar0_window_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) -{ - return 0x2000000U; -} -static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) -{ - return 0x3000000U; -} -static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) -{ - return 0x00000010U; -} -static inline u32 bus_bar1_block_r(void) -{ - return 0x00001704U; -} -static inline u32 bus_bar1_block_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 bus_bar1_block_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar1_block_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 bus_bar1_block_mode_virtual_f(void) -{ - return 0x80000000U; -} -static inline u32 bus_bar2_block_r(void) -{ - return 0x00001714U; -} -static inline u32 bus_bar2_block_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 bus_bar2_block_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar2_block_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 bus_bar2_block_mode_virtual_f(void) -{ - return 0x80000000U; -} -static inline u32 bus_bar1_block_ptr_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 bus_bar2_block_ptr_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 bus_bind_status_r(void) -{ - return 0x00001710U; -} -static inline u32 bus_bind_status_bar1_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 bus_bind_status_bar1_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar1_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 bus_bind_status_bar1_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 bus_bind_status_bar1_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar1_outstanding_true_f(void) -{ - return 0x2U; -} -static inline u32 bus_bind_status_bar2_pending_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 bus_bind_status_bar2_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar2_pending_busy_f(void) -{ - return 0x4U; -} -static inline u32 bus_bind_status_bar2_outstanding_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 bus_bind_status_bar2_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar2_outstanding_true_f(void) -{ - return 0x8U; -} -static inline u32 bus_intr_0_r(void) -{ - return 0x00001100U; -} -static inline u32 bus_intr_0_pri_squash_m(void) -{ - return 0x1U << 1U; -} -static inline u32 bus_intr_0_pri_fecserr_m(void) -{ - return 0x1U << 2U; -} -static inline u32 bus_intr_0_pri_timeout_m(void) -{ - return 0x1U << 3U; -} -static inline u32 bus_intr_en_0_r(void) -{ - return 0x00001140U; -} -static inline u32 bus_intr_en_0_pri_squash_m(void) -{ - return 0x1U << 1U; -} -static inline u32 bus_intr_en_0_pri_fecserr_m(void) -{ - return 0x1U << 2U; -} -static inline u32 bus_intr_en_0_pri_timeout_m(void) -{ - return 0x1U << 3U; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_ccsr_gv100.h b/include/nvgpu/hw/gv100/hw_ccsr_gv100.h deleted file mode 100644 index b147803..0000000 --- a/include/nvgpu/hw/gv100/hw_ccsr_gv100.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ccsr_gv100_h_ -#define _hw_ccsr_gv100_h_ - -static inline u32 ccsr_channel_inst_r(u32 i) -{ - return 0x00800000U + i*8U; -} -static inline u32 ccsr_channel_inst__size_1_v(void) -{ - return 0x00001000U; -} -static inline u32 ccsr_channel_inst_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 ccsr_channel_inst_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 ccsr_channel_inst_bind_false_f(void) -{ - return 0x0U; -} -static inline u32 ccsr_channel_inst_bind_true_f(void) -{ - return 0x80000000U; -} -static inline u32 ccsr_channel_r(u32 i) -{ - return 0x00800004U + i*8U; -} -static inline u32 ccsr_channel__size_1_v(void) -{ - return 0x00001000U; -} -static inline u32 ccsr_channel_enable_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ccsr_channel_enable_set_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 ccsr_channel_enable_set_true_f(void) -{ - return 0x400U; -} -static inline u32 ccsr_channel_enable_clr_true_f(void) -{ - return 0x800U; -} -static inline u32 ccsr_channel_status_v(u32 r) -{ - return (r >> 24U) & 0xfU; -} -static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) -{ - return 0x00000002U; -} -static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) -{ - return 0x00000004U; -} -static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) -{ - return 0x0000000aU; -} -static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) -{ - return 0x0000000bU; -} -static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) -{ - return 0x0000000cU; -} -static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) -{ - return 0x0000000dU; -} -static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) -{ - return 0x0000000eU; -} -static inline u32 ccsr_channel_next_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ccsr_channel_next_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_force_ctx_reload_true_f(void) -{ - return 0x100U; -} -static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 ccsr_channel_pbdma_faulted_reset_f(void) -{ - return 0x400000U; -} -static inline u32 ccsr_channel_eng_faulted_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 ccsr_channel_eng_faulted_v(u32 r) -{ - return (r >> 23U) & 0x1U; -} -static inline u32 ccsr_channel_eng_faulted_reset_f(void) -{ - return 0x800000U; -} -static inline u32 ccsr_channel_eng_faulted_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_busy_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_ce_gv100.h b/include/nvgpu/hw/gv100/hw_ce_gv100.h deleted file mode 100644 index 18b5fc6..0000000 --- a/include/nvgpu/hw/gv100/hw_ce_gv100.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ce_gv100_h_ -#define _hw_ce_gv100_h_ - -static inline u32 ce_intr_status_r(u32 i) -{ - return 0x00104410U + i*128U; -} -static inline u32 ce_intr_status_blockpipe_pending_f(void) -{ - return 0x1U; -} -static inline u32 ce_intr_status_blockpipe_reset_f(void) -{ - return 0x1U; -} -static inline u32 ce_intr_status_nonblockpipe_pending_f(void) -{ - return 0x2U; -} -static inline u32 ce_intr_status_nonblockpipe_reset_f(void) -{ - return 0x2U; -} -static inline u32 ce_intr_status_launcherr_pending_f(void) -{ - return 0x4U; -} -static inline u32 ce_intr_status_launcherr_reset_f(void) -{ - return 0x4U; -} -static inline u32 ce_intr_status_invalid_config_pending_f(void) -{ - return 0x8U; -} -static inline u32 ce_intr_status_invalid_config_reset_f(void) -{ - return 0x8U; -} -static inline u32 ce_intr_status_mthd_buffer_fault_pending_f(void) -{ - return 0x10U; -} -static inline u32 ce_intr_status_mthd_buffer_fault_reset_f(void) -{ - return 0x10U; -} -static inline u32 ce_pce_map_r(void) -{ - return 0x00104028U; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h b/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h deleted file mode 100644 index b7f3df2..0000000 --- a/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h +++ /dev/null @@ -1,459 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ctxsw_prog_gv100_h_ -#define _hw_ctxsw_prog_gv100_h_ - -static inline u32 ctxsw_prog_fecs_header_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) -{ - return 0x00000008U; -} -static inline u32 ctxsw_prog_main_image_ctl_o(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_main_image_ctl_type_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_undefined_v(void) -{ - return 0x00000000U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_opengl_v(void) -{ - return 0x00000008U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_dx9_v(void) -{ - return 0x00000010U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_dx10_v(void) -{ - return 0x00000011U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_dx11_v(void) -{ - return 0x00000012U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_compute_v(void) -{ - return 0x00000020U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_per_veid_header_v(void) -{ - return 0x00000021U; -} -static inline u32 ctxsw_prog_main_image_patch_count_o(void) -{ - return 0x00000010U; -} -static inline u32 ctxsw_prog_main_image_context_id_o(void) -{ - return 0x000000f0U; -} -static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) -{ - return 0x00000014U; -} -static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) -{ - return 0x00000018U; -} -static inline u32 ctxsw_prog_main_image_zcull_o(void) -{ - return 0x0000001cU; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) -{ - return 0x00000001U; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) -{ - return 0x00000020U; -} -static inline u32 ctxsw_prog_main_image_pm_o(void) -{ - return 0x00000028U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_m(void) -{ - return 0x7U << 0U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_stream_out_ctxsw_f(void) -{ - return 0x2U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) -{ - return 0x7U << 3U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) -{ - return 0x8U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) -{ - return 0x0000002cU; -} -static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) -{ - return 0x000000f4U; -} -static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void) -{ - return 0x000000d0U; -} -static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void) -{ - return 0x000000d4U; -} -static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void) -{ - return 0x000000d8U; -} -static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void) -{ - return 0x000000dcU; -} -static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) -{ - return 0x000000f8U; -} -static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_o(void) -{ - return 0x00000060U; -} -static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_pm_ptr_hi_o(void) -{ - return 0x00000094U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_o(void) -{ - return 0x00000064U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void) -{ - return 0x00000068U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_o(void) -{ - return 0x00000070U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_o(void) -{ - return 0x00000074U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_o(void) -{ - return 0x00000078U; -} -static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_context_buffer_ptr_o(void) -{ - return 0x0000007cU; -} -static inline u32 ctxsw_prog_main_image_context_buffer_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_magic_value_o(void) -{ - return 0x000000fcU; -} -static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) -{ - return 0x600dc0deU; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_main_image_global_cb_ptr_o(void) -{ - return 0x000000b8U; -} -static inline u32 ctxsw_prog_main_image_global_cb_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_o(void) -{ - return 0x000000bcU; -} -static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_o(void) -{ - return 0x000000c0U; -} -static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_o(void) -{ - return 0x000000c4U; -} -static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_control_block_ptr_o(void) -{ - return 0x000000c8U; -} -static inline u32 ctxsw_prog_main_image_control_block_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_o(void) -{ - return 0x000000ccU; -} -static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_o(void) -{ - return 0x000000e0U; -} -static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_o(void) -{ - return 0x000000e4U; -} -static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_local_image_ppc_info_o(void) -{ - return 0x000000f4U; -} -static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) -{ - return 0x000000f8U; -} -static inline u32 ctxsw_prog_local_magic_value_o(void) -{ - return 0x000000fcU; -} -static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) -{ - return 0xad0becabU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) -{ - return 0x000000ecU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) -{ - return 0x00000000U; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) -{ - return 0x000000a0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) -{ - return 2U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) -{ - return 0x3U << 0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) -{ - return 0x2U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) -{ - return 0x000000a4U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) -{ - return 0x000000a8U; -} -static inline u32 ctxsw_prog_main_image_misc_options_o(void) -{ - return 0x0000003cU; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) -{ - return 0x1U << 3U; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void) -{ - return 0x00000080U; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void) -{ - return 0x1U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void) -{ - return 0x00000084U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void) -{ - return 0x1U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void) -{ - return 0x2U; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_falcon_gv100.h b/include/nvgpu/hw/gv100/hw_falcon_gv100.h deleted file mode 100644 index 3492d68..0000000 --- a/include/nvgpu/hw/gv100/hw_falcon_gv100.h +++ /dev/null @@ -1,603 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_falcon_gv100_h_ -#define _hw_falcon_gv100_h_ - -static inline u32 falcon_falcon_irqsset_r(void) -{ - return 0x00000000U; -} -static inline u32 falcon_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 falcon_falcon_irqsclr_r(void) -{ - return 0x00000004U; -} -static inline u32 falcon_falcon_irqstat_r(void) -{ - return 0x00000008U; -} -static inline u32 falcon_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 falcon_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 falcon_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 falcon_falcon_irqmode_r(void) -{ - return 0x0000000cU; -} -static inline u32 falcon_falcon_irqmset_r(void) -{ - return 0x00000010U; -} -static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqmclr_r(void) -{ - return 0x00000014U; -} -static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_irqmask_r(void) -{ - return 0x00000018U; -} -static inline u32 falcon_falcon_irqdest_r(void) -{ - return 0x0000001cU; -} -static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 falcon_falcon_curctx_r(void) -{ - return 0x00000050U; -} -static inline u32 falcon_falcon_nxtctx_r(void) -{ - return 0x00000054U; -} -static inline u32 falcon_falcon_mailbox0_r(void) -{ - return 0x00000040U; -} -static inline u32 falcon_falcon_mailbox1_r(void) -{ - return 0x00000044U; -} -static inline u32 falcon_falcon_itfen_r(void) -{ - return 0x00000048U; -} -static inline u32 falcon_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 falcon_falcon_idlestate_r(void) -{ - return 0x0000004cU; -} -static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 falcon_falcon_os_r(void) -{ - return 0x00000080U; -} -static inline u32 falcon_falcon_engctl_r(void) -{ - return 0x000000a4U; -} -static inline u32 falcon_falcon_cpuctl_r(void) -{ - return 0x00000100U; -} -static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_m(void) -{ - return 0x1U << 4U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 falcon_falcon_cpuctl_stopped_m(void) -{ - return 0x1U << 5U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void) -{ - return 0x1U << 6U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 falcon_falcon_cpuctl_alias_r(void) -{ - return 0x00000130U; -} -static inline u32 falcon_falcon_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_imemc_r(u32 i) -{ - return 0x00000180U + i*16U; -} -static inline u32 falcon_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 falcon_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 falcon_falcon_imemc_secure_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 falcon_falcon_imemd_r(u32 i) -{ - return 0x00000184U + i*16U; -} -static inline u32 falcon_falcon_imemt_r(u32 i) -{ - return 0x00000188U + i*16U; -} -static inline u32 falcon_falcon_sctl_r(void) -{ - return 0x00000240U; -} -static inline u32 falcon_falcon_mmu_phys_sec_r(void) -{ - return 0x00100ce4U; -} -static inline u32 falcon_falcon_bootvec_r(void) -{ - return 0x00000104U; -} -static inline u32 falcon_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 falcon_falcon_dmactl_r(void) -{ - return 0x0000010cU; -} -static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void) -{ - return 0x1U << 1U; -} -static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void) -{ - return 0x1U << 2U; -} -static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_hwcfg_r(void) -{ - return 0x00000108U; -} -static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 falcon_falcon_dmatrfbase_r(void) -{ - return 0x00000110U; -} -static inline u32 falcon_falcon_dmatrfbase1_r(void) -{ - return 0x00000128U; -} -static inline u32 falcon_falcon_dmatrfmoffs_r(void) -{ - return 0x00000114U; -} -static inline u32 falcon_falcon_dmatrfcmd_r(void) -{ - return 0x00000118U; -} -static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 falcon_falcon_dmatrffboffs_r(void) -{ - return 0x0000011cU; -} -static inline u32 falcon_falcon_imctl_debug_r(void) -{ - return 0x0000015cU; -} -static inline u32 falcon_falcon_imctl_debug_addr_blk_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 falcon_falcon_imctl_debug_cmd_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 falcon_falcon_imstat_r(void) -{ - return 0x00000144U; -} -static inline u32 falcon_falcon_traceidx_r(void) -{ - return 0x00000148U; -} -static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 falcon_falcon_traceidx_idx_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 falcon_falcon_tracepc_r(void) -{ - return 0x0000014cU; -} -static inline u32 falcon_falcon_tracepc_pc_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 falcon_falcon_exterraddr_r(void) -{ - return 0x00000168U; -} -static inline u32 falcon_falcon_exterrstat_r(void) -{ - return 0x0000016cU; -} -static inline u32 falcon_falcon_exterrstat_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 falcon_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 falcon_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 falcon_falcon_icd_cmd_r(void) -{ - return 0x00000200U; -} -static inline u32 falcon_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 falcon_falcon_icd_cmd_opc_m(void) -{ - return 0xfU << 0U; -} -static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 falcon_falcon_icd_rdata_r(void) -{ - return 0x0000020cU; -} -static inline u32 falcon_falcon_dmemc_r(u32 i) -{ - return 0x000001c0U + i*8U; -} -static inline u32 falcon_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 falcon_falcon_dmemc_offs_m(void) -{ - return 0x3fU << 2U; -} -static inline u32 falcon_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_dmemc_blk_m(void) -{ - return 0xffU << 8U; -} -static inline u32 falcon_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 falcon_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 falcon_falcon_dmemd_r(u32 i) -{ - return 0x000001c4U + i*8U; -} -static inline u32 falcon_falcon_debug1_r(void) -{ - return 0x00000090U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void) -{ - return 1U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void) -{ - return 0x1U << 16U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void) -{ - return 0x0U; -} -static inline u32 falcon_falcon_debuginfo_r(void) -{ - return 0x00000094U; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_fb_gv100.h b/include/nvgpu/hw/gv100/hw_fb_gv100.h deleted file mode 100644 index ac248b5..0000000 --- a/include/nvgpu/hw/gv100/hw_fb_gv100.h +++ /dev/null @@ -1,1923 +0,0 @@ -/* - * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_fb_gv100_h_ -#define _hw_fb_gv100_h_ - -static inline u32 fb_fbhub_num_active_ltcs_r(void) -{ - return 0x00100800U; -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_m(void) -{ - return 0xffU << 16U; -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_f(u32 v, u32 i) -{ - return (v & 0x1U) << (16U + i*1U); -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_m(u32 i) -{ - return 0x1U << (16U + i*1U); -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_v(u32 r, u32 i) -{ - return (r >> (16U + i*1U)) & 0x1U; -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer___size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer___size_1_f(u32 i) -{ - return 0x0U << (32U + i*1U); -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_enabled_f(u32 i) -{ - return 0x1U << (32U + i*1U); -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_disabled_f(u32 i) -{ - return 0x0U << (32U + i*1U); -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_m(void) -{ - return 0x1U << 25U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_v(u32 r) -{ - return (r >> 25U) & 0x1U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_read_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_read_f(void) -{ - return 0x0U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f(void) -{ - return 0x2000000U; -} -static inline u32 fb_mmu_ctrl_r(void) -{ - return 0x00100c80U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_f(u32 v) -{ - return (v & 0x3U) << 24U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_m(void) -{ - return 0x3U << 24U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_v(u32 r) -{ - return (r >> 24U) & 0x3U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_l2_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_l2_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_atomic_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_atomic_f(void) -{ - return 0x1000000U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_rmw_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_rmw_f(void) -{ - return 0x2000000U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_power_v(void) -{ - return 0x00000003U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_power_f(void) -{ - return 0x3000000U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_r(void) -{ - return 0x001fac80U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_f(u32 v) -{ - return (v & 0x3U) << 24U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_m(void) -{ - return 0x3U << 24U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_v(u32 r) -{ - return (r >> 24U) & 0x3U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_l2_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_l2_f(void) -{ - return 0x0U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_atomic_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_atomic_f(void) -{ - return 0x1000000U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_rmw_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_rmw_f(void) -{ - return 0x2000000U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_power_v(void) -{ - return 0x00000003U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_power_f(void) -{ - return 0x3000000U; -} -static inline u32 fb_hsmmu_pri_mmu_debug_ctrl_r(void) -{ - return 0x001facc4U; -} -static inline u32 fb_hsmmu_pri_mmu_debug_ctrl_debug_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 fb_hsmmu_pri_mmu_debug_ctrl_debug_m(void) -{ - return 0x1U << 16U; -} -static inline u32 fb_hsmmu_pri_mmu_debug_ctrl_debug_enabled_f(void) -{ - return 0x10000U; -} -static inline u32 fb_hsmmu_pri_mmu_debug_ctrl_debug_disabled_f(void) -{ - return 0x0U; -} -static inline u32 fb_hshub_num_active_ltcs_r(void) -{ - return 0x001fbc20U; -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_m(void) -{ - return 0xffU << 16U; -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_f(u32 v, u32 i) -{ - return (v & 0x1U) << (16U + i*1U); -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_m(u32 i) -{ - return 0x1U << (16U + i*1U); -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_v(u32 r, u32 i) -{ - return (r >> (16U + i*1U)) & 0x1U; -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer___size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer___size_1_f(u32 i) -{ - return 0x0U << (32U + i*1U); -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_enabled_f(u32 i) -{ - return 0x1U << (32U + i*1U); -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_disabled_f(u32 i) -{ - return 0x0U << (32U + i*1U); -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m(void) -{ - return 0x1U << 25U; -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_v(u32 r) -{ - return (r >> 25U) & 0x1U; -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_read_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_read_f(void) -{ - return 0x0U; -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f(void) -{ - return 0x2000000U; -} -static inline u32 fb_priv_mmu_phy_secure_r(void) -{ - return 0x00100ce4U; -} -static inline u32 fb_mmu_invalidate_pdb_r(void) -{ - return 0x00100cb8U; -} -static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_invalidate_r(void) -{ - return 0x00100cbcU; -} -static inline u32 fb_mmu_invalidate_all_va_true_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_m(void) -{ - return 0x1U << 2U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_invalidate_replay_s(void) -{ - return 3U; -} -static inline u32 fb_mmu_invalidate_replay_f(u32 v) -{ - return (v & 0x7U) << 3U; -} -static inline u32 fb_mmu_invalidate_replay_m(void) -{ - return 0x7U << 3U; -} -static inline u32 fb_mmu_invalidate_replay_v(u32 r) -{ - return (r >> 3U) & 0x7U; -} -static inline u32 fb_mmu_invalidate_replay_none_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_replay_start_f(void) -{ - return 0x8U; -} -static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void) -{ - return 0x10U; -} -static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void) -{ - return 0x20U; -} -static inline u32 fb_mmu_invalidate_sys_membar_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 fb_mmu_invalidate_sys_membar_m(void) -{ - return 0x1U << 6U; -} -static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_sys_membar_true_f(void) -{ - return 0x40U; -} -static inline u32 fb_mmu_invalidate_ack_s(void) -{ - return 2U; -} -static inline u32 fb_mmu_invalidate_ack_f(u32 v) -{ - return (v & 0x3U) << 7U; -} -static inline u32 fb_mmu_invalidate_ack_m(void) -{ - return 0x3U << 7U; -} -static inline u32 fb_mmu_invalidate_ack_v(u32 r) -{ - return (r >> 7U) & 0x3U; -} -static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void) -{ - return 0x100U; -} -static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void) -{ - return 0x80U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_s(void) -{ - return 6U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v) -{ - return (v & 0x3fU) << 9U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_m(void) -{ - return 0x3fU << 9U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r) -{ - return (r >> 9U) & 0x3fU; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void) -{ - return 5U; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v) -{ - return (v & 0x1fU) << 15U; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void) -{ - return 0x1fU << 15U; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r) -{ - return (r >> 15U) & 0x1fU; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_m(void) -{ - return 0x1U << 20U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void) -{ - return 0x100000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void) -{ - return 3U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void) -{ - return 0x7U << 24U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r) -{ - return (r >> 24U) & 0x7U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void) -{ - return 0x1000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void) -{ - return 0x2000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void) -{ - return 0x3000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void) -{ - return 0x4000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void) -{ - return 0x5000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void) -{ - return 0x6000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void) -{ - return 0x7000000U; -} -static inline u32 fb_mmu_invalidate_trigger_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_trigger_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_invalidate_trigger_m(void) -{ - return 0x1U << 31U; -} -static inline u32 fb_mmu_invalidate_trigger_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_trigger_true_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_debug_wr_r(void) -{ - return 0x00100cc8U; -} -static inline u32 fb_mmu_debug_wr_aperture_s(void) -{ - return 2U; -} -static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 fb_mmu_debug_wr_aperture_m(void) -{ - return 0x3U << 0U; -} -static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_debug_wr_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_wr_vol_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_debug_wr_vol_true_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_debug_wr_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) -{ - return 0x0000000cU; -} -static inline u32 fb_mmu_debug_rd_r(void) -{ - return 0x00100cccU; -} -static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_debug_rd_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_rd_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) -{ - return 0x0000000cU; -} -static inline u32 fb_mmu_debug_ctrl_r(void) -{ - return 0x00100cc4U; -} -static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 fb_mmu_debug_ctrl_debug_m(void) -{ - return 0x1U << 16U; -} -static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_debug_ctrl_debug_enabled_f(void) -{ - return 0x10000U; -} -static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_debug_ctrl_debug_disabled_f(void) -{ - return 0x0U; -} -static inline u32 fb_niso_cfg1_r(void) -{ - return 0x00100c14U; -} -static inline u32 fb_niso_cfg1_sysmem_nvlink_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 fb_niso_cfg1_sysmem_nvlink_m(void) -{ - return 0x1U << 17U; -} -static inline u32 fb_niso_cfg1_sysmem_nvlink_v(u32 r) -{ - return (r >> 17U) & 0x1U; -} -static inline u32 fb_niso_cfg1_sysmem_nvlink_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_niso_cfg1_sysmem_nvlink_enabled_f(void) -{ - return 0x20000U; -} -static inline u32 fb_niso_flush_sysmem_addr_r(void) -{ - return 0x00100c10U; -} -static inline u32 fb_niso_intr_r(void) -{ - return 0x00100a20U; -} -static inline u32 fb_niso_intr_hub_access_counter_notify_m(void) -{ - return 0x1U << 0U; -} -static inline u32 fb_niso_intr_hub_access_counter_notify_pending_f(void) -{ - return 0x1U; -} -static inline u32 fb_niso_intr_hub_access_counter_error_m(void) -{ - return 0x1U << 1U; -} -static inline u32 fb_niso_intr_hub_access_counter_error_pending_f(void) -{ - return 0x2U; -} -static inline u32 fb_niso_intr_mmu_replayable_fault_notify_m(void) -{ - return 0x1U << 27U; -} -static inline u32 fb_niso_intr_mmu_replayable_fault_notify_pending_f(void) -{ - return 0x8000000U; -} -static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_m(void) -{ - return 0x1U << 28U; -} -static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_pending_f(void) -{ - return 0x10000000U; -} -static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_m(void) -{ - return 0x1U << 29U; -} -static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_m(void) -{ - return 0x1U << 30U; -} -static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_niso_intr_mmu_other_fault_notify_m(void) -{ - return 0x1U << 31U; -} -static inline u32 fb_niso_intr_mmu_other_fault_notify_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_niso_intr_en_r(u32 i) -{ - return 0x00100a24U + i*4U; -} -static inline u32 fb_niso_intr_en__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_niso_intr_en_hub_access_counter_notify_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 fb_niso_intr_en_hub_access_counter_notify_enabled_f(void) -{ - return 0x1U; -} -static inline u32 fb_niso_intr_en_hub_access_counter_error_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 fb_niso_intr_en_hub_access_counter_error_enabled_f(void) -{ - return 0x2U; -} -static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_f(u32 v) -{ - return (v & 0x1U) << 27U; -} -static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_enabled_f(void) -{ - return 0x8000000U; -} -static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_f(u32 v) -{ - return (v & 0x1U) << 29U; -} -static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_enabled_f(void) -{ - return 0x20000000U; -} -static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_enabled_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_niso_intr_en_mmu_other_fault_notify_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_niso_intr_en_mmu_other_fault_notify_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_niso_intr_en_set_r(u32 i) -{ - return 0x00100a2cU + i*4U; -} -static inline u32 fb_niso_intr_en_set__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_m(void) -{ - return 0x1U << 0U; -} -static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_set_f(void) -{ - return 0x1U; -} -static inline u32 fb_niso_intr_en_set_hub_access_counter_error_m(void) -{ - return 0x1U << 1U; -} -static inline u32 fb_niso_intr_en_set_hub_access_counter_error_set_f(void) -{ - return 0x2U; -} -static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_m(void) -{ - return 0x1U << 27U; -} -static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_set_f(void) -{ - return 0x8000000U; -} -static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_m(void) -{ - return 0x1U << 28U; -} -static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_set_f(void) -{ - return 0x10000000U; -} -static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m(void) -{ - return 0x1U << 29U; -} -static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_set_f(void) -{ - return 0x20000000U; -} -static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m(void) -{ - return 0x1U << 30U; -} -static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_set_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_m(void) -{ - return 0x1U << 31U; -} -static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_set_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_niso_intr_en_clr_r(u32 i) -{ - return 0x00100a34U + i*4U; -} -static inline u32 fb_niso_intr_en_clr__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_m(void) -{ - return 0x1U << 0U; -} -static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_set_f(void) -{ - return 0x1U; -} -static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_m(void) -{ - return 0x1U << 1U; -} -static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_set_f(void) -{ - return 0x2U; -} -static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_m(void) -{ - return 0x1U << 27U; -} -static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_set_f(void) -{ - return 0x8000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_m(void) -{ - return 0x1U << 28U; -} -static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_set_f(void) -{ - return 0x10000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_m(void) -{ - return 0x1U << 29U; -} -static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_set_f(void) -{ - return 0x20000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_m(void) -{ - return 0x1U << 30U; -} -static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_set_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_m(void) -{ - return 0x1U << 31U; -} -static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_set_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_non_replay_fault_buffer_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_replay_fault_buffer_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_lo_r(u32 i) -{ - return 0x00100e24U + i*20U; -} -static inline u32 fb_mmu_fault_buffer_lo__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_f(u32 v) -{ - return (v & 0x3U) << 1U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_v(u32 r) -{ - return (r >> 1U) & 0x3U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_v(void) -{ - return 0x00000003U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_f(void) -{ - return 0x6U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_vol_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_vol_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_v(u32 r) -{ - return (r >> 12U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_buffer_hi_r(u32 i) -{ - return 0x00100e28U + i*20U; -} -static inline u32 fb_mmu_fault_buffer_hi__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_hi_addr_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 fb_mmu_fault_buffer_hi_addr_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 fb_mmu_fault_buffer_get_r(u32 i) -{ - return 0x00100e2cU + i*20U; -} -static inline u32 fb_mmu_fault_buffer_get__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_get_ptr_f(u32 v) -{ - return (v & 0xfffffU) << 0U; -} -static inline u32 fb_mmu_fault_buffer_get_ptr_m(void) -{ - return 0xfffffU << 0U; -} -static inline u32 fb_mmu_fault_buffer_get_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_m(void) -{ - return 0x1U << 30U; -} -static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_m(void) -{ - return 0x1U << 31U; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_clear_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_fault_buffer_put_r(u32 i) -{ - return 0x00100e30U + i*20U; -} -static inline u32 fb_mmu_fault_buffer_put__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_put_ptr_f(u32 v) -{ - return (v & 0xfffffU) << 0U; -} -static inline u32 fb_mmu_fault_buffer_put_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_buffer_put_overflow_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_fault_buffer_put_overflow_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_put_overflow_yes_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_put_overflow_yes_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_fault_buffer_size_r(u32 i) -{ - return 0x00100e34U + i*20U; -} -static inline u32 fb_mmu_fault_buffer_size__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_size_val_f(u32 v) -{ - return (v & 0xfffffU) << 0U; -} -static inline u32 fb_mmu_fault_buffer_size_val_v(u32 r) -{ - return (r >> 0U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_buffer_size_overflow_intr_f(u32 v) -{ - return (v & 0x1U) << 29U; -} -static inline u32 fb_mmu_fault_buffer_size_overflow_intr_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_f(void) -{ - return 0x20000000U; -} -static inline u32 fb_mmu_fault_buffer_size_set_default_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_mmu_fault_buffer_size_set_default_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_size_set_default_yes_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_size_set_default_yes_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_fault_buffer_size_enable_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_fault_buffer_size_enable_m(void) -{ - return 0x1U << 31U; -} -static inline u32 fb_mmu_fault_buffer_size_enable_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_size_enable_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_size_enable_true_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_fault_addr_lo_r(void) -{ - return 0x00100e4cU; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_v(void) -{ - return 0x00000003U; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_fault_addr_lo_addr_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 fb_mmu_fault_addr_lo_addr_v(u32 r) -{ - return (r >> 12U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_addr_hi_r(void) -{ - return 0x00100e50U; -} -static inline u32 fb_mmu_fault_addr_hi_addr_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 fb_mmu_fault_addr_hi_addr_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 fb_mmu_fault_inst_lo_r(void) -{ - return 0x00100e54U; -} -static inline u32 fb_mmu_fault_inst_lo_engine_id_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 fb_mmu_fault_inst_lo_aperture_v(u32 r) -{ - return (r >> 10U) & 0x3U; -} -static inline u32 fb_mmu_fault_inst_lo_aperture_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_inst_lo_aperture_sys_nocoh_v(void) -{ - return 0x00000003U; -} -static inline u32 fb_mmu_fault_inst_lo_addr_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 fb_mmu_fault_inst_lo_addr_v(u32 r) -{ - return (r >> 12U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_inst_hi_r(void) -{ - return 0x00100e58U; -} -static inline u32 fb_mmu_fault_inst_hi_addr_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 fb_mmu_fault_info_r(void) -{ - return 0x00100e5cU; -} -static inline u32 fb_mmu_fault_info_fault_type_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 fb_mmu_fault_info_replayable_fault_v(u32 r) -{ - return (r >> 7U) & 0x1U; -} -static inline u32 fb_mmu_fault_info_client_v(u32 r) -{ - return (r >> 8U) & 0x7fU; -} -static inline u32 fb_mmu_fault_info_access_type_v(u32 r) -{ - return (r >> 16U) & 0xfU; -} -static inline u32 fb_mmu_fault_info_client_type_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 fb_mmu_fault_info_gpc_id_v(u32 r) -{ - return (r >> 24U) & 0x1fU; -} -static inline u32 fb_mmu_fault_info_protected_mode_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 fb_mmu_fault_info_replayable_fault_en_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fb_mmu_fault_info_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fb_mmu_fault_status_r(void) -{ - return 0x00100e60U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_m(void) -{ - return 0x1U << 0U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_m(void) -{ - return 0x1U << 1U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_m(void) -{ - return 0x1U << 2U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_m(void) -{ - return 0x1U << 3U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_f(void) -{ - return 0x8U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_f(void) -{ - return 0x8U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_m(void) -{ - return 0x1U << 4U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_f(void) -{ - return 0x10U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_f(void) -{ - return 0x10U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_m(void) -{ - return 0x1U << 5U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_f(void) -{ - return 0x20U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_f(void) -{ - return 0x20U; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_m(void) -{ - return 0x1U << 6U; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_set_f(void) -{ - return 0x40U; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_f(void) -{ - return 0x40U; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_m(void) -{ - return 0x1U << 7U; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_set_f(void) -{ - return 0x80U; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_f(void) -{ - return 0x80U; -} -static inline u32 fb_mmu_fault_status_replayable_m(void) -{ - return 0x1U << 8U; -} -static inline u32 fb_mmu_fault_status_replayable_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_replayable_set_f(void) -{ - return 0x100U; -} -static inline u32 fb_mmu_fault_status_replayable_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_non_replayable_m(void) -{ - return 0x1U << 9U; -} -static inline u32 fb_mmu_fault_status_non_replayable_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_non_replayable_set_f(void) -{ - return 0x200U; -} -static inline u32 fb_mmu_fault_status_non_replayable_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_replayable_error_m(void) -{ - return 0x1U << 10U; -} -static inline u32 fb_mmu_fault_status_replayable_error_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_replayable_error_set_f(void) -{ - return 0x400U; -} -static inline u32 fb_mmu_fault_status_replayable_error_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_non_replayable_error_m(void) -{ - return 0x1U << 11U; -} -static inline u32 fb_mmu_fault_status_non_replayable_error_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_non_replayable_error_set_f(void) -{ - return 0x800U; -} -static inline u32 fb_mmu_fault_status_non_replayable_error_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_replayable_overflow_m(void) -{ - return 0x1U << 12U; -} -static inline u32 fb_mmu_fault_status_replayable_overflow_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_replayable_overflow_set_f(void) -{ - return 0x1000U; -} -static inline u32 fb_mmu_fault_status_replayable_overflow_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_non_replayable_overflow_m(void) -{ - return 0x1U << 13U; -} -static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_f(void) -{ - return 0x2000U; -} -static inline u32 fb_mmu_fault_status_non_replayable_overflow_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_m(void) -{ - return 0x1U << 14U; -} -static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_f(void) -{ - return 0x4000U; -} -static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_m(void) -{ - return 0x1U << 15U; -} -static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_f(void) -{ - return 0x8000U; -} -static inline u32 fb_mmu_fault_status_busy_m(void) -{ - return 0x1U << 30U; -} -static inline u32 fb_mmu_fault_status_busy_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_busy_true_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_fault_status_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 fb_mmu_fault_status_valid_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_valid_set_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_fault_status_valid_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_valid_clear_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_local_memory_range_r(void) -{ - return 0x00100ce0U; -} -static inline u32 fb_mmu_local_memory_range_lower_scale_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 fb_mmu_local_memory_range_lower_mag_v(u32 r) -{ - return (r >> 4U) & 0x3fU; -} -static inline u32 fb_mmu_local_memory_range_ecc_mode_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fb_niso_scrub_status_r(void) -{ - return 0x00100b20U; -} -static inline u32 fb_niso_scrub_status_flag_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 fb_mmu_priv_level_mask_r(void) -{ - return 0x00100cdcU; -} -static inline u32 fb_mmu_priv_level_mask_write_violation_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 fb_mmu_priv_level_mask_write_violation_m(void) -{ - return 0x1U << 7U; -} -static inline u32 fb_mmu_priv_level_mask_write_violation_v(u32 r) -{ - return (r >> 7U) & 0x1U; -} -static inline u32 fb_hshub_config0_r(void) -{ - return 0x001fbc00U; -} -static inline u32 fb_hshub_config0_sysmem_nvlink_mask_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fb_hshub_config0_sysmem_nvlink_mask_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 fb_hshub_config0_sysmem_nvlink_mask_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_hshub_config0_peer_pcie_mask_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 fb_hshub_config0_peer_pcie_mask_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 fb_hshub_config1_r(void) -{ - return 0x001fbc04U; -} -static inline u32 fb_hshub_config1_peer_0_nvlink_mask_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fb_hshub_config1_peer_0_nvlink_mask_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 fb_hshub_config1_peer_1_nvlink_mask_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 fb_hshub_config1_peer_1_nvlink_mask_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} -static inline u32 fb_hshub_config1_peer_2_nvlink_mask_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 fb_hshub_config1_peer_2_nvlink_mask_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 fb_hshub_config1_peer_3_nvlink_mask_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 fb_hshub_config1_peer_3_nvlink_mask_v(u32 r) -{ - return (r >> 24U) & 0xffU; -} -static inline u32 fb_hshub_config2_r(void) -{ - return 0x001fbc08U; -} -static inline u32 fb_hshub_config2_peer_4_nvlink_mask_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fb_hshub_config2_peer_4_nvlink_mask_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 fb_hshub_config2_peer_5_nvlink_mask_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 fb_hshub_config2_peer_5_nvlink_mask_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} -static inline u32 fb_hshub_config2_peer_6_nvlink_mask_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 fb_hshub_config2_peer_6_nvlink_mask_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 fb_hshub_config2_peer_7_nvlink_mask_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 fb_hshub_config2_peer_7_nvlink_mask_v(u32 r) -{ - return (r >> 24U) & 0xffU; -} -static inline u32 fb_hshub_config6_r(void) -{ - return 0x001fbc18U; -} -static inline u32 fb_hshub_config7_r(void) -{ - return 0x001fbc1cU; -} -static inline u32 fb_hshub_config7_nvlink_logical_0_physical_portmap_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 fb_hshub_config7_nvlink_logical_0_physical_portmap_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 fb_hshub_config7_nvlink_logical_1_physical_portmap_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 fb_hshub_config7_nvlink_logical_1_physical_portmap_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 fb_hshub_config7_nvlink_logical_2_physical_portmap_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 fb_hshub_config7_nvlink_logical_2_physical_portmap_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 fb_hshub_config7_nvlink_logical_3_physical_portmap_f(u32 v) -{ - return (v & 0xfU) << 12U; -} -static inline u32 fb_hshub_config7_nvlink_logical_3_physical_portmap_v(u32 r) -{ - return (r >> 12U) & 0xfU; -} -static inline u32 fb_hshub_config7_nvlink_logical_4_physical_portmap_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 fb_hshub_config7_nvlink_logical_4_physical_portmap_v(u32 r) -{ - return (r >> 16U) & 0xfU; -} -static inline u32 fb_hshub_config7_nvlink_logical_5_physical_portmap_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 fb_hshub_config7_nvlink_logical_5_physical_portmap_v(u32 r) -{ - return (r >> 20U) & 0xfU; -} -static inline u32 fb_hshub_config7_nvlink_logical_6_physical_portmap_f(u32 v) -{ - return (v & 0xfU) << 24U; -} -static inline u32 fb_hshub_config7_nvlink_logical_6_physical_portmap_v(u32 r) -{ - return (r >> 24U) & 0xfU; -} -static inline u32 fb_hshub_config7_nvlink_logical_7_physical_portmap_f(u32 v) -{ - return (v & 0xfU) << 28U; -} -static inline u32 fb_hshub_config7_nvlink_logical_7_physical_portmap_v(u32 r) -{ - return (r >> 28U) & 0xfU; -} -static inline u32 fb_hshub_nvl_cfg_priv_level_mask_r(void) -{ - return 0x001fbc50U; -} -static inline u32 fb_hshub_nvl_cfg_priv_level_mask_write_protection_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 fb_hshub_nvl_cfg_priv_level_mask_write_protection_v(u32 r) -{ - return (r >> 4U) & 0x7U; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_fifo_gv100.h b/include/nvgpu/hw/gv100/hw_fifo_gv100.h deleted file mode 100644 index 4e9b590..0000000 --- a/include/nvgpu/hw/gv100/hw_fifo_gv100.h +++ /dev/null @@ -1,531 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_fifo_gv100_h_ -#define _hw_fifo_gv100_h_ - -static inline u32 fifo_bar1_base_r(void) -{ - return 0x00002254U; -} -static inline u32 fifo_bar1_base_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 fifo_bar1_base_ptr_align_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 fifo_bar1_base_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 fifo_bar1_base_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 fifo_userd_writeback_r(void) -{ - return 0x0000225cU; -} -static inline u32 fifo_userd_writeback_timer_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fifo_userd_writeback_timer_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_userd_writeback_timer_shorter_v(void) -{ - return 0x00000003U; -} -static inline u32 fifo_userd_writeback_timer_100us_v(void) -{ - return 0x00000064U; -} -static inline u32 fifo_userd_writeback_timescale_f(u32 v) -{ - return (v & 0xfU) << 12U; -} -static inline u32 fifo_userd_writeback_timescale_0_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_runlist_base_r(void) -{ - return 0x00002270U; -} -static inline u32 fifo_runlist_base_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 fifo_runlist_base_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 fifo_runlist_r(void) -{ - return 0x00002274U; -} -static inline u32 fifo_runlist_engine_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 fifo_eng_runlist_base_r(u32 i) -{ - return 0x00002280U + i*8U; -} -static inline u32 fifo_eng_runlist_base__size_1_v(void) -{ - return 0x0000000dU; -} -static inline u32 fifo_eng_runlist_r(u32 i) -{ - return 0x00002284U + i*8U; -} -static inline u32 fifo_eng_runlist__size_1_v(void) -{ - return 0x0000000dU; -} -static inline u32 fifo_eng_runlist_length_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fifo_eng_runlist_length_max_v(void) -{ - return 0x0000ffffU; -} -static inline u32 fifo_eng_runlist_pending_true_f(void) -{ - return 0x100000U; -} -static inline u32 fifo_pb_timeslice_r(u32 i) -{ - return 0x00002350U + i*4U; -} -static inline u32 fifo_pb_timeslice_timeout_16_f(void) -{ - return 0x10U; -} -static inline u32 fifo_pb_timeslice_timescale_0_f(void) -{ - return 0x0U; -} -static inline u32 fifo_pb_timeslice_enable_true_f(void) -{ - return 0x10000000U; -} -static inline u32 fifo_pbdma_map_r(u32 i) -{ - return 0x00002390U + i*4U; -} -static inline u32 fifo_intr_0_r(void) -{ - return 0x00002100U; -} -static inline u32 fifo_intr_0_bind_error_pending_f(void) -{ - return 0x1U; -} -static inline u32 fifo_intr_0_bind_error_reset_f(void) -{ - return 0x1U; -} -static inline u32 fifo_intr_0_sched_error_pending_f(void) -{ - return 0x100U; -} -static inline u32 fifo_intr_0_sched_error_reset_f(void) -{ - return 0x100U; -} -static inline u32 fifo_intr_0_chsw_error_pending_f(void) -{ - return 0x10000U; -} -static inline u32 fifo_intr_0_chsw_error_reset_f(void) -{ - return 0x10000U; -} -static inline u32 fifo_intr_0_memop_timeout_pending_f(void) -{ - return 0x800000U; -} -static inline u32 fifo_intr_0_memop_timeout_reset_f(void) -{ - return 0x800000U; -} -static inline u32 fifo_intr_0_lb_error_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_intr_0_lb_error_reset_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 fifo_intr_0_runlist_event_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 fifo_intr_0_channel_intr_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 fifo_intr_en_0_r(void) -{ - return 0x00002140U; -} -static inline u32 fifo_intr_en_0_sched_error_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 fifo_intr_en_0_sched_error_m(void) -{ - return 0x1U << 8U; -} -static inline u32 fifo_intr_en_1_r(void) -{ - return 0x00002528U; -} -static inline u32 fifo_intr_bind_error_r(void) -{ - return 0x0000252cU; -} -static inline u32 fifo_intr_sched_error_r(void) -{ - return 0x0000254cU; -} -static inline u32 fifo_intr_sched_error_code_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fifo_intr_chsw_error_r(void) -{ - return 0x0000256cU; -} -static inline u32 fifo_intr_pbdma_id_r(void) -{ - return 0x000025a0U; -} -static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) -{ - return (r >> (0U + i*1U)) & 0x1U; -} -static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) -{ - return 0x0000000eU; -} -static inline u32 fifo_intr_runlist_r(void) -{ - return 0x00002a00U; -} -static inline u32 fifo_fb_timeout_r(void) -{ - return 0x00002a04U; -} -static inline u32 fifo_fb_timeout_period_m(void) -{ - return 0x3fffffffU << 0U; -} -static inline u32 fifo_fb_timeout_period_max_f(void) -{ - return 0x3fffffffU; -} -static inline u32 fifo_fb_timeout_period_init_f(void) -{ - return 0x3c00U; -} -static inline u32 fifo_sched_disable_r(void) -{ - return 0x00002630U; -} -static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_sched_disable_runlist_m(u32 i) -{ - return 0x1U << (0U + i*1U); -} -static inline u32 fifo_sched_disable_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_runlist_preempt_r(void) -{ - return 0x00002638U; -} -static inline u32 fifo_runlist_preempt_runlist_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_runlist_preempt_runlist_m(u32 i) -{ - return 0x1U << (0U + i*1U); -} -static inline u32 fifo_runlist_preempt_runlist_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_preempt_r(void) -{ - return 0x00002634U; -} -static inline u32 fifo_preempt_pending_true_f(void) -{ - return 0x100000U; -} -static inline u32 fifo_preempt_type_channel_f(void) -{ - return 0x0U; -} -static inline u32 fifo_preempt_type_tsg_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_preempt_chid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 fifo_preempt_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 fifo_engine_status_r(u32 i) -{ - return 0x00002640U + i*8U; -} -static inline u32 fifo_engine_status__size_1_v(void) -{ - return 0x0000000fU; -} -static inline u32 fifo_engine_status_id_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 fifo_engine_status_id_type_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 fifo_engine_status_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctx_status_v(u32 r) -{ - return (r >> 13U) & 0x7U; -} -static inline u32 fifo_engine_status_ctx_status_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void) -{ - return 0x00000005U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void) -{ - return 0x00000006U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void) -{ - return 0x00000007U; -} -static inline u32 fifo_engine_status_next_id_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 fifo_engine_status_next_id_type_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 fifo_engine_status_next_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_eng_reload_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 fifo_engine_status_faulted_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fifo_engine_status_faulted_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_engine_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fifo_engine_status_engine_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_engine_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctxsw_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fifo_engine_status_ctxsw_in_progress_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) -{ - return 0x8000U; -} -static inline u32 fifo_pbdma_status_r(u32 i) -{ - return 0x00003080U + i*4U; -} -static inline u32 fifo_pbdma_status__size_1_v(void) -{ - return 0x0000000eU; -} -static inline u32 fifo_pbdma_status_id_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 fifo_pbdma_status_id_type_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 fifo_pbdma_status_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chan_status_v(u32 r) -{ - return (r >> 13U) & 0x7U; -} -static inline u32 fifo_pbdma_status_chan_status_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void) -{ - return 0x00000005U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void) -{ - return 0x00000006U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void) -{ - return 0x00000007U; -} -static inline u32 fifo_pbdma_status_next_id_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 fifo_pbdma_status_next_id_type_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 fifo_pbdma_status_next_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_pbdma_status_chsw_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_cfg0_r(void) -{ - return 0x00002004U; -} -static inline u32 fifo_cfg0_num_pbdma_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 fifo_cfg0_pbdma_fault_id_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_flush_gv100.h b/include/nvgpu/hw/gv100/hw_flush_gv100.h deleted file mode 100644 index b604562..0000000 --- a/include/nvgpu/hw/gv100/hw_flush_gv100.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_flush_gv100_h_ -#define _hw_flush_gv100_h_ - -static inline u32 flush_l2_system_invalidate_r(void) -{ - return 0x00070004U; -} -static inline u32 flush_l2_system_invalidate_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_system_invalidate_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_system_invalidate_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_system_invalidate_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_flush_dirty_r(void) -{ - return 0x00070010U; -} -static inline u32 flush_l2_flush_dirty_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_flush_dirty_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_flush_dirty_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_flush_dirty_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_flush_dirty_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_flush_dirty_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_flush_dirty_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_clean_comptags_r(void) -{ - return 0x0007000cU; -} -static inline u32 flush_l2_clean_comptags_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_clean_comptags_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_clean_comptags_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_clean_comptags_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_clean_comptags_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_clean_comptags_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_clean_comptags_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_clean_comptags_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_fb_flush_r(void) -{ - return 0x00070000U; -} -static inline u32 flush_fb_flush_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_fb_flush_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_fb_flush_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_fb_flush_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_fb_flush_outstanding_true_v(void) -{ - return 0x00000001U; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_fuse_gv100.h b/include/nvgpu/hw/gv100/hw_fuse_gv100.h deleted file mode 100644 index 48194ea..0000000 --- a/include/nvgpu/hw/gv100/hw_fuse_gv100.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_fuse_gv100_h_ -#define _hw_fuse_gv100_h_ - -static inline u32 fuse_status_opt_gpc_r(void) -{ - return 0x00021c1cU; -} -static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) -{ - return 0x00021c38U + i*4U; -} -static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i) -{ - return 0x00021838U + i*4U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void) -{ - return 0x00021944U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void) -{ - return 0xffU << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void) -{ - return 0x00021948U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void) -{ - return 0x1U << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void) -{ - return 0x1U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void) -{ - return 0x0U; -} -static inline u32 fuse_status_opt_fbio_r(void) -{ - return 0x00021c14U; -} -static inline u32 fuse_status_opt_fbio_data_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fuse_status_opt_fbio_data_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 fuse_status_opt_fbio_data_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i) -{ - return 0x00021d70U + i*4U; -} -static inline u32 fuse_status_opt_fbp_r(void) -{ - return 0x00021d38U; -} -static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) -{ - return (r >> (0U + i*1U)) & 0x1U; -} -static inline u32 fuse_opt_ecc_en_r(void) -{ - return 0x00021228U; -} -static inline u32 fuse_opt_feature_fuses_override_disable_r(void) -{ - return 0x000213f0U; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_gmmu_gv100.h b/include/nvgpu/hw/gv100/hw_gmmu_gv100.h deleted file mode 100644 index 8cccfa9..0000000 --- a/include/nvgpu/hw/gv100/hw_gmmu_gv100.h +++ /dev/null @@ -1,355 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_gmmu_gv100_h_ -#define _hw_gmmu_gv100_h_ - -static inline u32 gmmu_new_pde_is_pte_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_is_pte_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pde_aperture_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_aperture_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pde_aperture_video_memory_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_pde_address_sys_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_pde_address_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_vol_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_vol_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_pde_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pde_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_new_pde__size_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_new_dual_pde_is_pte_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_is_pte_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 gmmu_new_dual_pde_address_big_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_w(void) -{ - return 2U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_dual_pde_vol_small_w(void) -{ - return 2U; -} -static inline u32 gmmu_new_dual_pde_vol_small_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_dual_pde_vol_small_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_vol_big_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_vol_big_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_dual_pde_vol_big_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) -{ - return 2U; -} -static inline u32 gmmu_new_dual_pde_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_new_dual_pde_address_big_shift_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_new_dual_pde__size_v(void) -{ - return 0x00000010U; -} -static inline u32 gmmu_new_pte__size_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_new_pte_valid_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_valid_true_f(void) -{ - return 0x1U; -} -static inline u32 gmmu_new_pte_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_privilege_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_privilege_true_f(void) -{ - return 0x20U; -} -static inline u32 gmmu_new_pte_privilege_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_address_sys_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_pte_address_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_address_vid_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_pte_address_vid_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_vol_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_vol_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_pte_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_aperture_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_aperture_video_memory_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_pte_read_only_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_read_only_true_f(void) -{ - return 0x40U; -} -static inline u32 gmmu_new_pte_comptagline_f(u32 v) -{ - return (v & 0x3ffffU) << 4U; -} -static inline u32 gmmu_new_pte_comptagline_w(void) -{ - return 1U; -} -static inline u32 gmmu_new_pte_kind_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gmmu_new_pte_kind_w(void) -{ - return 1U; -} -static inline u32 gmmu_new_pte_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_pte_kind_f(u32 v) -{ - return (v & 0xffU) << 4U; -} -static inline u32 gmmu_pte_kind_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_kind_invalid_v(void) -{ - return 0x000000ffU; -} -static inline u32 gmmu_pte_kind_pitch_v(void) -{ - return 0x00000000U; -} -static inline u32 gmmu_fault_client_type_gpc_v(void) -{ - return 0x00000000U; -} -static inline u32 gmmu_fault_client_type_hub_v(void) -{ - return 0x00000001U; -} -static inline u32 gmmu_fault_type_unbound_inst_block_v(void) -{ - return 0x00000004U; -} -static inline u32 gmmu_fault_mmu_eng_id_bar2_v(void) -{ - return 0x00000005U; -} -static inline u32 gmmu_fault_mmu_eng_id_physical_v(void) -{ - return 0x0000001fU; -} -static inline u32 gmmu_fault_mmu_eng_id_ce0_v(void) -{ - return 0x0000000fU; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_gr_gv100.h b/include/nvgpu/hw/gv100/hw_gr_gv100.h deleted file mode 100644 index 3955a63..0000000 --- a/include/nvgpu/hw/gv100/hw_gr_gv100.h +++ /dev/null @@ -1,4123 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_gr_gv100_h_ -#define _hw_gr_gv100_h_ - -static inline u32 gr_intr_r(void) -{ - return 0x00400100U; -} -static inline u32 gr_intr_notify_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_intr_notify_reset_f(void) -{ - return 0x1U; -} -static inline u32 gr_intr_semaphore_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_semaphore_reset_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_illegal_method_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_intr_illegal_method_reset_f(void) -{ - return 0x10U; -} -static inline u32 gr_intr_illegal_notify_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_intr_illegal_notify_reset_f(void) -{ - return 0x40U; -} -static inline u32 gr_intr_firmware_method_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 gr_intr_firmware_method_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_intr_firmware_method_reset_f(void) -{ - return 0x100U; -} -static inline u32 gr_intr_illegal_class_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_intr_illegal_class_reset_f(void) -{ - return 0x20U; -} -static inline u32 gr_intr_fecs_error_pending_f(void) -{ - return 0x80000U; -} -static inline u32 gr_intr_fecs_error_reset_f(void) -{ - return 0x80000U; -} -static inline u32 gr_intr_class_error_pending_f(void) -{ - return 0x100000U; -} -static inline u32 gr_intr_class_error_reset_f(void) -{ - return 0x100000U; -} -static inline u32 gr_intr_exception_pending_f(void) -{ - return 0x200000U; -} -static inline u32 gr_intr_exception_reset_f(void) -{ - return 0x200000U; -} -static inline u32 gr_fecs_intr_r(void) -{ - return 0x00400144U; -} -static inline u32 gr_class_error_r(void) -{ - return 0x00400110U; -} -static inline u32 gr_class_error_code_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_intr_nonstall_r(void) -{ - return 0x00400120U; -} -static inline u32 gr_intr_nonstall_trap_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_en_r(void) -{ - return 0x0040013cU; -} -static inline u32 gr_exception_r(void) -{ - return 0x00400108U; -} -static inline u32 gr_exception_fe_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_exception_gpc_m(void) -{ - return 0x1U << 24U; -} -static inline u32 gr_exception_memfmt_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_exception_ds_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_exception_sked_m(void) -{ - return 0x1U << 8U; -} -static inline u32 gr_exception_pd_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_exception_scc_m(void) -{ - return 0x1U << 3U; -} -static inline u32 gr_exception_ssync_m(void) -{ - return 0x1U << 5U; -} -static inline u32 gr_exception_mme_m(void) -{ - return 0x1U << 7U; -} -static inline u32 gr_exception1_r(void) -{ - return 0x00400118U; -} -static inline u32 gr_exception1_gpc_0_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_exception2_r(void) -{ - return 0x0040011cU; -} -static inline u32 gr_exception_en_r(void) -{ - return 0x00400138U; -} -static inline u32 gr_exception_en_fe_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_exception_en_fe_enabled_f(void) -{ - return 0x1U; -} -static inline u32 gr_exception_en_gpc_m(void) -{ - return 0x1U << 24U; -} -static inline u32 gr_exception_en_gpc_enabled_f(void) -{ - return 0x1000000U; -} -static inline u32 gr_exception_en_memfmt_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_exception_en_memfmt_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_exception_en_ds_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_exception_en_ds_enabled_f(void) -{ - return 0x10U; -} -static inline u32 gr_exception_en_pd_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_exception_en_pd_enabled_f(void) -{ - return 0x4U; -} -static inline u32 gr_exception_en_scc_m(void) -{ - return 0x1U << 3U; -} -static inline u32 gr_exception_en_scc_enabled_f(void) -{ - return 0x8U; -} -static inline u32 gr_exception_en_ssync_m(void) -{ - return 0x1U << 5U; -} -static inline u32 gr_exception_en_ssync_enabled_f(void) -{ - return 0x20U; -} -static inline u32 gr_exception_en_mme_m(void) -{ - return 0x1U << 7U; -} -static inline u32 gr_exception_en_mme_enabled_f(void) -{ - return 0x80U; -} -static inline u32 gr_exception_en_sked_m(void) -{ - return 0x1U << 8U; -} -static inline u32 gr_exception_en_sked_enabled_f(void) -{ - return 0x100U; -} -static inline u32 gr_exception1_en_r(void) -{ - return 0x00400130U; -} -static inline u32 gr_exception2_en_r(void) -{ - return 0x00400134U; -} -static inline u32 gr_gpfifo_ctl_r(void) -{ - return 0x00400500U; -} -static inline u32 gr_gpfifo_ctl_access_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpfifo_ctl_access_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpfifo_ctl_access_enabled_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void) -{ - return 0x10000U; -} -static inline u32 gr_gpfifo_status_r(void) -{ - return 0x00400504U; -} -static inline u32 gr_trapped_addr_r(void) -{ - return 0x00400704U; -} -static inline u32 gr_trapped_addr_mthd_v(u32 r) -{ - return (r >> 2U) & 0xfffU; -} -static inline u32 gr_trapped_addr_subch_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 gr_trapped_addr_mme_generated_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 gr_trapped_addr_datahigh_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 gr_trapped_addr_priv_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 gr_trapped_addr_status_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_trapped_data_lo_r(void) -{ - return 0x00400708U; -} -static inline u32 gr_trapped_data_hi_r(void) -{ - return 0x0040070cU; -} -static inline u32 gr_trapped_data_mme_r(void) -{ - return 0x00400710U; -} -static inline u32 gr_trapped_data_mme_pc_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 gr_status_r(void) -{ - return 0x00400700U; -} -static inline u32 gr_status_fe_method_upper_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_status_fe_method_lower_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_status_fe_method_lower_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_status_fe_gi_v(u32 r) -{ - return (r >> 21U) & 0x1U; -} -static inline u32 gr_status_mask_r(void) -{ - return 0x00400610U; -} -static inline u32 gr_status_1_r(void) -{ - return 0x00400604U; -} -static inline u32 gr_status_2_r(void) -{ - return 0x00400608U; -} -static inline u32 gr_engine_status_r(void) -{ - return 0x0040060cU; -} -static inline u32 gr_engine_status_value_busy_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_be0_becs_be_exception_r(void) -{ - return 0x00410204U; -} -static inline u32 gr_pri_be0_becs_be_exception_en_r(void) -{ - return 0x00410208U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void) -{ - return 0x00502c90U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void) -{ - return 0x00502c94U; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void) -{ - return 0x00504508U; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void) -{ - return 0x0050450cU; -} -static inline u32 gr_activity_0_r(void) -{ - return 0x00400380U; -} -static inline u32 gr_activity_1_r(void) -{ - return 0x00400384U; -} -static inline u32 gr_activity_2_r(void) -{ - return 0x00400388U; -} -static inline u32 gr_activity_4_r(void) -{ - return 0x00400390U; -} -static inline u32 gr_activity_4_gpc0_s(void) -{ - return 3U; -} -static inline u32 gr_activity_4_gpc0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_activity_4_gpc0_m(void) -{ - return 0x7U << 0U; -} -static inline u32 gr_activity_4_gpc0_v(u32 r) -{ - return (r >> 0U) & 0x7U; -} -static inline u32 gr_activity_4_gpc0_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_activity_4_gpc0_preempted_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_pri_gpc0_gcc_dbg_r(void) -{ - return 0x00501000U; -} -static inline u32 gr_pri_gpcs_gcc_dbg_r(void) -{ - return 0x00419000U; -} -static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) -{ - return 0x0050433cU; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) -{ - return 0x00419b3cU; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_pri_sked_activity_r(void) -{ - return 0x00407054U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void) -{ - return 0x00502c80U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void) -{ - return 0x00502c84U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void) -{ - return 0x00502c88U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void) -{ - return 0x00502c8cU; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void) -{ - return 0x00504500U; -} -static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void) -{ - return 0x00504d00U; -} -static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void) -{ - return 0x00501d00U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void) -{ - return 0x0041ac80U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void) -{ - return 0x0041ac84U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void) -{ - return 0x0041ac88U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void) -{ - return 0x0041ac8cU; -} -static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void) -{ - return 0x0041c500U; -} -static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void) -{ - return 0x0041cd00U; -} -static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void) -{ - return 0x00419d00U; -} -static inline u32 gr_pri_be0_becs_be_activity0_r(void) -{ - return 0x00410200U; -} -static inline u32 gr_pri_be1_becs_be_activity0_r(void) -{ - return 0x00410600U; -} -static inline u32 gr_pri_bes_becs_be_activity0_r(void) -{ - return 0x00408a00U; -} -static inline u32 gr_pri_ds_mpipe_status_r(void) -{ - return 0x00405858U; -} -static inline u32 gr_pri_fe_go_idle_info_r(void) -{ - return 0x00404194U; -} -static inline u32 gr_pri_fe_chip_def_info_r(void) -{ - return 0x00404030U; -} -static inline u32 gr_pri_fe_chip_def_info_max_veid_count_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 gr_pri_fe_chip_def_info_max_veid_count_init_v(void) -{ - return 0x00000040U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) -{ - return 0x00504238U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) -{ - return 0x00504358U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp0_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp1_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp2_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp3_m(void) -{ - return 0x1U << 3U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp4_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp5_m(void) -{ - return 0x1U << 5U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp6_m(void) -{ - return 0x1U << 6U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp7_m(void) -{ - return 0x1U << 7U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp0_m(void) -{ - return 0x1U << 8U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp1_m(void) -{ - return 0x1U << 9U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp2_m(void) -{ - return 0x1U << 10U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp3_m(void) -{ - return 0x1U << 11U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp4_m(void) -{ - return 0x1U << 12U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp5_m(void) -{ - return 0x1U << 13U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp6_m(void) -{ - return 0x1U << 14U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp7_m(void) -{ - return 0x1U << 15U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 26U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r(void) -{ - return 0x0050435cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r(void) -{ - return 0x00504360U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r(void) -{ - return 0x0050436cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_0_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_1_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_1_m(void) -{ - return 0x1U << 3U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 10U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r(void) -{ - return 0x00504370U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r(void) -{ - return 0x00504374U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_r(void) -{ - return 0x00504638U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm0_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm1_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm0_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm1_m(void) -{ - return 0x1U << 3U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm0_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm1_m(void) -{ - return 0x1U << 5U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m(void) -{ - return 0x1U << 6U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm1_m(void) -{ - return 0x1U << 7U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 18U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r(void) -{ - return 0x0050463cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r(void) -{ - return 0x00504640U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) -{ - return 0x005042c4U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_tpc0_mpc_hww_esr_r(void) -{ - return 0x00504430U; -} -static inline u32 gr_gpc0_tpc0_mpc_hww_esr_reset_trigger_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_r(void) -{ - return 0x00504434U; -} -static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_veid_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_pri_be0_crop_status1_r(void) -{ - return 0x00410134U; -} -static inline u32 gr_pri_bes_crop_status1_r(void) -{ - return 0x00408934U; -} -static inline u32 gr_pri_be0_zrop_status_r(void) -{ - return 0x00410048U; -} -static inline u32 gr_pri_be0_zrop_status2_r(void) -{ - return 0x0041004cU; -} -static inline u32 gr_pri_bes_zrop_status_r(void) -{ - return 0x00408848U; -} -static inline u32 gr_pri_bes_zrop_status2_r(void) -{ - return 0x0040884cU; -} -static inline u32 gr_pipe_bundle_address_r(void) -{ - return 0x00400200U; -} -static inline u32 gr_pipe_bundle_address_value_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pipe_bundle_address_veid_f(u32 v) -{ - return (v & 0x3fU) << 20U; -} -static inline u32 gr_pipe_bundle_address_veid_w(void) -{ - return 0U; -} -static inline u32 gr_pipe_bundle_data_r(void) -{ - return 0x00400204U; -} -static inline u32 gr_pipe_bundle_config_r(void) -{ - return 0x00400208U; -} -static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fe_hww_esr_r(void) -{ - return 0x00404000U; -} -static inline u32 gr_fe_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_fe_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fe_hww_esr_info_r(void) -{ - return 0x004041b0U; -} -static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(void) -{ - return 0x00419eacU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r(void) -{ - return 0x0050472cU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_int_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_pause_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_single_step_complete_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_error_in_trap_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_r(void) -{ - return 0x00419eb4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_r(void) -{ - return 0x00504734U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_m(void) -{ - return 0x1U << 5U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_m(void) -{ - return 0x1U << 6U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_m(void) -{ - return 0x1U << 8U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_fe_go_idle_timeout_r(void) -{ - return 0x00404154U; -} -static inline u32 gr_fe_go_idle_timeout_count_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) -{ - return 0x1800U; -} -static inline u32 gr_fe_object_table_r(u32 i) -{ - return 0x00404200U + i*4U; -} -static inline u32 gr_fe_object_table_nvclass_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_fe_tpc_fs_r(u32 i) -{ - return 0x0040a200U + i*4U; -} -static inline u32 gr_pri_mme_shadow_raw_index_r(void) -{ - return 0x00404488U; -} -static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pri_mme_shadow_raw_data_r(void) -{ - return 0x0040448cU; -} -static inline u32 gr_mme_hww_esr_r(void) -{ - return 0x00404490U; -} -static inline u32 gr_mme_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_mme_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_mme_hww_esr_info_r(void) -{ - return 0x00404494U; -} -static inline u32 gr_memfmt_hww_esr_r(void) -{ - return 0x00404600U; -} -static inline u32 gr_memfmt_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_memfmt_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fecs_cpuctl_r(void) -{ - return 0x00409100U; -} -static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_cpuctl_alias_r(void) -{ - return 0x00409130U; -} -static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_dmactl_r(void) -{ - return 0x0040910cU; -} -static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_fecs_os_r(void) -{ - return 0x00409080U; -} -static inline u32 gr_fecs_idlestate_r(void) -{ - return 0x0040904cU; -} -static inline u32 gr_fecs_mailbox0_r(void) -{ - return 0x00409040U; -} -static inline u32 gr_fecs_mailbox1_r(void) -{ - return 0x00409044U; -} -static inline u32 gr_fecs_irqstat_r(void) -{ - return 0x00409008U; -} -static inline u32 gr_fecs_irqmode_r(void) -{ - return 0x0040900cU; -} -static inline u32 gr_fecs_irqmask_r(void) -{ - return 0x00409018U; -} -static inline u32 gr_fecs_irqdest_r(void) -{ - return 0x0040901cU; -} -static inline u32 gr_fecs_curctx_r(void) -{ - return 0x00409050U; -} -static inline u32 gr_fecs_nxtctx_r(void) -{ - return 0x00409054U; -} -static inline u32 gr_fecs_engctl_r(void) -{ - return 0x004090a4U; -} -static inline u32 gr_fecs_debug1_r(void) -{ - return 0x00409090U; -} -static inline u32 gr_fecs_debuginfo_r(void) -{ - return 0x00409094U; -} -static inline u32 gr_fecs_icd_cmd_r(void) -{ - return 0x00409200U; -} -static inline u32 gr_fecs_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 gr_fecs_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_fecs_icd_cmd_opc_m(void) -{ - return 0xfU << 0U; -} -static inline u32 gr_fecs_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 gr_fecs_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 gr_fecs_icd_rdata_r(void) -{ - return 0x0040920cU; -} -static inline u32 gr_fecs_imemc_r(u32 i) -{ - return 0x00409180U + i*16U; -} -static inline u32 gr_fecs_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_fecs_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_fecs_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_fecs_imemd_r(u32 i) -{ - return 0x00409184U + i*16U; -} -static inline u32 gr_fecs_imemt_r(u32 i) -{ - return 0x00409188U + i*16U; -} -static inline u32 gr_fecs_imemt_tag_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_fecs_dmemc_r(u32 i) -{ - return 0x004091c0U + i*8U; -} -static inline u32 gr_fecs_dmemc_offs_s(void) -{ - return 6U; -} -static inline u32 gr_fecs_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_fecs_dmemc_offs_m(void) -{ - return 0x3fU << 2U; -} -static inline u32 gr_fecs_dmemc_offs_v(u32 r) -{ - return (r >> 2U) & 0x3fU; -} -static inline u32 gr_fecs_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_fecs_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_fecs_dmemd_r(u32 i) -{ - return 0x004091c4U + i*8U; -} -static inline u32 gr_fecs_dmatrfbase_r(void) -{ - return 0x00409110U; -} -static inline u32 gr_fecs_dmatrfmoffs_r(void) -{ - return 0x00409114U; -} -static inline u32 gr_fecs_dmatrffboffs_r(void) -{ - return 0x0040911cU; -} -static inline u32 gr_fecs_dmatrfcmd_r(void) -{ - return 0x00409118U; -} -static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_fecs_bootvec_r(void) -{ - return 0x00409104U; -} -static inline u32 gr_fecs_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_falcon_hwcfg_r(void) -{ - return 0x00409108U; -} -static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void) -{ - return 0x0041a108U; -} -static inline u32 gr_fecs_falcon_rm_r(void) -{ - return 0x00409084U; -} -static inline u32 gr_fecs_current_ctx_r(void) -{ - return 0x00409b00U; -} -static inline u32 gr_fecs_current_ctx_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_current_ctx_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_current_ctx_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_current_ctx_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_current_ctx_target_m(void) -{ - return 0x3U << 28U; -} -static inline u32 gr_fecs_current_ctx_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 gr_fecs_current_ctx_valid_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_current_ctx_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_fecs_current_ctx_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_fecs_current_ctx_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_fecs_current_ctx_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_method_data_r(void) -{ - return 0x00409500U; -} -static inline u32 gr_fecs_method_push_r(void) -{ - return 0x00409504U; -} -static inline u32 gr_fecs_method_push_adr_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void) -{ - return 0x00000003U; -} -static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void) -{ - return 0x3U; -} -static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void) -{ - return 0x00000009U; -} -static inline u32 gr_fecs_method_push_adr_restore_golden_v(void) -{ - return 0x00000015U; -} -static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void) -{ - return 0x00000016U; -} -static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void) -{ - return 0x00000025U; -} -static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void) -{ - return 0x00000030U; -} -static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void) -{ - return 0x00000031U; -} -static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void) -{ - return 0x00000032U; -} -static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void) -{ - return 0x00000038U; -} -static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void) -{ - return 0x00000039U; -} -static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) -{ - return 0x21U; -} -static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void) -{ - return 0x0000001aU; -} -static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(void) -{ - return 0x0000003aU; -} -static inline u32 gr_fecs_host_int_status_r(void) -{ - return 0x00409c18U; -} -static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_fecs_host_int_clear_r(void) -{ - return 0x00409c20U; -} -static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void) -{ - return 0x2U; -} -static inline u32 gr_fecs_host_int_enable_r(void) -{ - return 0x00409c24U; -} -static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void) -{ - return 0x2U; -} -static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void) -{ - return 0x10000U; -} -static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void) -{ - return 0x20000U; -} -static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void) -{ - return 0x40000U; -} -static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void) -{ - return 0x80000U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) -{ - return 0x00409614U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void) -{ - return 0x10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void) -{ - return 0x20U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void) -{ - return 0x40U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void) -{ - return 0x100U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void) -{ - return 0x200U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void) -{ - return 0x1U << 10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r) -{ - return (r >> 10U) & 0x1U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void) -{ - return 0x400U; -} -static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void) -{ - return 0x0040960cU; -} -static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i) -{ - return 0x00409800U + i*4U; -} -static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void) -{ - return 0x00000002U; -} -static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i) -{ - return 0x004098c0U + i*4U; -} -static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i) -{ - return 0x00409840U + i*4U; -} -static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_fs_r(void) -{ - return 0x00409604U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_m(void) -{ - return 0x1fU << 0U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_fecs_fs_num_available_fbps_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 gr_fecs_fs_num_available_fbps_m(void) -{ - return 0x1fU << 16U; -} -static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -static inline u32 gr_fecs_cfg_r(void) -{ - return 0x00409620U; -} -static inline u32 gr_fecs_cfg_imem_sz_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_fecs_rc_lanes_r(void) -{ - return 0x00409880U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_s(void) -{ - return 6U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_fecs_ctxsw_status_1_r(void) -{ - return 0x00409400U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void) -{ - return 0x1U << 12U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 gr_fecs_arb_ctx_adr_r(void) -{ - return 0x00409a24U; -} -static inline u32 gr_fecs_new_ctx_r(void) -{ - return 0x00409b04U; -} -static inline u32 gr_fecs_new_ctx_ptr_s(void) -{ - return 28U; -} -static inline u32 gr_fecs_new_ctx_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_new_ctx_ptr_m(void) -{ - return 0xfffffffU << 0U; -} -static inline u32 gr_fecs_new_ctx_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_new_ctx_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_new_ctx_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_new_ctx_target_m(void) -{ - return 0x3U << 28U; -} -static inline u32 gr_fecs_new_ctx_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_new_ctx_valid_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_new_ctx_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_fecs_new_ctx_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_fecs_new_ctx_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_fecs_arb_ctx_ptr_r(void) -{ - return 0x00409a0cU; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void) -{ - return 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void) -{ - return 0xfffffffU << 0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_m(void) -{ - return 0x3U << 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_arb_ctx_cmd_r(void) -{ - return 0x00409a10U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void) -{ - return 0x1fU << 0U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_fecs_ctxsw_status_fe_0_r(void) -{ - return 0x00409c00U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void) -{ - return 0x00502c04U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) -{ - return 0x00502400U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_mailbox__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_fecs_ctxsw_idlestate_r(void) -{ - return 0x00409420U; -} -static inline u32 gr_fecs_feature_override_ecc_r(void) -{ - return 0x00409658U; -} -static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) -{ - return 0x00502420U; -} -static inline u32 gr_rstr2d_gpc_map_r(u32 i) -{ - return 0x0040780cU + i*4U; -} -static inline u32 gr_rstr2d_map_table_cfg_r(void) -{ - return 0x004078bcU; -} -static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_pd_hww_esr_r(void) -{ - return 0x00406018U; -} -static inline u32 gr_pd_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pd_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i) -{ - return 0x00406028U + i*4U; -} -static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v) -{ - return (v & 0xfU) << 12U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v) -{ - return (v & 0xfU) << 24U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v) -{ - return (v & 0xfU) << 28U; -} -static inline u32 gr_pd_ab_dist_cfg0_r(void) -{ - return 0x004064c0U; -} -static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void) -{ - return 0x0U; -} -static inline u32 gr_pd_ab_dist_cfg1_r(void) -{ - return 0x004064c4U; -} -static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void) -{ - return 0xffffU; -} -static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void) -{ - return 0x00000080U; -} -static inline u32 gr_pd_ab_dist_cfg2_r(void) -{ - return 0x004064c8U; -} -static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) -{ - return (v & 0x1fffU) << 0U; -} -static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) -{ - return 0x00001680U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) -{ - return (v & 0x1fffU) << 16U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) -{ - return 0x00001680U; -} -static inline u32 gr_pd_dist_skip_table_r(u32 i) -{ - return 0x004064d0U + i*4U; -} -static inline u32 gr_pd_dist_skip_table__size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gr_ds_debug_r(void) -{ - return 0x00405800U; -} -static inline u32 gr_ds_debug_timeslice_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_debug_timeslice_mode_enable_f(void) -{ - return 0x8000000U; -} -static inline u32 gr_ds_zbc_color_r_r(void) -{ - return 0x00405804U; -} -static inline u32 gr_ds_zbc_color_r_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_g_r(void) -{ - return 0x00405808U; -} -static inline u32 gr_ds_zbc_color_g_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_b_r(void) -{ - return 0x0040580cU; -} -static inline u32 gr_ds_zbc_color_b_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_a_r(void) -{ - return 0x00405810U; -} -static inline u32 gr_ds_zbc_color_a_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_fmt_r(void) -{ - return 0x00405814U; -} -static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v) -{ - return (v & 0x7fU) << 0U; -} -static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void) -{ - return 0x00000002U; -} -static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) -{ - return 0x00000028U; -} -static inline u32 gr_ds_zbc_z_r(void) -{ - return 0x00405818U; -} -static inline u32 gr_ds_zbc_z_val_s(void) -{ - return 32U; -} -static inline u32 gr_ds_zbc_z_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_z_val_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 gr_ds_zbc_z_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gr_ds_zbc_z_val__init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_ds_zbc_z_val__init_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_z_fmt_r(void) -{ - return 0x0040581cU; -} -static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_zbc_tbl_index_r(void) -{ - return 0x00405820U; -} -static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_ds_zbc_tbl_ld_r(void) -{ - return 0x00405824U; -} -static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) -{ - return 0x4U; -} -static inline u32 gr_ds_tga_constraintlogic_beta_r(void) -{ - return 0x00405830U; -} -static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_ds_tga_constraintlogic_alpha_r(void) -{ - return 0x0040585cU; -} -static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_ds_hww_esr_r(void) -{ - return 0x00405840U; -} -static inline u32 gr_ds_hww_esr_reset_s(void) -{ - return 1U; -} -static inline u32 gr_ds_hww_esr_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_reset_m(void) -{ - return 0x1U << 30U; -} -static inline u32 gr_ds_hww_esr_reset_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_ds_hww_esr_reset_task_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_hww_esr_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_ds_hww_esr_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_ds_hww_esr_2_r(void) -{ - return 0x00405848U; -} -static inline u32 gr_ds_hww_esr_2_reset_s(void) -{ - return 1U; -} -static inline u32 gr_ds_hww_esr_2_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_2_reset_m(void) -{ - return 0x1U << 30U; -} -static inline u32 gr_ds_hww_esr_2_reset_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_ds_hww_esr_2_reset_task_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_hww_esr_2_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_ds_hww_esr_2_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_ds_hww_report_mask_r(void) -{ - return 0x00405844U; -} -static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void) -{ - return 0x8U; -} -static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void) -{ - return 0x80U; -} -static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void) -{ - return 0x200U; -} -static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void) -{ - return 0x400U; -} -static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void) -{ - return 0x800U; -} -static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void) -{ - return 0x1000U; -} -static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void) -{ - return 0x2000U; -} -static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void) -{ - return 0x4000U; -} -static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void) -{ - return 0x8000U; -} -static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void) -{ - return 0x10000U; -} -static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void) -{ - return 0x20000U; -} -static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void) -{ - return 0x40000U; -} -static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void) -{ - return 0x80000U; -} -static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void) -{ - return 0x100000U; -} -static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void) -{ - return 0x200000U; -} -static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void) -{ - return 0x400000U; -} -static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void) -{ - return 0x800000U; -} -static inline u32 gr_ds_hww_report_mask_2_r(void) -{ - return 0x0040584cU; -} -static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i) -{ - return 0x00405870U + i*4U; -} -static inline u32 gr_scc_bundle_cb_base_r(void) -{ - return 0x00408004U; -} -static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_scc_bundle_cb_size_r(void) -{ - return 0x00408008U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7ffU) << 0U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) -{ - return 0x00000030U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_scc_bundle_cb_size_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_scc_bundle_cb_size_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_scc_bundle_cb_size_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_scc_pagepool_base_r(void) -{ - return 0x0040800cU; -} -static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_scc_pagepool_r(void) -{ - return 0x00408010U; -} -static inline u32 gr_scc_pagepool_total_pages_f(u32 v) -{ - return (v & 0x3ffU) << 0U; -} -static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void) -{ - return 0x00000200U; -} -static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_s(void) -{ - return 10U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) -{ - return (v & 0x3ffU) << 10U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_m(void) -{ - return 0x3ffU << 10U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) -{ - return (r >> 10U) & 0x3ffU; -} -static inline u32 gr_scc_pagepool_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_scc_init_r(void) -{ - return 0x0040802cU; -} -static inline u32 gr_scc_init_ram_trigger_f(void) -{ - return 0x1U; -} -static inline u32 gr_scc_hww_esr_r(void) -{ - return 0x00408030U; -} -static inline u32 gr_scc_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_scc_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_ssync_hww_esr_r(void) -{ - return 0x00405a14U; -} -static inline u32 gr_ssync_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_ssync_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_sked_hww_esr_r(void) -{ - return 0x00407020U; -} -static inline u32 gr_sked_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_sked_hww_esr_en_r(void) -{ - return 0x00407024U; -} -static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(void) -{ - return 0x1U << 25U; -} -static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f(void) -{ - return 0x2000000U; -} -static inline u32 gr_cwd_fs_r(void) -{ - return 0x00405b00U; -} -static inline u32 gr_cwd_fs_num_gpcs_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_cwd_fs_num_tpcs_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_cwd_gpc_tpc_id_r(u32 i) -{ - return 0x00405b60U + i*4U; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void) -{ - return 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void) -{ - return 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_cwd_sm_id_r(u32 i) -{ - return 0x00405ba0U + i*4U; -} -static inline u32 gr_cwd_sm_id__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_cwd_sm_id_tpc1_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpc0_fs_gpc_r(void) -{ - return 0x00502608U; -} -static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -static inline u32 gr_gpc0_cfg_r(void) -{ - return 0x00502620U; -} -static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpccs_rc_lanes_r(void) -{ - return 0x00502880U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_gpccs_rc_lane_size_r(void) -{ - return 0x00502910U; -} -static inline u32 gr_gpccs_rc_lane_size_v_s(void) -{ - return 24U; -} -static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_gpccs_rc_lane_size_v_m(void) -{ - return 0xffffffU << 0U; -} -static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_zcull_fs_r(void) -{ - return 0x00500910U; -} -static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 gr_gpc0_zcull_ram_addr_r(void) -{ - return 0x00500914U; -} -static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void) -{ - return 0x00500918U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void) -{ - return 0x00800000U; -} -static inline u32 gr_gpc0_zcull_total_ram_size_r(void) -{ - return 0x00500920U; -} -static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_zcull_zcsize_r(u32 i) -{ - return 0x00500a04U + i*32U; -} -static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void) -{ - return 0x00000040U; -} -static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i) -{ - return 0x00500c10U + i*4U; -} -static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i) -{ - return 0x00500c30U + i*4U; -} -static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void) -{ - return 0x00504088U; -} -static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) -{ - return 0x00504608U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_r(void) -{ - return 0x00504330U; -} -static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r) -{ - return (r >> 8U) & 0xfffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r) -{ - return (r >> 20U) & 0xfffU; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) -{ - return 0x00503018U; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void) -{ - return 0x005030c0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) -{ - return 0x3fffffU << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) -{ - return 0x00000480U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) -{ - return 0x00000d10U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void) -{ - return 0x005030f4U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void) -{ - return 0x005030e4U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void) -{ - return 0x00000800U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) -{ - return 0x005030f8U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void) -{ - return 0x005030f0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) -{ - return 0x00000480U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) -{ - return 0x00419e00U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void) -{ - return 0x00419e04U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void) -{ - return 21U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v) -{ - return (v & 0x1fffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void) -{ - return 0x1fffffU << 0U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r) -{ - return (r >> 0U) & 0x1fffffU; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void) -{ - return 0x80U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void) -{ - return 1U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpccs_falcon_addr_r(void) -{ - return 0x0041a0acU; -} -static inline u32 gr_gpccs_falcon_addr_lsb_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpccs_falcon_addr_msb_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v) -{ - return (v & 0x3fU) << 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_m(void) -{ - return 0x3fU << 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r) -{ - return (r >> 6U) & 0x3fU; -} -static inline u32 gr_gpccs_falcon_addr_msb_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_falcon_addr_msb_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_s(void) -{ - return 12U; -} -static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_m(void) -{ - return 0xfffU << 0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 gr_gpccs_cpuctl_r(void) -{ - return 0x0041a100U; -} -static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_gpccs_dmactl_r(void) -{ - return 0x0041a10cU; -} -static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_gpccs_imemc_r(u32 i) -{ - return 0x0041a180U + i*16U; -} -static inline u32 gr_gpccs_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_gpccs_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpccs_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_gpccs_imemd_r(u32 i) -{ - return 0x0041a184U + i*16U; -} -static inline u32 gr_gpccs_imemt_r(u32 i) -{ - return 0x0041a188U + i*16U; -} -static inline u32 gr_gpccs_imemt__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_gpccs_imemt_tag_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpccs_dmemc_r(u32 i) -{ - return 0x0041a1c0U + i*8U; -} -static inline u32 gr_gpccs_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_gpccs_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpccs_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_gpccs_dmemd_r(u32 i) -{ - return 0x0041a1c4U + i*8U; -} -static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i) -{ - return 0x0041a800U + i*4U; -} -static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void) -{ - return 0x00418e24U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void) -{ - return 32U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void) -{ - return 0x00418e28U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void) -{ - return 11U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7ffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void) -{ - return 0x7ffU << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) -{ - return (r >> 0U) & 0x7ffU; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) -{ - return 0x00000030U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) -{ - return 0x30U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) -{ - return 1U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void) -{ - return 0x005001dcU; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void) -{ - return 0x000004b0U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void) -{ - return 0x005001d8U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void) -{ - return 0x004181e4U; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void) -{ - return 0x0041befcU; -} -static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) -{ - return 0x00418ea0U + i*4U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) -{ - return 0x3fffffU << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i) -{ - return 0x00418010U + i*4U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i) -{ - return 0x0041804cU + i*4U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i) -{ - return 0x00418088U + i*4U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i) -{ - return 0x004180c4U + i*4U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void) -{ - return 0x00418100U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i) -{ - return 0x00418110U + i*4U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void) -{ - return 0x0041814cU; -} -static inline u32 gr_gpcs_swdx_dss_zbc_s_r(u32 i) -{ - return 0x0041815cU + i*4U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_s_val_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r(void) -{ - return 0x00418198U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) -{ - return 0x00418810U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void) -{ - return 0x0000000cU; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_crstr_gpc_map_r(u32 i) -{ - return 0x00418b08U + i*4U; -} -static inline u32 gr_crstr_gpc_map_tile0_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_crstr_gpc_map_tile1_f(u32 v) -{ - return (v & 0x1fU) << 5U; -} -static inline u32 gr_crstr_gpc_map_tile2_f(u32 v) -{ - return (v & 0x1fU) << 10U; -} -static inline u32 gr_crstr_gpc_map_tile3_f(u32 v) -{ - return (v & 0x1fU) << 15U; -} -static inline u32 gr_crstr_gpc_map_tile4_f(u32 v) -{ - return (v & 0x1fU) << 20U; -} -static inline u32 gr_crstr_gpc_map_tile5_f(u32 v) -{ - return (v & 0x1fU) << 25U; -} -static inline u32 gr_crstr_map_table_cfg_r(void) -{ - return 0x00418bb8U; -} -static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_r(u32 i) -{ - return 0x00418980U + i*4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_gpm_pd_cfg_r(void) -{ - return 0x00418c6cU; -} -static inline u32 gr_gpcs_gcc_pagepool_base_r(void) -{ - return 0x00419004U; -} -static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_gcc_pagepool_r(void) -{ - return 0x00419008U; -} -static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v) -{ - return (v & 0x3ffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_pe_vaf_r(void) -{ - return 0x0041980cU; -} -static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void) -{ - return 0x00419848U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) -{ - return 0x00419c00U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void) -{ - return 0x00419c2cU; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(void) -{ - return 0x00419ea8U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r(void) -{ - return 0x00504728U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_error_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_api_stack_error_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_wrap_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_overflow_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) -{ - return 0x200U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) -{ - return 0x800U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_reg_report_f(void) -{ - return 0x2000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_addr_report_f(void) -{ - return 0x4000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f(void) -{ - return 0x8000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) -{ - return 0x10000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) -{ - return 0x40000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_fault_report_f(void) -{ - return 0x800000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_overflow_report_f(void) -{ - return 0x400000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_nack_report_f(void) -{ - return 0x4000000U; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) -{ - return 0x00419d0cU; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) -{ - return 0x0050450cU; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_mpc_enabled_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) -{ - return 0x0041ac94U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_gcc_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) -{ - return 0x00502c90U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) -{ - return 0x00504508U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_r(void) -{ - return 0x00504704U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m(void) -{ - return 0x1U << 3U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_0_r(void) -{ - return 0x00504708U; -} -static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_1_r(void) -{ - return 0x0050470cU; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_0_r(void) -{ - return 0x00504710U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_1_r(void) -{ - return 0x00504714U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_0_r(void) -{ - return 0x00504718U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_1_r(void) -{ - return 0x0050471cU; -} -static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r(void) -{ - return 0x00419e90U; -} -static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_1_r(void) -{ - return 0x00419e94U; -} -static inline u32 gr_gpcs_tpcs_sms_dbgr_status0_r(void) -{ - return 0x00419e80U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_r(void) -{ - return 0x00504700U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_sm_in_trap_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_r(void) -{ - return 0x00504730U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_stack_error_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_api_stack_error_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_pc_wrap_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_pc_f(void) -{ - return 0x5U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_pc_overflow_f(void) -{ - return 0x6U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_reg_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_illegal_instr_encoding_f(void) -{ - return 0x9U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_illegal_instr_param_f(void) -{ - return 0xbU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_oor_reg_f(void) -{ - return 0xdU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_oor_addr_f(void) -{ - return 0xeU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_addr_f(void) -{ - return 0xfU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_invalid_addr_space_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_invalid_const_addr_ldc_f(void) -{ - return 0x12U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_stack_overflow_f(void) -{ - return 0x16U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_fault_f(void) -{ - return 0x17U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_tex_format_f(void) -{ - return 0x18U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_tex_layout_f(void) -{ - return 0x19U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_nack_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m(void) -{ - return 0xffU << 16U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m(void) -{ - return 0xfU << 24U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_r(void) -{ - return 0x0050460cU; -} -static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm0_error_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm1_error_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(void) -{ - return 0x00504738U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_hi_r(void) -{ - return 0x0050473cU; -} -static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) -{ - return 0x005043a0U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) -{ - return 0x00419ba0U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) -{ - return 0x005043b0U; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) -{ - return 0x00419bb0U; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) -{ - return 0x0041be08U; -} -static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) -{ - return 0x4U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map_r(u32 i) -{ - return 0x0041bf00U + i*4U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) -{ - return 0x0041bfd0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) -{ - return (v & 0x7U) << 21U; -} -static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) -{ - return 0x0041bfd4U; -} -static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_r(u32 i) -{ - return 0x0041bfb0U + i*4U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v(void) -{ - return 0x00000005U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gr_bes_zrop_settings_r(void) -{ - return 0x00408850U; -} -static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_be0_crop_debug3_r(void) -{ - return 0x00410108U; -} -static inline u32 gr_bes_crop_debug3_r(void) -{ - return 0x00408908U; -} -static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_bes_crop_debug3_blendopt_fill_override_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_bes_crop_debug3_blendopt_fill_override_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_bes_crop_debug3_blendopt_fill_override_enabled_f(void) -{ - return 0x4U; -} -static inline u32 gr_bes_crop_debug4_r(void) -{ - return 0x0040894cU; -} -static inline u32 gr_bes_crop_debug4_clamp_fp_blend_m(void) -{ - return 0x1U << 18U; -} -static inline u32 gr_bes_crop_debug4_clamp_fp_blend_to_inf_f(void) -{ - return 0x0U; -} -static inline u32 gr_bes_crop_debug4_clamp_fp_blend_to_maxval_f(void) -{ - return 0x40000U; -} -static inline u32 gr_bes_crop_settings_r(void) -{ - return 0x00408958U; -} -static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void) -{ - return 0x000000c0U; -} -static inline u32 gr_zcull_subregion_qty_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_gpcs_tpcs_tex_in_dbg_r(void) -{ - return 0x00419a00U; -} -static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m(void) -{ - return 0x1U << 19U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_r(void) -{ - return 0x00419bf0U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m(void) -{ - return 0x1U << 5U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void) -{ - return 0x1U << 10U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_m(void) -{ - return 0x1U << 28U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_enable_f(void) -{ - return 0x10000000U; -} -static inline u32 gr_fe_pwr_mode_r(void) -{ - return 0x00404170U; -} -static inline u32 gr_fe_pwr_mode_mode_auto_f(void) -{ - return 0x0U; -} -static inline u32 gr_fe_pwr_mode_mode_force_on_f(void) -{ - return 0x2U; -} -static inline u32 gr_fe_pwr_mode_req_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 gr_fe_pwr_mode_req_send_f(void) -{ - return 0x10U; -} -static inline u32 gr_fe_pwr_mode_req_done_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) -{ - return 0x00418880U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void) -{ - return 0x1U << 11U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void) -{ - return 0x3U << 3U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void) -{ - return 0x3U << 5U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void) -{ - return 0x3U << 28U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void) -{ - return 0x1U << 30U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) -{ - return 0x00418890U; -} -static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void) -{ - return 0x00418894U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) -{ - return 0x004188b0U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) -{ - return 0x004188b4U; -} -static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void) -{ - return 0x004188b8U; -} -static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) -{ - return 0x004188acU; -} -static inline u32 gr_gpcs_tpcs_sms_dbgr_control0_r(void) -{ - return 0x00419e84U; -} -static inline u32 gr_fe_gfxp_wfi_timeout_r(void) -{ - return 0x004041c0U; -} -static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void) -{ - return 0x00419bd8U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void) -{ - return 0x7U << 8U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void) -{ - return 0x00419ba4U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void) -{ - return 0x3U << 11U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void) -{ - return 0x1000U; -} -static inline u32 gr_gpcs_tc_debug0_r(void) -{ - return 0x00418708U; -} -static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) -{ - return 0x1ffU << 0U; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_ioctrl_gv100.h b/include/nvgpu/hw/gv100/hw_ioctrl_gv100.h deleted file mode 100644 index c27e607..0000000 --- a/include/nvgpu/hw/gv100/hw_ioctrl_gv100.h +++ /dev/null @@ -1,331 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ioctrl_gv100_h_ -#define _hw_ioctrl_gv100_h_ - -static inline u32 ioctrl_reset_r(void) -{ - return 0x00000140U; -} -static inline u32 ioctrl_reset_sw_post_reset_delay_microseconds_v(void) -{ - return 0x00000008U; -} -static inline u32 ioctrl_reset_linkreset_f(u32 v) -{ - return (v & 0x3fU) << 8U; -} -static inline u32 ioctrl_reset_linkreset_m(void) -{ - return 0x3fU << 8U; -} -static inline u32 ioctrl_reset_linkreset_v(u32 r) -{ - return (r >> 8U) & 0x3fU; -} -static inline u32 ioctrl_debug_reset_r(void) -{ - return 0x00000144U; -} -static inline u32 ioctrl_debug_reset_link_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 ioctrl_debug_reset_link_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 ioctrl_debug_reset_link_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 ioctrl_debug_reset_common_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 ioctrl_debug_reset_common_m(void) -{ - return 0x1U << 31U; -} -static inline u32 ioctrl_debug_reset_common_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 ioctrl_clock_control_r(u32 i) -{ - return 0x00000180U + i*4U; -} -static inline u32 ioctrl_clock_control__size_1_v(void) -{ - return 0x00000006U; -} -static inline u32 ioctrl_clock_control_clkdis_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrl_clock_control_clkdis_m(void) -{ - return 0x1U << 0U; -} -static inline u32 ioctrl_clock_control_clkdis_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrl_top_intr_0_status_r(void) -{ - return 0x00000200U; -} -static inline u32 ioctrl_top_intr_0_status_link_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 ioctrl_top_intr_0_status_link_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 ioctrl_top_intr_0_status_link_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 ioctrl_top_intr_0_status_common_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 ioctrl_top_intr_0_status_common_m(void) -{ - return 0x1U << 31U; -} -static inline u32 ioctrl_top_intr_0_status_common_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_mask_r(void) -{ - return 0x00000220U; -} -static inline u32 ioctrl_common_intr_0_mask_fatal_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrl_common_intr_0_mask_fatal_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_mask_nonfatal_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ioctrl_common_intr_0_mask_nonfatal_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_mask_correctable_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 ioctrl_common_intr_0_mask_correctable_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_mask_intra_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ioctrl_common_intr_0_mask_intra_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_mask_intrb_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ioctrl_common_intr_0_mask_intrb_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_status_r(void) -{ - return 0x00000224U; -} -static inline u32 ioctrl_common_intr_0_status_fatal_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrl_common_intr_0_status_fatal_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_status_nonfatal_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ioctrl_common_intr_0_status_nonfatal_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_status_correctable_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 ioctrl_common_intr_0_status_correctable_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_status_intra_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ioctrl_common_intr_0_status_intra_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_status_intrb_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ioctrl_common_intr_0_status_intrb_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_mask_r(u32 i) -{ - return 0x00000240U + i*20U; -} -static inline u32 ioctrl_link_intr_0_mask_fatal_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrl_link_intr_0_mask_fatal_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_mask_nonfatal_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ioctrl_link_intr_0_mask_nonfatal_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_mask_correctable_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 ioctrl_link_intr_0_mask_correctable_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_mask_intra_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ioctrl_link_intr_0_mask_intra_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_mask_intrb_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ioctrl_link_intr_0_mask_intrb_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_status_r(u32 i) -{ - return 0x00000244U + i*20U; -} -static inline u32 ioctrl_link_intr_0_status_fatal_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrl_link_intr_0_status_fatal_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_status_nonfatal_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ioctrl_link_intr_0_status_nonfatal_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_status_correctable_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 ioctrl_link_intr_0_status_correctable_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_status_intra_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ioctrl_link_intr_0_status_intra_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_status_intrb_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ioctrl_link_intr_0_status_intrb_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_ioctrlmif_gv100.h b/include/nvgpu/hw/gv100/hw_ioctrlmif_gv100.h deleted file mode 100644 index 5747a9b..0000000 --- a/include/nvgpu/hw/gv100/hw_ioctrlmif_gv100.h +++ /dev/null @@ -1,331 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ioctrlmif_gv100_h_ -#define _hw_ioctrlmif_gv100_h_ - -static inline u32 ioctrlmif_rx_err_contain_en_0_r(void) -{ - return 0x00000e0cU; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_m(void) -{ - return 0x1U << 3U; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr__prod_v(void) -{ - return 0x00000001U; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr__prod_f(void) -{ - return 0x8U; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_m(void) -{ - return 0x1U << 4U; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr__prod_v(void) -{ - return 0x00000001U; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr__prod_f(void) -{ - return 0x10U; -} -static inline u32 ioctrlmif_rx_err_log_en_0_r(void) -{ - return 0x00000e04U; -} -static inline u32 ioctrlmif_rx_err_log_en_0_rxramdataparityerr_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ioctrlmif_rx_err_log_en_0_rxramdataparityerr_m(void) -{ - return 0x1U << 3U; -} -static inline u32 ioctrlmif_rx_err_log_en_0_rxramdataparityerr_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_m(void) -{ - return 0x1U << 4U; -} -static inline u32 ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 ioctrlmif_rx_err_report_en_0_r(void) -{ - return 0x00000e08U; -} -static inline u32 ioctrlmif_rx_err_report_en_0_rxramdataparityerr_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ioctrlmif_rx_err_report_en_0_rxramdataparityerr_m(void) -{ - return 0x1U << 3U; -} -static inline u32 ioctrlmif_rx_err_report_en_0_rxramdataparityerr_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_m(void) -{ - return 0x1U << 4U; -} -static inline u32 ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 ioctrlmif_rx_err_status_0_r(void) -{ - return 0x00000e00U; -} -static inline u32 ioctrlmif_rx_err_status_0_rxramdataparityerr_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ioctrlmif_rx_err_status_0_rxramdataparityerr_m(void) -{ - return 0x1U << 3U; -} -static inline u32 ioctrlmif_rx_err_status_0_rxramdataparityerr_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 ioctrlmif_rx_err_status_0_rxramhdrparityerr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ioctrlmif_rx_err_status_0_rxramhdrparityerr_m(void) -{ - return 0x1U << 4U; -} -static inline u32 ioctrlmif_rx_err_status_0_rxramhdrparityerr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 ioctrlmif_rx_err_first_0_r(void) -{ - return 0x00000e14U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_r(void) -{ - return 0x00000a90U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr_m(void) -{ - return 0x1U << 0U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr__prod_v(void) -{ - return 0x00000001U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr__prod_f(void) -{ - return 0x1U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_m(void) -{ - return 0x1U << 1U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr__prod_v(void) -{ - return 0x00000001U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr__prod_f(void) -{ - return 0x2U; -} -static inline u32 ioctrlmif_tx_err_log_en_0_r(void) -{ - return 0x00000a88U; -} -static inline u32 ioctrlmif_tx_err_log_en_0_txramdataparityerr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrlmif_tx_err_log_en_0_txramdataparityerr_m(void) -{ - return 0x1U << 0U; -} -static inline u32 ioctrlmif_tx_err_log_en_0_txramdataparityerr_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrlmif_tx_err_log_en_0_txramhdrparityerr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ioctrlmif_tx_err_log_en_0_txramhdrparityerr_m(void) -{ - return 0x1U << 1U; -} -static inline u32 ioctrlmif_tx_err_log_en_0_txramhdrparityerr_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ioctrlmif_tx_err_report_en_0_r(void) -{ - return 0x00000e08U; -} -static inline u32 ioctrlmif_tx_err_report_en_0_txramdataparityerr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrlmif_tx_err_report_en_0_txramdataparityerr_m(void) -{ - return 0x1U << 0U; -} -static inline u32 ioctrlmif_tx_err_report_en_0_txramdataparityerr_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrlmif_tx_err_report_en_0_txramhdrparityerr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ioctrlmif_tx_err_report_en_0_txramhdrparityerr_m(void) -{ - return 0x1U << 1U; -} -static inline u32 ioctrlmif_tx_err_report_en_0_txramhdrparityerr_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ioctrlmif_tx_err_status_0_r(void) -{ - return 0x00000a84U; -} -static inline u32 ioctrlmif_tx_err_status_0_txramdataparityerr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrlmif_tx_err_status_0_txramdataparityerr_m(void) -{ - return 0x1U << 0U; -} -static inline u32 ioctrlmif_tx_err_status_0_txramdataparityerr_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrlmif_tx_err_status_0_txramhdrparityerr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ioctrlmif_tx_err_status_0_txramhdrparityerr_m(void) -{ - return 0x1U << 1U; -} -static inline u32 ioctrlmif_tx_err_status_0_txramhdrparityerr_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ioctrlmif_tx_err_first_0_r(void) -{ - return 0x00000a98U; -} -static inline u32 ioctrlmif_tx_ctrl_buffer_ready_r(void) -{ - return 0x00000a7cU; -} -static inline u32 ioctrlmif_rx_ctrl_buffer_ready_r(void) -{ - return 0x00000dfcU; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_ltc_gv100.h b/include/nvgpu/hw/gv100/hw_ltc_gv100.h deleted file mode 100644 index 042cb7d..0000000 --- a/include/nvgpu/hw/gv100/hw_ltc_gv100.h +++ /dev/null @@ -1,631 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ltc_gv100_h_ -#define _hw_ltc_gv100_h_ - -static inline u32 ltc_pltcg_base_v(void) -{ - return 0x00140000U; -} -static inline u32 ltc_pltcg_extent_v(void) -{ - return 0x0017ffffU; -} -static inline u32 ltc_ltc0_ltss_v(void) -{ - return 0x00140200U; -} -static inline u32 ltc_ltc0_lts0_v(void) -{ - return 0x00140400U; -} -static inline u32 ltc_ltcs_ltss_v(void) -{ - return 0x0017e200U; -} -static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) -{ - return 0x0014046cU; -} -static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) -{ - return 0x00140518U; -} -static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) -{ - return 0x0017e318U; -} -static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void) -{ - return 0x1U << 15U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) -{ - return 0x00140494U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) -{ - return (r >> 16U) & 0x3U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) -{ - return 0x00000000U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) -{ - return 0x00000002U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) -{ - return 0x0017e26cU; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) -{ - return 0x2U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) -{ - return 0x4U; -} -static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) -{ - return 0x0014046cU; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) -{ - return 0x0017e270U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) -{ - return (v & 0x3ffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) -{ - return 0x0017e274U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) -{ - return (v & 0x3ffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) -{ - return 0x0003ffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_base_r(void) -{ - return 0x0017e278U; -} -static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) -{ - return 0x0000000bU; -} -static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) -{ - return (r >> 0U) & 0x3ffffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) -{ - return 0x0017e27cU; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs__v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_v(u32 r) -{ - return (r >> 25U) & 0x1U; -} -static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) -{ - return 0x0017e000U; -} -static inline u32 ltc_ltcs_ltss_cbc_param_r(void) -{ - return 0x0017e280U; -} -static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r) -{ - return (r >> 24U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r) -{ - return (r >> 28U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_cbc_param2_r(void) -{ - return 0x0017e3f4U; -} -static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) -{ - return 0x0017e2acU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) -{ - return 0x0017e338U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) -{ - return 0x0017e33cU + i*4U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) -{ - return 0x0017e34cU; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) -{ - return 32U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(void) -{ - return 0x0017e204U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_s(void) -{ - return 8U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_m(void) -{ - return 0xffU << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) -{ - return 0x0017e2b0U; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_r(void) -{ - return 0x0017e214U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_r(void) -{ - return 0x00140214U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc1_ltss_g_elpg_r(void) -{ - return 0x00142214U; -} -static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_intr_r(void) -{ - return 0x0017e20cU; -} -static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void) -{ - return 0x100U; -} -static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void) -{ - return 0x200U; -} -static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) -{ - return 0x1U << 20U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_m(void) -{ - return 0x1U << 21U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_disabled_f(void) -{ - return 0x0U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) -{ - return 0x1U << 30U; -} -static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void) -{ - return 0x1000000U; -} -static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void) -{ - return 0x2000000U; -} -static inline u32 ltc_ltc0_lts0_intr_r(void) -{ - return 0x0014040cU; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void) -{ - return 0x0014051cU; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void) -{ - return 0xffU << 0U; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void) -{ - return 0xffU << 16U; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) -{ - return 0x0017e2a0U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) -{ - return 0x300U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) -{ - return 0x20000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) -{ - return 0x40000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) -{ - return 0x0017e2a4U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) -{ - return 0x300U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) -{ - return 0x10000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) -{ - return 0x20000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) -{ - return 0x40000000U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) -{ - return 0x001402a0U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) -{ - return 0x001402a4U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void) -{ - return 0x001422a0U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void) -{ - return 0x001422a4U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void) -{ - return 0x0014058cU; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_mc_gv100.h b/include/nvgpu/hw/gv100/hw_mc_gv100.h deleted file mode 100644 index cf406c3..0000000 --- a/include/nvgpu/hw/gv100/hw_mc_gv100.h +++ /dev/null @@ -1,259 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_mc_gv100_h_ -#define _hw_mc_gv100_h_ - -static inline u32 mc_boot_0_r(void) -{ - return 0x00000000U; -} -static inline u32 mc_boot_0_architecture_v(u32 r) -{ - return (r >> 24U) & 0x1fU; -} -static inline u32 mc_boot_0_implementation_v(u32 r) -{ - return (r >> 20U) & 0xfU; -} -static inline u32 mc_boot_0_major_revision_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 mc_boot_0_minor_revision_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 mc_intr_r(u32 i) -{ - return 0x00000100U + i*4U; -} -static inline u32 mc_intr_pfifo_pending_f(void) -{ - return 0x100U; -} -static inline u32 mc_intr_hub_pending_f(void) -{ - return 0x200U; -} -static inline u32 mc_intr_pgraph_pending_f(void) -{ - return 0x1000U; -} -static inline u32 mc_intr_pmu_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 mc_intr_ltc_pending_f(void) -{ - return 0x2000000U; -} -static inline u32 mc_intr_priv_ring_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 mc_intr_pbus_pending_f(void) -{ - return 0x10000000U; -} -static inline u32 mc_intr_nvlink_pending_f(void) -{ - return 0x400000U; -} -static inline u32 mc_intr_en_r(u32 i) -{ - return 0x00000140U + i*4U; -} -static inline u32 mc_intr_en_set_r(u32 i) -{ - return 0x00000160U + i*4U; -} -static inline u32 mc_intr_en_clear_r(u32 i) -{ - return 0x00000180U + i*4U; -} -static inline u32 mc_enable_r(void) -{ - return 0x00000200U; -} -static inline u32 mc_enable_xbar_enabled_f(void) -{ - return 0x4U; -} -static inline u32 mc_enable_l2_enabled_f(void) -{ - return 0x8U; -} -static inline u32 mc_enable_pmedia_s(void) -{ - return 1U; -} -static inline u32 mc_enable_pmedia_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 mc_enable_pmedia_m(void) -{ - return 0x1U << 4U; -} -static inline u32 mc_enable_pmedia_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 mc_enable_ce0_m(void) -{ - return 0x1U << 6U; -} -static inline u32 mc_enable_pfifo_enabled_f(void) -{ - return 0x100U; -} -static inline u32 mc_enable_pgraph_enabled_f(void) -{ - return 0x1000U; -} -static inline u32 mc_enable_pwr_v(u32 r) -{ - return (r >> 13U) & 0x1U; -} -static inline u32 mc_enable_pwr_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 mc_enable_pwr_enabled_f(void) -{ - return 0x2000U; -} -static inline u32 mc_enable_pfb_enabled_f(void) -{ - return 0x100000U; -} -static inline u32 mc_enable_ce2_m(void) -{ - return 0x1U << 21U; -} -static inline u32 mc_enable_ce2_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 mc_enable_blg_enabled_f(void) -{ - return 0x8000000U; -} -static inline u32 mc_enable_perfmon_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 mc_enable_hub_enabled_f(void) -{ - return 0x20000000U; -} -static inline u32 mc_enable_nvdec_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 mc_enable_nvdec_enabled_f(void) -{ - return 0x8000U; -} -static inline u32 mc_enable_nvlink_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 mc_enable_nvlink_disabled_f(void) -{ - return 0x0U; -} -static inline u32 mc_enable_nvlink_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 mc_enable_nvlink_enabled_f(void) -{ - return 0x2000000U; -} -static inline u32 mc_intr_ltc_r(void) -{ - return 0x000001c0U; -} -static inline u32 mc_enable_pb_r(void) -{ - return 0x00000204U; -} -static inline u32 mc_enable_pb_0_s(void) -{ - return 1U; -} -static inline u32 mc_enable_pb_0_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 mc_enable_pb_0_m(void) -{ - return 0x1U << 0U; -} -static inline u32 mc_enable_pb_0_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 mc_enable_pb_0_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 mc_enable_pb_sel_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_minion_gv100.h b/include/nvgpu/hw/gv100/hw_minion_gv100.h deleted file mode 100644 index e4bbf23..0000000 --- a/include/nvgpu/hw/gv100/hw_minion_gv100.h +++ /dev/null @@ -1,943 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_minion_gv100_h_ -#define _hw_minion_gv100_h_ - -static inline u32 minion_minion_status_r(void) -{ - return 0x00000830U; -} -static inline u32 minion_minion_status_status_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 minion_minion_status_status_m(void) -{ - return 0xffU << 0U; -} -static inline u32 minion_minion_status_status_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 minion_minion_status_status_boot_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_minion_status_status_boot_f(void) -{ - return 0x1U; -} -static inline u32 minion_minion_status_intr_code_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 minion_minion_status_intr_code_m(void) -{ - return 0xffffffU << 8U; -} -static inline u32 minion_minion_status_intr_code_v(u32 r) -{ - return (r >> 8U) & 0xffffffU; -} -static inline u32 minion_falcon_irqstat_r(void) -{ - return 0x00000008U; -} -static inline u32 minion_falcon_irqstat_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 minion_falcon_irqstat_halt_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 minion_falcon_irqstat_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 minion_falcon_irqstat_exterr_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 minion_falcon_irqstat_exterr_true_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 minion_falcon_irqmask_r(void) -{ - return 0x00000018U; -} -static inline u32 minion_falcon_irqsclr_r(void) -{ - return 0x00000004U; -} -static inline u32 minion_falcon_irqsset_r(void) -{ - return 0x00000000U; -} -static inline u32 minion_falcon_irqmset_r(void) -{ - return 0x00000010U; -} -static inline u32 minion_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 minion_falcon_irqmset_wdtmr_m(void) -{ - return 0x1U << 1U; -} -static inline u32 minion_falcon_irqmset_wdtmr_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 minion_falcon_irqmset_wdtmr_set_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqmset_wdtmr_set_f(void) -{ - return 0x2U; -} -static inline u32 minion_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 minion_falcon_irqmset_halt_m(void) -{ - return 0x1U << 4U; -} -static inline u32 minion_falcon_irqmset_halt_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 minion_falcon_irqmset_halt_set_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqmset_halt_set_f(void) -{ - return 0x10U; -} -static inline u32 minion_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 minion_falcon_irqmset_exterr_m(void) -{ - return 0x1U << 5U; -} -static inline u32 minion_falcon_irqmset_exterr_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 minion_falcon_irqmset_exterr_set_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqmset_exterr_set_f(void) -{ - return 0x20U; -} -static inline u32 minion_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 minion_falcon_irqmset_swgen0_m(void) -{ - return 0x1U << 6U; -} -static inline u32 minion_falcon_irqmset_swgen0_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 minion_falcon_irqmset_swgen0_set_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqmset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 minion_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 minion_falcon_irqmset_swgen1_m(void) -{ - return 0x1U << 7U; -} -static inline u32 minion_falcon_irqmset_swgen1_v(u32 r) -{ - return (r >> 7U) & 0x1U; -} -static inline u32 minion_falcon_irqmset_swgen1_set_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqmset_swgen1_set_f(void) -{ - return 0x80U; -} -static inline u32 minion_falcon_irqdest_r(void) -{ - return 0x0000001cU; -} -static inline u32 minion_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 minion_falcon_irqdest_host_wdtmr_m(void) -{ - return 0x1U << 1U; -} -static inline u32 minion_falcon_irqdest_host_wdtmr_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_host_wdtmr_host_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqdest_host_wdtmr_host_f(void) -{ - return 0x2U; -} -static inline u32 minion_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 minion_falcon_irqdest_host_halt_m(void) -{ - return 0x1U << 4U; -} -static inline u32 minion_falcon_irqdest_host_halt_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_host_halt_host_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqdest_host_halt_host_f(void) -{ - return 0x10U; -} -static inline u32 minion_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 minion_falcon_irqdest_host_exterr_m(void) -{ - return 0x1U << 5U; -} -static inline u32 minion_falcon_irqdest_host_exterr_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_host_exterr_host_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqdest_host_exterr_host_f(void) -{ - return 0x20U; -} -static inline u32 minion_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 minion_falcon_irqdest_host_swgen0_m(void) -{ - return 0x1U << 6U; -} -static inline u32 minion_falcon_irqdest_host_swgen0_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_host_swgen0_host_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqdest_host_swgen0_host_f(void) -{ - return 0x40U; -} -static inline u32 minion_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 minion_falcon_irqdest_host_swgen1_m(void) -{ - return 0x1U << 7U; -} -static inline u32 minion_falcon_irqdest_host_swgen1_v(u32 r) -{ - return (r >> 7U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_host_swgen1_host_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqdest_host_swgen1_host_f(void) -{ - return 0x80U; -} -static inline u32 minion_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 minion_falcon_irqdest_target_wdtmr_m(void) -{ - return 0x1U << 17U; -} -static inline u32 minion_falcon_irqdest_target_wdtmr_v(u32 r) -{ - return (r >> 17U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_target_wdtmr_host_normal_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_falcon_irqdest_target_wdtmr_host_normal_f(void) -{ - return 0x0U; -} -static inline u32 minion_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 minion_falcon_irqdest_target_halt_m(void) -{ - return 0x1U << 20U; -} -static inline u32 minion_falcon_irqdest_target_halt_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_target_halt_host_normal_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_falcon_irqdest_target_halt_host_normal_f(void) -{ - return 0x0U; -} -static inline u32 minion_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 minion_falcon_irqdest_target_exterr_m(void) -{ - return 0x1U << 21U; -} -static inline u32 minion_falcon_irqdest_target_exterr_v(u32 r) -{ - return (r >> 21U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_target_exterr_host_normal_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_falcon_irqdest_target_exterr_host_normal_f(void) -{ - return 0x0U; -} -static inline u32 minion_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 minion_falcon_irqdest_target_swgen0_m(void) -{ - return 0x1U << 22U; -} -static inline u32 minion_falcon_irqdest_target_swgen0_v(u32 r) -{ - return (r >> 22U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_target_swgen0_host_normal_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_falcon_irqdest_target_swgen0_host_normal_f(void) -{ - return 0x0U; -} -static inline u32 minion_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 minion_falcon_irqdest_target_swgen1_m(void) -{ - return 0x1U << 23U; -} -static inline u32 minion_falcon_irqdest_target_swgen1_v(u32 r) -{ - return (r >> 23U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_target_swgen1_host_normal_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_falcon_irqdest_target_swgen1_host_normal_f(void) -{ - return 0x0U; -} -static inline u32 minion_falcon_os_r(void) -{ - return 0x00000080U; -} -static inline u32 minion_falcon_mailbox1_r(void) -{ - return 0x00000044U; -} -static inline u32 minion_minion_intr_r(void) -{ - return 0x00000810U; -} -static inline u32 minion_minion_intr_fatal_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 minion_minion_intr_fatal_m(void) -{ - return 0x1U << 0U; -} -static inline u32 minion_minion_intr_fatal_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 minion_minion_intr_nonfatal_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 minion_minion_intr_nonfatal_m(void) -{ - return 0x1U << 1U; -} -static inline u32 minion_minion_intr_nonfatal_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 minion_minion_intr_falcon_stall_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 minion_minion_intr_falcon_stall_m(void) -{ - return 0x1U << 2U; -} -static inline u32 minion_minion_intr_falcon_stall_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 minion_minion_intr_falcon_nostall_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 minion_minion_intr_falcon_nostall_m(void) -{ - return 0x1U << 3U; -} -static inline u32 minion_minion_intr_falcon_nostall_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 minion_minion_intr_link_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 minion_minion_intr_link_m(void) -{ - return 0xffffU << 16U; -} -static inline u32 minion_minion_intr_link_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 minion_minion_intr_nonstall_en_r(void) -{ - return 0x0000081cU; -} -static inline u32 minion_minion_intr_stall_en_r(void) -{ - return 0x00000818U; -} -static inline u32 minion_minion_intr_stall_en_fatal_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 minion_minion_intr_stall_en_fatal_m(void) -{ - return 0x1U << 0U; -} -static inline u32 minion_minion_intr_stall_en_fatal_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 minion_minion_intr_stall_en_fatal_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_minion_intr_stall_en_fatal_enable_f(void) -{ - return 0x1U; -} -static inline u32 minion_minion_intr_stall_en_fatal_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_minion_intr_stall_en_fatal_disable_f(void) -{ - return 0x0U; -} -static inline u32 minion_minion_intr_stall_en_nonfatal_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 minion_minion_intr_stall_en_nonfatal_m(void) -{ - return 0x1U << 1U; -} -static inline u32 minion_minion_intr_stall_en_nonfatal_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 minion_minion_intr_stall_en_nonfatal_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_minion_intr_stall_en_nonfatal_enable_f(void) -{ - return 0x2U; -} -static inline u32 minion_minion_intr_stall_en_nonfatal_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_minion_intr_stall_en_nonfatal_disable_f(void) -{ - return 0x0U; -} -static inline u32 minion_minion_intr_stall_en_falcon_stall_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 minion_minion_intr_stall_en_falcon_stall_m(void) -{ - return 0x1U << 2U; -} -static inline u32 minion_minion_intr_stall_en_falcon_stall_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 minion_minion_intr_stall_en_falcon_stall_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_minion_intr_stall_en_falcon_stall_enable_f(void) -{ - return 0x4U; -} -static inline u32 minion_minion_intr_stall_en_falcon_stall_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_minion_intr_stall_en_falcon_stall_disable_f(void) -{ - return 0x0U; -} -static inline u32 minion_minion_intr_stall_en_falcon_nostall_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 minion_minion_intr_stall_en_falcon_nostall_m(void) -{ - return 0x1U << 3U; -} -static inline u32 minion_minion_intr_stall_en_falcon_nostall_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 minion_minion_intr_stall_en_falcon_nostall_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_minion_intr_stall_en_falcon_nostall_enable_f(void) -{ - return 0x8U; -} -static inline u32 minion_minion_intr_stall_en_falcon_nostall_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_minion_intr_stall_en_falcon_nostall_disable_f(void) -{ - return 0x0U; -} -static inline u32 minion_minion_intr_stall_en_link_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 minion_minion_intr_stall_en_link_m(void) -{ - return 0xffffU << 16U; -} -static inline u32 minion_minion_intr_stall_en_link_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 minion_nvlink_dl_cmd_r(u32 i) -{ - return 0x00000900U + i*4U; -} -static inline u32 minion_nvlink_dl_cmd___size_1_v(void) -{ - return 0x00000006U; -} -static inline u32 minion_nvlink_dl_cmd_command_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 minion_nvlink_dl_cmd_command_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 minion_nvlink_dl_cmd_command_configeom_v(void) -{ - return 0x00000040U; -} -static inline u32 minion_nvlink_dl_cmd_command_configeom_f(void) -{ - return 0x40U; -} -static inline u32 minion_nvlink_dl_cmd_command_nop_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_nvlink_dl_cmd_command_nop_f(void) -{ - return 0x0U; -} -static inline u32 minion_nvlink_dl_cmd_command_initphy_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_nvlink_dl_cmd_command_initphy_f(void) -{ - return 0x1U; -} -static inline u32 minion_nvlink_dl_cmd_command_initlaneenable_v(void) -{ - return 0x00000003U; -} -static inline u32 minion_nvlink_dl_cmd_command_initlaneenable_f(void) -{ - return 0x3U; -} -static inline u32 minion_nvlink_dl_cmd_command_initdlpl_v(void) -{ - return 0x00000004U; -} -static inline u32 minion_nvlink_dl_cmd_command_initdlpl_f(void) -{ - return 0x4U; -} -static inline u32 minion_nvlink_dl_cmd_command_lanedisable_v(void) -{ - return 0x00000008U; -} -static inline u32 minion_nvlink_dl_cmd_command_lanedisable_f(void) -{ - return 0x8U; -} -static inline u32 minion_nvlink_dl_cmd_command_fastlanedisable_v(void) -{ - return 0x00000009U; -} -static inline u32 minion_nvlink_dl_cmd_command_fastlanedisable_f(void) -{ - return 0x9U; -} -static inline u32 minion_nvlink_dl_cmd_command_laneshutdown_v(void) -{ - return 0x0000000cU; -} -static inline u32 minion_nvlink_dl_cmd_command_laneshutdown_f(void) -{ - return 0xcU; -} -static inline u32 minion_nvlink_dl_cmd_command_setacmode_v(void) -{ - return 0x0000000aU; -} -static inline u32 minion_nvlink_dl_cmd_command_setacmode_f(void) -{ - return 0xaU; -} -static inline u32 minion_nvlink_dl_cmd_command_clracmode_v(void) -{ - return 0x0000000bU; -} -static inline u32 minion_nvlink_dl_cmd_command_clracmode_f(void) -{ - return 0xbU; -} -static inline u32 minion_nvlink_dl_cmd_command_enablepm_v(void) -{ - return 0x00000010U; -} -static inline u32 minion_nvlink_dl_cmd_command_enablepm_f(void) -{ - return 0x10U; -} -static inline u32 minion_nvlink_dl_cmd_command_disablepm_v(void) -{ - return 0x00000011U; -} -static inline u32 minion_nvlink_dl_cmd_command_disablepm_f(void) -{ - return 0x11U; -} -static inline u32 minion_nvlink_dl_cmd_command_savestate_v(void) -{ - return 0x00000018U; -} -static inline u32 minion_nvlink_dl_cmd_command_savestate_f(void) -{ - return 0x18U; -} -static inline u32 minion_nvlink_dl_cmd_command_restorestate_v(void) -{ - return 0x00000019U; -} -static inline u32 minion_nvlink_dl_cmd_command_restorestate_f(void) -{ - return 0x19U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_0_v(void) -{ - return 0x00000020U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_0_f(void) -{ - return 0x20U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_1_v(void) -{ - return 0x00000021U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_1_f(void) -{ - return 0x21U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_2_v(void) -{ - return 0x00000022U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_2_f(void) -{ - return 0x22U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_3_v(void) -{ - return 0x00000023U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_3_f(void) -{ - return 0x23U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_4_v(void) -{ - return 0x00000024U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_4_f(void) -{ - return 0x24U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_5_v(void) -{ - return 0x00000025U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_5_f(void) -{ - return 0x25U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_6_v(void) -{ - return 0x00000026U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_6_f(void) -{ - return 0x26U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_7_v(void) -{ - return 0x00000027U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_7_f(void) -{ - return 0x27U; -} -static inline u32 minion_nvlink_dl_cmd_fault_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 minion_nvlink_dl_cmd_fault_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 minion_nvlink_dl_cmd_ready_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 minion_nvlink_dl_cmd_ready_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 minion_misc_0_r(void) -{ - return 0x000008b0U; -} -static inline u32 minion_misc_0_scratch_swrw_0_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 minion_misc_0_scratch_swrw_0_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 minion_nvlink_link_intr_r(u32 i) -{ - return 0x00000a00U + i*4U; -} -static inline u32 minion_nvlink_link_intr___size_1_v(void) -{ - return 0x00000006U; -} -static inline u32 minion_nvlink_link_intr_code_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 minion_nvlink_link_intr_code_m(void) -{ - return 0xffU << 0U; -} -static inline u32 minion_nvlink_link_intr_code_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 minion_nvlink_link_intr_code_na_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_nvlink_link_intr_code_na_f(void) -{ - return 0x0U; -} -static inline u32 minion_nvlink_link_intr_code_swreq_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_nvlink_link_intr_code_swreq_f(void) -{ - return 0x1U; -} -static inline u32 minion_nvlink_link_intr_code_dlreq_v(void) -{ - return 0x00000002U; -} -static inline u32 minion_nvlink_link_intr_code_dlreq_f(void) -{ - return 0x2U; -} -static inline u32 minion_nvlink_link_intr_code_pmdisabled_v(void) -{ - return 0x00000003U; -} -static inline u32 minion_nvlink_link_intr_code_pmdisabled_f(void) -{ - return 0x3U; -} -static inline u32 minion_nvlink_link_intr_subcode_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 minion_nvlink_link_intr_subcode_m(void) -{ - return 0xffU << 8U; -} -static inline u32 minion_nvlink_link_intr_subcode_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} -static inline u32 minion_nvlink_link_intr_state_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 minion_nvlink_link_intr_state_m(void) -{ - return 0x1U << 31U; -} -static inline u32 minion_nvlink_link_intr_state_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_nvl_gv100.h b/include/nvgpu/hw/gv100/hw_nvl_gv100.h deleted file mode 100644 index 2e4ec16..0000000 --- a/include/nvgpu/hw/gv100/hw_nvl_gv100.h +++ /dev/null @@ -1,1571 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_nvl_gv100_h_ -#define _hw_nvl_gv100_h_ - -static inline u32 nvl_link_state_r(void) -{ - return 0x00000000U; -} -static inline u32 nvl_link_state_state_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 nvl_link_state_state_m(void) -{ - return 0xffU << 0U; -} -static inline u32 nvl_link_state_state_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 nvl_link_state_state_init_v(void) -{ - return 0x00000000U; -} -static inline u32 nvl_link_state_state_init_f(void) -{ - return 0x0U; -} -static inline u32 nvl_link_state_state_hwcfg_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_state_state_hwcfg_f(void) -{ - return 0x1U; -} -static inline u32 nvl_link_state_state_swcfg_v(void) -{ - return 0x00000002U; -} -static inline u32 nvl_link_state_state_swcfg_f(void) -{ - return 0x2U; -} -static inline u32 nvl_link_state_state_active_v(void) -{ - return 0x00000003U; -} -static inline u32 nvl_link_state_state_active_f(void) -{ - return 0x3U; -} -static inline u32 nvl_link_state_state_fault_v(void) -{ - return 0x00000004U; -} -static inline u32 nvl_link_state_state_fault_f(void) -{ - return 0x4U; -} -static inline u32 nvl_link_state_state_rcvy_ac_v(void) -{ - return 0x00000008U; -} -static inline u32 nvl_link_state_state_rcvy_ac_f(void) -{ - return 0x8U; -} -static inline u32 nvl_link_state_state_rcvy_sw_v(void) -{ - return 0x00000009U; -} -static inline u32 nvl_link_state_state_rcvy_sw_f(void) -{ - return 0x9U; -} -static inline u32 nvl_link_state_state_rcvy_rx_v(void) -{ - return 0x0000000aU; -} -static inline u32 nvl_link_state_state_rcvy_rx_f(void) -{ - return 0xaU; -} -static inline u32 nvl_link_state_an0_busy_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 nvl_link_state_an0_busy_m(void) -{ - return 0x1U << 12U; -} -static inline u32 nvl_link_state_an0_busy_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 nvl_link_state_tl_busy_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 nvl_link_state_tl_busy_m(void) -{ - return 0x1U << 13U; -} -static inline u32 nvl_link_state_tl_busy_v(u32 r) -{ - return (r >> 13U) & 0x1U; -} -static inline u32 nvl_link_state_dbg_substate_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 nvl_link_state_dbg_substate_m(void) -{ - return 0xffffU << 16U; -} -static inline u32 nvl_link_state_dbg_substate_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 nvl_link_activity_r(void) -{ - return 0x0000000cU; -} -static inline u32 nvl_link_activity_blkact_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 nvl_link_activity_blkact_m(void) -{ - return 0x7U << 0U; -} -static inline u32 nvl_link_activity_blkact_v(u32 r) -{ - return (r >> 0U) & 0x7U; -} -static inline u32 nvl_sublink_activity_r(u32 i) -{ - return 0x00000010U + i*4U; -} -static inline u32 nvl_sublink_activity_blkact0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 nvl_sublink_activity_blkact0_m(void) -{ - return 0x7U << 0U; -} -static inline u32 nvl_sublink_activity_blkact0_v(u32 r) -{ - return (r >> 0U) & 0x7U; -} -static inline u32 nvl_sublink_activity_blkact1_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 nvl_sublink_activity_blkact1_m(void) -{ - return 0x7U << 8U; -} -static inline u32 nvl_sublink_activity_blkact1_v(u32 r) -{ - return (r >> 8U) & 0x7U; -} -static inline u32 nvl_link_config_r(void) -{ - return 0x00000018U; -} -static inline u32 nvl_link_config_ac_safe_en_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 nvl_link_config_ac_safe_en_m(void) -{ - return 0x1U << 30U; -} -static inline u32 nvl_link_config_ac_safe_en_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 nvl_link_config_ac_safe_en_on_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_config_ac_safe_en_on_f(void) -{ - return 0x40000000U; -} -static inline u32 nvl_link_config_link_en_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 nvl_link_config_link_en_m(void) -{ - return 0x1U << 31U; -} -static inline u32 nvl_link_config_link_en_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 nvl_link_config_link_en_on_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_config_link_en_on_f(void) -{ - return 0x80000000U; -} -static inline u32 nvl_link_change_r(void) -{ - return 0x00000040U; -} -static inline u32 nvl_link_change_oldstate_mask_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 nvl_link_change_oldstate_mask_m(void) -{ - return 0xfU << 16U; -} -static inline u32 nvl_link_change_oldstate_mask_v(u32 r) -{ - return (r >> 16U) & 0xfU; -} -static inline u32 nvl_link_change_oldstate_mask_dontcare_v(void) -{ - return 0x0000000fU; -} -static inline u32 nvl_link_change_oldstate_mask_dontcare_f(void) -{ - return 0xf0000U; -} -static inline u32 nvl_link_change_newstate_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 nvl_link_change_newstate_m(void) -{ - return 0xfU << 4U; -} -static inline u32 nvl_link_change_newstate_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 nvl_link_change_newstate_hwcfg_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_change_newstate_hwcfg_f(void) -{ - return 0x10U; -} -static inline u32 nvl_link_change_newstate_swcfg_v(void) -{ - return 0x00000002U; -} -static inline u32 nvl_link_change_newstate_swcfg_f(void) -{ - return 0x20U; -} -static inline u32 nvl_link_change_newstate_active_v(void) -{ - return 0x00000003U; -} -static inline u32 nvl_link_change_newstate_active_f(void) -{ - return 0x30U; -} -static inline u32 nvl_link_change_action_f(u32 v) -{ - return (v & 0x3U) << 2U; -} -static inline u32 nvl_link_change_action_m(void) -{ - return 0x3U << 2U; -} -static inline u32 nvl_link_change_action_v(u32 r) -{ - return (r >> 2U) & 0x3U; -} -static inline u32 nvl_link_change_action_ltssm_change_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_change_action_ltssm_change_f(void) -{ - return 0x4U; -} -static inline u32 nvl_link_change_status_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 nvl_link_change_status_m(void) -{ - return 0x3U << 0U; -} -static inline u32 nvl_link_change_status_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 nvl_link_change_status_done_v(void) -{ - return 0x00000000U; -} -static inline u32 nvl_link_change_status_done_f(void) -{ - return 0x0U; -} -static inline u32 nvl_link_change_status_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_change_status_busy_f(void) -{ - return 0x1U; -} -static inline u32 nvl_link_change_status_fault_v(void) -{ - return 0x00000002U; -} -static inline u32 nvl_link_change_status_fault_f(void) -{ - return 0x2U; -} -static inline u32 nvl_sublink_change_r(void) -{ - return 0x00000044U; -} -static inline u32 nvl_sublink_change_countdown_f(u32 v) -{ - return (v & 0xfffU) << 20U; -} -static inline u32 nvl_sublink_change_countdown_m(void) -{ - return 0xfffU << 20U; -} -static inline u32 nvl_sublink_change_countdown_v(u32 r) -{ - return (r >> 20U) & 0xfffU; -} -static inline u32 nvl_sublink_change_oldstate_mask_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 nvl_sublink_change_oldstate_mask_m(void) -{ - return 0xfU << 16U; -} -static inline u32 nvl_sublink_change_oldstate_mask_v(u32 r) -{ - return (r >> 16U) & 0xfU; -} -static inline u32 nvl_sublink_change_oldstate_mask_dontcare_v(void) -{ - return 0x0000000fU; -} -static inline u32 nvl_sublink_change_oldstate_mask_dontcare_f(void) -{ - return 0xf0000U; -} -static inline u32 nvl_sublink_change_sublink_f(u32 v) -{ - return (v & 0xfU) << 12U; -} -static inline u32 nvl_sublink_change_sublink_m(void) -{ - return 0xfU << 12U; -} -static inline u32 nvl_sublink_change_sublink_v(u32 r) -{ - return (r >> 12U) & 0xfU; -} -static inline u32 nvl_sublink_change_sublink_tx_v(void) -{ - return 0x00000000U; -} -static inline u32 nvl_sublink_change_sublink_tx_f(void) -{ - return 0x0U; -} -static inline u32 nvl_sublink_change_sublink_rx_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_sublink_change_sublink_rx_f(void) -{ - return 0x1000U; -} -static inline u32 nvl_sublink_change_newstate_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 nvl_sublink_change_newstate_m(void) -{ - return 0xfU << 4U; -} -static inline u32 nvl_sublink_change_newstate_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 nvl_sublink_change_newstate_hs_v(void) -{ - return 0x00000000U; -} -static inline u32 nvl_sublink_change_newstate_hs_f(void) -{ - return 0x0U; -} -static inline u32 nvl_sublink_change_newstate_eighth_v(void) -{ - return 0x00000004U; -} -static inline u32 nvl_sublink_change_newstate_eighth_f(void) -{ - return 0x40U; -} -static inline u32 nvl_sublink_change_newstate_train_v(void) -{ - return 0x00000005U; -} -static inline u32 nvl_sublink_change_newstate_train_f(void) -{ - return 0x50U; -} -static inline u32 nvl_sublink_change_newstate_safe_v(void) -{ - return 0x00000006U; -} -static inline u32 nvl_sublink_change_newstate_safe_f(void) -{ - return 0x60U; -} -static inline u32 nvl_sublink_change_newstate_off_v(void) -{ - return 0x00000007U; -} -static inline u32 nvl_sublink_change_newstate_off_f(void) -{ - return 0x70U; -} -static inline u32 nvl_sublink_change_action_f(u32 v) -{ - return (v & 0x3U) << 2U; -} -static inline u32 nvl_sublink_change_action_m(void) -{ - return 0x3U << 2U; -} -static inline u32 nvl_sublink_change_action_v(u32 r) -{ - return (r >> 2U) & 0x3U; -} -static inline u32 nvl_sublink_change_action_slsm_change_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_sublink_change_action_slsm_change_f(void) -{ - return 0x4U; -} -static inline u32 nvl_sublink_change_status_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 nvl_sublink_change_status_m(void) -{ - return 0x3U << 0U; -} -static inline u32 nvl_sublink_change_status_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 nvl_sublink_change_status_done_v(void) -{ - return 0x00000000U; -} -static inline u32 nvl_sublink_change_status_done_f(void) -{ - return 0x0U; -} -static inline u32 nvl_sublink_change_status_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_sublink_change_status_busy_f(void) -{ - return 0x1U; -} -static inline u32 nvl_sublink_change_status_fault_v(void) -{ - return 0x00000002U; -} -static inline u32 nvl_sublink_change_status_fault_f(void) -{ - return 0x2U; -} -static inline u32 nvl_link_test_r(void) -{ - return 0x00000048U; -} -static inline u32 nvl_link_test_mode_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 nvl_link_test_mode_m(void) -{ - return 0x1U << 0U; -} -static inline u32 nvl_link_test_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 nvl_link_test_mode_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_test_mode_enable_f(void) -{ - return 0x1U; -} -static inline u32 nvl_link_test_auto_hwcfg_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 nvl_link_test_auto_hwcfg_m(void) -{ - return 0x1U << 30U; -} -static inline u32 nvl_link_test_auto_hwcfg_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 nvl_link_test_auto_hwcfg_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_test_auto_hwcfg_enable_f(void) -{ - return 0x40000000U; -} -static inline u32 nvl_link_test_auto_nvhs_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 nvl_link_test_auto_nvhs_m(void) -{ - return 0x1U << 31U; -} -static inline u32 nvl_link_test_auto_nvhs_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 nvl_link_test_auto_nvhs_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_test_auto_nvhs_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 nvl_sl0_slsm_status_tx_r(void) -{ - return 0x00002024U; -} -static inline u32 nvl_sl0_slsm_status_tx_substate_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 nvl_sl0_slsm_status_tx_substate_m(void) -{ - return 0xfU << 0U; -} -static inline u32 nvl_sl0_slsm_status_tx_substate_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_m(void) -{ - return 0xfU << 4U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_hs_v(void) -{ - return 0x00000000U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_hs_f(void) -{ - return 0x0U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_eighth_v(void) -{ - return 0x00000004U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_eighth_f(void) -{ - return 0x40U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_train_v(void) -{ - return 0x00000005U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_train_f(void) -{ - return 0x50U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_off_v(void) -{ - return 0x00000007U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_off_f(void) -{ - return 0x70U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_safe_v(void) -{ - return 0x00000006U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_safe_f(void) -{ - return 0x60U; -} -static inline u32 nvl_sl1_slsm_status_rx_r(void) -{ - return 0x00003014U; -} -static inline u32 nvl_sl1_slsm_status_rx_substate_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 nvl_sl1_slsm_status_rx_substate_m(void) -{ - return 0xfU << 0U; -} -static inline u32 nvl_sl1_slsm_status_rx_substate_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_m(void) -{ - return 0xfU << 4U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_hs_v(void) -{ - return 0x00000000U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_hs_f(void) -{ - return 0x0U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_eighth_v(void) -{ - return 0x00000004U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_eighth_f(void) -{ - return 0x40U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_train_v(void) -{ - return 0x00000005U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_train_f(void) -{ - return 0x50U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_off_v(void) -{ - return 0x00000007U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_off_f(void) -{ - return 0x70U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_safe_v(void) -{ - return 0x00000006U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_safe_f(void) -{ - return 0x60U; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_r(void) -{ - return 0x00002008U; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_f(u32 v) -{ - return (v & 0x7ffU) << 0U; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_m(void) -{ - return 0x7ffU << 0U; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_v(u32 r) -{ - return (r >> 0U) & 0x7ffU; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_init_v(void) -{ - return 0x00000728U; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_init_f(void) -{ - return 0x728U; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_f(u32 v) -{ - return (v & 0x1fU) << 11U; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_m(void) -{ - return 0x1fU << 11U; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_v(u32 r) -{ - return (r >> 11U) & 0x1fU; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_init_v(void) -{ - return 0x0000000fU; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_init_f(void) -{ - return 0x7800U; -} -static inline u32 nvl_sl1_error_rate_ctrl_r(void) -{ - return 0x00003284U; -} -static inline u32 nvl_sl1_error_rate_ctrl_short_threshold_man_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 nvl_sl1_error_rate_ctrl_short_threshold_man_m(void) -{ - return 0x7U << 0U; -} -static inline u32 nvl_sl1_error_rate_ctrl_short_threshold_man_v(u32 r) -{ - return (r >> 0U) & 0x7U; -} -static inline u32 nvl_sl1_error_rate_ctrl_long_threshold_man_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 nvl_sl1_error_rate_ctrl_long_threshold_man_m(void) -{ - return 0x7U << 16U; -} -static inline u32 nvl_sl1_error_rate_ctrl_long_threshold_man_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 nvl_sl1_rxslsm_timeout_2_r(void) -{ - return 0x00003034U; -} -static inline u32 nvl_txiobist_configreg_r(void) -{ - return 0x00002e14U; -} -static inline u32 nvl_txiobist_configreg_io_bist_mode_in_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 nvl_txiobist_configreg_io_bist_mode_in_m(void) -{ - return 0x1U << 17U; -} -static inline u32 nvl_txiobist_configreg_io_bist_mode_in_v(u32 r) -{ - return (r >> 17U) & 0x1U; -} -static inline u32 nvl_txiobist_config_r(void) -{ - return 0x00002e10U; -} -static inline u32 nvl_txiobist_config_dpg_prbsseedld_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 nvl_txiobist_config_dpg_prbsseedld_m(void) -{ - return 0x1U << 2U; -} -static inline u32 nvl_txiobist_config_dpg_prbsseedld_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 nvl_intr_r(void) -{ - return 0x00000050U; -} -static inline u32 nvl_intr_tx_replay_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 nvl_intr_tx_replay_m(void) -{ - return 0x1U << 0U; -} -static inline u32 nvl_intr_tx_replay_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 nvl_intr_tx_recovery_short_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 nvl_intr_tx_recovery_short_m(void) -{ - return 0x1U << 1U; -} -static inline u32 nvl_intr_tx_recovery_short_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 nvl_intr_tx_recovery_long_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 nvl_intr_tx_recovery_long_m(void) -{ - return 0x1U << 2U; -} -static inline u32 nvl_intr_tx_recovery_long_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 nvl_intr_tx_fault_ram_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 nvl_intr_tx_fault_ram_m(void) -{ - return 0x1U << 4U; -} -static inline u32 nvl_intr_tx_fault_ram_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 nvl_intr_tx_fault_interface_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 nvl_intr_tx_fault_interface_m(void) -{ - return 0x1U << 5U; -} -static inline u32 nvl_intr_tx_fault_interface_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 nvl_intr_tx_fault_sublink_change_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 nvl_intr_tx_fault_sublink_change_m(void) -{ - return 0x1U << 8U; -} -static inline u32 nvl_intr_tx_fault_sublink_change_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 nvl_intr_rx_fault_sublink_change_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 nvl_intr_rx_fault_sublink_change_m(void) -{ - return 0x1U << 16U; -} -static inline u32 nvl_intr_rx_fault_sublink_change_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 nvl_intr_rx_fault_dl_protocol_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 nvl_intr_rx_fault_dl_protocol_m(void) -{ - return 0x1U << 20U; -} -static inline u32 nvl_intr_rx_fault_dl_protocol_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 nvl_intr_rx_short_error_rate_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 nvl_intr_rx_short_error_rate_m(void) -{ - return 0x1U << 21U; -} -static inline u32 nvl_intr_rx_short_error_rate_v(u32 r) -{ - return (r >> 21U) & 0x1U; -} -static inline u32 nvl_intr_rx_long_error_rate_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 nvl_intr_rx_long_error_rate_m(void) -{ - return 0x1U << 22U; -} -static inline u32 nvl_intr_rx_long_error_rate_v(u32 r) -{ - return (r >> 22U) & 0x1U; -} -static inline u32 nvl_intr_rx_ila_trigger_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 nvl_intr_rx_ila_trigger_m(void) -{ - return 0x1U << 23U; -} -static inline u32 nvl_intr_rx_ila_trigger_v(u32 r) -{ - return (r >> 23U) & 0x1U; -} -static inline u32 nvl_intr_rx_crc_counter_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 nvl_intr_rx_crc_counter_m(void) -{ - return 0x1U << 24U; -} -static inline u32 nvl_intr_rx_crc_counter_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 nvl_intr_ltssm_fault_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 nvl_intr_ltssm_fault_m(void) -{ - return 0x1U << 28U; -} -static inline u32 nvl_intr_ltssm_fault_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 nvl_intr_ltssm_protocol_f(u32 v) -{ - return (v & 0x1U) << 29U; -} -static inline u32 nvl_intr_ltssm_protocol_m(void) -{ - return 0x1U << 29U; -} -static inline u32 nvl_intr_ltssm_protocol_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 nvl_intr_minion_request_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 nvl_intr_minion_request_m(void) -{ - return 0x1U << 30U; -} -static inline u32 nvl_intr_minion_request_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 nvl_intr_sw2_r(void) -{ - return 0x00000054U; -} -static inline u32 nvl_intr_minion_r(void) -{ - return 0x00000060U; -} -static inline u32 nvl_intr_minion_tx_replay_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 nvl_intr_minion_tx_replay_m(void) -{ - return 0x1U << 0U; -} -static inline u32 nvl_intr_minion_tx_replay_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 nvl_intr_minion_tx_recovery_short_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 nvl_intr_minion_tx_recovery_short_m(void) -{ - return 0x1U << 1U; -} -static inline u32 nvl_intr_minion_tx_recovery_short_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 nvl_intr_minion_tx_recovery_long_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 nvl_intr_minion_tx_recovery_long_m(void) -{ - return 0x1U << 2U; -} -static inline u32 nvl_intr_minion_tx_recovery_long_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 nvl_intr_minion_tx_fault_ram_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 nvl_intr_minion_tx_fault_ram_m(void) -{ - return 0x1U << 4U; -} -static inline u32 nvl_intr_minion_tx_fault_ram_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 nvl_intr_minion_tx_fault_interface_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 nvl_intr_minion_tx_fault_interface_m(void) -{ - return 0x1U << 5U; -} -static inline u32 nvl_intr_minion_tx_fault_interface_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 nvl_intr_minion_tx_fault_sublink_change_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 nvl_intr_minion_tx_fault_sublink_change_m(void) -{ - return 0x1U << 8U; -} -static inline u32 nvl_intr_minion_tx_fault_sublink_change_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 nvl_intr_minion_rx_fault_sublink_change_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 nvl_intr_minion_rx_fault_sublink_change_m(void) -{ - return 0x1U << 16U; -} -static inline u32 nvl_intr_minion_rx_fault_sublink_change_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 nvl_intr_minion_rx_fault_dl_protocol_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 nvl_intr_minion_rx_fault_dl_protocol_m(void) -{ - return 0x1U << 20U; -} -static inline u32 nvl_intr_minion_rx_fault_dl_protocol_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 nvl_intr_minion_rx_short_error_rate_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 nvl_intr_minion_rx_short_error_rate_m(void) -{ - return 0x1U << 21U; -} -static inline u32 nvl_intr_minion_rx_short_error_rate_v(u32 r) -{ - return (r >> 21U) & 0x1U; -} -static inline u32 nvl_intr_minion_rx_long_error_rate_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 nvl_intr_minion_rx_long_error_rate_m(void) -{ - return 0x1U << 22U; -} -static inline u32 nvl_intr_minion_rx_long_error_rate_v(u32 r) -{ - return (r >> 22U) & 0x1U; -} -static inline u32 nvl_intr_minion_rx_ila_trigger_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 nvl_intr_minion_rx_ila_trigger_m(void) -{ - return 0x1U << 23U; -} -static inline u32 nvl_intr_minion_rx_ila_trigger_v(u32 r) -{ - return (r >> 23U) & 0x1U; -} -static inline u32 nvl_intr_minion_rx_crc_counter_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 nvl_intr_minion_rx_crc_counter_m(void) -{ - return 0x1U << 24U; -} -static inline u32 nvl_intr_minion_rx_crc_counter_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 nvl_intr_minion_ltssm_fault_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 nvl_intr_minion_ltssm_fault_m(void) -{ - return 0x1U << 28U; -} -static inline u32 nvl_intr_minion_ltssm_fault_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 nvl_intr_minion_ltssm_protocol_f(u32 v) -{ - return (v & 0x1U) << 29U; -} -static inline u32 nvl_intr_minion_ltssm_protocol_m(void) -{ - return 0x1U << 29U; -} -static inline u32 nvl_intr_minion_ltssm_protocol_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 nvl_intr_minion_minion_request_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 nvl_intr_minion_minion_request_m(void) -{ - return 0x1U << 30U; -} -static inline u32 nvl_intr_minion_minion_request_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 nvl_intr_nonstall_en_r(void) -{ - return 0x0000005cU; -} -static inline u32 nvl_intr_stall_en_r(void) -{ - return 0x00000058U; -} -static inline u32 nvl_intr_stall_en_tx_replay_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 nvl_intr_stall_en_tx_replay_m(void) -{ - return 0x1U << 0U; -} -static inline u32 nvl_intr_stall_en_tx_replay_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_short_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_short_m(void) -{ - return 0x1U << 1U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_short_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_short_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_short_enable_f(void) -{ - return 0x2U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_long_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_long_m(void) -{ - return 0x1U << 2U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_long_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_long_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_long_enable_f(void) -{ - return 0x4U; -} -static inline u32 nvl_intr_stall_en_tx_fault_ram_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 nvl_intr_stall_en_tx_fault_ram_m(void) -{ - return 0x1U << 4U; -} -static inline u32 nvl_intr_stall_en_tx_fault_ram_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_tx_fault_ram_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_tx_fault_ram_enable_f(void) -{ - return 0x10U; -} -static inline u32 nvl_intr_stall_en_tx_fault_interface_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 nvl_intr_stall_en_tx_fault_interface_m(void) -{ - return 0x1U << 5U; -} -static inline u32 nvl_intr_stall_en_tx_fault_interface_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_tx_fault_interface_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_tx_fault_interface_enable_f(void) -{ - return 0x20U; -} -static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_m(void) -{ - return 0x1U << 8U; -} -static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_enable_f(void) -{ - return 0x100U; -} -static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_m(void) -{ - return 0x1U << 16U; -} -static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_enable_f(void) -{ - return 0x10000U; -} -static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_m(void) -{ - return 0x1U << 20U; -} -static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_enable_f(void) -{ - return 0x100000U; -} -static inline u32 nvl_intr_stall_en_rx_short_error_rate_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 nvl_intr_stall_en_rx_short_error_rate_m(void) -{ - return 0x1U << 21U; -} -static inline u32 nvl_intr_stall_en_rx_short_error_rate_v(u32 r) -{ - return (r >> 21U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_rx_short_error_rate_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_rx_short_error_rate_enable_f(void) -{ - return 0x200000U; -} -static inline u32 nvl_intr_stall_en_rx_long_error_rate_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 nvl_intr_stall_en_rx_long_error_rate_m(void) -{ - return 0x1U << 22U; -} -static inline u32 nvl_intr_stall_en_rx_long_error_rate_v(u32 r) -{ - return (r >> 22U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_rx_long_error_rate_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_rx_long_error_rate_enable_f(void) -{ - return 0x400000U; -} -static inline u32 nvl_intr_stall_en_rx_ila_trigger_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 nvl_intr_stall_en_rx_ila_trigger_m(void) -{ - return 0x1U << 23U; -} -static inline u32 nvl_intr_stall_en_rx_ila_trigger_v(u32 r) -{ - return (r >> 23U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_rx_ila_trigger_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_rx_ila_trigger_enable_f(void) -{ - return 0x800000U; -} -static inline u32 nvl_intr_stall_en_rx_crc_counter_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 nvl_intr_stall_en_rx_crc_counter_m(void) -{ - return 0x1U << 24U; -} -static inline u32 nvl_intr_stall_en_rx_crc_counter_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_rx_crc_counter_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_rx_crc_counter_enable_f(void) -{ - return 0x1000000U; -} -static inline u32 nvl_intr_stall_en_ltssm_fault_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 nvl_intr_stall_en_ltssm_fault_m(void) -{ - return 0x1U << 28U; -} -static inline u32 nvl_intr_stall_en_ltssm_fault_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_ltssm_fault_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_ltssm_fault_enable_f(void) -{ - return 0x10000000U; -} -static inline u32 nvl_intr_stall_en_ltssm_protocol_f(u32 v) -{ - return (v & 0x1U) << 29U; -} -static inline u32 nvl_intr_stall_en_ltssm_protocol_m(void) -{ - return 0x1U << 29U; -} -static inline u32 nvl_intr_stall_en_ltssm_protocol_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_ltssm_protocol_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_ltssm_protocol_enable_f(void) -{ - return 0x20000000U; -} -static inline u32 nvl_intr_stall_en_minion_request_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 nvl_intr_stall_en_minion_request_m(void) -{ - return 0x1U << 30U; -} -static inline u32 nvl_intr_stall_en_minion_request_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_minion_request_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_minion_request_enable_f(void) -{ - return 0x40000000U; -} -static inline u32 nvl_br0_cfg_cal_r(void) -{ - return 0x0000281cU; -} -static inline u32 nvl_br0_cfg_cal_rxcal_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 nvl_br0_cfg_cal_rxcal_m(void) -{ - return 0x1U << 0U; -} -static inline u32 nvl_br0_cfg_cal_rxcal_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 nvl_br0_cfg_cal_rxcal_on_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_br0_cfg_cal_rxcal_on_f(void) -{ - return 0x1U; -} -static inline u32 nvl_br0_cfg_status_cal_r(void) -{ - return 0x00002838U; -} -static inline u32 nvl_br0_cfg_status_cal_rxcal_done_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 nvl_br0_cfg_status_cal_rxcal_done_m(void) -{ - return 0x1U << 2U; -} -static inline u32 nvl_br0_cfg_status_cal_rxcal_done_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_nvlinkip_discovery_gv100.h b/include/nvgpu/hw/gv100/hw_nvlinkip_discovery_gv100.h deleted file mode 100644 index 9d33a9f..0000000 --- a/include/nvgpu/hw/gv100/hw_nvlinkip_discovery_gv100.h +++ /dev/null @@ -1,311 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_nvlinkip_discovery_gv100_h_ -#define _hw_nvlinkip_discovery_gv100_h_ - -static inline u32 nvlinkip_discovery_common_r(void) -{ - return 0x00000000U; -} -static inline u32 nvlinkip_discovery_common_entry_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 nvlinkip_discovery_common_entry_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 nvlinkip_discovery_common_entry_invalid_v(void) -{ - return 0x00000000U; -} -static inline u32 nvlinkip_discovery_common_entry_enum_v(void) -{ - return 0x00000001U; -} -static inline u32 nvlinkip_discovery_common_entry_data1_v(void) -{ - return 0x00000002U; -} -static inline u32 nvlinkip_discovery_common_entry_data2_v(void) -{ - return 0x00000003U; -} -static inline u32 nvlinkip_discovery_common_contents_f(u32 v) -{ - return (v & 0x1fffffffU) << 2U; -} -static inline u32 nvlinkip_discovery_common_contents_v(u32 r) -{ - return (r >> 2U) & 0x1fffffffU; -} -static inline u32 nvlinkip_discovery_common_chain_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 nvlinkip_discovery_common_chain_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 nvlinkip_discovery_common_chain_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvlinkip_discovery_common_device_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 nvlinkip_discovery_common_device_v(u32 r) -{ - return (r >> 2U) & 0x3fU; -} -static inline u32 nvlinkip_discovery_common_device_invalid_v(void) -{ - return 0x00000000U; -} -static inline u32 nvlinkip_discovery_common_device_ioctrl_v(void) -{ - return 0x00000001U; -} -static inline u32 nvlinkip_discovery_common_device_nvltl_v(void) -{ - return 0x00000002U; -} -static inline u32 nvlinkip_discovery_common_device_nvlink_v(void) -{ - return 0x00000003U; -} -static inline u32 nvlinkip_discovery_common_device_minion_v(void) -{ - return 0x00000004U; -} -static inline u32 nvlinkip_discovery_common_device_nvlipt_v(void) -{ - return 0x00000005U; -} -static inline u32 nvlinkip_discovery_common_device_nvltlc_v(void) -{ - return 0x00000006U; -} -static inline u32 nvlinkip_discovery_common_device_dlpl_v(void) -{ - return 0x0000000bU; -} -static inline u32 nvlinkip_discovery_common_device_ioctrlmif_v(void) -{ - return 0x00000007U; -} -static inline u32 nvlinkip_discovery_common_device_dlpl_multicast_v(void) -{ - return 0x00000008U; -} -static inline u32 nvlinkip_discovery_common_device_nvltlc_multicast_v(void) -{ - return 0x00000009U; -} -static inline u32 nvlinkip_discovery_common_device_ioctrlmif_multicast_v(void) -{ - return 0x0000000aU; -} -static inline u32 nvlinkip_discovery_common_device_sioctrl_v(void) -{ - return 0x0000000cU; -} -static inline u32 nvlinkip_discovery_common_device_tioctrl_v(void) -{ - return 0x0000000dU; -} -static inline u32 nvlinkip_discovery_common_id_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 nvlinkip_discovery_common_id_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} -static inline u32 nvlinkip_discovery_common_version_f(u32 v) -{ - return (v & 0x7ffU) << 20U; -} -static inline u32 nvlinkip_discovery_common_version_v(u32 r) -{ - return (r >> 20U) & 0x7ffU; -} -static inline u32 nvlinkip_discovery_common_pri_base_f(u32 v) -{ - return (v & 0xfffU) << 12U; -} -static inline u32 nvlinkip_discovery_common_pri_base_v(u32 r) -{ - return (r >> 12U) & 0xfffU; -} -static inline u32 nvlinkip_discovery_common_intr_f(u32 v) -{ - return (v & 0x1fU) << 7U; -} -static inline u32 nvlinkip_discovery_common_intr_v(u32 r) -{ - return (r >> 7U) & 0x1fU; -} -static inline u32 nvlinkip_discovery_common_reset_f(u32 v) -{ - return (v & 0x1fU) << 2U; -} -static inline u32 nvlinkip_discovery_common_reset_v(u32 r) -{ - return (r >> 2U) & 0x1fU; -} -static inline u32 nvlinkip_discovery_common_ioctrl_length_f(u32 v) -{ - return (v & 0x3fU) << 24U; -} -static inline u32 nvlinkip_discovery_common_ioctrl_length_v(u32 r) -{ - return (r >> 24U) & 0x3fU; -} -static inline u32 nvlinkip_discovery_common_dlpl_num_tx_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 nvlinkip_discovery_common_dlpl_num_tx_v(u32 r) -{ - return (r >> 24U) & 0x7U; -} -static inline u32 nvlinkip_discovery_common_dlpl_num_rx_f(u32 v) -{ - return (v & 0x7U) << 27U; -} -static inline u32 nvlinkip_discovery_common_dlpl_num_rx_v(u32 r) -{ - return (r >> 27U) & 0x7U; -} -static inline u32 nvlinkip_discovery_common_data1_ioctrl_length_f(u32 v) -{ - return (v & 0x7ffffU) << 12U; -} -static inline u32 nvlinkip_discovery_common_data1_ioctrl_length_v(u32 r) -{ - return (r >> 12U) & 0x7ffffU; -} -static inline u32 nvlinkip_discovery_common_data2_type_f(u32 v) -{ - return (v & 0x1fU) << 26U; -} -static inline u32 nvlinkip_discovery_common_data2_type_v(u32 r) -{ - return (r >> 26U) & 0x1fU; -} -static inline u32 nvlinkip_discovery_common_data2_type_invalid_v(void) -{ - return 0x00000000U; -} -static inline u32 nvlinkip_discovery_common_data2_type_pllcontrol_v(void) -{ - return 0x00000001U; -} -static inline u32 nvlinkip_discovery_common_data2_type_resetreg_v(void) -{ - return 0x00000002U; -} -static inline u32 nvlinkip_discovery_common_data2_type_intrreg_v(void) -{ - return 0x00000003U; -} -static inline u32 nvlinkip_discovery_common_data2_type_discovery_v(void) -{ - return 0x00000004U; -} -static inline u32 nvlinkip_discovery_common_data2_type_unicast_v(void) -{ - return 0x00000005U; -} -static inline u32 nvlinkip_discovery_common_data2_type_broadcast_v(void) -{ - return 0x00000006U; -} -static inline u32 nvlinkip_discovery_common_data2_addr_f(u32 v) -{ - return (v & 0xffffffU) << 2U; -} -static inline u32 nvlinkip_discovery_common_data2_addr_v(u32 r) -{ - return (r >> 2U) & 0xffffffU; -} -static inline u32 nvlinkip_discovery_common_dlpl_data2_type_f(u32 v) -{ - return (v & 0x1fU) << 26U; -} -static inline u32 nvlinkip_discovery_common_dlpl_data2_type_v(u32 r) -{ - return (r >> 26U) & 0x1fU; -} -static inline u32 nvlinkip_discovery_common_dlpl_data2_master_f(u32 v) -{ - return (v & 0x1U) << 15U; -} -static inline u32 nvlinkip_discovery_common_dlpl_data2_master_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 nvlinkip_discovery_common_dlpl_data2_masterid_f(u32 v) -{ - return (v & 0x7fU) << 8U; -} -static inline u32 nvlinkip_discovery_common_dlpl_data2_masterid_v(u32 r) -{ - return (r >> 8U) & 0x7fU; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_nvlipt_gv100.h b/include/nvgpu/hw/gv100/hw_nvlipt_gv100.h deleted file mode 100644 index 5f73fab..0000000 --- a/include/nvgpu/hw/gv100/hw_nvlipt_gv100.h +++ /dev/null @@ -1,279 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_nvlipt_gv100_h_ -#define _hw_nvlipt_gv100_h_ - -static inline u32 nvlipt_intr_control_link0_r(void) -{ - return 0x000004b4U; -} -static inline u32 nvlipt_intr_control_link0_stallenable_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 nvlipt_intr_control_link0_stallenable_m(void) -{ - return 0x1U << 0U; -} -static inline u32 nvlipt_intr_control_link0_stallenable_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 nvlipt_intr_control_link0_nostallenable_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 nvlipt_intr_control_link0_nostallenable_m(void) -{ - return 0x1U << 1U; -} -static inline u32 nvlipt_intr_control_link0_nostallenable_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_r(void) -{ - return 0x00000524U; -} -static inline u32 nvlipt_err_uc_status_link0_dlprotocol_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 nvlipt_err_uc_status_link0_dlprotocol_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_datapoisoned_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 nvlipt_err_uc_status_link0_datapoisoned_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_flowcontrol_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 nvlipt_err_uc_status_link0_flowcontrol_v(u32 r) -{ - return (r >> 13U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_responsetimeout_f(u32 v) -{ - return (v & 0x1U) << 14U; -} -static inline u32 nvlipt_err_uc_status_link0_responsetimeout_v(u32 r) -{ - return (r >> 14U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_targeterror_f(u32 v) -{ - return (v & 0x1U) << 15U; -} -static inline u32 nvlipt_err_uc_status_link0_targeterror_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_unexpectedresponse_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 nvlipt_err_uc_status_link0_unexpectedresponse_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_receiveroverflow_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 nvlipt_err_uc_status_link0_receiveroverflow_v(u32 r) -{ - return (r >> 17U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_malformedpacket_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 nvlipt_err_uc_status_link0_malformedpacket_v(u32 r) -{ - return (r >> 18U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_stompedpacketreceived_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 nvlipt_err_uc_status_link0_stompedpacketreceived_v(u32 r) -{ - return (r >> 19U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_unsupportedrequest_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 nvlipt_err_uc_status_link0_unsupportedrequest_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_ucinternal_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 nvlipt_err_uc_status_link0_ucinternal_v(u32 r) -{ - return (r >> 22U) & 0x1U; -} -static inline u32 nvlipt_err_uc_mask_link0_r(void) -{ - return 0x00000528U; -} -static inline u32 nvlipt_err_uc_severity_link0_r(void) -{ - return 0x0000052cU; -} -static inline u32 nvlipt_err_uc_first_link0_r(void) -{ - return 0x00000530U; -} -static inline u32 nvlipt_err_uc_advisory_link0_r(void) -{ - return 0x00000534U; -} -static inline u32 nvlipt_err_c_status_link0_r(void) -{ - return 0x00000538U; -} -static inline u32 nvlipt_err_c_mask_link0_r(void) -{ - return 0x0000053cU; -} -static inline u32 nvlipt_err_c_first_link0_r(void) -{ - return 0x00000540U; -} -static inline u32 nvlipt_err_control_link0_r(void) -{ - return 0x00000544U; -} -static inline u32 nvlipt_err_control_link0_fatalenable_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 nvlipt_err_control_link0_fatalenable_m(void) -{ - return 0x1U << 1U; -} -static inline u32 nvlipt_err_control_link0_fatalenable_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 nvlipt_err_control_link0_nonfatalenable_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 nvlipt_err_control_link0_nonfatalenable_m(void) -{ - return 0x1U << 2U; -} -static inline u32 nvlipt_err_control_link0_nonfatalenable_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 nvlipt_intr_control_common_r(void) -{ - return 0x000004b0U; -} -static inline u32 nvlipt_intr_control_common_stallenable_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 nvlipt_intr_control_common_stallenable_m(void) -{ - return 0x1U << 0U; -} -static inline u32 nvlipt_intr_control_common_stallenable_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 nvlipt_intr_control_common_nonstallenable_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 nvlipt_intr_control_common_nonstallenable_m(void) -{ - return 0x1U << 1U; -} -static inline u32 nvlipt_intr_control_common_nonstallenable_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 nvlipt_scratch_cold_r(void) -{ - return 0x000007d4U; -} -static inline u32 nvlipt_scratch_cold_data_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 nvlipt_scratch_cold_data_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 nvlipt_scratch_cold_data_init_v(void) -{ - return 0xdeadbaadU; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_nvtlc_gv100.h b/include/nvgpu/hw/gv100/hw_nvtlc_gv100.h deleted file mode 100644 index cc31b12..0000000 --- a/include/nvgpu/hw/gv100/hw_nvtlc_gv100.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_nvtlc_gv100_h_ -#define _hw_nvtlc_gv100_h_ - -static inline u32 nvtlc_tx_err_report_en_0_r(void) -{ - return 0x00000708U; -} -static inline u32 nvtlc_rx_err_report_en_0_r(void) -{ - return 0x00000f08U; -} -static inline u32 nvtlc_rx_err_report_en_1_r(void) -{ - return 0x00000f20U; -} -static inline u32 nvtlc_tx_err_status_0_r(void) -{ - return 0x00000700U; -} -static inline u32 nvtlc_rx_err_status_0_r(void) -{ - return 0x00000f00U; -} -static inline u32 nvtlc_rx_err_status_1_r(void) -{ - return 0x00000f18U; -} -static inline u32 nvtlc_tx_err_first_0_r(void) -{ - return 0x00000714U; -} -static inline u32 nvtlc_rx_err_first_0_r(void) -{ - return 0x00000f14U; -} -static inline u32 nvtlc_rx_err_first_1_r(void) -{ - return 0x00000f2cU; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_pbdma_gv100.h b/include/nvgpu/hw/gv100/hw_pbdma_gv100.h deleted file mode 100644 index 41d7d1b..0000000 --- a/include/nvgpu/hw/gv100/hw_pbdma_gv100.h +++ /dev/null @@ -1,651 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pbdma_gv100_h_ -#define _hw_pbdma_gv100_h_ - -static inline u32 pbdma_gp_entry1_r(void) -{ - return 0x10000004U; -} -static inline u32 pbdma_gp_entry1_get_hi_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pbdma_gp_entry1_length_f(u32 v) -{ - return (v & 0x1fffffU) << 10U; -} -static inline u32 pbdma_gp_entry1_length_v(u32 r) -{ - return (r >> 10U) & 0x1fffffU; -} -static inline u32 pbdma_gp_base_r(u32 i) -{ - return 0x00040048U + i*8192U; -} -static inline u32 pbdma_gp_base__size_1_v(void) -{ - return 0x0000000eU; -} -static inline u32 pbdma_gp_base_offset_f(u32 v) -{ - return (v & 0x1fffffffU) << 3U; -} -static inline u32 pbdma_gp_base_rsvd_s(void) -{ - return 3U; -} -static inline u32 pbdma_gp_base_hi_r(u32 i) -{ - return 0x0004004cU + i*8192U; -} -static inline u32 pbdma_gp_base_hi_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pbdma_gp_base_hi_limit2_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 pbdma_gp_fetch_r(u32 i) -{ - return 0x00040050U + i*8192U; -} -static inline u32 pbdma_gp_get_r(u32 i) -{ - return 0x00040014U + i*8192U; -} -static inline u32 pbdma_gp_put_r(u32 i) -{ - return 0x00040000U + i*8192U; -} -static inline u32 pbdma_pb_fetch_r(u32 i) -{ - return 0x00040054U + i*8192U; -} -static inline u32 pbdma_pb_fetch_hi_r(u32 i) -{ - return 0x00040058U + i*8192U; -} -static inline u32 pbdma_get_r(u32 i) -{ - return 0x00040018U + i*8192U; -} -static inline u32 pbdma_get_hi_r(u32 i) -{ - return 0x0004001cU + i*8192U; -} -static inline u32 pbdma_put_r(u32 i) -{ - return 0x0004005cU + i*8192U; -} -static inline u32 pbdma_put_hi_r(u32 i) -{ - return 0x00040060U + i*8192U; -} -static inline u32 pbdma_pb_header_r(u32 i) -{ - return 0x00040084U + i*8192U; -} -static inline u32 pbdma_pb_header_priv_user_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_method_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_subchannel_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_level_main_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_first_true_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_pb_header_type_inc_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_pb_header_type_non_inc_f(void) -{ - return 0x60000000U; -} -static inline u32 pbdma_hdr_shadow_r(u32 i) -{ - return 0x00040118U + i*8192U; -} -static inline u32 pbdma_gp_shadow_0_r(u32 i) -{ - return 0x00040110U + i*8192U; -} -static inline u32 pbdma_gp_shadow_1_r(u32 i) -{ - return 0x00040114U + i*8192U; -} -static inline u32 pbdma_subdevice_r(u32 i) -{ - return 0x00040094U + i*8192U; -} -static inline u32 pbdma_subdevice_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 pbdma_subdevice_status_active_f(void) -{ - return 0x10000000U; -} -static inline u32 pbdma_subdevice_channel_dma_enable_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_method0_r(u32 i) -{ - return 0x000400c0U + i*8192U; -} -static inline u32 pbdma_method0_fifo_size_v(void) -{ - return 0x00000004U; -} -static inline u32 pbdma_method0_addr_f(u32 v) -{ - return (v & 0xfffU) << 2U; -} -static inline u32 pbdma_method0_addr_v(u32 r) -{ - return (r >> 2U) & 0xfffU; -} -static inline u32 pbdma_method0_subch_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 pbdma_method0_first_true_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_method0_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_method1_r(u32 i) -{ - return 0x000400c8U + i*8192U; -} -static inline u32 pbdma_method2_r(u32 i) -{ - return 0x000400d0U + i*8192U; -} -static inline u32 pbdma_method3_r(u32 i) -{ - return 0x000400d8U + i*8192U; -} -static inline u32 pbdma_data0_r(u32 i) -{ - return 0x000400c4U + i*8192U; -} -static inline u32 pbdma_acquire_r(u32 i) -{ - return 0x00040030U + i*8192U; -} -static inline u32 pbdma_acquire_retry_man_2_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_acquire_retry_exp_2_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_acquire_timeout_exp_f(u32 v) -{ - return (v & 0xfU) << 11U; -} -static inline u32 pbdma_acquire_timeout_exp_max_v(void) -{ - return 0x0000000fU; -} -static inline u32 pbdma_acquire_timeout_exp_max_f(void) -{ - return 0x7800U; -} -static inline u32 pbdma_acquire_timeout_man_f(u32 v) -{ - return (v & 0xffffU) << 15U; -} -static inline u32 pbdma_acquire_timeout_man_max_v(void) -{ - return 0x0000ffffU; -} -static inline u32 pbdma_acquire_timeout_man_max_f(void) -{ - return 0x7fff8000U; -} -static inline u32 pbdma_acquire_timeout_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_acquire_timeout_en_disable_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_status_r(u32 i) -{ - return 0x00040100U + i*8192U; -} -static inline u32 pbdma_channel_r(u32 i) -{ - return 0x00040120U + i*8192U; -} -static inline u32 pbdma_signature_r(u32 i) -{ - return 0x00040010U + i*8192U; -} -static inline u32 pbdma_signature_hw_valid_f(void) -{ - return 0xfaceU; -} -static inline u32 pbdma_signature_sw_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_userd_r(u32 i) -{ - return 0x00040008U + i*8192U; -} -static inline u32 pbdma_userd_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_userd_target_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 pbdma_userd_addr_f(u32 v) -{ - return (v & 0x7fffffU) << 9U; -} -static inline u32 pbdma_config_r(u32 i) -{ - return 0x000400f4U + i*8192U; -} -static inline u32 pbdma_config_l2_evict_first_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_config_l2_evict_normal_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_config_ce_split_enable_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_config_ce_split_disable_f(void) -{ - return 0x10U; -} -static inline u32 pbdma_config_auth_level_non_privileged_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_config_auth_level_privileged_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_config_userd_writeback_disable_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_config_userd_writeback_enable_f(void) -{ - return 0x1000U; -} -static inline u32 pbdma_userd_hi_r(u32 i) -{ - return 0x0004000cU + i*8192U; -} -static inline u32 pbdma_userd_hi_addr_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pbdma_hce_ctrl_r(u32 i) -{ - return 0x000400e4U + i*8192U; -} -static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void) -{ - return 0x20U; -} -static inline u32 pbdma_intr_0_r(u32 i) -{ - return 0x00040108U + i*8192U; -} -static inline u32 pbdma_intr_0_memreq_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pbdma_intr_0_memreq_pending_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_intr_0_memack_timeout_pending_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_intr_0_memack_extra_pending_f(void) -{ - return 0x4U; -} -static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void) -{ - return 0x8U; -} -static inline u32 pbdma_intr_0_memdat_extra_pending_f(void) -{ - return 0x10U; -} -static inline u32 pbdma_intr_0_memflush_pending_f(void) -{ - return 0x20U; -} -static inline u32 pbdma_intr_0_memop_pending_f(void) -{ - return 0x40U; -} -static inline u32 pbdma_intr_0_lbconnect_pending_f(void) -{ - return 0x80U; -} -static inline u32 pbdma_intr_0_lbreq_pending_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_0_lback_timeout_pending_f(void) -{ - return 0x200U; -} -static inline u32 pbdma_intr_0_lback_extra_pending_f(void) -{ - return 0x400U; -} -static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void) -{ - return 0x800U; -} -static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void) -{ - return 0x1000U; -} -static inline u32 pbdma_intr_0_gpfifo_pending_f(void) -{ - return 0x2000U; -} -static inline u32 pbdma_intr_0_gpptr_pending_f(void) -{ - return 0x4000U; -} -static inline u32 pbdma_intr_0_gpentry_pending_f(void) -{ - return 0x8000U; -} -static inline u32 pbdma_intr_0_gpcrc_pending_f(void) -{ - return 0x10000U; -} -static inline u32 pbdma_intr_0_pbptr_pending_f(void) -{ - return 0x20000U; -} -static inline u32 pbdma_intr_0_pbentry_pending_f(void) -{ - return 0x40000U; -} -static inline u32 pbdma_intr_0_pbcrc_pending_f(void) -{ - return 0x80000U; -} -static inline u32 pbdma_intr_0_clear_faulted_error_pending_f(void) -{ - return 0x100000U; -} -static inline u32 pbdma_intr_0_method_pending_f(void) -{ - return 0x200000U; -} -static inline u32 pbdma_intr_0_methodcrc_pending_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_intr_0_device_pending_f(void) -{ - return 0x800000U; -} -static inline u32 pbdma_intr_0_eng_reset_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 pbdma_intr_0_semaphore_pending_f(void) -{ - return 0x2000000U; -} -static inline u32 pbdma_intr_0_acquire_pending_f(void) -{ - return 0x4000000U; -} -static inline u32 pbdma_intr_0_pri_pending_f(void) -{ - return 0x8000000U; -} -static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_intr_0_pbseg_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 pbdma_intr_0_signature_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_intr_1_r(u32 i) -{ - return 0x00040148U + i*8192U; -} -static inline u32 pbdma_intr_1_ctxnotvalid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 pbdma_intr_1_ctxnotvalid_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_intr_en_0_r(u32 i) -{ - return 0x0004010cU + i*8192U; -} -static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_en_1_r(u32 i) -{ - return 0x0004014cU + i*8192U; -} -static inline u32 pbdma_intr_stall_r(u32 i) -{ - return 0x0004013cU + i*8192U; -} -static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_stall_1_r(u32 i) -{ - return 0x00040140U + i*8192U; -} -static inline u32 pbdma_intr_stall_1_hce_illegal_op_enabled_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_udma_nop_r(void) -{ - return 0x00000008U; -} -static inline u32 pbdma_runlist_timeslice_r(u32 i) -{ - return 0x000400f8U + i*8192U; -} -static inline u32 pbdma_runlist_timeslice_timeout_128_f(void) -{ - return 0x80U; -} -static inline u32 pbdma_runlist_timeslice_timescale_3_f(void) -{ - return 0x3000U; -} -static inline u32 pbdma_runlist_timeslice_enable_true_f(void) -{ - return 0x10000000U; -} -static inline u32 pbdma_target_r(u32 i) -{ - return 0x000400acU + i*8192U; -} -static inline u32 pbdma_target_engine_sw_f(void) -{ - return 0x1fU; -} -static inline u32 pbdma_target_eng_ctx_valid_true_f(void) -{ - return 0x10000U; -} -static inline u32 pbdma_target_eng_ctx_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_target_ce_ctx_valid_true_f(void) -{ - return 0x20000U; -} -static inline u32 pbdma_target_ce_ctx_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_target_host_tsg_event_reason_pbdma_idle_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_target_host_tsg_event_reason_semaphore_acquire_failure_f(void) -{ - return 0x1000000U; -} -static inline u32 pbdma_target_host_tsg_event_reason_tsg_yield_f(void) -{ - return 0x2000000U; -} -static inline u32 pbdma_target_host_tsg_event_reason_host_subchannel_switch_f(void) -{ - return 0x3000000U; -} -static inline u32 pbdma_target_should_send_tsg_event_true_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_target_should_send_tsg_event_false_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_target_needs_host_tsg_event_true_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_target_needs_host_tsg_event_false_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_set_channel_info_r(u32 i) -{ - return 0x000400fcU + i*8192U; -} -static inline u32 pbdma_set_channel_info_veid_f(u32 v) -{ - return (v & 0x3fU) << 8U; -} -static inline u32 pbdma_timeout_r(u32 i) -{ - return 0x0004012cU + i*8192U; -} -static inline u32 pbdma_timeout_period_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 pbdma_timeout_period_max_f(void) -{ - return 0xffffffffU; -} -static inline u32 pbdma_timeout_period_init_f(void) -{ - return 0x10000U; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_perf_gv100.h b/include/nvgpu/hw/gv100/hw_perf_gv100.h deleted file mode 100644 index 40107ee..0000000 --- a/include/nvgpu/hw/gv100/hw_perf_gv100.h +++ /dev/null @@ -1,263 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_perf_gv100_h_ -#define _hw_perf_gv100_h_ - -static inline u32 perf_pmmgpc_perdomain_offset_v(void) -{ - return 0x00000200U; -} -static inline u32 perf_pmmsys_perdomain_offset_v(void) -{ - return 0x00000200U; -} -static inline u32 perf_pmmgpc_base_v(void) -{ - return 0x00180000U; -} -static inline u32 perf_pmmgpc_extent_v(void) -{ - return 0x00183fffU; -} -static inline u32 perf_pmmsys_base_v(void) -{ - return 0x00240000U; -} -static inline u32 perf_pmmsys_extent_v(void) -{ - return 0x00243fffU; -} -static inline u32 perf_pmmfbp_base_v(void) -{ - return 0x00200000U; -} -static inline u32 perf_pmasys_control_r(void) -{ - return 0x0024a000U; -} -static inline u32 perf_pmasys_control_membuf_status_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void) -{ - return 0x10U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) -{ - return 0x20U; -} -static inline u32 perf_pmasys_mem_block_r(void) -{ - return 0x0024a070U; -} -static inline u32 perf_pmasys_mem_block_base_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 perf_pmasys_mem_block_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 perf_pmasys_mem_block_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 perf_pmasys_mem_block_target_lfb_v(void) -{ - return 0x00000000U; -} -static inline u32 perf_pmasys_mem_block_target_lfb_f(void) -{ - return 0x0U; -} -static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 perf_pmasys_mem_block_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 perf_pmasys_mem_block_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 perf_pmasys_mem_block_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_mem_block_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 perf_pmasys_mem_block_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 perf_pmasys_mem_block_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 perf_pmasys_outbase_r(void) -{ - return 0x0024a074U; -} -static inline u32 perf_pmasys_outbase_ptr_f(u32 v) -{ - return (v & 0x7ffffffU) << 5U; -} -static inline u32 perf_pmasys_outbaseupper_r(void) -{ - return 0x0024a078U; -} -static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 perf_pmasys_outsize_r(void) -{ - return 0x0024a07cU; -} -static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) -{ - return (v & 0x7ffffffU) << 5U; -} -static inline u32 perf_pmasys_mem_bytes_r(void) -{ - return 0x0024a084U; -} -static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 perf_pmasys_mem_bump_r(void) -{ - return 0x0024a088U; -} -static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 perf_pmasys_enginestatus_r(void) -{ - return 0x0024a0a4U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void) -{ - return 0x10U; -} -static inline u32 perf_pmmsys_engine_sel_r(u32 i) -{ - return 0x0024006cU + i*512U; -} -static inline u32 perf_pmmsys_engine_sel__size_1_v(void) -{ - return 0x00000020U; -} -static inline u32 perf_pmmfbp_engine_sel_r(u32 i) -{ - return 0x0020006cU + i*512U; -} -static inline u32 perf_pmmfbp_engine_sel__size_1_v(void) -{ - return 0x00000020U; -} -static inline u32 perf_pmmgpc_engine_sel_r(u32 i) -{ - return 0x0018006cU + i*512U; -} -static inline u32 perf_pmmgpc_engine_sel__size_1_v(void) -{ - return 0x00000020U; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_pgsp_gv100.h b/include/nvgpu/hw/gv100/hw_pgsp_gv100.h deleted file mode 100644 index 34d0eae..0000000 --- a/include/nvgpu/hw/gv100/hw_pgsp_gv100.h +++ /dev/null @@ -1,643 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pgsp_gv100_h_ -#define _hw_pgsp_gv100_h_ - -static inline u32 pgsp_falcon_irqsset_r(void) -{ - return 0x00110000U; -} -static inline u32 pgsp_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 pgsp_falcon_irqsclr_r(void) -{ - return 0x00110004U; -} -static inline u32 pgsp_falcon_irqstat_r(void) -{ - return 0x00110008U; -} -static inline u32 pgsp_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 pgsp_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 pgsp_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 pgsp_falcon_irqmode_r(void) -{ - return 0x0011000cU; -} -static inline u32 pgsp_falcon_irqmset_r(void) -{ - return 0x00110010U; -} -static inline u32 pgsp_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pgsp_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pgsp_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pgsp_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pgsp_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pgsp_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pgsp_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pgsp_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pgsp_falcon_irqmclr_r(void) -{ - return 0x00110014U; -} -static inline u32 pgsp_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pgsp_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pgsp_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pgsp_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pgsp_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pgsp_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pgsp_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pgsp_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pgsp_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pgsp_falcon_irqmask_r(void) -{ - return 0x00110018U; -} -static inline u32 pgsp_falcon_irqdest_r(void) -{ - return 0x0011001cU; -} -static inline u32 pgsp_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pgsp_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pgsp_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pgsp_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pgsp_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pgsp_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pgsp_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pgsp_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pgsp_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pgsp_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 pgsp_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 pgsp_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 pgsp_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 pgsp_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 pgsp_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 pgsp_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 pgsp_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 pgsp_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 pgsp_falcon_curctx_r(void) -{ - return 0x00110050U; -} -static inline u32 pgsp_falcon_nxtctx_r(void) -{ - return 0x00110054U; -} -static inline u32 pgsp_falcon_nxtctx_ctxptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 pgsp_falcon_nxtctx_ctxtgt_fb_f(void) -{ - return 0x0U; -} -static inline u32 pgsp_falcon_nxtctx_ctxtgt_sys_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 pgsp_falcon_nxtctx_ctxtgt_sys_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 pgsp_falcon_nxtctx_ctxvalid_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 pgsp_falcon_mailbox0_r(void) -{ - return 0x00110040U; -} -static inline u32 pgsp_falcon_mailbox1_r(void) -{ - return 0x00110044U; -} -static inline u32 pgsp_falcon_itfen_r(void) -{ - return 0x00110048U; -} -static inline u32 pgsp_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 pgsp_falcon_idlestate_r(void) -{ - return 0x0011004cU; -} -static inline u32 pgsp_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pgsp_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 pgsp_falcon_os_r(void) -{ - return 0x00110080U; -} -static inline u32 pgsp_falcon_engctl_r(void) -{ - return 0x001100a4U; -} -static inline u32 pgsp_falcon_engctl_switch_context_true_f(void) -{ - return 0x8U; -} -static inline u32 pgsp_falcon_engctl_switch_context_false_f(void) -{ - return 0x0U; -} -static inline u32 pgsp_falcon_cpuctl_r(void) -{ - return 0x00110100U; -} -static inline u32 pgsp_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pgsp_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pgsp_falcon_cpuctl_halt_intr_m(void) -{ - return 0x1U << 4U; -} -static inline u32 pgsp_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 pgsp_falcon_cpuctl_cpuctl_alias_en_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pgsp_falcon_cpuctl_cpuctl_alias_en_m(void) -{ - return 0x1U << 6U; -} -static inline u32 pgsp_falcon_cpuctl_cpuctl_alias_en_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 pgsp_falcon_cpuctl_alias_r(void) -{ - return 0x00110130U; -} -static inline u32 pgsp_falcon_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pgsp_falcon_imemc_r(u32 i) -{ - return 0x00110180U + i*16U; -} -static inline u32 pgsp_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pgsp_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pgsp_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pgsp_falcon_imemd_r(u32 i) -{ - return 0x00110184U + i*16U; -} -static inline u32 pgsp_falcon_imemt_r(u32 i) -{ - return 0x00110188U + i*16U; -} -static inline u32 pgsp_falcon_sctl_r(void) -{ - return 0x00110240U; -} -static inline u32 pgsp_falcon_mmu_phys_sec_r(void) -{ - return 0x00100ce4U; -} -static inline u32 pgsp_falcon_bootvec_r(void) -{ - return 0x00110104U; -} -static inline u32 pgsp_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pgsp_falcon_dmactl_r(void) -{ - return 0x0011010cU; -} -static inline u32 pgsp_falcon_dmactl_dmem_scrubbing_m(void) -{ - return 0x1U << 1U; -} -static inline u32 pgsp_falcon_dmactl_imem_scrubbing_m(void) -{ - return 0x1U << 2U; -} -static inline u32 pgsp_falcon_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pgsp_falcon_hwcfg_r(void) -{ - return 0x00110108U; -} -static inline u32 pgsp_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 pgsp_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 pgsp_falcon_dmatrfbase_r(void) -{ - return 0x00110110U; -} -static inline u32 pgsp_falcon_dmatrfbase1_r(void) -{ - return 0x00110128U; -} -static inline u32 pgsp_falcon_dmatrfmoffs_r(void) -{ - return 0x00110114U; -} -static inline u32 pgsp_falcon_dmatrfcmd_r(void) -{ - return 0x00110118U; -} -static inline u32 pgsp_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pgsp_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pgsp_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 pgsp_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 pgsp_falcon_dmatrffboffs_r(void) -{ - return 0x0011011cU; -} -static inline u32 pgsp_falcon_exterraddr_r(void) -{ - return 0x00110168U; -} -static inline u32 pgsp_falcon_exterrstat_r(void) -{ - return 0x0011016cU; -} -static inline u32 pgsp_falcon_exterrstat_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 pgsp_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 pgsp_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 pgsp_sec2_falcon_icd_cmd_r(void) -{ - return 0x00110200U; -} -static inline u32 pgsp_sec2_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 pgsp_sec2_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 pgsp_sec2_falcon_icd_cmd_opc_m(void) -{ - return 0xfU << 0U; -} -static inline u32 pgsp_sec2_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 pgsp_sec2_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 pgsp_sec2_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 pgsp_sec2_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 pgsp_sec2_falcon_icd_rdata_r(void) -{ - return 0x0011020cU; -} -static inline u32 pgsp_falcon_dmemc_r(u32 i) -{ - return 0x001101c0U + i*8U; -} -static inline u32 pgsp_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pgsp_falcon_dmemc_offs_m(void) -{ - return 0x3fU << 2U; -} -static inline u32 pgsp_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pgsp_falcon_dmemc_blk_m(void) -{ - return 0xffU << 8U; -} -static inline u32 pgsp_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pgsp_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 pgsp_falcon_dmemd_r(u32 i) -{ - return 0x001101c4U + i*8U; -} -static inline u32 pgsp_falcon_debug1_r(void) -{ - return 0x00110090U; -} -static inline u32 pgsp_falcon_debug1_ctxsw_mode_s(void) -{ - return 1U; -} -static inline u32 pgsp_falcon_debug1_ctxsw_mode_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 pgsp_falcon_debug1_ctxsw_mode_m(void) -{ - return 0x1U << 16U; -} -static inline u32 pgsp_falcon_debug1_ctxsw_mode_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 pgsp_falcon_debug1_ctxsw_mode_init_f(void) -{ - return 0x0U; -} -static inline u32 pgsp_fbif_transcfg_r(u32 i) -{ - return 0x00110600U + i*4U; -} -static inline u32 pgsp_fbif_transcfg_target_local_fb_f(void) -{ - return 0x0U; -} -static inline u32 pgsp_fbif_transcfg_target_coherent_sysmem_f(void) -{ - return 0x1U; -} -static inline u32 pgsp_fbif_transcfg_target_noncoherent_sysmem_f(void) -{ - return 0x2U; -} -static inline u32 pgsp_fbif_transcfg_mem_type_s(void) -{ - return 1U; -} -static inline u32 pgsp_fbif_transcfg_mem_type_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pgsp_fbif_transcfg_mem_type_m(void) -{ - return 0x1U << 2U; -} -static inline u32 pgsp_fbif_transcfg_mem_type_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 pgsp_fbif_transcfg_mem_type_virtual_f(void) -{ - return 0x0U; -} -static inline u32 pgsp_fbif_transcfg_mem_type_physical_f(void) -{ - return 0x4U; -} -static inline u32 pgsp_falcon_engine_r(void) -{ - return 0x001103c0U; -} -static inline u32 pgsp_falcon_engine_reset_true_f(void) -{ - return 0x1U; -} -static inline u32 pgsp_falcon_engine_reset_false_f(void) -{ - return 0x0U; -} -static inline u32 pgsp_fbif_ctl_r(void) -{ - return 0x00110624U; -} -static inline u32 pgsp_fbif_ctl_allow_phys_no_ctx_init_f(void) -{ - return 0x0U; -} -static inline u32 pgsp_fbif_ctl_allow_phys_no_ctx_disallow_f(void) -{ - return 0x0U; -} -static inline u32 pgsp_fbif_ctl_allow_phys_no_ctx_allow_f(void) -{ - return 0x80U; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_pram_gv100.h b/include/nvgpu/hw/gv100/hw_pram_gv100.h deleted file mode 100644 index 8f005a2..0000000 --- a/include/nvgpu/hw/gv100/hw_pram_gv100.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pram_gv100_h_ -#define _hw_pram_gv100_h_ - -static inline u32 pram_data032_r(u32 i) -{ - return 0x00700000U + i*4U; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h b/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h deleted file mode 100644 index 5eca93c..0000000 --- a/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pri_ringmaster_gv100_h_ -#define _hw_pri_ringmaster_gv100_h_ - -static inline u32 pri_ringmaster_command_r(void) -{ - return 0x0012004cU; -} -static inline u32 pri_ringmaster_command_cmd_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 pri_ringmaster_command_cmd_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void) -{ - return 0x00000000U; -} -static inline u32 pri_ringmaster_command_cmd_start_ring_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void) -{ - return 0x2U; -} -static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void) -{ - return 0x3U; -} -static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void) -{ - return 0x0U; -} -static inline u32 pri_ringmaster_command_data_r(void) -{ - return 0x00120048U; -} -static inline u32 pri_ringmaster_start_results_r(void) -{ - return 0x00120050U; -} -static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void) -{ - return 0x00000001U; -} -static inline u32 pri_ringmaster_intr_status0_r(void) -{ - return 0x00120058U; -} -static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status1_r(void) -{ - return 0x0012005cU; -} -static inline u32 pri_ringmaster_global_ctl_r(void) -{ - return 0x00120060U; -} -static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void) -{ - return 0x0U; -} -static inline u32 pri_ringmaster_enum_fbp_r(void) -{ - return 0x00120074U; -} -static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 pri_ringmaster_enum_gpc_r(void) -{ - return 0x00120078U; -} -static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 pri_ringmaster_enum_ltc_r(void) -{ - return 0x0012006cU; -} -static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h b/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h deleted file mode 100644 index fc522d5..0000000 --- a/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pri_ringstation_gpc_gv100_h_ -#define _hw_pri_ringstation_gpc_gv100_h_ - -static inline u32 pri_ringstation_gpc_master_config_r(u32 i) -{ - return 0x00128300U + i*4U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void) -{ - return 0x00128120U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void) -{ - return 0x00128124U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void) -{ - return 0x00128128U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void) -{ - return 0x0012812cU; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h b/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h deleted file mode 100644 index 885ea30..0000000 --- a/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pri_ringstation_sys_gv100_h_ -#define _hw_pri_ringstation_sys_gv100_h_ - -static inline u32 pri_ringstation_sys_master_config_r(u32 i) -{ - return 0x00122300U + i*4U; -} -static inline u32 pri_ringstation_sys_decode_config_r(void) -{ - return 0x00122204U; -} -static inline u32 pri_ringstation_sys_decode_config_ring_m(void) -{ - return 0x7U << 0U; -} -static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringstation_sys_priv_error_adr_r(void) -{ - return 0x00122120U; -} -static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void) -{ - return 0x00122124U; -} -static inline u32 pri_ringstation_sys_priv_error_info_r(void) -{ - return 0x00122128U; -} -static inline u32 pri_ringstation_sys_priv_error_code_r(void) -{ - return 0x0012212cU; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_proj_gv100.h b/include/nvgpu/hw/gv100/hw_proj_gv100.h deleted file mode 100644 index f46eaa0..0000000 --- a/include/nvgpu/hw/gv100/hw_proj_gv100.h +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_proj_gv100_h_ -#define _hw_proj_gv100_h_ - -static inline u32 proj_gpc_base_v(void) -{ - return 0x00500000U; -} -static inline u32 proj_gpc_shared_base_v(void) -{ - return 0x00418000U; -} -static inline u32 proj_gpc_stride_v(void) -{ - return 0x00008000U; -} -static inline u32 proj_gpc_priv_stride_v(void) -{ - return 0x00000800U; -} -static inline u32 proj_ltc_stride_v(void) -{ - return 0x00002000U; -} -static inline u32 proj_lts_stride_v(void) -{ - return 0x00000200U; -} -static inline u32 proj_fbpa_base_v(void) -{ - return 0x00900000U; -} -static inline u32 proj_fbpa_shared_base_v(void) -{ - return 0x009a0000U; -} -static inline u32 proj_fbpa_stride_v(void) -{ - return 0x00004000U; -} -static inline u32 proj_ppc_in_gpc_base_v(void) -{ - return 0x00003000U; -} -static inline u32 proj_ppc_in_gpc_shared_base_v(void) -{ - return 0x00003e00U; -} -static inline u32 proj_ppc_in_gpc_stride_v(void) -{ - return 0x00000200U; -} -static inline u32 proj_rop_base_v(void) -{ - return 0x00410000U; -} -static inline u32 proj_rop_shared_base_v(void) -{ - return 0x00408800U; -} -static inline u32 proj_rop_stride_v(void) -{ - return 0x00000400U; -} -static inline u32 proj_tpc_in_gpc_base_v(void) -{ - return 0x00004000U; -} -static inline u32 proj_tpc_in_gpc_stride_v(void) -{ - return 0x00000800U; -} -static inline u32 proj_tpc_in_gpc_shared_base_v(void) -{ - return 0x00001800U; -} -static inline u32 proj_smpc_base_v(void) -{ - return 0x00000200U; -} -static inline u32 proj_smpc_shared_base_v(void) -{ - return 0x00000300U; -} -static inline u32 proj_smpc_unique_base_v(void) -{ - return 0x00000600U; -} -static inline u32 proj_smpc_stride_v(void) -{ - return 0x00000100U; -} -static inline u32 proj_host_num_engines_v(void) -{ - return 0x0000000fU; -} -static inline u32 proj_host_num_pbdma_v(void) -{ - return 0x0000000eU; -} -static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) -{ - return 0x00000007U; -} -static inline u32 proj_scal_litter_num_fbps_v(void) -{ - return 0x00000008U; -} -static inline u32 proj_scal_litter_num_fbpas_v(void) -{ - return 0x00000010U; -} -static inline u32 proj_scal_litter_num_gpcs_v(void) -{ - return 0x00000006U; -} -static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) -{ - return 0x00000003U; -} -static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) -{ - return 0x00000003U; -} -static inline u32 proj_scal_litter_num_zcull_banks_v(void) -{ - return 0x00000004U; -} -static inline u32 proj_scal_litter_num_sm_per_tpc_v(void) -{ - return 0x00000002U; -} -static inline u32 proj_scal_max_gpcs_v(void) -{ - return 0x00000020U; -} -static inline u32 proj_scal_max_tpc_per_gpc_v(void) -{ - return 0x00000008U; -} -static inline u32 proj_sm_stride_v(void) -{ - return 0x00000080U; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_pwr_gv100.h b/include/nvgpu/hw/gv100/hw_pwr_gv100.h deleted file mode 100644 index c719226..0000000 --- a/include/nvgpu/hw/gv100/hw_pwr_gv100.h +++ /dev/null @@ -1,983 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pwr_gv100_h_ -#define _hw_pwr_gv100_h_ - -static inline u32 pwr_falcon_irqsset_r(void) -{ - return 0x0010a000U; -} -static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 pwr_falcon_irqsclr_r(void) -{ - return 0x0010a004U; -} -static inline u32 pwr_falcon_irqstat_r(void) -{ - return 0x0010a008U; -} -static inline u32 pwr_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 pwr_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 pwr_falcon_irqstat_ext_second_true_f(void) -{ - return 0x800U; -} -static inline u32 pwr_falcon_irqmode_r(void) -{ - return 0x0010a00cU; -} -static inline u32 pwr_falcon_irqmset_r(void) -{ - return 0x0010a010U; -} -static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqmset_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqmset_ext_ctxe_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 pwr_falcon_irqmset_ext_limitv_f(u32 v) -{ - return (v & 0x1U) << 9U; -} -static inline u32 pwr_falcon_irqmset_ext_second_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 pwr_falcon_irqmset_ext_therm_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 pwr_falcon_irqmset_ext_miscio_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 pwr_falcon_irqmset_ext_rttimer_f(u32 v) -{ - return (v & 0x1U) << 14U; -} -static inline u32 pwr_falcon_irqmclr_r(void) -{ - return 0x0010a014U; -} -static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqmclr_ext_ctxe_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 pwr_falcon_irqmclr_ext_limitv_f(u32 v) -{ - return (v & 0x1U) << 9U; -} -static inline u32 pwr_falcon_irqmclr_ext_second_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 pwr_falcon_irqmclr_ext_therm_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 pwr_falcon_irqmclr_ext_miscio_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 pwr_falcon_irqmclr_ext_rttimer_f(u32 v) -{ - return (v & 0x1U) << 14U; -} -static inline u32 pwr_falcon_irqmask_r(void) -{ - return 0x0010a018U; -} -static inline u32 pwr_falcon_irqdest_r(void) -{ - return 0x0010a01cU; -} -static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqdest_host_ext_ctxe_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 pwr_falcon_irqdest_host_ext_limitv_f(u32 v) -{ - return (v & 0x1U) << 9U; -} -static inline u32 pwr_falcon_irqdest_host_ext_second_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 pwr_falcon_irqdest_host_ext_therm_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 pwr_falcon_irqdest_host_ext_miscio_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 pwr_falcon_irqdest_host_ext_rttimer_f(u32 v) -{ - return (v & 0x1U) << 14U; -} -static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 pwr_falcon_irqdest_target_ext_ctxe_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_irqdest_target_ext_limitv_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 pwr_falcon_irqdest_target_ext_second_f(u32 v) -{ - return (v & 0x1U) << 27U; -} -static inline u32 pwr_falcon_irqdest_target_ext_therm_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 pwr_falcon_irqdest_target_ext_miscio_f(u32 v) -{ - return (v & 0x1U) << 29U; -} -static inline u32 pwr_falcon_irqdest_target_ext_rttimer_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 pwr_falcon_curctx_r(void) -{ - return 0x0010a050U; -} -static inline u32 pwr_falcon_nxtctx_r(void) -{ - return 0x0010a054U; -} -static inline u32 pwr_falcon_mailbox0_r(void) -{ - return 0x0010a040U; -} -static inline u32 pwr_falcon_mailbox1_r(void) -{ - return 0x0010a044U; -} -static inline u32 pwr_falcon_itfen_r(void) -{ - return 0x0010a048U; -} -static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 pwr_falcon_idlestate_r(void) -{ - return 0x0010a04cU; -} -static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 pwr_falcon_os_r(void) -{ - return 0x0010a080U; -} -static inline u32 pwr_falcon_engctl_r(void) -{ - return 0x0010a0a4U; -} -static inline u32 pwr_falcon_cpuctl_r(void) -{ - return 0x0010a100U; -} -static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) -{ - return 0x1U << 4U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void) -{ - return 0x1U << 6U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 pwr_falcon_cpuctl_alias_r(void) -{ - return 0x0010a130U; -} -static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_pmu_scpctl_stat_r(void) -{ - return 0x0010ac08U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void) -{ - return 0x1U << 20U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 pwr_falcon_imemc_r(u32 i) -{ - return 0x0010a180U + i*16U; -} -static inline u32 pwr_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pwr_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_imemd_r(u32 i) -{ - return 0x0010a184U + i*16U; -} -static inline u32 pwr_falcon_imemt_r(u32 i) -{ - return 0x0010a188U + i*16U; -} -static inline u32 pwr_falcon_sctl_r(void) -{ - return 0x0010a240U; -} -static inline u32 pwr_falcon_mmu_phys_sec_r(void) -{ - return 0x00100ce4U; -} -static inline u32 pwr_falcon_bootvec_r(void) -{ - return 0x0010a104U; -} -static inline u32 pwr_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_falcon_dmactl_r(void) -{ - return 0x0010a10cU; -} -static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) -{ - return 0x1U << 1U; -} -static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) -{ - return 0x1U << 2U; -} -static inline u32 pwr_falcon_hwcfg_r(void) -{ - return 0x0010a108U; -} -static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 pwr_falcon_dmatrfbase_r(void) -{ - return 0x0010a110U; -} -static inline u32 pwr_falcon_dmatrfbase1_r(void) -{ - return 0x0010a128U; -} -static inline u32 pwr_falcon_dmatrfmoffs_r(void) -{ - return 0x0010a114U; -} -static inline u32 pwr_falcon_dmatrfcmd_r(void) -{ - return 0x0010a118U; -} -static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 pwr_falcon_dmatrffboffs_r(void) -{ - return 0x0010a11cU; -} -static inline u32 pwr_falcon_exterraddr_r(void) -{ - return 0x0010a168U; -} -static inline u32 pwr_falcon_exterrstat_r(void) -{ - return 0x0010a16cU; -} -static inline u32 pwr_falcon_exterrstat_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 pwr_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_r(void) -{ - return 0x0010a200U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) -{ - return 0xfU << 0U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 pwr_pmu_falcon_icd_rdata_r(void) -{ - return 0x0010a20cU; -} -static inline u32 pwr_falcon_dmemc_r(u32 i) -{ - return 0x0010a1c0U + i*8U; -} -static inline u32 pwr_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pwr_falcon_dmemc_offs_m(void) -{ - return 0x3fU << 2U; -} -static inline u32 pwr_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_dmemc_blk_m(void) -{ - return 0xffU << 8U; -} -static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 pwr_falcon_dmemd_r(u32 i) -{ - return 0x0010a1c4U + i*8U; -} -static inline u32 pwr_pmu_new_instblk_r(void) -{ - return 0x0010a480U; -} -static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 pwr_pmu_new_instblk_target_fb_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 pwr_pmu_mutex_id_r(void) -{ - return 0x0010a488U; -} -static inline u32 pwr_pmu_mutex_id_value_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pwr_pmu_mutex_id_value_init_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) -{ - return 0x000000ffU; -} -static inline u32 pwr_pmu_mutex_id_release_r(void) -{ - return 0x0010a48cU; -} -static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_id_release_value_m(void) -{ - return 0xffU << 0U; -} -static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_mutex_r(u32 i) -{ - return 0x0010a580U + i*4U; -} -static inline u32 pwr_pmu_mutex__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 pwr_pmu_mutex_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_value_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_queue_head_r(u32 i) -{ - return 0x0010a800U + i*4U; -} -static inline u32 pwr_pmu_queue_head__size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 pwr_pmu_queue_head_address_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_queue_head_address_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_queue_tail_r(u32 i) -{ - return 0x0010a820U + i*4U; -} -static inline u32 pwr_pmu_queue_tail__size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 pwr_pmu_queue_tail_address_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_queue_tail_address_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_msgq_head_r(void) -{ - return 0x0010a4c8U; -} -static inline u32 pwr_pmu_msgq_head_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_msgq_head_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_msgq_tail_r(void) -{ - return 0x0010a4ccU; -} -static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_idle_mask_r(u32 i) -{ - return 0x0010a504U + i*16U; -} -static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) -{ - return 0x1U; -} -static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 pwr_pmu_idle_count_r(u32 i) -{ - return 0x0010a508U + i*16U; -} -static inline u32 pwr_pmu_idle_count_value_f(u32 v) -{ - return (v & 0x7fffffffU) << 0U; -} -static inline u32 pwr_pmu_idle_count_value_v(u32 r) -{ - return (r >> 0U) & 0x7fffffffU; -} -static inline u32 pwr_pmu_idle_count_reset_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 pwr_pmu_idle_ctrl_r(u32 i) -{ - return 0x0010a50cU + i*16U; -} -static inline u32 pwr_pmu_idle_ctrl_value_m(void) -{ - return 0x3U << 0U; -} -static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) -{ - return 0x2U; -} -static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) -{ - return 0x3U; -} -static inline u32 pwr_pmu_idle_ctrl_filter_m(void) -{ - return 0x1U << 2U; -} -static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_idle_threshold_r(u32 i) -{ - return 0x0010a8a0U + i*4U; -} -static inline u32 pwr_pmu_idle_threshold_value_f(u32 v) -{ - return (v & 0x7fffffffU) << 0U; -} -static inline u32 pwr_pmu_idle_intr_r(void) -{ - return 0x0010a9e8U; -} -static inline u32 pwr_pmu_idle_intr_en_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_en_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_idle_intr_en_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_intr_status_r(void) -{ - return 0x0010a9ecU; -} -static inline u32 pwr_pmu_idle_intr_status_intr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) -{ - return 0x0010a9f0U + i*8U; -} -static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) -{ - return 0x0010a9f4U + i*8U; -} -static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) -{ - return 0x0010aa30U + i*8U; -} -static inline u32 pwr_pmu_debug_r(u32 i) -{ - return 0x0010a5c0U + i*4U; -} -static inline u32 pwr_pmu_debug__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 pwr_pmu_mailbox_r(u32 i) -{ - return 0x0010a450U + i*4U; -} -static inline u32 pwr_pmu_mailbox__size_1_v(void) -{ - return 0x0000000cU; -} -static inline u32 pwr_pmu_bar0_addr_r(void) -{ - return 0x0010a7a0U; -} -static inline u32 pwr_pmu_bar0_data_r(void) -{ - return 0x0010a7a4U; -} -static inline u32 pwr_pmu_bar0_ctl_r(void) -{ - return 0x0010a7acU; -} -static inline u32 pwr_pmu_bar0_timeout_r(void) -{ - return 0x0010a7a8U; -} -static inline u32 pwr_pmu_bar0_fecs_error_r(void) -{ - return 0x0010a988U; -} -static inline u32 pwr_pmu_bar0_error_status_r(void) -{ - return 0x0010a7b0U; -} -static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) -{ - return 0x0010a6c0U + i*4U; -} -static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) -{ - return 0x0010a6e8U + i*4U; -} -static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) -{ - return 0x0010a710U + i*4U; -} -static inline u32 pwr_pmu_pg_intren_r(u32 i) -{ - return 0x0010a760U + i*4U; -} -static inline u32 pwr_fbif_transcfg_r(u32 i) -{ - return 0x0010ae00U + i*4U; -} -static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) -{ - return 0x0U; -} -static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) -{ - return 0x1U; -} -static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) -{ - return 0x2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_s(void) -{ - return 1U; -} -static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_m(void) -{ - return 0x1U << 2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) -{ - return 0x0U; -} -static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) -{ - return 0x4U; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_ram_gv100.h b/include/nvgpu/hw/gv100/hw_ram_gv100.h deleted file mode 100644 index 55aa25f..0000000 --- a/include/nvgpu/hw/gv100/hw_ram_gv100.h +++ /dev/null @@ -1,791 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ram_gv100_h_ -#define _hw_ram_gv100_h_ - -static inline u32 ram_in_ramfc_s(void) -{ - return 4096U; -} -static inline u32 ram_in_ramfc_w(void) -{ - return 0U; -} -static inline u32 ram_in_page_dir_base_target_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ram_in_page_dir_base_target_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 ram_in_page_dir_base_vol_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_vol_true_f(void) -{ - return 0x4U; -} -static inline u32 ram_in_page_dir_base_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) -{ - return 0x1U << 4U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) -{ - return 0x10U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) -{ - return 0x1U << 5U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void) -{ - return 0x20U; -} -static inline u32 ram_in_use_ver2_pt_format_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 ram_in_use_ver2_pt_format_m(void) -{ - return 0x1U << 10U; -} -static inline u32 ram_in_use_ver2_pt_format_w(void) -{ - return 128U; -} -static inline u32 ram_in_use_ver2_pt_format_true_f(void) -{ - return 0x400U; -} -static inline u32 ram_in_use_ver2_pt_format_false_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_big_page_size_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 ram_in_big_page_size_m(void) -{ - return 0x1U << 11U; -} -static inline u32 ram_in_big_page_size_w(void) -{ - return 128U; -} -static inline u32 ram_in_big_page_size_128kb_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_big_page_size_64kb_f(void) -{ - return 0x800U; -} -static inline u32 ram_in_page_dir_base_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_page_dir_base_lo_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_hi_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_in_page_dir_base_hi_w(void) -{ - return 129U; -} -static inline u32 ram_in_engine_cs_w(void) -{ - return 132U; -} -static inline u32 ram_in_engine_cs_wfi_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_engine_cs_wfi_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_engine_cs_fg_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_engine_cs_fg_f(void) -{ - return 0x8U; -} -static inline u32 ram_in_engine_wfi_mode_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 ram_in_engine_wfi_mode_w(void) -{ - return 132U; -} -static inline u32 ram_in_engine_wfi_mode_physical_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_engine_wfi_mode_virtual_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_engine_wfi_target_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ram_in_engine_wfi_target_w(void) -{ - return 132U; -} -static inline u32 ram_in_engine_wfi_target_sys_mem_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 ram_in_engine_wfi_target_sys_mem_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 ram_in_engine_wfi_target_local_mem_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_engine_wfi_ptr_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_engine_wfi_ptr_lo_w(void) -{ - return 132U; -} -static inline u32 ram_in_engine_wfi_ptr_hi_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ram_in_engine_wfi_ptr_hi_w(void) -{ - return 133U; -} -static inline u32 ram_in_engine_wfi_veid_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 ram_in_engine_wfi_veid_w(void) -{ - return 134U; -} -static inline u32 ram_in_eng_method_buffer_addr_lo_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_in_eng_method_buffer_addr_lo_w(void) -{ - return 136U; -} -static inline u32 ram_in_eng_method_buffer_addr_hi_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ram_in_eng_method_buffer_addr_hi_w(void) -{ - return 137U; -} -static inline u32 ram_in_sc_page_dir_base_target_f(u32 v, u32 i) -{ - return (v & 0x3U) << (0U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_target__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_target_vid_mem_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_sc_page_dir_base_target_invalid_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_page_dir_base_target_sys_mem_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 ram_in_sc_page_dir_base_vol_f(u32 v, u32 i) -{ - return (v & 0x1U) << (2U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_vol__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_vol_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_page_dir_base_vol_false_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_f(u32 v, u32 i) -{ - return (v & 0x1U) << (4U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_f(u32 v, u32 i) -{ - return (v & 0x1U) << (5U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_sc_use_ver2_pt_format_f(u32 v, u32 i) -{ - return (v & 0x1U) << (10U + i*0U); -} -static inline u32 ram_in_sc_use_ver2_pt_format__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_use_ver2_pt_format_false_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_sc_use_ver2_pt_format_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_big_page_size_f(u32 v, u32 i) -{ - return (v & 0x1U) << (11U + i*0U); -} -static inline u32 ram_in_sc_big_page_size__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_big_page_size_64kb_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_page_dir_base_lo_f(u32 v, u32 i) -{ - return (v & 0xfffffU) << (12U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_lo__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_hi_f(u32 v, u32 i) -{ - return (v & 0xffffffffU) << (0U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_hi__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_target_0_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ram_in_sc_page_dir_base_target_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_page_dir_base_vol_0_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 ram_in_sc_page_dir_base_vol_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_use_ver2_pt_format_0_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 ram_in_sc_use_ver2_pt_format_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_big_page_size_0_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 ram_in_sc_big_page_size_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_page_dir_base_lo_0_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_sc_page_dir_base_lo_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_page_dir_base_hi_0_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_in_sc_page_dir_base_hi_0_w(void) -{ - return 169U; -} -static inline u32 ram_in_base_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 ram_in_alloc_size_v(void) -{ - return 0x00001000U; -} -static inline u32 ram_fc_size_val_v(void) -{ - return 0x00000200U; -} -static inline u32 ram_fc_gp_put_w(void) -{ - return 0U; -} -static inline u32 ram_fc_userd_w(void) -{ - return 2U; -} -static inline u32 ram_fc_userd_hi_w(void) -{ - return 3U; -} -static inline u32 ram_fc_signature_w(void) -{ - return 4U; -} -static inline u32 ram_fc_gp_get_w(void) -{ - return 5U; -} -static inline u32 ram_fc_pb_get_w(void) -{ - return 6U; -} -static inline u32 ram_fc_pb_get_hi_w(void) -{ - return 7U; -} -static inline u32 ram_fc_pb_top_level_get_w(void) -{ - return 8U; -} -static inline u32 ram_fc_pb_top_level_get_hi_w(void) -{ - return 9U; -} -static inline u32 ram_fc_acquire_w(void) -{ - return 12U; -} -static inline u32 ram_fc_sem_addr_hi_w(void) -{ - return 14U; -} -static inline u32 ram_fc_sem_addr_lo_w(void) -{ - return 15U; -} -static inline u32 ram_fc_sem_payload_lo_w(void) -{ - return 16U; -} -static inline u32 ram_fc_sem_payload_hi_w(void) -{ - return 39U; -} -static inline u32 ram_fc_sem_execute_w(void) -{ - return 17U; -} -static inline u32 ram_fc_gp_base_w(void) -{ - return 18U; -} -static inline u32 ram_fc_gp_base_hi_w(void) -{ - return 19U; -} -static inline u32 ram_fc_gp_fetch_w(void) -{ - return 20U; -} -static inline u32 ram_fc_pb_fetch_w(void) -{ - return 21U; -} -static inline u32 ram_fc_pb_fetch_hi_w(void) -{ - return 22U; -} -static inline u32 ram_fc_pb_put_w(void) -{ - return 23U; -} -static inline u32 ram_fc_pb_put_hi_w(void) -{ - return 24U; -} -static inline u32 ram_fc_pb_header_w(void) -{ - return 33U; -} -static inline u32 ram_fc_pb_count_w(void) -{ - return 34U; -} -static inline u32 ram_fc_subdevice_w(void) -{ - return 37U; -} -static inline u32 ram_fc_target_w(void) -{ - return 43U; -} -static inline u32 ram_fc_hce_ctrl_w(void) -{ - return 57U; -} -static inline u32 ram_fc_chid_w(void) -{ - return 58U; -} -static inline u32 ram_fc_chid_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_fc_chid_id_w(void) -{ - return 0U; -} -static inline u32 ram_fc_config_w(void) -{ - return 61U; -} -static inline u32 ram_fc_runlist_timeslice_w(void) -{ - return 62U; -} -static inline u32 ram_fc_set_channel_info_w(void) -{ - return 63U; -} -static inline u32 ram_userd_base_shift_v(void) -{ - return 0x00000009U; -} -static inline u32 ram_userd_chan_size_v(void) -{ - return 0x00000200U; -} -static inline u32 ram_userd_put_w(void) -{ - return 16U; -} -static inline u32 ram_userd_get_w(void) -{ - return 17U; -} -static inline u32 ram_userd_ref_w(void) -{ - return 18U; -} -static inline u32 ram_userd_put_hi_w(void) -{ - return 19U; -} -static inline u32 ram_userd_ref_threshold_w(void) -{ - return 20U; -} -static inline u32 ram_userd_top_level_get_w(void) -{ - return 22U; -} -static inline u32 ram_userd_top_level_get_hi_w(void) -{ - return 23U; -} -static inline u32 ram_userd_get_hi_w(void) -{ - return 24U; -} -static inline u32 ram_userd_gp_get_w(void) -{ - return 34U; -} -static inline u32 ram_userd_gp_put_w(void) -{ - return 35U; -} -static inline u32 ram_userd_gp_top_level_get_w(void) -{ - return 22U; -} -static inline u32 ram_userd_gp_top_level_get_hi_w(void) -{ - return 23U; -} -static inline u32 ram_rl_entry_size_v(void) -{ - return 0x00000010U; -} -static inline u32 ram_rl_entry_type_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ram_rl_entry_type_channel_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_rl_entry_type_tsg_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_rl_entry_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_chan_runqueue_selector_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ram_rl_entry_chan_inst_target_f(u32 v) -{ - return (v & 0x3U) << 4U; -} -static inline u32 ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 ram_rl_entry_chan_inst_target_sys_mem_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 ram_rl_entry_chan_inst_target_vid_mem_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_rl_entry_chan_userd_target_f(u32 v) -{ - return (v & 0x3U) << 6U; -} -static inline u32 ram_rl_entry_chan_userd_target_vid_mem_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_rl_entry_chan_userd_target_vid_mem_nvlink_coh_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_rl_entry_chan_userd_target_sys_mem_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 ram_rl_entry_chan_userd_ptr_lo_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 ram_rl_entry_chan_userd_ptr_hi_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_rl_entry_chid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_chan_inst_ptr_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_rl_entry_chan_inst_ptr_hi_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_rl_entry_tsg_timeslice_scale_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 ram_rl_entry_tsg_timeslice_scale_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ram_rl_entry_tsg_timeslice_timeout_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 ram_rl_entry_tsg_timeslice_timeout_128_v(void) -{ - return 0x00000080U; -} -static inline u32 ram_rl_entry_tsg_length_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ram_rl_entry_tsg_length_init_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_rl_entry_tsg_length_min_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_rl_entry_tsg_length_max_v(void) -{ - return 0x00000080U; -} -static inline u32 ram_rl_entry_tsg_tsgid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_chan_userd_ptr_align_shift_v(void) -{ - return 0x00000008U; -} -static inline u32 ram_rl_entry_chan_userd_align_shift_v(void) -{ - return 0x00000008U; -} -static inline u32 ram_rl_entry_chan_inst_ptr_align_shift_v(void) -{ - return 0x0000000cU; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_therm_gv100.h b/include/nvgpu/hw/gv100/hw_therm_gv100.h deleted file mode 100644 index 2ea71ef..0000000 --- a/include/nvgpu/hw/gv100/hw_therm_gv100.h +++ /dev/null @@ -1,299 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_therm_gv100_h_ -#define _hw_therm_gv100_h_ - -static inline u32 therm_weight_1_r(void) -{ - return 0x00020024U; -} -static inline u32 therm_config1_r(void) -{ - return 0x00020050U; -} -static inline u32 therm_config2_r(void) -{ - return 0x00020130U; -} -static inline u32 therm_config2_slowdown_factor_extended_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 therm_config2_grad_enable_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 therm_gate_ctrl_r(u32 i) -{ - return 0x00020200U + i*4U; -} -static inline u32 therm_gate_ctrl_eng_clk_m(void) -{ - return 0x3U << 0U; -} -static inline u32 therm_gate_ctrl_eng_clk_run_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) -{ - return 0x1U; -} -static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) -{ - return 0x2U; -} -static inline u32 therm_gate_ctrl_blk_clk_m(void) -{ - return 0x3U << 2U; -} -static inline u32 therm_gate_ctrl_blk_clk_run_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) -{ - return 0x4U; -} -static inline u32 therm_gate_ctrl_idle_holdoff_m(void) -{ - return 0x1U << 4U; -} -static inline u32 therm_gate_ctrl_idle_holdoff_off_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_idle_holdoff_on_f(void) -{ - return 0x10U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) -{ - return 0x1fU << 8U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) -{ - return (v & 0x7U) << 13U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) -{ - return 0x7U << 13U; -} -static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 therm_gate_ctrl_eng_delay_before_m(void) -{ - return 0xfU << 16U; -} -static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 therm_gate_ctrl_eng_delay_after_m(void) -{ - return 0xfU << 20U; -} -static inline u32 therm_fecs_idle_filter_r(void) -{ - return 0x00020288U; -} -static inline u32 therm_fecs_idle_filter_value_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 therm_hubmmu_idle_filter_r(void) -{ - return 0x0002028cU; -} -static inline u32 therm_hubmmu_idle_filter_value_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 therm_clk_slowdown_r(u32 i) -{ - return 0x00020160U + i*4U; -} -static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) -{ - return (v & 0x3fU) << 16U; -} -static inline u32 therm_clk_slowdown_idle_factor_m(void) -{ - return 0x3fU << 16U; -} -static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) -{ - return (r >> 16U) & 0x3fU; -} -static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) -{ - return 0x0U; -} -static inline u32 therm_grad_stepping_table_r(u32 i) -{ - return 0x000202c8U + i*4U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void) -{ - return 0x1U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void) -{ - return 0x2U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void) -{ - return 0x6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void) -{ - return 0xeU; -} -static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v) -{ - return (v & 0x3fU) << 6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void) -{ - return 0x3fU << 6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) -{ - return (v & 0x3fU) << 12U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void) -{ - return 0x3fU << 12U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) -{ - return (v & 0x3fU) << 18U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void) -{ - return 0x3fU << 18U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) -{ - return (v & 0x3fU) << 24U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void) -{ - return 0x3fU << 24U; -} -static inline u32 therm_grad_stepping0_r(void) -{ - return 0x000202c0U; -} -static inline u32 therm_grad_stepping0_feature_s(void) -{ - return 1U; -} -static inline u32 therm_grad_stepping0_feature_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 therm_grad_stepping0_feature_m(void) -{ - return 0x1U << 0U; -} -static inline u32 therm_grad_stepping0_feature_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 therm_grad_stepping0_feature_enable_f(void) -{ - return 0x1U; -} -static inline u32 therm_grad_stepping1_r(void) -{ - return 0x000202c4U; -} -static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 therm_clk_timing_r(u32 i) -{ - return 0x000203c0U + i*4U; -} -static inline u32 therm_clk_timing_grad_slowdown_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 therm_clk_timing_grad_slowdown_m(void) -{ - return 0x1U << 16U; -} -static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void) -{ - return 0x10000U; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_timer_gv100.h b/include/nvgpu/hw/gv100/hw_timer_gv100.h deleted file mode 100644 index 9d76e24..0000000 --- a/include/nvgpu/hw/gv100/hw_timer_gv100.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_timer_gv100_h_ -#define _hw_timer_gv100_h_ - -static inline u32 timer_pri_timeout_r(void) -{ - return 0x00009080U; -} -static inline u32 timer_pri_timeout_period_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 timer_pri_timeout_period_m(void) -{ - return 0xffffffU << 0U; -} -static inline u32 timer_pri_timeout_period_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 timer_pri_timeout_en_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 timer_pri_timeout_en_m(void) -{ - return 0x1U << 31U; -} -static inline u32 timer_pri_timeout_en_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 timer_pri_timeout_en_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 timer_pri_timeout_en_en_disabled_f(void) -{ - return 0x0U; -} -static inline u32 timer_pri_timeout_save_0_r(void) -{ - return 0x00009084U; -} -static inline u32 timer_pri_timeout_save_1_r(void) -{ - return 0x00009088U; -} -static inline u32 timer_pri_timeout_fecs_errcode_r(void) -{ - return 0x0000908cU; -} -static inline u32 timer_time_0_r(void) -{ - return 0x00009400U; -} -static inline u32 timer_time_1_r(void) -{ - return 0x00009410U; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_top_gv100.h b/include/nvgpu/hw/gv100/hw_top_gv100.h deleted file mode 100644 index 506a818..0000000 --- a/include/nvgpu/hw/gv100/hw_top_gv100.h +++ /dev/null @@ -1,343 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_top_gv100_h_ -#define _hw_top_gv100_h_ - -static inline u32 top_num_gpcs_r(void) -{ - return 0x00022430U; -} -static inline u32 top_num_gpcs_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_tpc_per_gpc_r(void) -{ - return 0x00022434U; -} -static inline u32 top_tpc_per_gpc_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_num_fbps_r(void) -{ - return 0x00022438U; -} -static inline u32 top_num_fbps_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_num_fbpas_r(void) -{ - return 0x0002243cU; -} -static inline u32 top_num_fbpas_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_ltc_per_fbp_r(void) -{ - return 0x00022450U; -} -static inline u32 top_ltc_per_fbp_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_slices_per_ltc_r(void) -{ - return 0x0002245cU; -} -static inline u32 top_slices_per_ltc_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_num_ltcs_r(void) -{ - return 0x00022454U; -} -static inline u32 top_num_ces_r(void) -{ - return 0x00022444U; -} -static inline u32 top_num_ces_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_device_info_r(u32 i) -{ - return 0x00022700U + i*4U; -} -static inline u32 top_device_info__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 top_device_info_chain_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 top_device_info_chain_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_engine_enum_v(u32 r) -{ - return (r >> 26U) & 0xfU; -} -static inline u32 top_device_info_runlist_enum_v(u32 r) -{ - return (r >> 21U) & 0xfU; -} -static inline u32 top_device_info_intr_enum_v(u32 r) -{ - return (r >> 15U) & 0x1fU; -} -static inline u32 top_device_info_reset_enum_v(u32 r) -{ - return (r >> 9U) & 0x1fU; -} -static inline u32 top_device_info_type_enum_v(u32 r) -{ - return (r >> 2U) & 0x1fffffffU; -} -static inline u32 top_device_info_type_enum_graphics_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_type_enum_graphics_f(void) -{ - return 0x0U; -} -static inline u32 top_device_info_type_enum_copy2_v(void) -{ - return 0x00000003U; -} -static inline u32 top_device_info_type_enum_copy2_f(void) -{ - return 0xcU; -} -static inline u32 top_device_info_type_enum_lce_v(void) -{ - return 0x00000013U; -} -static inline u32 top_device_info_type_enum_lce_f(void) -{ - return 0x4cU; -} -static inline u32 top_device_info_type_enum_ioctrl_v(void) -{ - return 0x00000012U; -} -static inline u32 top_device_info_type_enum_ioctrl_f(void) -{ - return 0x48U; -} -static inline u32 top_device_info_engine_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 top_device_info_runlist_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 top_device_info_intr_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 top_device_info_reset_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 top_device_info_entry_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 top_device_info_entry_not_valid_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_entry_enum_v(void) -{ - return 0x00000002U; -} -static inline u32 top_device_info_entry_data_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_entry_engine_type_v(void) -{ - return 0x00000003U; -} -static inline u32 top_device_info_data_type_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 top_device_info_data_type_enum2_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_data_inst_id_v(u32 r) -{ - return (r >> 26U) & 0xfU; -} -static inline u32 top_device_info_data_pri_base_v(u32 r) -{ - return (r >> 12U) & 0xfffU; -} -static inline u32 top_device_info_data_pri_base_align_v(void) -{ - return 0x0000000cU; -} -static inline u32 top_device_info_data_fault_id_enum_v(u32 r) -{ - return (r >> 3U) & 0x7fU; -} -static inline u32 top_device_info_data_fault_id_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 top_device_info_data_fault_id_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 top_nvhsclk_ctrl_r(void) -{ - return 0x00022424U; -} -static inline u32 top_nvhsclk_ctrl_e_clk_nvl_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 top_nvhsclk_ctrl_e_clk_nvl_m(void) -{ - return 0x7U << 0U; -} -static inline u32 top_nvhsclk_ctrl_e_clk_nvl_v(u32 r) -{ - return (r >> 0U) & 0x7U; -} -static inline u32 top_nvhsclk_ctrl_e_clk_pcie_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 top_nvhsclk_ctrl_e_clk_pcie_m(void) -{ - return 0x1U << 3U; -} -static inline u32 top_nvhsclk_ctrl_e_clk_pcie_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 top_nvhsclk_ctrl_e_clk_core_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 top_nvhsclk_ctrl_e_clk_core_m(void) -{ - return 0x1U << 4U; -} -static inline u32 top_nvhsclk_ctrl_e_clk_core_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 top_nvhsclk_ctrl_rfu_f(u32 v) -{ - return (v & 0xfU) << 5U; -} -static inline u32 top_nvhsclk_ctrl_rfu_m(void) -{ - return 0xfU << 5U; -} -static inline u32 top_nvhsclk_ctrl_rfu_v(u32 r) -{ - return (r >> 5U) & 0xfU; -} -static inline u32 top_nvhsclk_ctrl_swap_clk_nvl_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 top_nvhsclk_ctrl_swap_clk_nvl_m(void) -{ - return 0x7U << 10U; -} -static inline u32 top_nvhsclk_ctrl_swap_clk_nvl_v(u32 r) -{ - return (r >> 10U) & 0x7U; -} -static inline u32 top_nvhsclk_ctrl_swap_clk_pcie_f(u32 v) -{ - return (v & 0x1U) << 9U; -} -static inline u32 top_nvhsclk_ctrl_swap_clk_pcie_m(void) -{ - return 0x1U << 9U; -} -static inline u32 top_nvhsclk_ctrl_swap_clk_pcie_v(u32 r) -{ - return (r >> 9U) & 0x1U; -} -static inline u32 top_nvhsclk_ctrl_swap_clk_core_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 top_nvhsclk_ctrl_swap_clk_core_m(void) -{ - return 0x1U << 13U; -} -static inline u32 top_nvhsclk_ctrl_swap_clk_core_v(u32 r) -{ - return (r >> 13U) & 0x1U; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_trim_gv100.h b/include/nvgpu/hw/gv100/hw_trim_gv100.h deleted file mode 100644 index f1b6da2..0000000 --- a/include/nvgpu/hw/gv100/hw_trim_gv100.h +++ /dev/null @@ -1,247 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_trim_gv100_h_ -#define _hw_trim_gv100_h_ - -static inline u32 trim_sys_nvlink_uphy_cfg_r(void) -{ - return 0x00132410U; -} -static inline u32 trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_f(u32 v) -{ - return (v & 0x3ffU) << 0U; -} -static inline u32 trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_m(void) -{ - return 0x3ffU << 0U; -} -static inline u32 trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_v(u32 r) -{ - return (r >> 0U) & 0x3ffU; -} -static inline u32 trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_m(void) -{ - return 0x1U << 12U; -} -static inline u32 trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_m(void) -{ - return 0xffU << 16U; -} -static inline u32 trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 trim_sys_nvlink0_ctrl_r(void) -{ - return 0x00132420U; -} -static inline u32 trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_m(void) -{ - return 0x1U << 0U; -} -static inline u32 trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 trim_sys_nvlink0_status_r(void) -{ - return 0x00132424U; -} -static inline u32 trim_sys_nvlink0_status_pll_off_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 trim_sys_nvlink0_status_pll_off_m(void) -{ - return 0x1U << 5U; -} -static inline u32 trim_sys_nvlink0_status_pll_off_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_r(void) -{ - return 0x001371c4U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_f(u32 v) -{ - return (v & 0x3U) << 16U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_m(void) -{ - return 0x3U << 16U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_v(u32 r) -{ - return (r >> 16U) & 0x3U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_xtal4x_v(void) -{ - return 0x00000003U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_xtal4x_f(void) -{ - return 0x30000U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_xtal_in_v(void) -{ - return 0x00000000U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_xtal_in_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_m(void) -{ - return 0x3U << 0U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_slowclk_v(void) -{ - return 0x00000000U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_slowclk_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_miscclk_v(void) -{ - return 0x00000002U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_miscclk_f(void) -{ - return 0x2U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_onesrcclk_v(void) -{ - return 0x00000003U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_onesrcclk_f(void) -{ - return 0x3U; -} -static inline u32 trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_r(void) -{ - return 0x00132a70U; -} -static inline u32 trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_source_gpcclk_f(void) -{ - return 0x10000000U; -} -static inline u32 trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cnt0_r(void) -{ - return 0x00132a74U; -} -static inline u32 trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cnt1_r(void) -{ - return 0x00132a78U; -} -static inline u32 trim_sys_nafll_fr_clk_cntr_xbarclk_cfg_r(void) -{ - return 0x00136470U; -} -static inline u32 trim_sys_nafll_fr_clk_cntr_xbarclk_cfg_source_xbarclk_f(void) -{ - return 0x10000000U; -} -static inline u32 trim_sys_nafll_fr_clk_cntr_xbarclk_cntr0_r(void) -{ - return 0x00136474U; -} -static inline u32 trim_sys_nafll_fr_clk_cntr_xbarclk_cntr1_r(void) -{ - return 0x00136478U; -} -static inline u32 trim_sys_fr_clk_cntr_sysclk_cfg_r(void) -{ - return 0x0013762cU; -} -static inline u32 trim_sys_fr_clk_cntr_sysclk_cfg_source_sysclk_f(void) -{ - return 0x20000000U; -} -static inline u32 trim_sys_fr_clk_cntr_sysclk_cntr0_r(void) -{ - return 0x00137630U; -} -static inline u32 trim_sys_fr_clk_cntr_sysclk_cntr1_r(void) -{ - return 0x00137634U; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_usermode_gv100.h b/include/nvgpu/hw/gv100/hw_usermode_gv100.h deleted file mode 100644 index 7b1d861..0000000 --- a/include/nvgpu/hw/gv100/hw_usermode_gv100.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_usermode_gv100_h_ -#define _hw_usermode_gv100_h_ - -static inline u32 usermode_cfg0_r(void) -{ - return 0x00810000U; -} -static inline u32 usermode_cfg0_class_id_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 usermode_cfg0_class_id_value_v(void) -{ - return 0x0000c361U; -} -static inline u32 usermode_time_0_r(void) -{ - return 0x00810080U; -} -static inline u32 usermode_time_0_nsec_f(u32 v) -{ - return (v & 0x7ffffffU) << 5U; -} -static inline u32 usermode_time_1_r(void) -{ - return 0x00810084U; -} -static inline u32 usermode_time_1_nsec_f(u32 v) -{ - return (v & 0x1fffffffU) << 0U; -} -static inline u32 usermode_notify_channel_pending_r(void) -{ - return 0x00810090U; -} -static inline u32 usermode_notify_channel_pending_id_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_xp_gv100.h b/include/nvgpu/hw/gv100/hw_xp_gv100.h deleted file mode 100644 index 4296e04..0000000 --- a/include/nvgpu/hw/gv100/hw_xp_gv100.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_xp_gv100_h_ -#define _hw_xp_gv100_h_ - -static inline u32 xp_dl_mgr_r(u32 i) -{ - return 0x0008b8c0U + i*4U; -} -static inline u32 xp_dl_mgr_safe_timing_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 xp_pl_link_config_r(u32 i) -{ - return 0x0008c040U + i*4U; -} -static inline u32 xp_pl_link_config_ltssm_status_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 xp_pl_link_config_ltssm_status_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 xp_pl_link_config_ltssm_directive_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 xp_pl_link_config_ltssm_directive_m(void) -{ - return 0xfU << 0U; -} -static inline u32 xp_pl_link_config_ltssm_directive_normal_operations_v(void) -{ - return 0x00000000U; -} -static inline u32 xp_pl_link_config_ltssm_directive_change_speed_v(void) -{ - return 0x00000001U; -} -static inline u32 xp_pl_link_config_max_link_rate_f(u32 v) -{ - return (v & 0x3U) << 18U; -} -static inline u32 xp_pl_link_config_max_link_rate_m(void) -{ - return 0x3U << 18U; -} -static inline u32 xp_pl_link_config_max_link_rate_2500_mtps_v(void) -{ - return 0x00000002U; -} -static inline u32 xp_pl_link_config_max_link_rate_5000_mtps_v(void) -{ - return 0x00000001U; -} -static inline u32 xp_pl_link_config_max_link_rate_8000_mtps_v(void) -{ - return 0x00000000U; -} -static inline u32 xp_pl_link_config_target_tx_width_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 xp_pl_link_config_target_tx_width_m(void) -{ - return 0x7U << 20U; -} -static inline u32 xp_pl_link_config_target_tx_width_x1_v(void) -{ - return 0x00000007U; -} -static inline u32 xp_pl_link_config_target_tx_width_x2_v(void) -{ - return 0x00000006U; -} -static inline u32 xp_pl_link_config_target_tx_width_x4_v(void) -{ - return 0x00000005U; -} -static inline u32 xp_pl_link_config_target_tx_width_x8_v(void) -{ - return 0x00000004U; -} -static inline u32 xp_pl_link_config_target_tx_width_x16_v(void) -{ - return 0x00000000U; -} -#endif diff --git a/include/nvgpu/hw/gv100/hw_xve_gv100.h b/include/nvgpu/hw/gv100/hw_xve_gv100.h deleted file mode 100644 index fc7aa72..0000000 --- a/include/nvgpu/hw/gv100/hw_xve_gv100.h +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_xve_gv100_h_ -#define _hw_xve_gv100_h_ - -static inline u32 xve_rom_ctrl_r(void) -{ - return 0x00000050U; -} -static inline u32 xve_rom_ctrl_rom_shadow_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 xve_rom_ctrl_rom_shadow_disabled_f(void) -{ - return 0x0U; -} -static inline u32 xve_rom_ctrl_rom_shadow_enabled_f(void) -{ - return 0x1U; -} -static inline u32 xve_link_control_status_r(void) -{ - return 0x00000088U; -} -static inline u32 xve_link_control_status_link_speed_m(void) -{ - return 0xfU << 16U; -} -static inline u32 xve_link_control_status_link_speed_v(u32 r) -{ - return (r >> 16U) & 0xfU; -} -static inline u32 xve_link_control_status_link_speed_link_speed_2p5_v(void) -{ - return 0x00000001U; -} -static inline u32 xve_link_control_status_link_speed_link_speed_5p0_v(void) -{ - return 0x00000002U; -} -static inline u32 xve_link_control_status_link_speed_link_speed_8p0_v(void) -{ - return 0x00000003U; -} -static inline u32 xve_link_control_status_link_width_m(void) -{ - return 0x3fU << 20U; -} -static inline u32 xve_link_control_status_link_width_v(u32 r) -{ - return (r >> 20U) & 0x3fU; -} -static inline u32 xve_link_control_status_link_width_x1_v(void) -{ - return 0x00000001U; -} -static inline u32 xve_link_control_status_link_width_x2_v(void) -{ - return 0x00000002U; -} -static inline u32 xve_link_control_status_link_width_x4_v(void) -{ - return 0x00000004U; -} -static inline u32 xve_link_control_status_link_width_x8_v(void) -{ - return 0x00000008U; -} -static inline u32 xve_link_control_status_link_width_x16_v(void) -{ - return 0x00000010U; -} -static inline u32 xve_priv_xv_r(void) -{ - return 0x00000150U; -} -static inline u32 xve_priv_xv_cya_l0s_enable_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 xve_priv_xv_cya_l0s_enable_m(void) -{ - return 0x1U << 7U; -} -static inline u32 xve_priv_xv_cya_l0s_enable_v(u32 r) -{ - return (r >> 7U) & 0x1U; -} -static inline u32 xve_priv_xv_cya_l1_enable_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 xve_priv_xv_cya_l1_enable_m(void) -{ - return 0x1U << 8U; -} -static inline u32 xve_priv_xv_cya_l1_enable_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 xve_cya_2_r(void) -{ - return 0x00000704U; -} -static inline u32 xve_reset_r(void) -{ - return 0x00000718U; -} -static inline u32 xve_reset_reset_m(void) -{ - return 0x1U << 0U; -} -static inline u32 xve_reset_gpu_on_sw_reset_m(void) -{ - return 0x1U << 1U; -} -static inline u32 xve_reset_counter_en_m(void) -{ - return 0x1U << 2U; -} -static inline u32 xve_reset_counter_val_f(u32 v) -{ - return (v & 0x7ffU) << 4U; -} -static inline u32 xve_reset_counter_val_m(void) -{ - return 0x7ffU << 4U; -} -static inline u32 xve_reset_counter_val_v(u32 r) -{ - return (r >> 4U) & 0x7ffU; -} -static inline u32 xve_reset_clock_on_sw_reset_m(void) -{ - return 0x1U << 15U; -} -static inline u32 xve_reset_clock_counter_en_m(void) -{ - return 0x1U << 16U; -} -static inline u32 xve_reset_clock_counter_val_f(u32 v) -{ - return (v & 0x7ffU) << 17U; -} -static inline u32 xve_reset_clock_counter_val_m(void) -{ - return 0x7ffU << 17U; -} -static inline u32 xve_reset_clock_counter_val_v(u32 r) -{ - return (r >> 17U) & 0x7ffU; -} -#endif diff --git a/include/nvgpu/hw/gv11b/hw_bus_gv11b.h b/include/nvgpu/hw/gv11b/hw_bus_gv11b.h deleted file mode 100644 index d1d9b34..0000000 --- a/include/nvgpu/hw/gv11b/hw_bus_gv11b.h +++ /dev/null @@ -1,223 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_bus_gv11b_h_ -#define _hw_bus_gv11b_h_ - -static inline u32 bus_bar0_window_r(void) -{ - return 0x00001700U; -} -static inline u32 bus_bar0_window_base_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 bus_bar0_window_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) -{ - return 0x2000000U; -} -static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) -{ - return 0x3000000U; -} -static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) -{ - return 0x00000010U; -} -static inline u32 bus_bar1_block_r(void) -{ - return 0x00001704U; -} -static inline u32 bus_bar1_block_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 bus_bar1_block_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar1_block_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 bus_bar1_block_mode_virtual_f(void) -{ - return 0x80000000U; -} -static inline u32 bus_bar2_block_r(void) -{ - return 0x00001714U; -} -static inline u32 bus_bar2_block_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 bus_bar2_block_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar2_block_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 bus_bar2_block_mode_virtual_f(void) -{ - return 0x80000000U; -} -static inline u32 bus_bar1_block_ptr_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 bus_bar2_block_ptr_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 bus_bind_status_r(void) -{ - return 0x00001710U; -} -static inline u32 bus_bind_status_bar1_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 bus_bind_status_bar1_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar1_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 bus_bind_status_bar1_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 bus_bind_status_bar1_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar1_outstanding_true_f(void) -{ - return 0x2U; -} -static inline u32 bus_bind_status_bar2_pending_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 bus_bind_status_bar2_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar2_pending_busy_f(void) -{ - return 0x4U; -} -static inline u32 bus_bind_status_bar2_outstanding_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 bus_bind_status_bar2_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar2_outstanding_true_f(void) -{ - return 0x8U; -} -static inline u32 bus_intr_0_r(void) -{ - return 0x00001100U; -} -static inline u32 bus_intr_0_pri_squash_m(void) -{ - return 0x1U << 1U; -} -static inline u32 bus_intr_0_pri_fecserr_m(void) -{ - return 0x1U << 2U; -} -static inline u32 bus_intr_0_pri_timeout_m(void) -{ - return 0x1U << 3U; -} -static inline u32 bus_intr_en_0_r(void) -{ - return 0x00001140U; -} -static inline u32 bus_intr_en_0_pri_squash_m(void) -{ - return 0x1U << 1U; -} -static inline u32 bus_intr_en_0_pri_fecserr_m(void) -{ - return 0x1U << 2U; -} -static inline u32 bus_intr_en_0_pri_timeout_m(void) -{ - return 0x1U << 3U; -} -#endif diff --git a/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h b/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h deleted file mode 100644 index e21a473..0000000 --- a/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ccsr_gv11b_h_ -#define _hw_ccsr_gv11b_h_ - -static inline u32 ccsr_channel_inst_r(u32 i) -{ - return 0x00800000U + i*8U; -} -static inline u32 ccsr_channel_inst__size_1_v(void) -{ - return 0x00000200U; -} -static inline u32 ccsr_channel_inst_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 ccsr_channel_inst_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 ccsr_channel_inst_bind_false_f(void) -{ - return 0x0U; -} -static inline u32 ccsr_channel_inst_bind_true_f(void) -{ - return 0x80000000U; -} -static inline u32 ccsr_channel_r(u32 i) -{ - return 0x00800004U + i*8U; -} -static inline u32 ccsr_channel__size_1_v(void) -{ - return 0x00000200U; -} -static inline u32 ccsr_channel_enable_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ccsr_channel_enable_set_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 ccsr_channel_enable_set_true_f(void) -{ - return 0x400U; -} -static inline u32 ccsr_channel_enable_clr_true_f(void) -{ - return 0x800U; -} -static inline u32 ccsr_channel_status_v(u32 r) -{ - return (r >> 24U) & 0xfU; -} -static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) -{ - return 0x00000002U; -} -static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) -{ - return 0x00000004U; -} -static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) -{ - return 0x0000000aU; -} -static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) -{ - return 0x0000000bU; -} -static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) -{ - return 0x0000000cU; -} -static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) -{ - return 0x0000000dU; -} -static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) -{ - return 0x0000000eU; -} -static inline u32 ccsr_channel_next_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ccsr_channel_next_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_force_ctx_reload_true_f(void) -{ - return 0x100U; -} -static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 ccsr_channel_pbdma_faulted_reset_f(void) -{ - return 0x400000U; -} -static inline u32 ccsr_channel_eng_faulted_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 ccsr_channel_eng_faulted_v(u32 r) -{ - return (r >> 23U) & 0x1U; -} -static inline u32 ccsr_channel_eng_faulted_reset_f(void) -{ - return 0x800000U; -} -static inline u32 ccsr_channel_eng_faulted_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_busy_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -#endif diff --git a/include/nvgpu/hw/gv11b/hw_ce_gv11b.h b/include/nvgpu/hw/gv11b/hw_ce_gv11b.h deleted file mode 100644 index 57a76e6..0000000 --- a/include/nvgpu/hw/gv11b/hw_ce_gv11b.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ce_gv11b_h_ -#define _hw_ce_gv11b_h_ - -static inline u32 ce_intr_status_r(u32 i) -{ - return 0x00104410U + i*128U; -} -static inline u32 ce_intr_status_blockpipe_pending_f(void) -{ - return 0x1U; -} -static inline u32 ce_intr_status_blockpipe_reset_f(void) -{ - return 0x1U; -} -static inline u32 ce_intr_status_nonblockpipe_pending_f(void) -{ - return 0x2U; -} -static inline u32 ce_intr_status_nonblockpipe_reset_f(void) -{ - return 0x2U; -} -static inline u32 ce_intr_status_launcherr_pending_f(void) -{ - return 0x4U; -} -static inline u32 ce_intr_status_launcherr_reset_f(void) -{ - return 0x4U; -} -static inline u32 ce_intr_status_invalid_config_pending_f(void) -{ - return 0x8U; -} -static inline u32 ce_intr_status_invalid_config_reset_f(void) -{ - return 0x8U; -} -static inline u32 ce_intr_status_mthd_buffer_fault_pending_f(void) -{ - return 0x10U; -} -static inline u32 ce_intr_status_mthd_buffer_fault_reset_f(void) -{ - return 0x10U; -} -static inline u32 ce_pce_map_r(void) -{ - return 0x00104028U; -} -static inline u32 ce_lce_opt_r(u32 i) -{ - return 0x00104414U + i*128U; -} -static inline u32 ce_lce_opt_force_barriers_npl__prod_f(void) -{ - return 0x8U; -} -#endif diff --git a/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h b/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h deleted file mode 100644 index 8b095b1..0000000 --- a/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h +++ /dev/null @@ -1,463 +0,0 @@ -/* - * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ctxsw_prog_gv11b_h_ -#define _hw_ctxsw_prog_gv11b_h_ - -static inline u32 ctxsw_prog_fecs_header_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) -{ - return 0x00000008U; -} -static inline u32 ctxsw_prog_main_image_ctl_o(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_main_image_ctl_type_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_undefined_v(void) -{ - return 0x00000000U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_opengl_v(void) -{ - return 0x00000008U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_dx9_v(void) -{ - return 0x00000010U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_dx10_v(void) -{ - return 0x00000011U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_dx11_v(void) -{ - return 0x00000012U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_compute_v(void) -{ - return 0x00000020U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_per_veid_header_v(void) -{ - return 0x00000021U; -} -static inline u32 ctxsw_prog_main_image_patch_count_o(void) -{ - return 0x00000010U; -} -static inline u32 ctxsw_prog_main_image_context_id_o(void) -{ - return 0x000000f0U; -} -static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) -{ - return 0x00000014U; -} -static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) -{ - return 0x00000018U; -} -static inline u32 ctxsw_prog_main_image_zcull_o(void) -{ - return 0x0000001cU; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) -{ - return 0x00000001U; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) -{ - return 0x00000020U; -} -static inline u32 ctxsw_prog_main_image_pm_o(void) -{ - return 0x00000028U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_m(void) -{ - return 0x7U << 0U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_ctxsw_f(void) -{ - return 0x1U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_stream_out_ctxsw_f(void) -{ - return 0x2U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) -{ - return 0x7U << 3U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) -{ - return 0x8U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) -{ - return 0x0000002cU; -} -static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) -{ - return 0x000000f4U; -} -static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void) -{ - return 0x000000d0U; -} -static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void) -{ - return 0x000000d4U; -} -static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void) -{ - return 0x000000d8U; -} -static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void) -{ - return 0x000000dcU; -} -static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) -{ - return 0x000000f8U; -} -static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_o(void) -{ - return 0x00000060U; -} -static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_pm_ptr_hi_o(void) -{ - return 0x00000094U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_o(void) -{ - return 0x00000064U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void) -{ - return 0x00000068U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_o(void) -{ - return 0x00000070U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_o(void) -{ - return 0x00000074U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_o(void) -{ - return 0x00000078U; -} -static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_context_buffer_ptr_o(void) -{ - return 0x0000007cU; -} -static inline u32 ctxsw_prog_main_image_context_buffer_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_magic_value_o(void) -{ - return 0x000000fcU; -} -static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) -{ - return 0x600dc0deU; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_main_image_global_cb_ptr_o(void) -{ - return 0x000000b8U; -} -static inline u32 ctxsw_prog_main_image_global_cb_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_o(void) -{ - return 0x000000bcU; -} -static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_o(void) -{ - return 0x000000c0U; -} -static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_o(void) -{ - return 0x000000c4U; -} -static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_control_block_ptr_o(void) -{ - return 0x000000c8U; -} -static inline u32 ctxsw_prog_main_image_control_block_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_o(void) -{ - return 0x000000ccU; -} -static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_o(void) -{ - return 0x000000e0U; -} -static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_o(void) -{ - return 0x000000e4U; -} -static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_local_image_ppc_info_o(void) -{ - return 0x000000f4U; -} -static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) -{ - return 0x000000f8U; -} -static inline u32 ctxsw_prog_local_magic_value_o(void) -{ - return 0x000000fcU; -} -static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) -{ - return 0xad0becabU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) -{ - return 0x000000ecU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) -{ - return 0x00000000U; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) -{ - return 0x000000a0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) -{ - return 2U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) -{ - return 0x3U << 0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) -{ - return 0x2U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) -{ - return 0x000000a4U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) -{ - return 0x000000a8U; -} -static inline u32 ctxsw_prog_main_image_misc_options_o(void) -{ - return 0x0000003cU; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) -{ - return 0x1U << 3U; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void) -{ - return 0x00000080U; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void) -{ - return 0x1U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void) -{ - return 0x00000084U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void) -{ - return 0x1U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void) -{ - return 0x2U; -} -#endif diff --git a/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h b/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h deleted file mode 100644 index 31e883e..0000000 --- a/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h +++ /dev/null @@ -1,603 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_falcon_gv11b_h_ -#define _hw_falcon_gv11b_h_ - -static inline u32 falcon_falcon_irqsset_r(void) -{ - return 0x00000000U; -} -static inline u32 falcon_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 falcon_falcon_irqsclr_r(void) -{ - return 0x00000004U; -} -static inline u32 falcon_falcon_irqstat_r(void) -{ - return 0x00000008U; -} -static inline u32 falcon_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 falcon_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 falcon_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 falcon_falcon_irqmode_r(void) -{ - return 0x0000000cU; -} -static inline u32 falcon_falcon_irqmset_r(void) -{ - return 0x00000010U; -} -static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqmclr_r(void) -{ - return 0x00000014U; -} -static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_irqmask_r(void) -{ - return 0x00000018U; -} -static inline u32 falcon_falcon_irqdest_r(void) -{ - return 0x0000001cU; -} -static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 falcon_falcon_curctx_r(void) -{ - return 0x00000050U; -} -static inline u32 falcon_falcon_nxtctx_r(void) -{ - return 0x00000054U; -} -static inline u32 falcon_falcon_mailbox0_r(void) -{ - return 0x00000040U; -} -static inline u32 falcon_falcon_mailbox1_r(void) -{ - return 0x00000044U; -} -static inline u32 falcon_falcon_itfen_r(void) -{ - return 0x00000048U; -} -static inline u32 falcon_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 falcon_falcon_idlestate_r(void) -{ - return 0x0000004cU; -} -static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 falcon_falcon_os_r(void) -{ - return 0x00000080U; -} -static inline u32 falcon_falcon_engctl_r(void) -{ - return 0x000000a4U; -} -static inline u32 falcon_falcon_cpuctl_r(void) -{ - return 0x00000100U; -} -static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_m(void) -{ - return 0x1U << 4U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 falcon_falcon_cpuctl_stopped_m(void) -{ - return 0x1U << 5U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void) -{ - return 0x1U << 6U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 falcon_falcon_cpuctl_alias_r(void) -{ - return 0x00000130U; -} -static inline u32 falcon_falcon_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_imemc_r(u32 i) -{ - return 0x00000180U + i*16U; -} -static inline u32 falcon_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 falcon_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 falcon_falcon_imemc_secure_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 falcon_falcon_imemd_r(u32 i) -{ - return 0x00000184U + i*16U; -} -static inline u32 falcon_falcon_imemt_r(u32 i) -{ - return 0x00000188U + i*16U; -} -static inline u32 falcon_falcon_sctl_r(void) -{ - return 0x00000240U; -} -static inline u32 falcon_falcon_mmu_phys_sec_r(void) -{ - return 0x00100ce4U; -} -static inline u32 falcon_falcon_bootvec_r(void) -{ - return 0x00000104U; -} -static inline u32 falcon_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 falcon_falcon_dmactl_r(void) -{ - return 0x0000010cU; -} -static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void) -{ - return 0x1U << 1U; -} -static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void) -{ - return 0x1U << 2U; -} -static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_hwcfg_r(void) -{ - return 0x00000108U; -} -static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 falcon_falcon_dmatrfbase_r(void) -{ - return 0x00000110U; -} -static inline u32 falcon_falcon_dmatrfbase1_r(void) -{ - return 0x00000128U; -} -static inline u32 falcon_falcon_dmatrfmoffs_r(void) -{ - return 0x00000114U; -} -static inline u32 falcon_falcon_dmatrfcmd_r(void) -{ - return 0x00000118U; -} -static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 falcon_falcon_dmatrffboffs_r(void) -{ - return 0x0000011cU; -} -static inline u32 falcon_falcon_imctl_debug_r(void) -{ - return 0x0000015cU; -} -static inline u32 falcon_falcon_imctl_debug_addr_blk_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 falcon_falcon_imctl_debug_cmd_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 falcon_falcon_imstat_r(void) -{ - return 0x00000144U; -} -static inline u32 falcon_falcon_traceidx_r(void) -{ - return 0x00000148U; -} -static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 falcon_falcon_traceidx_idx_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 falcon_falcon_tracepc_r(void) -{ - return 0x0000014cU; -} -static inline u32 falcon_falcon_tracepc_pc_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 falcon_falcon_exterraddr_r(void) -{ - return 0x00000168U; -} -static inline u32 falcon_falcon_exterrstat_r(void) -{ - return 0x0000016cU; -} -static inline u32 falcon_falcon_exterrstat_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 falcon_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 falcon_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 falcon_falcon_icd_cmd_r(void) -{ - return 0x00000200U; -} -static inline u32 falcon_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 falcon_falcon_icd_cmd_opc_m(void) -{ - return 0xfU << 0U; -} -static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 falcon_falcon_icd_rdata_r(void) -{ - return 0x0000020cU; -} -static inline u32 falcon_falcon_dmemc_r(u32 i) -{ - return 0x000001c0U + i*8U; -} -static inline u32 falcon_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 falcon_falcon_dmemc_offs_m(void) -{ - return 0x3fU << 2U; -} -static inline u32 falcon_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_dmemc_blk_m(void) -{ - return 0xffU << 8U; -} -static inline u32 falcon_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 falcon_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 falcon_falcon_dmemd_r(u32 i) -{ - return 0x000001c4U + i*8U; -} -static inline u32 falcon_falcon_debug1_r(void) -{ - return 0x00000090U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void) -{ - return 1U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void) -{ - return 0x1U << 16U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void) -{ - return 0x0U; -} -static inline u32 falcon_falcon_debuginfo_r(void) -{ - return 0x00000094U; -} -#endif diff --git a/include/nvgpu/hw/gv11b/hw_fb_gv11b.h b/include/nvgpu/hw/gv11b/hw_fb_gv11b.h deleted file mode 100644 index 767fc5a..0000000 --- a/include/nvgpu/hw/gv11b/hw_fb_gv11b.h +++ /dev/null @@ -1,1867 +0,0 @@ -/* - * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_fb_gv11b_h_ -#define _hw_fb_gv11b_h_ - -static inline u32 fb_fbhub_num_active_ltcs_r(void) -{ - return 0x00100800U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_m(void) -{ - return 0x1U << 25U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f(void) -{ - return 0x2000000U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_ncoh_atomic_mode_m(void) -{ - return 0x1U << 26U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_ncoh_atomic_mode_use_read_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_ctrl_r(void) -{ - return 0x00100c80U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_m(void) -{ - return 0x3U << 24U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_l2_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_rmw_f(void) -{ - return 0x2000000U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_m(void) -{ - return 0x1U << 27U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_l2_f(void) -{ - return 0x0U; -} -static inline u32 fb_hshub_num_active_ltcs_r(void) -{ - return 0x001fbc20U; -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m(void) -{ - return 0x1U << 25U; -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_read_f(void) -{ - return 0x0U; -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f(void) -{ - return 0x2000000U; -} -static inline u32 fb_priv_mmu_phy_secure_r(void) -{ - return 0x00100ce4U; -} -static inline u32 fb_mmu_invalidate_pdb_r(void) -{ - return 0x00100cb8U; -} -static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_invalidate_r(void) -{ - return 0x00100cbcU; -} -static inline u32 fb_mmu_invalidate_all_va_true_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_m(void) -{ - return 0x1U << 2U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_invalidate_replay_s(void) -{ - return 3U; -} -static inline u32 fb_mmu_invalidate_replay_f(u32 v) -{ - return (v & 0x7U) << 3U; -} -static inline u32 fb_mmu_invalidate_replay_m(void) -{ - return 0x7U << 3U; -} -static inline u32 fb_mmu_invalidate_replay_v(u32 r) -{ - return (r >> 3U) & 0x7U; -} -static inline u32 fb_mmu_invalidate_replay_none_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_replay_start_f(void) -{ - return 0x8U; -} -static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void) -{ - return 0x10U; -} -static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void) -{ - return 0x20U; -} -static inline u32 fb_mmu_invalidate_sys_membar_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 fb_mmu_invalidate_sys_membar_m(void) -{ - return 0x1U << 6U; -} -static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_sys_membar_true_f(void) -{ - return 0x40U; -} -static inline u32 fb_mmu_invalidate_ack_s(void) -{ - return 2U; -} -static inline u32 fb_mmu_invalidate_ack_f(u32 v) -{ - return (v & 0x3U) << 7U; -} -static inline u32 fb_mmu_invalidate_ack_m(void) -{ - return 0x3U << 7U; -} -static inline u32 fb_mmu_invalidate_ack_v(u32 r) -{ - return (r >> 7U) & 0x3U; -} -static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void) -{ - return 0x100U; -} -static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void) -{ - return 0x80U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_s(void) -{ - return 6U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v) -{ - return (v & 0x3fU) << 9U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_m(void) -{ - return 0x3fU << 9U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r) -{ - return (r >> 9U) & 0x3fU; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void) -{ - return 5U; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v) -{ - return (v & 0x1fU) << 15U; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void) -{ - return 0x1fU << 15U; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r) -{ - return (r >> 15U) & 0x1fU; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_m(void) -{ - return 0x1U << 20U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void) -{ - return 0x100000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void) -{ - return 3U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void) -{ - return 0x7U << 24U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r) -{ - return (r >> 24U) & 0x7U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void) -{ - return 0x1000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void) -{ - return 0x2000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void) -{ - return 0x3000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void) -{ - return 0x4000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void) -{ - return 0x5000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void) -{ - return 0x6000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void) -{ - return 0x7000000U; -} -static inline u32 fb_mmu_invalidate_trigger_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_trigger_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_invalidate_trigger_m(void) -{ - return 0x1U << 31U; -} -static inline u32 fb_mmu_invalidate_trigger_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_trigger_true_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_debug_wr_r(void) -{ - return 0x00100cc8U; -} -static inline u32 fb_mmu_debug_wr_aperture_s(void) -{ - return 2U; -} -static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 fb_mmu_debug_wr_aperture_m(void) -{ - return 0x3U << 0U; -} -static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_debug_wr_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_wr_vol_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_debug_wr_vol_true_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_debug_wr_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) -{ - return 0x0000000cU; -} -static inline u32 fb_mmu_debug_rd_r(void) -{ - return 0x00100cccU; -} -static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_debug_rd_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_rd_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) -{ - return 0x0000000cU; -} -static inline u32 fb_mmu_debug_ctrl_r(void) -{ - return 0x00100cc4U; -} -static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 fb_mmu_debug_ctrl_debug_m(void) -{ - return 0x1U << 16U; -} -static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_vpr_info_r(void) -{ - return 0x00100cd0U; -} -static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 fb_mmu_vpr_info_fetch_false_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_vpr_info_fetch_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_l2tlb_ecc_status_r(void) -{ - return 0x00100e70U; -} -static inline u32 fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb_sa_data_m(void) -{ - return 0x1U << 0U; -} -static inline u32 fb_mmu_l2tlb_ecc_status_uncorrected_err_l2tlb_sa_data_m(void) -{ - return 0x1U << 1U; -} -static inline u32 fb_mmu_l2tlb_ecc_status_corrected_err_total_counter_overflow_m(void) -{ - return 0x1U << 16U; -} -static inline u32 fb_mmu_l2tlb_ecc_status_uncorrected_err_total_counter_overflow_m(void) -{ - return 0x1U << 18U; -} -static inline u32 fb_mmu_l2tlb_ecc_status_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_mmu_l2tlb_ecc_status_reset_clear_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_r(void) -{ - return 0x00100e74U; -} -static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_r(void) -{ - return 0x00100e78U; -} -static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_mmu_l2tlb_ecc_address_r(void) -{ - return 0x00100e7cU; -} -static inline u32 fb_mmu_l2tlb_ecc_address_index_s(void) -{ - return 32U; -} -static inline u32 fb_mmu_l2tlb_ecc_address_index_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 fb_mmu_l2tlb_ecc_address_index_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 fb_mmu_l2tlb_ecc_address_index_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 fb_mmu_hubtlb_ecc_status_r(void) -{ - return 0x00100e84U; -} -static inline u32 fb_mmu_hubtlb_ecc_status_corrected_err_sa_data_m(void) -{ - return 0x1U << 0U; -} -static inline u32 fb_mmu_hubtlb_ecc_status_uncorrected_err_sa_data_m(void) -{ - return 0x1U << 1U; -} -static inline u32 fb_mmu_hubtlb_ecc_status_corrected_err_total_counter_overflow_m(void) -{ - return 0x1U << 16U; -} -static inline u32 fb_mmu_hubtlb_ecc_status_uncorrected_err_total_counter_overflow_m(void) -{ - return 0x1U << 18U; -} -static inline u32 fb_mmu_hubtlb_ecc_status_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_mmu_hubtlb_ecc_status_reset_clear_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_r(void) -{ - return 0x00100e88U; -} -static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_r(void) -{ - return 0x00100e8cU; -} -static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_mmu_hubtlb_ecc_address_r(void) -{ - return 0x00100e90U; -} -static inline u32 fb_mmu_hubtlb_ecc_address_index_s(void) -{ - return 32U; -} -static inline u32 fb_mmu_hubtlb_ecc_address_index_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 fb_mmu_hubtlb_ecc_address_index_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 fb_mmu_hubtlb_ecc_address_index_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 fb_mmu_fillunit_ecc_status_r(void) -{ - return 0x00100e98U; -} -static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_pte_data_m(void) -{ - return 0x1U << 0U; -} -static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_pte_data_m(void) -{ - return 0x1U << 1U; -} -static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_pde0_data_m(void) -{ - return 0x1U << 2U; -} -static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_pde0_data_m(void) -{ - return 0x1U << 3U; -} -static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_total_counter_overflow_m(void) -{ - return 0x1U << 16U; -} -static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_total_counter_overflow_m(void) -{ - return 0x1U << 18U; -} -static inline u32 fb_mmu_fillunit_ecc_status_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_mmu_fillunit_ecc_status_reset_clear_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_r(void) -{ - return 0x00100e9cU; -} -static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_r(void) -{ - return 0x00100ea0U; -} -static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_mmu_fillunit_ecc_address_r(void) -{ - return 0x00100ea4U; -} -static inline u32 fb_mmu_fillunit_ecc_address_index_s(void) -{ - return 32U; -} -static inline u32 fb_mmu_fillunit_ecc_address_index_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 fb_mmu_fillunit_ecc_address_index_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 fb_mmu_fillunit_ecc_address_index_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 fb_niso_flush_sysmem_addr_r(void) -{ - return 0x00100c10U; -} -static inline u32 fb_niso_intr_r(void) -{ - return 0x00100a20U; -} -static inline u32 fb_niso_intr_hub_access_counter_notify_m(void) -{ - return 0x1U << 0U; -} -static inline u32 fb_niso_intr_hub_access_counter_notify_pending_f(void) -{ - return 0x1U; -} -static inline u32 fb_niso_intr_hub_access_counter_error_m(void) -{ - return 0x1U << 1U; -} -static inline u32 fb_niso_intr_hub_access_counter_error_pending_f(void) -{ - return 0x2U; -} -static inline u32 fb_niso_intr_mmu_replayable_fault_notify_m(void) -{ - return 0x1U << 27U; -} -static inline u32 fb_niso_intr_mmu_replayable_fault_notify_pending_f(void) -{ - return 0x8000000U; -} -static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_m(void) -{ - return 0x1U << 28U; -} -static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_pending_f(void) -{ - return 0x10000000U; -} -static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_m(void) -{ - return 0x1U << 29U; -} -static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_m(void) -{ - return 0x1U << 30U; -} -static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_niso_intr_mmu_other_fault_notify_m(void) -{ - return 0x1U << 31U; -} -static inline u32 fb_niso_intr_mmu_other_fault_notify_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_niso_intr_mmu_ecc_uncorrected_error_notify_m(void) -{ - return 0x1U << 26U; -} -static inline u32 fb_niso_intr_mmu_ecc_uncorrected_error_notify_pending_f(void) -{ - return 0x4000000U; -} -static inline u32 fb_niso_intr_en_r(u32 i) -{ - return 0x00100a24U + i*4U; -} -static inline u32 fb_niso_intr_en__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_niso_intr_en_hub_access_counter_notify_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 fb_niso_intr_en_hub_access_counter_notify_enabled_f(void) -{ - return 0x1U; -} -static inline u32 fb_niso_intr_en_hub_access_counter_error_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 fb_niso_intr_en_hub_access_counter_error_enabled_f(void) -{ - return 0x2U; -} -static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_f(u32 v) -{ - return (v & 0x1U) << 27U; -} -static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_enabled_f(void) -{ - return 0x8000000U; -} -static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_f(u32 v) -{ - return (v & 0x1U) << 29U; -} -static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_enabled_f(void) -{ - return 0x20000000U; -} -static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_enabled_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_niso_intr_en_mmu_other_fault_notify_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_niso_intr_en_mmu_other_fault_notify_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_niso_intr_en_mmu_ecc_uncorrected_error_notify_f(u32 v) -{ - return (v & 0x1U) << 26U; -} -static inline u32 fb_niso_intr_en_mmu_ecc_uncorrected_error_notify_enabled_f(void) -{ - return 0x4000000U; -} -static inline u32 fb_niso_intr_en_set_r(u32 i) -{ - return 0x00100a2cU + i*4U; -} -static inline u32 fb_niso_intr_en_set__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_m(void) -{ - return 0x1U << 0U; -} -static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_set_f(void) -{ - return 0x1U; -} -static inline u32 fb_niso_intr_en_set_hub_access_counter_error_m(void) -{ - return 0x1U << 1U; -} -static inline u32 fb_niso_intr_en_set_hub_access_counter_error_set_f(void) -{ - return 0x2U; -} -static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_m(void) -{ - return 0x1U << 27U; -} -static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_set_f(void) -{ - return 0x8000000U; -} -static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_m(void) -{ - return 0x1U << 28U; -} -static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_set_f(void) -{ - return 0x10000000U; -} -static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m(void) -{ - return 0x1U << 29U; -} -static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_set_f(void) -{ - return 0x20000000U; -} -static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m(void) -{ - return 0x1U << 30U; -} -static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_set_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_m(void) -{ - return 0x1U << 31U; -} -static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_set_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_m(void) -{ - return 0x1U << 26U; -} -static inline u32 fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_set_f(void) -{ - return 0x4000000U; -} -static inline u32 fb_niso_intr_en_clr_r(u32 i) -{ - return 0x00100a34U + i*4U; -} -static inline u32 fb_niso_intr_en_clr__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_m(void) -{ - return 0x1U << 0U; -} -static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_set_f(void) -{ - return 0x1U; -} -static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_m(void) -{ - return 0x1U << 1U; -} -static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_set_f(void) -{ - return 0x2U; -} -static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_m(void) -{ - return 0x1U << 27U; -} -static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_set_f(void) -{ - return 0x8000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_m(void) -{ - return 0x1U << 28U; -} -static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_set_f(void) -{ - return 0x10000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_m(void) -{ - return 0x1U << 29U; -} -static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_set_f(void) -{ - return 0x20000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_m(void) -{ - return 0x1U << 30U; -} -static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_set_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_m(void) -{ - return 0x1U << 31U; -} -static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_set_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_m(void) -{ - return 0x1U << 26U; -} -static inline u32 fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_set_f(void) -{ - return 0x4000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_non_replay_fault_buffer_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_replay_fault_buffer_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_lo_r(u32 i) -{ - return 0x00100e24U + i*20U; -} -static inline u32 fb_mmu_fault_buffer_lo__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_f(u32 v) -{ - return (v & 0x3U) << 1U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_v(u32 r) -{ - return (r >> 1U) & 0x3U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_v(void) -{ - return 0x00000003U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_f(void) -{ - return 0x6U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_vol_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_vol_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_v(u32 r) -{ - return (r >> 12U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_b(void) -{ - return 12U; -} -static inline u32 fb_mmu_fault_buffer_hi_r(u32 i) -{ - return 0x00100e28U + i*20U; -} -static inline u32 fb_mmu_fault_buffer_hi__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_hi_addr_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 fb_mmu_fault_buffer_hi_addr_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 fb_mmu_fault_buffer_get_r(u32 i) -{ - return 0x00100e2cU + i*20U; -} -static inline u32 fb_mmu_fault_buffer_get__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_get_ptr_f(u32 v) -{ - return (v & 0xfffffU) << 0U; -} -static inline u32 fb_mmu_fault_buffer_get_ptr_m(void) -{ - return 0xfffffU << 0U; -} -static inline u32 fb_mmu_fault_buffer_get_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_m(void) -{ - return 0x1U << 30U; -} -static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_m(void) -{ - return 0x1U << 31U; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_clear_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_fault_buffer_put_r(u32 i) -{ - return 0x00100e30U + i*20U; -} -static inline u32 fb_mmu_fault_buffer_put__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_put_ptr_f(u32 v) -{ - return (v & 0xfffffU) << 0U; -} -static inline u32 fb_mmu_fault_buffer_put_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_buffer_put_overflow_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_fault_buffer_put_overflow_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_put_overflow_yes_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_put_overflow_yes_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_fault_buffer_size_r(u32 i) -{ - return 0x00100e34U + i*20U; -} -static inline u32 fb_mmu_fault_buffer_size__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_size_val_f(u32 v) -{ - return (v & 0xfffffU) << 0U; -} -static inline u32 fb_mmu_fault_buffer_size_val_v(u32 r) -{ - return (r >> 0U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_buffer_size_overflow_intr_f(u32 v) -{ - return (v & 0x1U) << 29U; -} -static inline u32 fb_mmu_fault_buffer_size_overflow_intr_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_f(void) -{ - return 0x20000000U; -} -static inline u32 fb_mmu_fault_buffer_size_set_default_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_mmu_fault_buffer_size_set_default_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_size_set_default_yes_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_size_set_default_yes_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_fault_buffer_size_enable_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_fault_buffer_size_enable_m(void) -{ - return 0x1U << 31U; -} -static inline u32 fb_mmu_fault_buffer_size_enable_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_size_enable_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_size_enable_true_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_fault_addr_lo_r(void) -{ - return 0x00100e4cU; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_v(void) -{ - return 0x00000003U; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_fault_addr_lo_addr_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 fb_mmu_fault_addr_lo_addr_v(u32 r) -{ - return (r >> 12U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_addr_lo_addr_b(void) -{ - return 12U; -} -static inline u32 fb_mmu_fault_addr_hi_r(void) -{ - return 0x00100e50U; -} -static inline u32 fb_mmu_fault_addr_hi_addr_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 fb_mmu_fault_addr_hi_addr_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 fb_mmu_fault_inst_lo_r(void) -{ - return 0x00100e54U; -} -static inline u32 fb_mmu_fault_inst_lo_engine_id_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 fb_mmu_fault_inst_lo_aperture_v(u32 r) -{ - return (r >> 10U) & 0x3U; -} -static inline u32 fb_mmu_fault_inst_lo_aperture_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_inst_lo_aperture_sys_nocoh_v(void) -{ - return 0x00000003U; -} -static inline u32 fb_mmu_fault_inst_lo_addr_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 fb_mmu_fault_inst_lo_addr_v(u32 r) -{ - return (r >> 12U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_inst_lo_addr_b(void) -{ - return 12U; -} -static inline u32 fb_mmu_fault_inst_hi_r(void) -{ - return 0x00100e58U; -} -static inline u32 fb_mmu_fault_inst_hi_addr_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 fb_mmu_fault_info_r(void) -{ - return 0x00100e5cU; -} -static inline u32 fb_mmu_fault_info_fault_type_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 fb_mmu_fault_info_replayable_fault_v(u32 r) -{ - return (r >> 7U) & 0x1U; -} -static inline u32 fb_mmu_fault_info_client_v(u32 r) -{ - return (r >> 8U) & 0x7fU; -} -static inline u32 fb_mmu_fault_info_access_type_v(u32 r) -{ - return (r >> 16U) & 0xfU; -} -static inline u32 fb_mmu_fault_info_client_type_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 fb_mmu_fault_info_gpc_id_v(u32 r) -{ - return (r >> 24U) & 0x1fU; -} -static inline u32 fb_mmu_fault_info_protected_mode_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 fb_mmu_fault_info_replayable_fault_en_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fb_mmu_fault_info_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fb_mmu_fault_status_r(void) -{ - return 0x00100e60U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_m(void) -{ - return 0x1U << 0U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_m(void) -{ - return 0x1U << 1U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_m(void) -{ - return 0x1U << 2U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_m(void) -{ - return 0x1U << 3U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_f(void) -{ - return 0x8U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_f(void) -{ - return 0x8U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_m(void) -{ - return 0x1U << 4U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_f(void) -{ - return 0x10U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_f(void) -{ - return 0x10U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_m(void) -{ - return 0x1U << 5U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_f(void) -{ - return 0x20U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_f(void) -{ - return 0x20U; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_m(void) -{ - return 0x1U << 6U; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_set_f(void) -{ - return 0x40U; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_f(void) -{ - return 0x40U; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_m(void) -{ - return 0x1U << 7U; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_set_f(void) -{ - return 0x80U; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_f(void) -{ - return 0x80U; -} -static inline u32 fb_mmu_fault_status_replayable_m(void) -{ - return 0x1U << 8U; -} -static inline u32 fb_mmu_fault_status_replayable_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_replayable_set_f(void) -{ - return 0x100U; -} -static inline u32 fb_mmu_fault_status_replayable_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_non_replayable_m(void) -{ - return 0x1U << 9U; -} -static inline u32 fb_mmu_fault_status_non_replayable_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_non_replayable_set_f(void) -{ - return 0x200U; -} -static inline u32 fb_mmu_fault_status_non_replayable_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_replayable_error_m(void) -{ - return 0x1U << 10U; -} -static inline u32 fb_mmu_fault_status_replayable_error_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_replayable_error_set_f(void) -{ - return 0x400U; -} -static inline u32 fb_mmu_fault_status_replayable_error_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_non_replayable_error_m(void) -{ - return 0x1U << 11U; -} -static inline u32 fb_mmu_fault_status_non_replayable_error_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_non_replayable_error_set_f(void) -{ - return 0x800U; -} -static inline u32 fb_mmu_fault_status_non_replayable_error_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_replayable_overflow_m(void) -{ - return 0x1U << 12U; -} -static inline u32 fb_mmu_fault_status_replayable_overflow_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_replayable_overflow_set_f(void) -{ - return 0x1000U; -} -static inline u32 fb_mmu_fault_status_replayable_overflow_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_non_replayable_overflow_m(void) -{ - return 0x1U << 13U; -} -static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_f(void) -{ - return 0x2000U; -} -static inline u32 fb_mmu_fault_status_non_replayable_overflow_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_m(void) -{ - return 0x1U << 14U; -} -static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_f(void) -{ - return 0x4000U; -} -static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_m(void) -{ - return 0x1U << 15U; -} -static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_f(void) -{ - return 0x8000U; -} -static inline u32 fb_mmu_fault_status_busy_m(void) -{ - return 0x1U << 30U; -} -static inline u32 fb_mmu_fault_status_busy_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_busy_true_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_fault_status_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 fb_mmu_fault_status_valid_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_valid_set_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_fault_status_valid_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_valid_clear_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_num_active_ltcs_r(void) -{ - return 0x00100ec0U; -} -static inline u32 fb_mmu_num_active_ltcs_count_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 fb_mmu_num_active_ltcs_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 fb_mmu_cbc_base_r(void) -{ - return 0x00100ec4U; -} -static inline u32 fb_mmu_cbc_base_address_f(u32 v) -{ - return (v & 0x3ffffffU) << 0U; -} -static inline u32 fb_mmu_cbc_base_address_v(u32 r) -{ - return (r >> 0U) & 0x3ffffffU; -} -static inline u32 fb_mmu_cbc_base_address_alignment_shift_v(void) -{ - return 0x0000000bU; -} -static inline u32 fb_mmu_cbc_top_r(void) -{ - return 0x00100ec8U; -} -static inline u32 fb_mmu_cbc_top_size_f(u32 v) -{ - return (v & 0x7fffU) << 0U; -} -static inline u32 fb_mmu_cbc_top_size_v(u32 r) -{ - return (r >> 0U) & 0x7fffU; -} -static inline u32 fb_mmu_cbc_top_size_alignment_shift_v(void) -{ - return 0x0000000bU; -} -static inline u32 fb_mmu_cbc_max_r(void) -{ - return 0x00100eccU; -} -static inline u32 fb_mmu_cbc_max_comptagline_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 fb_mmu_cbc_max_comptagline_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 fb_mmu_cbc_max_safe_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_mmu_cbc_max_safe_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_cbc_max_safe_false_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_cbc_max_unsafe_fault_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_cbc_max_unsafe_fault_enabled_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_cbc_max_unsafe_fault_disabled_v(void) -{ - return 0x00000001U; -} -#endif diff --git a/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h deleted file mode 100644 index 9ec30bf..0000000 --- a/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h +++ /dev/null @@ -1,667 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_fifo_gv11b_h_ -#define _hw_fifo_gv11b_h_ - -static inline u32 fifo_bar1_base_r(void) -{ - return 0x00002254U; -} -static inline u32 fifo_bar1_base_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 fifo_bar1_base_ptr_align_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 fifo_bar1_base_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 fifo_bar1_base_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 fifo_userd_writeback_r(void) -{ - return 0x0000225cU; -} -static inline u32 fifo_userd_writeback_timer_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fifo_userd_writeback_timer_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_userd_writeback_timer_shorter_v(void) -{ - return 0x00000003U; -} -static inline u32 fifo_userd_writeback_timer_100us_v(void) -{ - return 0x00000064U; -} -static inline u32 fifo_userd_writeback_timescale_f(u32 v) -{ - return (v & 0xfU) << 12U; -} -static inline u32 fifo_userd_writeback_timescale_0_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_runlist_base_r(void) -{ - return 0x00002270U; -} -static inline u32 fifo_runlist_base_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 fifo_runlist_base_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 fifo_runlist_r(void) -{ - return 0x00002274U; -} -static inline u32 fifo_runlist_engine_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 fifo_eng_runlist_base_r(u32 i) -{ - return 0x00002280U + i*8U; -} -static inline u32 fifo_eng_runlist_base__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fifo_eng_runlist_r(u32 i) -{ - return 0x00002284U + i*8U; -} -static inline u32 fifo_eng_runlist__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fifo_eng_runlist_length_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fifo_eng_runlist_length_max_v(void) -{ - return 0x0000ffffU; -} -static inline u32 fifo_eng_runlist_pending_true_f(void) -{ - return 0x100000U; -} -static inline u32 fifo_pb_timeslice_r(u32 i) -{ - return 0x00002350U + i*4U; -} -static inline u32 fifo_pb_timeslice_timeout_16_f(void) -{ - return 0x10U; -} -static inline u32 fifo_pb_timeslice_timescale_0_f(void) -{ - return 0x0U; -} -static inline u32 fifo_pb_timeslice_enable_true_f(void) -{ - return 0x10000000U; -} -static inline u32 fifo_pbdma_map_r(u32 i) -{ - return 0x00002390U + i*4U; -} -static inline u32 fifo_intr_0_r(void) -{ - return 0x00002100U; -} -static inline u32 fifo_intr_0_bind_error_pending_f(void) -{ - return 0x1U; -} -static inline u32 fifo_intr_0_bind_error_reset_f(void) -{ - return 0x1U; -} -static inline u32 fifo_intr_0_sched_error_pending_f(void) -{ - return 0x100U; -} -static inline u32 fifo_intr_0_sched_error_reset_f(void) -{ - return 0x100U; -} -static inline u32 fifo_intr_0_chsw_error_pending_f(void) -{ - return 0x10000U; -} -static inline u32 fifo_intr_0_chsw_error_reset_f(void) -{ - return 0x10000U; -} -static inline u32 fifo_intr_0_memop_timeout_pending_f(void) -{ - return 0x800000U; -} -static inline u32 fifo_intr_0_memop_timeout_reset_f(void) -{ - return 0x800000U; -} -static inline u32 fifo_intr_0_lb_error_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_intr_0_lb_error_reset_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 fifo_intr_0_runlist_event_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 fifo_intr_0_channel_intr_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 fifo_intr_0_ctxsw_timeout_pending_f(void) -{ - return 0x2U; -} -static inline u32 fifo_intr_en_0_r(void) -{ - return 0x00002140U; -} -static inline u32 fifo_intr_en_0_sched_error_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 fifo_intr_en_0_sched_error_m(void) -{ - return 0x1U << 8U; -} -static inline u32 fifo_intr_en_0_ctxsw_timeout_pending_f(void) -{ - return 0x2U; -} -static inline u32 fifo_intr_en_1_r(void) -{ - return 0x00002528U; -} -static inline u32 fifo_intr_bind_error_r(void) -{ - return 0x0000252cU; -} -static inline u32 fifo_intr_sched_error_r(void) -{ - return 0x0000254cU; -} -static inline u32 fifo_intr_sched_error_code_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fifo_intr_chsw_error_r(void) -{ - return 0x0000256cU; -} -static inline u32 fifo_intr_ctxsw_timeout_r(void) -{ - return 0x00002a30U; -} -static inline u32 fifo_intr_ctxsw_timeout_engine_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_intr_ctxsw_timeout_engine_v(u32 r, u32 i) -{ - return (r >> (0U + i*1U)) & 0x1U; -} -static inline u32 fifo_intr_ctxsw_timeout_engine__size_1_v(void) -{ - return 0x00000020U; -} -static inline u32 fifo_intr_ctxsw_timeout_engine_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_intr_ctxsw_timeout_engine_pending_f(u32 i) -{ - return 0x1U << (0U + i*1U); -} -static inline u32 fifo_intr_ctxsw_timeout_info_r(u32 i) -{ - return 0x00003200U + i*4U; -} -static inline u32 fifo_intr_ctxsw_timeout_info__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_v(u32 r) -{ - return (r >> 14U) & 0x3U; -} -static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_load_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_save_v(void) -{ - return 0x00000002U; -} -static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_switch_v(void) -{ - return 0x00000003U; -} -static inline u32 fifo_intr_ctxsw_timeout_info_prev_tsgid_v(u32 r) -{ - return (r >> 0U) & 0x3fffU; -} -static inline u32 fifo_intr_ctxsw_timeout_info_next_tsgid_v(u32 r) -{ - return (r >> 16U) & 0x3fffU; -} -static inline u32 fifo_intr_ctxsw_timeout_info_status_v(u32 r) -{ - return (r >> 30U) & 0x3U; -} -static inline u32 fifo_intr_ctxsw_timeout_info_status_awaiting_ack_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_intr_ctxsw_timeout_info_status_eng_was_reset_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_intr_ctxsw_timeout_info_status_ack_received_v(void) -{ - return 0x00000002U; -} -static inline u32 fifo_intr_ctxsw_timeout_info_status_dropped_timeout_v(void) -{ - return 0x00000003U; -} -static inline u32 fifo_intr_pbdma_id_r(void) -{ - return 0x000025a0U; -} -static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) -{ - return (r >> (0U + i*1U)) & 0x1U; -} -static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) -{ - return 0x00000003U; -} -static inline u32 fifo_intr_runlist_r(void) -{ - return 0x00002a00U; -} -static inline u32 fifo_fb_timeout_r(void) -{ - return 0x00002a04U; -} -static inline u32 fifo_fb_timeout_period_m(void) -{ - return 0x3fffffffU << 0U; -} -static inline u32 fifo_fb_timeout_period_max_f(void) -{ - return 0x3fffffffU; -} -static inline u32 fifo_fb_timeout_period_init_f(void) -{ - return 0x3c00U; -} -static inline u32 fifo_fb_timeout_detection_m(void) -{ - return 0x1U << 31U; -} -static inline u32 fifo_fb_timeout_detection_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 fifo_fb_timeout_detection_disabled_f(void) -{ - return 0x0U; -} -static inline u32 fifo_sched_disable_r(void) -{ - return 0x00002630U; -} -static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_sched_disable_runlist_m(u32 i) -{ - return 0x1U << (0U + i*1U); -} -static inline u32 fifo_sched_disable_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_runlist_preempt_r(void) -{ - return 0x00002638U; -} -static inline u32 fifo_runlist_preempt_runlist_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_runlist_preempt_runlist_m(u32 i) -{ - return 0x1U << (0U + i*1U); -} -static inline u32 fifo_runlist_preempt_runlist_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_preempt_r(void) -{ - return 0x00002634U; -} -static inline u32 fifo_preempt_pending_true_f(void) -{ - return 0x100000U; -} -static inline u32 fifo_preempt_type_channel_f(void) -{ - return 0x0U; -} -static inline u32 fifo_preempt_type_tsg_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_preempt_chid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 fifo_preempt_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 fifo_engine_status_r(u32 i) -{ - return 0x00002640U + i*8U; -} -static inline u32 fifo_engine_status__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 fifo_engine_status_id_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 fifo_engine_status_id_type_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 fifo_engine_status_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctx_status_v(u32 r) -{ - return (r >> 13U) & 0x7U; -} -static inline u32 fifo_engine_status_ctx_status_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void) -{ - return 0x00000005U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void) -{ - return 0x00000006U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void) -{ - return 0x00000007U; -} -static inline u32 fifo_engine_status_next_id_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 fifo_engine_status_next_id_type_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 fifo_engine_status_next_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_eng_reload_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 fifo_engine_status_faulted_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fifo_engine_status_faulted_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_engine_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fifo_engine_status_engine_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_engine_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctxsw_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fifo_engine_status_ctxsw_in_progress_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) -{ - return 0x8000U; -} -static inline u32 fifo_eng_ctxsw_timeout_r(void) -{ - return 0x00002a0cU; -} -static inline u32 fifo_eng_ctxsw_timeout_period_f(u32 v) -{ - return (v & 0x7fffffffU) << 0U; -} -static inline u32 fifo_eng_ctxsw_timeout_period_m(void) -{ - return 0x7fffffffU << 0U; -} -static inline u32 fifo_eng_ctxsw_timeout_period_v(u32 r) -{ - return (r >> 0U) & 0x7fffffffU; -} -static inline u32 fifo_eng_ctxsw_timeout_period_init_f(void) -{ - return 0x3fffffU; -} -static inline u32 fifo_eng_ctxsw_timeout_period_max_f(void) -{ - return 0x7fffffffU; -} -static inline u32 fifo_eng_ctxsw_timeout_detection_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fifo_eng_ctxsw_timeout_detection_m(void) -{ - return 0x1U << 31U; -} -static inline u32 fifo_eng_ctxsw_timeout_detection_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 fifo_eng_ctxsw_timeout_detection_disabled_f(void) -{ - return 0x0U; -} -static inline u32 fifo_pbdma_status_r(u32 i) -{ - return 0x00003080U + i*4U; -} -static inline u32 fifo_pbdma_status__size_1_v(void) -{ - return 0x00000003U; -} -static inline u32 fifo_pbdma_status_id_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 fifo_pbdma_status_id_type_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 fifo_pbdma_status_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chan_status_v(u32 r) -{ - return (r >> 13U) & 0x7U; -} -static inline u32 fifo_pbdma_status_chan_status_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void) -{ - return 0x00000005U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void) -{ - return 0x00000006U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void) -{ - return 0x00000007U; -} -static inline u32 fifo_pbdma_status_next_id_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 fifo_pbdma_status_next_id_type_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 fifo_pbdma_status_next_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_pbdma_status_chsw_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_cfg0_r(void) -{ - return 0x00002004U; -} -static inline u32 fifo_cfg0_num_pbdma_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 fifo_cfg0_pbdma_fault_id_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -#endif diff --git a/include/nvgpu/hw/gv11b/hw_flush_gv11b.h b/include/nvgpu/hw/gv11b/hw_flush_gv11b.h deleted file mode 100644 index 45c01de..0000000 --- a/include/nvgpu/hw/gv11b/hw_flush_gv11b.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_flush_gv11b_h_ -#define _hw_flush_gv11b_h_ - -static inline u32 flush_l2_system_invalidate_r(void) -{ - return 0x00070004U; -} -static inline u32 flush_l2_system_invalidate_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_system_invalidate_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_system_invalidate_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_system_invalidate_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_flush_dirty_r(void) -{ - return 0x00070010U; -} -static inline u32 flush_l2_flush_dirty_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_flush_dirty_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_flush_dirty_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_flush_dirty_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_flush_dirty_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_flush_dirty_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_flush_dirty_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_clean_comptags_r(void) -{ - return 0x0007000cU; -} -static inline u32 flush_l2_clean_comptags_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_clean_comptags_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_clean_comptags_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_clean_comptags_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_clean_comptags_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_clean_comptags_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_clean_comptags_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_clean_comptags_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_fb_flush_r(void) -{ - return 0x00070000U; -} -static inline u32 flush_fb_flush_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_fb_flush_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_fb_flush_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_fb_flush_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_fb_flush_outstanding_true_v(void) -{ - return 0x00000001U; -} -#endif diff --git a/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h b/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h deleted file mode 100644 index 9395da3..0000000 --- a/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_fuse_gv11b_h_ -#define _hw_fuse_gv11b_h_ - -static inline u32 fuse_status_opt_gpc_r(void) -{ - return 0x00021c1cU; -} -static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) -{ - return 0x00021c38U + i*4U; -} -static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i) -{ - return 0x00021838U + i*4U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void) -{ - return 0x00021944U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void) -{ - return 0xffU << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void) -{ - return 0x00021948U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void) -{ - return 0x1U << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void) -{ - return 0x1U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void) -{ - return 0x0U; -} -static inline u32 fuse_status_opt_fbio_r(void) -{ - return 0x00021c14U; -} -static inline u32 fuse_status_opt_fbio_data_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fuse_status_opt_fbio_data_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 fuse_status_opt_fbio_data_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i) -{ - return 0x00021d70U + i*4U; -} -static inline u32 fuse_status_opt_fbp_r(void) -{ - return 0x00021d38U; -} -static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) -{ - return (r >> (0U + i*1U)) & 0x1U; -} -static inline u32 fuse_opt_ecc_en_r(void) -{ - return 0x00021228U; -} -static inline u32 fuse_opt_feature_fuses_override_disable_r(void) -{ - return 0x000213f0U; -} -static inline u32 fuse_opt_sec_debug_en_r(void) -{ - return 0x00021218U; -} -static inline u32 fuse_opt_priv_sec_en_r(void) -{ - return 0x00021434U; -} -#endif diff --git a/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h b/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h deleted file mode 100644 index 922dd68..0000000 --- a/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h +++ /dev/null @@ -1,571 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_gmmu_gv11b_h_ -#define _hw_gmmu_gv11b_h_ - -static inline u32 gmmu_new_pde_is_pte_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_is_pte_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pde_aperture_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_aperture_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pde_aperture_video_memory_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_pde_address_sys_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_pde_address_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_vol_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_vol_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_pde_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pde_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_new_pde__size_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_new_dual_pde_is_pte_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_is_pte_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 gmmu_new_dual_pde_address_big_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_w(void) -{ - return 2U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_dual_pde_vol_small_w(void) -{ - return 2U; -} -static inline u32 gmmu_new_dual_pde_vol_small_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_dual_pde_vol_small_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_vol_big_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_vol_big_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_dual_pde_vol_big_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) -{ - return 2U; -} -static inline u32 gmmu_new_dual_pde_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_new_dual_pde_address_big_shift_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_new_dual_pde__size_v(void) -{ - return 0x00000010U; -} -static inline u32 gmmu_new_pte__size_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_new_pte_valid_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_valid_true_f(void) -{ - return 0x1U; -} -static inline u32 gmmu_new_pte_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_privilege_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_privilege_true_f(void) -{ - return 0x20U; -} -static inline u32 gmmu_new_pte_privilege_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_address_sys_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_pte_address_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_address_vid_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_pte_address_vid_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_vol_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_vol_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_pte_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_aperture_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_aperture_video_memory_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_pte_read_only_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_read_only_true_f(void) -{ - return 0x40U; -} -static inline u32 gmmu_new_pte_comptagline_f(u32 v) -{ - return (v & 0x3ffffU) << 4U; -} -static inline u32 gmmu_new_pte_comptagline_w(void) -{ - return 1U; -} -static inline u32 gmmu_new_pte_kind_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gmmu_new_pte_kind_w(void) -{ - return 1U; -} -static inline u32 gmmu_new_pte_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_pte_kind_f(u32 v) -{ - return (v & 0xffU) << 4U; -} -static inline u32 gmmu_pte_kind_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_kind_invalid_v(void) -{ - return 0x000000ffU; -} -static inline u32 gmmu_pte_kind_pitch_v(void) -{ - return 0x00000000U; -} -static inline u32 gmmu_fault_client_type_gpc_v(void) -{ - return 0x00000000U; -} -static inline u32 gmmu_fault_client_type_hub_v(void) -{ - return 0x00000001U; -} -static inline u32 gmmu_fault_type_unbound_inst_block_v(void) -{ - return 0x00000004U; -} -static inline u32 gmmu_fault_type_pte_v(void) -{ - return 0x00000002U; -} -static inline u32 gmmu_fault_mmu_eng_id_bar2_v(void) -{ - return 0x00000005U; -} -static inline u32 gmmu_fault_mmu_eng_id_physical_v(void) -{ - return 0x0000001fU; -} -static inline u32 gmmu_fault_mmu_eng_id_ce0_v(void) -{ - return 0x0000000fU; -} -static inline u32 gmmu_fault_buf_size_v(void) -{ - return 0x00000020U; -} -static inline u32 gmmu_fault_buf_entry_inst_aperture_v(u32 r) -{ - return (r >> 8U) & 0x3U; -} -static inline u32 gmmu_fault_buf_entry_inst_aperture_w(void) -{ - return 0U; -} -static inline u32 gmmu_fault_buf_entry_inst_aperture_vid_mem_v(void) -{ - return 0x00000000U; -} -static inline u32 gmmu_fault_buf_entry_inst_aperture_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 gmmu_fault_buf_entry_inst_aperture_sys_nocoh_v(void) -{ - return 0x00000003U; -} -static inline u32 gmmu_fault_buf_entry_inst_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 gmmu_fault_buf_entry_inst_lo_v(u32 r) -{ - return (r >> 12U) & 0xfffffU; -} -static inline u32 gmmu_fault_buf_entry_inst_lo_b(void) -{ - return 12U; -} -static inline u32 gmmu_fault_buf_entry_inst_lo_w(void) -{ - return 0U; -} -static inline u32 gmmu_fault_buf_entry_inst_hi_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gmmu_fault_buf_entry_inst_hi_w(void) -{ - return 1U; -} -static inline u32 gmmu_fault_buf_entry_addr_phys_aperture_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 gmmu_fault_buf_entry_addr_phys_aperture_w(void) -{ - return 2U; -} -static inline u32 gmmu_fault_buf_entry_addr_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 gmmu_fault_buf_entry_addr_lo_v(u32 r) -{ - return (r >> 12U) & 0xfffffU; -} -static inline u32 gmmu_fault_buf_entry_addr_lo_b(void) -{ - return 12U; -} -static inline u32 gmmu_fault_buf_entry_addr_lo_w(void) -{ - return 2U; -} -static inline u32 gmmu_fault_buf_entry_addr_hi_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gmmu_fault_buf_entry_addr_hi_w(void) -{ - return 3U; -} -static inline u32 gmmu_fault_buf_entry_timestamp_lo_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gmmu_fault_buf_entry_timestamp_lo_w(void) -{ - return 4U; -} -static inline u32 gmmu_fault_buf_entry_timestamp_hi_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gmmu_fault_buf_entry_timestamp_hi_w(void) -{ - return 5U; -} -static inline u32 gmmu_fault_buf_entry_engine_id_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 gmmu_fault_buf_entry_engine_id_w(void) -{ - return 6U; -} -static inline u32 gmmu_fault_buf_entry_fault_type_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gmmu_fault_buf_entry_fault_type_w(void) -{ - return 7U; -} -static inline u32 gmmu_fault_buf_entry_replayable_fault_v(u32 r) -{ - return (r >> 7U) & 0x1U; -} -static inline u32 gmmu_fault_buf_entry_replayable_fault_w(void) -{ - return 7U; -} -static inline u32 gmmu_fault_buf_entry_replayable_fault_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gmmu_fault_buf_entry_replayable_fault_true_f(void) -{ - return 0x80U; -} -static inline u32 gmmu_fault_buf_entry_client_v(u32 r) -{ - return (r >> 8U) & 0x7fU; -} -static inline u32 gmmu_fault_buf_entry_client_w(void) -{ - return 7U; -} -static inline u32 gmmu_fault_buf_entry_access_type_v(u32 r) -{ - return (r >> 16U) & 0xfU; -} -static inline u32 gmmu_fault_buf_entry_access_type_w(void) -{ - return 7U; -} -static inline u32 gmmu_fault_buf_entry_mmu_client_type_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 gmmu_fault_buf_entry_mmu_client_type_w(void) -{ - return 7U; -} -static inline u32 gmmu_fault_buf_entry_gpc_id_v(u32 r) -{ - return (r >> 24U) & 0x1fU; -} -static inline u32 gmmu_fault_buf_entry_gpc_id_w(void) -{ - return 7U; -} -static inline u32 gmmu_fault_buf_entry_protected_mode_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 gmmu_fault_buf_entry_protected_mode_w(void) -{ - return 7U; -} -static inline u32 gmmu_fault_buf_entry_protected_mode_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gmmu_fault_buf_entry_protected_mode_true_f(void) -{ - return 0x20000000U; -} -static inline u32 gmmu_fault_buf_entry_replayable_fault_en_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gmmu_fault_buf_entry_replayable_fault_en_w(void) -{ - return 7U; -} -static inline u32 gmmu_fault_buf_entry_replayable_fault_en_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gmmu_fault_buf_entry_replayable_fault_en_true_f(void) -{ - return 0x40000000U; -} -static inline u32 gmmu_fault_buf_entry_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gmmu_fault_buf_entry_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gmmu_fault_buf_entry_valid_w(void) -{ - return 7U; -} -static inline u32 gmmu_fault_buf_entry_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gmmu_fault_buf_entry_valid_true_f(void) -{ - return 0x80000000U; -} -#endif diff --git a/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/include/nvgpu/hw/gv11b/hw_gr_gv11b.h deleted file mode 100644 index 4a3da79..0000000 --- a/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ /dev/null @@ -1,5703 +0,0 @@ -/* - * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_gr_gv11b_h_ -#define _hw_gr_gv11b_h_ - -static inline u32 gr_intr_r(void) -{ - return 0x00400100U; -} -static inline u32 gr_intr_notify_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_intr_notify_reset_f(void) -{ - return 0x1U; -} -static inline u32 gr_intr_semaphore_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_semaphore_reset_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_illegal_method_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_intr_illegal_method_reset_f(void) -{ - return 0x10U; -} -static inline u32 gr_intr_illegal_notify_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_intr_illegal_notify_reset_f(void) -{ - return 0x40U; -} -static inline u32 gr_intr_firmware_method_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 gr_intr_firmware_method_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_intr_firmware_method_reset_f(void) -{ - return 0x100U; -} -static inline u32 gr_intr_illegal_class_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_intr_illegal_class_reset_f(void) -{ - return 0x20U; -} -static inline u32 gr_intr_fecs_error_pending_f(void) -{ - return 0x80000U; -} -static inline u32 gr_intr_fecs_error_reset_f(void) -{ - return 0x80000U; -} -static inline u32 gr_intr_class_error_pending_f(void) -{ - return 0x100000U; -} -static inline u32 gr_intr_class_error_reset_f(void) -{ - return 0x100000U; -} -static inline u32 gr_intr_exception_pending_f(void) -{ - return 0x200000U; -} -static inline u32 gr_intr_exception_reset_f(void) -{ - return 0x200000U; -} -static inline u32 gr_fecs_intr_r(void) -{ - return 0x00400144U; -} -static inline u32 gr_class_error_r(void) -{ - return 0x00400110U; -} -static inline u32 gr_class_error_code_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_intr_nonstall_r(void) -{ - return 0x00400120U; -} -static inline u32 gr_intr_nonstall_trap_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_en_r(void) -{ - return 0x0040013cU; -} -static inline u32 gr_exception_r(void) -{ - return 0x00400108U; -} -static inline u32 gr_exception_fe_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_exception_gpc_m(void) -{ - return 0x1U << 24U; -} -static inline u32 gr_exception_memfmt_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_exception_ds_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_exception_sked_m(void) -{ - return 0x1U << 8U; -} -static inline u32 gr_exception_pd_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_exception_scc_m(void) -{ - return 0x1U << 3U; -} -static inline u32 gr_exception_ssync_m(void) -{ - return 0x1U << 5U; -} -static inline u32 gr_exception_mme_m(void) -{ - return 0x1U << 7U; -} -static inline u32 gr_exception1_r(void) -{ - return 0x00400118U; -} -static inline u32 gr_exception1_gpc_0_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_exception2_r(void) -{ - return 0x0040011cU; -} -static inline u32 gr_exception_en_r(void) -{ - return 0x00400138U; -} -static inline u32 gr_exception_en_fe_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_exception_en_fe_enabled_f(void) -{ - return 0x1U; -} -static inline u32 gr_exception_en_gpc_m(void) -{ - return 0x1U << 24U; -} -static inline u32 gr_exception_en_gpc_enabled_f(void) -{ - return 0x1000000U; -} -static inline u32 gr_exception_en_memfmt_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_exception_en_memfmt_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_exception_en_ds_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_exception_en_ds_enabled_f(void) -{ - return 0x10U; -} -static inline u32 gr_exception_en_pd_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_exception_en_pd_enabled_f(void) -{ - return 0x4U; -} -static inline u32 gr_exception_en_scc_m(void) -{ - return 0x1U << 3U; -} -static inline u32 gr_exception_en_scc_enabled_f(void) -{ - return 0x8U; -} -static inline u32 gr_exception_en_ssync_m(void) -{ - return 0x1U << 5U; -} -static inline u32 gr_exception_en_ssync_enabled_f(void) -{ - return 0x20U; -} -static inline u32 gr_exception_en_mme_m(void) -{ - return 0x1U << 7U; -} -static inline u32 gr_exception_en_mme_enabled_f(void) -{ - return 0x80U; -} -static inline u32 gr_exception_en_sked_m(void) -{ - return 0x1U << 8U; -} -static inline u32 gr_exception_en_sked_enabled_f(void) -{ - return 0x100U; -} -static inline u32 gr_exception1_en_r(void) -{ - return 0x00400130U; -} -static inline u32 gr_exception2_en_r(void) -{ - return 0x00400134U; -} -static inline u32 gr_gpfifo_ctl_r(void) -{ - return 0x00400500U; -} -static inline u32 gr_gpfifo_ctl_access_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpfifo_ctl_access_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpfifo_ctl_access_enabled_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void) -{ - return 0x10000U; -} -static inline u32 gr_gpfifo_status_r(void) -{ - return 0x00400504U; -} -static inline u32 gr_trapped_addr_r(void) -{ - return 0x00400704U; -} -static inline u32 gr_trapped_addr_mthd_v(u32 r) -{ - return (r >> 2U) & 0xfffU; -} -static inline u32 gr_trapped_addr_subch_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 gr_trapped_addr_mme_generated_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 gr_trapped_addr_datahigh_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 gr_trapped_addr_priv_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 gr_trapped_addr_status_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_trapped_data_lo_r(void) -{ - return 0x00400708U; -} -static inline u32 gr_trapped_data_hi_r(void) -{ - return 0x0040070cU; -} -static inline u32 gr_trapped_data_mme_r(void) -{ - return 0x00400710U; -} -static inline u32 gr_trapped_data_mme_pc_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 gr_status_r(void) -{ - return 0x00400700U; -} -static inline u32 gr_status_fe_method_upper_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_status_fe_method_lower_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_status_fe_method_lower_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_status_fe_gi_v(u32 r) -{ - return (r >> 21U) & 0x1U; -} -static inline u32 gr_status_mask_r(void) -{ - return 0x00400610U; -} -static inline u32 gr_status_1_r(void) -{ - return 0x00400604U; -} -static inline u32 gr_status_2_r(void) -{ - return 0x00400608U; -} -static inline u32 gr_engine_status_r(void) -{ - return 0x0040060cU; -} -static inline u32 gr_engine_status_value_busy_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_be0_becs_be_exception_r(void) -{ - return 0x00410204U; -} -static inline u32 gr_pri_be0_becs_be_exception_en_r(void) -{ - return 0x00410208U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void) -{ - return 0x00502c90U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void) -{ - return 0x00502c94U; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void) -{ - return 0x00504508U; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void) -{ - return 0x0050450cU; -} -static inline u32 gr_activity_0_r(void) -{ - return 0x00400380U; -} -static inline u32 gr_activity_1_r(void) -{ - return 0x00400384U; -} -static inline u32 gr_activity_2_r(void) -{ - return 0x00400388U; -} -static inline u32 gr_activity_4_r(void) -{ - return 0x00400390U; -} -static inline u32 gr_activity_4_gpc0_s(void) -{ - return 3U; -} -static inline u32 gr_activity_4_gpc0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_activity_4_gpc0_m(void) -{ - return 0x7U << 0U; -} -static inline u32 gr_activity_4_gpc0_v(u32 r) -{ - return (r >> 0U) & 0x7U; -} -static inline u32 gr_activity_4_gpc0_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_activity_4_gpc0_preempted_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_pri_gpc0_gcc_dbg_r(void) -{ - return 0x00501000U; -} -static inline u32 gr_pri_gpcs_gcc_dbg_r(void) -{ - return 0x00419000U; -} -static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) -{ - return 0x0050433cU; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) -{ - return 0x00419b3cU; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_pri_sked_activity_r(void) -{ - return 0x00407054U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void) -{ - return 0x00502c80U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void) -{ - return 0x00502c84U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void) -{ - return 0x00502c88U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void) -{ - return 0x00502c8cU; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void) -{ - return 0x00504500U; -} -static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void) -{ - return 0x00504d00U; -} -static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void) -{ - return 0x00501d00U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void) -{ - return 0x0041ac80U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void) -{ - return 0x0041ac84U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void) -{ - return 0x0041ac88U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void) -{ - return 0x0041ac8cU; -} -static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void) -{ - return 0x0041c500U; -} -static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void) -{ - return 0x0041cd00U; -} -static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void) -{ - return 0x00419d00U; -} -static inline u32 gr_pri_be0_becs_be_activity0_r(void) -{ - return 0x00410200U; -} -static inline u32 gr_pri_be1_becs_be_activity0_r(void) -{ - return 0x00410600U; -} -static inline u32 gr_pri_bes_becs_be_activity0_r(void) -{ - return 0x00408a00U; -} -static inline u32 gr_pri_ds_mpipe_status_r(void) -{ - return 0x00405858U; -} -static inline u32 gr_pri_fe_go_idle_info_r(void) -{ - return 0x00404194U; -} -static inline u32 gr_pri_fe_chip_def_info_r(void) -{ - return 0x00404030U; -} -static inline u32 gr_pri_fe_chip_def_info_max_veid_count_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 gr_pri_fe_chip_def_info_max_veid_count_init_v(void) -{ - return 0x00000040U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) -{ - return 0x00504238U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) -{ - return 0x00504358U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp0_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp1_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp2_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp3_m(void) -{ - return 0x1U << 3U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp4_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp5_m(void) -{ - return 0x1U << 5U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp6_m(void) -{ - return 0x1U << 6U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp7_m(void) -{ - return 0x1U << 7U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp0_m(void) -{ - return 0x1U << 8U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp1_m(void) -{ - return 0x1U << 9U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp2_m(void) -{ - return 0x1U << 10U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp3_m(void) -{ - return 0x1U << 11U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp4_m(void) -{ - return 0x1U << 12U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp5_m(void) -{ - return 0x1U << 13U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp6_m(void) -{ - return 0x1U << 14U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp7_m(void) -{ - return 0x1U << 15U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 26U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r(void) -{ - return 0x0050435cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r(void) -{ - return 0x00504360U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r(void) -{ - return 0x0050436cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_0_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_1_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_1_m(void) -{ - return 0x1U << 3U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 10U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r(void) -{ - return 0x00504370U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r(void) -{ - return 0x00504374U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_r(void) -{ - return 0x0050464cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l0_data_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l0_predecode_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_data_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_predecode_m(void) -{ - return 0x1U << 3U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l0_data_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l0_predecode_m(void) -{ - return 0x1U << 5U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_data_m(void) -{ - return 0x1U << 6U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_predecode_m(void) -{ - return 0x1U << 7U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 18U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_r(void) -{ - return 0x00504650U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_r(void) -{ - return 0x00504654U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_r(void) -{ - return 0x00504624U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_el1_0_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_el1_1_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_el1_0_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_el1_1_m(void) -{ - return 0x1U << 3U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_pixrpf_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_miss_fifo_m(void) -{ - return 0x1U << 5U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_pixrpf_m(void) -{ - return 0x1U << 6U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_miss_fifo_m(void) -{ - return 0x1U << 7U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 10U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_r(void) -{ - return 0x00504628U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_r(void) -{ - return 0x0050462cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_r(void) -{ - return 0x00504638U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm0_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm1_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm0_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm1_m(void) -{ - return 0x1U << 3U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm0_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm1_m(void) -{ - return 0x1U << 5U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m(void) -{ - return 0x1U << 6U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm1_m(void) -{ - return 0x1U << 7U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 18U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r(void) -{ - return 0x0050463cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r(void) -{ - return 0x00504640U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_r(void) -{ - return 0x00419b54U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp0_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp0_task_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp1_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp1_task_f(void) -{ - return 0x2U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp2_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp2_task_f(void) -{ - return 0x4U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp3_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp3_task_f(void) -{ - return 0x8U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp4_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp4_task_f(void) -{ - return 0x10U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp5_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp5_task_f(void) -{ - return 0x20U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp6_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp6_task_f(void) -{ - return 0x40U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp7_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp7_task_f(void) -{ - return 0x80U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_r(void) -{ - return 0x00504354U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp0_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp0_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp1_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp1_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp2_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp2_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp3_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp3_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp4_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp4_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp5_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp5_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp6_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp6_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp7_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp7_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_r(void) -{ - return 0x00419b68U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_scrub_el1_0_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_scrub_el1_0_task_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_scrub_el1_1_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_scrub_el1_1_task_f(void) -{ - return 0x2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_r(void) -{ - return 0x00504368U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_scrub_el1_0_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_scrub_el1_0_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_scrub_el1_1_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_scrub_el1_1_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_r(void) -{ - return 0x00419e20U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_el1_0_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_el1_0_task_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_el1_1_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_el1_1_task_f(void) -{ - return 0x2U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_pixprf_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_pixprf_task_f(void) -{ - return 0x10U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_miss_fifo_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_miss_fifo_task_f(void) -{ - return 0x20U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_r(void) -{ - return 0x00504620U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_el1_0_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_el1_0_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_el1_1_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_el1_1_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_pixprf_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_pixprf_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_miss_fifo_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_miss_fifo_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_r(void) -{ - return 0x00419e34U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_warp_sm0_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_warp_sm0_task_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_warp_sm1_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_warp_sm1_task_f(void) -{ - return 0x2U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_barrier_sm0_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_barrier_sm0_task_f(void) -{ - return 0x4U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_barrier_sm1_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_barrier_sm1_task_f(void) -{ - return 0x8U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_r(void) -{ - return 0x00504634U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_warp_sm0_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_warp_sm0_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_warp_sm1_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_warp_sm1_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_barrier_sm0_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_barrier_sm0_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_barrier_sm1_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_barrier_sm1_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_r(void) -{ - return 0x00419e48U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l0_data_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l0_data_task_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l0_predecode_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l0_predecode_task_f(void) -{ - return 0x2U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l1_data_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l1_data_task_f(void) -{ - return 0x4U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l1_predecode_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l1_predecode_task_f(void) -{ - return 0x8U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_r(void) -{ - return 0x00504648U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l0_data_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l0_data_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l0_predecode_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l0_predecode_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l1_data_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l1_data_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l1_predecode_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l1_predecode_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) -{ - return 0x005042c4U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_tpc0_mpc_hww_esr_r(void) -{ - return 0x00504430U; -} -static inline u32 gr_gpc0_tpc0_mpc_hww_esr_reset_trigger_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_r(void) -{ - return 0x00504434U; -} -static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_veid_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_pri_be0_crop_status1_r(void) -{ - return 0x00410134U; -} -static inline u32 gr_pri_bes_crop_status1_r(void) -{ - return 0x00408934U; -} -static inline u32 gr_pri_be0_zrop_status_r(void) -{ - return 0x00410048U; -} -static inline u32 gr_pri_be0_zrop_status2_r(void) -{ - return 0x0041004cU; -} -static inline u32 gr_pri_bes_zrop_status_r(void) -{ - return 0x00408848U; -} -static inline u32 gr_pri_bes_zrop_status2_r(void) -{ - return 0x0040884cU; -} -static inline u32 gr_pipe_bundle_address_r(void) -{ - return 0x00400200U; -} -static inline u32 gr_pipe_bundle_address_value_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pipe_bundle_address_veid_f(u32 v) -{ - return (v & 0x3fU) << 20U; -} -static inline u32 gr_pipe_bundle_address_veid_w(void) -{ - return 0U; -} -static inline u32 gr_pipe_bundle_data_r(void) -{ - return 0x00400204U; -} -static inline u32 gr_pipe_bundle_config_r(void) -{ - return 0x00400208U; -} -static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fe_hww_esr_r(void) -{ - return 0x00404000U; -} -static inline u32 gr_fe_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_fe_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fe_hww_esr_info_r(void) -{ - return 0x004041b0U; -} -static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(void) -{ - return 0x00419eacU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r(void) -{ - return 0x0050472cU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_int_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_pause_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_single_step_complete_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_error_in_trap_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_r(void) -{ - return 0x00419eb4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_r(void) -{ - return 0x00504734U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_m(void) -{ - return 0x1U << 5U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_m(void) -{ - return 0x1U << 6U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_m(void) -{ - return 0x1U << 8U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_fe_go_idle_timeout_r(void) -{ - return 0x00404154U; -} -static inline u32 gr_fe_go_idle_timeout_count_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) -{ - return 0x1800U; -} -static inline u32 gr_fe_object_table_r(u32 i) -{ - return 0x00404200U + i*4U; -} -static inline u32 gr_fe_object_table_nvclass_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_fe_tpc_fs_r(u32 i) -{ - return 0x0040a200U + i*4U; -} -static inline u32 gr_fe_tpc_pesmask_r(void) -{ - return 0x0040a260U; -} -static inline u32 gr_fe_tpc_pesmask_pesid_f(u32 v) -{ - return (v & 0x3fU) << 24U; -} -static inline u32 gr_fe_tpc_pesmask_gpcid_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_fe_tpc_pesmask_action_m(void) -{ - return 0x1U << 30U; -} -static inline u32 gr_fe_tpc_pesmask_action_write_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_fe_tpc_pesmask_action_read_f(void) -{ - return 0x0U; -} -static inline u32 gr_fe_tpc_pesmask_req_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_fe_tpc_pesmask_req_send_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fe_tpc_pesmask_mask_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 gr_pri_mme_shadow_raw_index_r(void) -{ - return 0x00404488U; -} -static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pri_mme_shadow_raw_data_r(void) -{ - return 0x0040448cU; -} -static inline u32 gr_mme_hww_esr_r(void) -{ - return 0x00404490U; -} -static inline u32 gr_mme_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_mme_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_mme_hww_esr_info_r(void) -{ - return 0x00404494U; -} -static inline u32 gr_memfmt_hww_esr_r(void) -{ - return 0x00404600U; -} -static inline u32 gr_memfmt_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_memfmt_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fecs_cpuctl_r(void) -{ - return 0x00409100U; -} -static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_cpuctl_alias_r(void) -{ - return 0x00409130U; -} -static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_dmactl_r(void) -{ - return 0x0040910cU; -} -static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_fecs_os_r(void) -{ - return 0x00409080U; -} -static inline u32 gr_fecs_idlestate_r(void) -{ - return 0x0040904cU; -} -static inline u32 gr_fecs_mailbox0_r(void) -{ - return 0x00409040U; -} -static inline u32 gr_fecs_mailbox1_r(void) -{ - return 0x00409044U; -} -static inline u32 gr_fecs_irqstat_r(void) -{ - return 0x00409008U; -} -static inline u32 gr_fecs_irqmode_r(void) -{ - return 0x0040900cU; -} -static inline u32 gr_fecs_irqmask_r(void) -{ - return 0x00409018U; -} -static inline u32 gr_fecs_irqdest_r(void) -{ - return 0x0040901cU; -} -static inline u32 gr_fecs_curctx_r(void) -{ - return 0x00409050U; -} -static inline u32 gr_fecs_nxtctx_r(void) -{ - return 0x00409054U; -} -static inline u32 gr_fecs_engctl_r(void) -{ - return 0x004090a4U; -} -static inline u32 gr_fecs_debug1_r(void) -{ - return 0x00409090U; -} -static inline u32 gr_fecs_debuginfo_r(void) -{ - return 0x00409094U; -} -static inline u32 gr_fecs_icd_cmd_r(void) -{ - return 0x00409200U; -} -static inline u32 gr_fecs_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 gr_fecs_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_fecs_icd_cmd_opc_m(void) -{ - return 0xfU << 0U; -} -static inline u32 gr_fecs_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 gr_fecs_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 gr_fecs_icd_rdata_r(void) -{ - return 0x0040920cU; -} -static inline u32 gr_fecs_imemc_r(u32 i) -{ - return 0x00409180U + i*16U; -} -static inline u32 gr_fecs_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_fecs_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_fecs_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_fecs_imemd_r(u32 i) -{ - return 0x00409184U + i*16U; -} -static inline u32 gr_fecs_imemt_r(u32 i) -{ - return 0x00409188U + i*16U; -} -static inline u32 gr_fecs_imemt_tag_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_fecs_dmemc_r(u32 i) -{ - return 0x004091c0U + i*8U; -} -static inline u32 gr_fecs_dmemc_offs_s(void) -{ - return 6U; -} -static inline u32 gr_fecs_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_fecs_dmemc_offs_m(void) -{ - return 0x3fU << 2U; -} -static inline u32 gr_fecs_dmemc_offs_v(u32 r) -{ - return (r >> 2U) & 0x3fU; -} -static inline u32 gr_fecs_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_fecs_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_fecs_dmemd_r(u32 i) -{ - return 0x004091c4U + i*8U; -} -static inline u32 gr_fecs_dmatrfbase_r(void) -{ - return 0x00409110U; -} -static inline u32 gr_fecs_dmatrfmoffs_r(void) -{ - return 0x00409114U; -} -static inline u32 gr_fecs_dmatrffboffs_r(void) -{ - return 0x0040911cU; -} -static inline u32 gr_fecs_dmatrfcmd_r(void) -{ - return 0x00409118U; -} -static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_fecs_bootvec_r(void) -{ - return 0x00409104U; -} -static inline u32 gr_fecs_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_falcon_hwcfg_r(void) -{ - return 0x00409108U; -} -static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void) -{ - return 0x0041a108U; -} -static inline u32 gr_fecs_falcon_rm_r(void) -{ - return 0x00409084U; -} -static inline u32 gr_fecs_current_ctx_r(void) -{ - return 0x00409b00U; -} -static inline u32 gr_fecs_current_ctx_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_current_ctx_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_current_ctx_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_current_ctx_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_current_ctx_target_m(void) -{ - return 0x3U << 28U; -} -static inline u32 gr_fecs_current_ctx_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 gr_fecs_current_ctx_valid_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_current_ctx_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_fecs_current_ctx_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_fecs_current_ctx_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_fecs_current_ctx_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_method_data_r(void) -{ - return 0x00409500U; -} -static inline u32 gr_fecs_method_push_r(void) -{ - return 0x00409504U; -} -static inline u32 gr_fecs_method_push_adr_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void) -{ - return 0x00000003U; -} -static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void) -{ - return 0x3U; -} -static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void) -{ - return 0x00000009U; -} -static inline u32 gr_fecs_method_push_adr_restore_golden_v(void) -{ - return 0x00000015U; -} -static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void) -{ - return 0x00000016U; -} -static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void) -{ - return 0x00000025U; -} -static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void) -{ - return 0x00000030U; -} -static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void) -{ - return 0x00000031U; -} -static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void) -{ - return 0x00000032U; -} -static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void) -{ - return 0x00000038U; -} -static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void) -{ - return 0x00000039U; -} -static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) -{ - return 0x21U; -} -static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void) -{ - return 0x0000001aU; -} -static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(void) -{ - return 0x0000003aU; -} -static inline u32 gr_fecs_host_int_status_r(void) -{ - return 0x00409c18U; -} -static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 gr_fecs_host_int_status_watchdog_active_f(void) -{ - return 0x80000U; -} -static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_fecs_host_int_status_ecc_corrected_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 gr_fecs_host_int_status_ecc_corrected_m(void) -{ - return 0x1U << 21U; -} -static inline u32 gr_fecs_host_int_status_ecc_uncorrected_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 gr_fecs_host_int_status_ecc_uncorrected_m(void) -{ - return 0x1U << 22U; -} -static inline u32 gr_fecs_host_int_clear_r(void) -{ - return 0x00409c20U; -} -static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void) -{ - return 0x2U; -} -static inline u32 gr_fecs_host_int_enable_r(void) -{ - return 0x00409c24U; -} -static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void) -{ - return 0x2U; -} -static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void) -{ - return 0x10000U; -} -static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void) -{ - return 0x20000U; -} -static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void) -{ - return 0x40000U; -} -static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void) -{ - return 0x80000U; -} -static inline u32 gr_fecs_host_int_enable_flush_when_busy_enable_f(void) -{ - return 0x100000U; -} -static inline u32 gr_fecs_host_int_enable_ecc_corrected_enable_f(void) -{ - return 0x200000U; -} -static inline u32 gr_fecs_host_int_enable_ecc_uncorrected_enable_f(void) -{ - return 0x400000U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) -{ - return 0x00409614U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void) -{ - return 0x10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void) -{ - return 0x20U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void) -{ - return 0x40U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void) -{ - return 0x100U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void) -{ - return 0x200U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void) -{ - return 0x1U << 10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r) -{ - return (r >> 10U) & 0x1U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void) -{ - return 0x400U; -} -static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void) -{ - return 0x0040960cU; -} -static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i) -{ - return 0x00409800U + i*4U; -} -static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void) -{ - return 0x00000002U; -} -static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i) -{ - return 0x004098c0U + i*4U; -} -static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i) -{ - return 0x00409840U + i*4U; -} -static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_fs_r(void) -{ - return 0x00409604U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_m(void) -{ - return 0x1fU << 0U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_fecs_fs_num_available_fbps_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 gr_fecs_fs_num_available_fbps_m(void) -{ - return 0x1fU << 16U; -} -static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -static inline u32 gr_fecs_cfg_r(void) -{ - return 0x00409620U; -} -static inline u32 gr_fecs_cfg_imem_sz_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_fecs_rc_lanes_r(void) -{ - return 0x00409880U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_s(void) -{ - return 6U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_fecs_ctxsw_status_1_r(void) -{ - return 0x00409400U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void) -{ - return 0x1U << 12U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 gr_fecs_arb_ctx_adr_r(void) -{ - return 0x00409a24U; -} -static inline u32 gr_fecs_new_ctx_r(void) -{ - return 0x00409b04U; -} -static inline u32 gr_fecs_new_ctx_ptr_s(void) -{ - return 28U; -} -static inline u32 gr_fecs_new_ctx_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_new_ctx_ptr_m(void) -{ - return 0xfffffffU << 0U; -} -static inline u32 gr_fecs_new_ctx_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_new_ctx_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_new_ctx_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_new_ctx_target_m(void) -{ - return 0x3U << 28U; -} -static inline u32 gr_fecs_new_ctx_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_new_ctx_valid_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_new_ctx_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_fecs_new_ctx_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_fecs_new_ctx_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_fecs_arb_ctx_ptr_r(void) -{ - return 0x00409a0cU; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void) -{ - return 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void) -{ - return 0xfffffffU << 0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_m(void) -{ - return 0x3U << 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_arb_ctx_cmd_r(void) -{ - return 0x00409a10U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void) -{ - return 0x1fU << 0U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_fecs_ctxsw_status_fe_0_r(void) -{ - return 0x00409c00U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void) -{ - return 0x00502c04U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) -{ - return 0x00502400U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_mailbox__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_fecs_ctxsw_idlestate_r(void) -{ - return 0x00409420U; -} -static inline u32 gr_fecs_feature_override_ecc_r(void) -{ - return 0x00409658U; -} -static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_sm_l1_data_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_sm_l1_data_override_v(u32 r) -{ - return (r >> 7U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_sm_l1_tag_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_sm_l1_tag_override_v(u32 r) -{ - return (r >> 11U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_sm_cbu_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_sm_cbu_override_v(u32 r) -{ - return (r >> 23U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_1_r(void) -{ - return 0x0040965cU; -} -static inline u32 gr_fecs_feature_override_ecc_1_sm_l0_icache_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_1_sm_l0_icache_override_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_1_sm_l1_icache_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_1_sm_l1_icache_override_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) -{ - return 0x00502420U; -} -static inline u32 gr_rstr2d_gpc_map_r(u32 i) -{ - return 0x0040780cU + i*4U; -} -static inline u32 gr_rstr2d_map_table_cfg_r(void) -{ - return 0x004078bcU; -} -static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_pd_hww_esr_r(void) -{ - return 0x00406018U; -} -static inline u32 gr_pd_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pd_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i) -{ - return 0x00406028U + i*4U; -} -static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v) -{ - return (v & 0xfU) << 12U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v) -{ - return (v & 0xfU) << 24U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v) -{ - return (v & 0xfU) << 28U; -} -static inline u32 gr_pd_ab_dist_cfg0_r(void) -{ - return 0x004064c0U; -} -static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void) -{ - return 0x0U; -} -static inline u32 gr_pd_ab_dist_cfg1_r(void) -{ - return 0x004064c4U; -} -static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void) -{ - return 0xffffU; -} -static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void) -{ - return 0x00000080U; -} -static inline u32 gr_pd_ab_dist_cfg2_r(void) -{ - return 0x004064c8U; -} -static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) -{ - return (v & 0x1fffU) << 0U; -} -static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) -{ - return 0x00000380U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) -{ - return (v & 0x1fffU) << 16U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) -{ - return 0x00000302U; -} -static inline u32 gr_pd_dist_skip_table_r(u32 i) -{ - return 0x004064d0U + i*4U; -} -static inline u32 gr_pd_dist_skip_table__size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gr_ds_debug_r(void) -{ - return 0x00405800U; -} -static inline u32 gr_ds_debug_timeslice_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_debug_timeslice_mode_enable_f(void) -{ - return 0x8000000U; -} -static inline u32 gr_ds_zbc_color_r_r(void) -{ - return 0x00405804U; -} -static inline u32 gr_ds_zbc_color_r_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_g_r(void) -{ - return 0x00405808U; -} -static inline u32 gr_ds_zbc_color_g_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_b_r(void) -{ - return 0x0040580cU; -} -static inline u32 gr_ds_zbc_color_b_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_a_r(void) -{ - return 0x00405810U; -} -static inline u32 gr_ds_zbc_color_a_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_fmt_r(void) -{ - return 0x00405814U; -} -static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v) -{ - return (v & 0x7fU) << 0U; -} -static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void) -{ - return 0x00000002U; -} -static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) -{ - return 0x00000028U; -} -static inline u32 gr_ds_zbc_z_r(void) -{ - return 0x00405818U; -} -static inline u32 gr_ds_zbc_z_val_s(void) -{ - return 32U; -} -static inline u32 gr_ds_zbc_z_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_z_val_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 gr_ds_zbc_z_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gr_ds_zbc_z_val__init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_ds_zbc_z_val__init_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_z_fmt_r(void) -{ - return 0x0040581cU; -} -static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_zbc_tbl_index_r(void) -{ - return 0x00405820U; -} -static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_ds_zbc_tbl_ld_r(void) -{ - return 0x00405824U; -} -static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) -{ - return 0x4U; -} -static inline u32 gr_ds_tga_constraintlogic_beta_r(void) -{ - return 0x00405830U; -} -static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_ds_tga_constraintlogic_alpha_r(void) -{ - return 0x0040585cU; -} -static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_ds_hww_esr_r(void) -{ - return 0x00405840U; -} -static inline u32 gr_ds_hww_esr_reset_s(void) -{ - return 1U; -} -static inline u32 gr_ds_hww_esr_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_reset_m(void) -{ - return 0x1U << 30U; -} -static inline u32 gr_ds_hww_esr_reset_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_ds_hww_esr_reset_task_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_hww_esr_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_ds_hww_esr_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_ds_hww_esr_2_r(void) -{ - return 0x00405848U; -} -static inline u32 gr_ds_hww_esr_2_reset_s(void) -{ - return 1U; -} -static inline u32 gr_ds_hww_esr_2_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_2_reset_m(void) -{ - return 0x1U << 30U; -} -static inline u32 gr_ds_hww_esr_2_reset_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_ds_hww_esr_2_reset_task_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_hww_esr_2_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_ds_hww_esr_2_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_ds_hww_report_mask_r(void) -{ - return 0x00405844U; -} -static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void) -{ - return 0x8U; -} -static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void) -{ - return 0x80U; -} -static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void) -{ - return 0x200U; -} -static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void) -{ - return 0x400U; -} -static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void) -{ - return 0x800U; -} -static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void) -{ - return 0x1000U; -} -static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void) -{ - return 0x2000U; -} -static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void) -{ - return 0x4000U; -} -static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void) -{ - return 0x8000U; -} -static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void) -{ - return 0x10000U; -} -static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void) -{ - return 0x20000U; -} -static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void) -{ - return 0x40000U; -} -static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void) -{ - return 0x80000U; -} -static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void) -{ - return 0x100000U; -} -static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void) -{ - return 0x200000U; -} -static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void) -{ - return 0x400000U; -} -static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void) -{ - return 0x800000U; -} -static inline u32 gr_ds_hww_report_mask_2_r(void) -{ - return 0x0040584cU; -} -static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i) -{ - return 0x00405870U + i*4U; -} -static inline u32 gr_scc_debug_r(void) -{ - return 0x00408000U; -} -static inline u32 gr_scc_debug_pagepool_invalidates_m(void) -{ - return 0x1U << 9U; -} -static inline u32 gr_scc_debug_pagepool_invalidates_disable_f(void) -{ - return 0x200U; -} -static inline u32 gr_scc_debug_pagepool_invalidates_enable_f(void) -{ - return 0x0U; -} -static inline u32 gr_scc_bundle_cb_base_r(void) -{ - return 0x00408004U; -} -static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_scc_bundle_cb_size_r(void) -{ - return 0x00408008U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7ffU) << 0U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) -{ - return 0x00000030U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_scc_bundle_cb_size_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_scc_bundle_cb_size_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_scc_bundle_cb_size_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_scc_pagepool_base_r(void) -{ - return 0x0040800cU; -} -static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_scc_pagepool_r(void) -{ - return 0x00408010U; -} -static inline u32 gr_scc_pagepool_total_pages_f(u32 v) -{ - return (v & 0x3ffU) << 0U; -} -static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void) -{ - return 0x00000200U; -} -static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_s(void) -{ - return 10U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) -{ - return (v & 0x3ffU) << 10U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_m(void) -{ - return 0x3ffU << 10U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) -{ - return (r >> 10U) & 0x3ffU; -} -static inline u32 gr_scc_pagepool_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_scc_init_r(void) -{ - return 0x0040802cU; -} -static inline u32 gr_scc_init_ram_trigger_f(void) -{ - return 0x1U; -} -static inline u32 gr_scc_hww_esr_r(void) -{ - return 0x00408030U; -} -static inline u32 gr_scc_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_scc_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_ssync_hww_esr_r(void) -{ - return 0x00405a14U; -} -static inline u32 gr_ssync_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_ssync_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_sked_hww_esr_r(void) -{ - return 0x00407020U; -} -static inline u32 gr_sked_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_sked_hww_esr_en_r(void) -{ - return 0x00407024U; -} -static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(void) -{ - return 0x1U << 25U; -} -static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f(void) -{ - return 0x2000000U; -} -static inline u32 gr_cwd_fs_r(void) -{ - return 0x00405b00U; -} -static inline u32 gr_cwd_fs_num_gpcs_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_cwd_fs_num_tpcs_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_cwd_gpc_tpc_id_r(u32 i) -{ - return 0x00405b60U + i*4U; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void) -{ - return 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void) -{ - return 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_cwd_sm_id_r(u32 i) -{ - return 0x00405ba0U + i*4U; -} -static inline u32 gr_cwd_sm_id__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_cwd_sm_id_tpc1_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpc0_fs_gpc_r(void) -{ - return 0x00502608U; -} -static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -static inline u32 gr_gpc0_cfg_r(void) -{ - return 0x00502620U; -} -static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpccs_rc_lanes_r(void) -{ - return 0x00502880U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_gpccs_rc_lane_size_r(void) -{ - return 0x00502910U; -} -static inline u32 gr_gpccs_rc_lane_size_v_s(void) -{ - return 24U; -} -static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_gpccs_rc_lane_size_v_m(void) -{ - return 0xffffffU << 0U; -} -static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_zcull_fs_r(void) -{ - return 0x00500910U; -} -static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 gr_gpc0_zcull_ram_addr_r(void) -{ - return 0x00500914U; -} -static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void) -{ - return 0x00500918U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void) -{ - return 0x00800000U; -} -static inline u32 gr_gpc0_zcull_total_ram_size_r(void) -{ - return 0x00500920U; -} -static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_zcull_zcsize_r(u32 i) -{ - return 0x00500a04U + i*32U; -} -static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void) -{ - return 0x00000040U; -} -static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i) -{ - return 0x00500c10U + i*4U; -} -static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i) -{ - return 0x00500c30U + i*4U; -} -static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void) -{ - return 0x00504088U; -} -static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) -{ - return 0x00504608U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_r(void) -{ - return 0x00504330U; -} -static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r) -{ - return (r >> 8U) & 0xfffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r) -{ - return (r >> 20U) & 0xfffU; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) -{ - return 0x00503018U; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void) -{ - return 0x005030c0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) -{ - return 0x3fffffU << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) -{ - return 0x00000800U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) -{ - return 0x00001100U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void) -{ - return 0x005030f4U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void) -{ - return 0x005030e4U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void) -{ - return 0x00000800U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) -{ - return 0x005030f8U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void) -{ - return 0x005030f0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) -{ - return 0x00000800U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) -{ - return 0x00419e00U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void) -{ - return 0x00419e04U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void) -{ - return 21U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v) -{ - return (v & 0x1fffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void) -{ - return 0x1fffffU << 0U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r) -{ - return (r >> 0U) & 0x1fffffU; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void) -{ - return 0x80U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void) -{ - return 1U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpccs_falcon_addr_r(void) -{ - return 0x0041a0acU; -} -static inline u32 gr_gpccs_falcon_addr_lsb_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpccs_falcon_addr_msb_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v) -{ - return (v & 0x3fU) << 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_m(void) -{ - return 0x3fU << 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r) -{ - return (r >> 6U) & 0x3fU; -} -static inline u32 gr_gpccs_falcon_addr_msb_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_falcon_addr_msb_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_s(void) -{ - return 12U; -} -static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_m(void) -{ - return 0xfffU << 0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 gr_gpccs_cpuctl_r(void) -{ - return 0x0041a100U; -} -static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_gpccs_dmactl_r(void) -{ - return 0x0041a10cU; -} -static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_gpccs_imemc_r(u32 i) -{ - return 0x0041a180U + i*16U; -} -static inline u32 gr_gpccs_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_gpccs_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpccs_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_gpccs_imemd_r(u32 i) -{ - return 0x0041a184U + i*16U; -} -static inline u32 gr_gpccs_imemt_r(u32 i) -{ - return 0x0041a188U + i*16U; -} -static inline u32 gr_gpccs_imemt__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_gpccs_imemt_tag_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpccs_dmemc_r(u32 i) -{ - return 0x0041a1c0U + i*8U; -} -static inline u32 gr_gpccs_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_gpccs_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpccs_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_gpccs_dmemd_r(u32 i) -{ - return 0x0041a1c4U + i*8U; -} -static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i) -{ - return 0x0041a800U + i*4U; -} -static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void) -{ - return 0x00418e24U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void) -{ - return 32U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void) -{ - return 0x00418e28U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void) -{ - return 11U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7ffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void) -{ - return 0x7ffU << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) -{ - return (r >> 0U) & 0x7ffU; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) -{ - return 0x00000030U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) -{ - return 0x30U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) -{ - return 1U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void) -{ - return 0x005001dcU; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void) -{ - return 0x00000170U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void) -{ - return 0x005001d8U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void) -{ - return 0x004181e4U; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void) -{ - return 0x0041befcU; -} -static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpcs_ppcs_cbm_debug_r(void) -{ - return 0x0041bec4U; -} -static inline u32 gr_gpcs_ppcs_cbm_debug_invalidate_alpha_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_gpcs_ppcs_cbm_debug_invalidate_alpha_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_ppcs_cbm_debug_invalidate_alpha_enable_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpcs_ppcs_cbm_debug_invalidate_beta_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_gpcs_ppcs_cbm_debug_invalidate_beta_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_ppcs_cbm_debug_invalidate_beta_enable_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) -{ - return 0x00418ea0U + i*4U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) -{ - return 0x3fffffU << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i) -{ - return 0x00418010U + i*4U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i) -{ - return 0x0041804cU + i*4U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i) -{ - return 0x00418088U + i*4U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i) -{ - return 0x004180c4U + i*4U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void) -{ - return 0x00418100U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i) -{ - return 0x00418110U + i*4U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void) -{ - return 0x0041814cU; -} -static inline u32 gr_gpcs_swdx_dss_zbc_s_r(u32 i) -{ - return 0x0041815cU + i*4U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_s_val_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r(void) -{ - return 0x00418198U; -} -static inline u32 gr_gpcs_swdx_spill_unit_r(void) -{ - return 0x00418e9cU; -} -static inline u32 gr_gpcs_swdx_spill_unit_spill_buffer_cache_mgmt_mode_m(void) -{ - return 0x1U << 16U; -} -static inline u32 gr_gpcs_swdx_spill_unit_spill_buffer_cache_mgmt_mode_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_swdx_spill_unit_spill_buffer_cache_mgmt_mode_enabled_f(void) -{ - return 0x10000U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) -{ - return 0x00418810U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void) -{ - return 0x0000000cU; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_crstr_gpc_map_r(u32 i) -{ - return 0x00418b08U + i*4U; -} -static inline u32 gr_crstr_gpc_map_tile0_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_crstr_gpc_map_tile1_f(u32 v) -{ - return (v & 0x1fU) << 5U; -} -static inline u32 gr_crstr_gpc_map_tile2_f(u32 v) -{ - return (v & 0x1fU) << 10U; -} -static inline u32 gr_crstr_gpc_map_tile3_f(u32 v) -{ - return (v & 0x1fU) << 15U; -} -static inline u32 gr_crstr_gpc_map_tile4_f(u32 v) -{ - return (v & 0x1fU) << 20U; -} -static inline u32 gr_crstr_gpc_map_tile5_f(u32 v) -{ - return (v & 0x1fU) << 25U; -} -static inline u32 gr_crstr_map_table_cfg_r(void) -{ - return 0x00418bb8U; -} -static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_r(u32 i) -{ - return 0x00418980U + i*4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_gpm_pd_cfg_r(void) -{ - return 0x00418c6cU; -} -static inline u32 gr_gpcs_gcc_pagepool_base_r(void) -{ - return 0x00419004U; -} -static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_gcc_pagepool_r(void) -{ - return 0x00419008U; -} -static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v) -{ - return (v & 0x3ffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_pe_vaf_r(void) -{ - return 0x0041980cU; -} -static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void) -{ - return 0x00419848U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) -{ - return 0x00419c00U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void) -{ - return 0x00419c2cU; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(void) -{ - return 0x00419ea8U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r(void) -{ - return 0x00504728U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_error_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_api_stack_error_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_wrap_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_overflow_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) -{ - return 0x200U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) -{ - return 0x800U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_reg_report_f(void) -{ - return 0x2000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_addr_report_f(void) -{ - return 0x4000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f(void) -{ - return 0x8000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) -{ - return 0x10000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) -{ - return 0x40000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_fault_report_f(void) -{ - return 0x800000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_overflow_report_f(void) -{ - return 0x400000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_nack_report_f(void) -{ - return 0x4000000U; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) -{ - return 0x00419d0cU; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) -{ - return 0x0050450cU; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_mpc_enabled_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) -{ - return 0x0041ac94U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_gcc_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_gpccs_f(u32 v) -{ - return (v & 0x1U) << 14U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_gpcmmu_f(u32 v) -{ - return (v & 0x1U) << 15U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) -{ - return 0x00502c90U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_f(u32 v) -{ - return (v & 0x1U) << 14U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_m(void) -{ - return 0x1U << 14U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_pending_f(void) -{ - return 0x4000U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_gpcmmu_f(u32 v) -{ - return (v & 0x1U) << 15U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_gpcmmu_m(void) -{ - return 0x1U << 15U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_gpcmmu_pending_f(void) -{ - return 0x8000U; -} -static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_r(void) -{ - return 0x00501048U; -} -static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_bank0_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_bank1_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_bank0_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_bank1_m(void) -{ - return 0x1U << 5U; -} -static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 10U) & 0x1U; -} -static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_r(void) -{ - return 0x0050104cU; -} -static inline u32 gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_r(void) -{ - return 0x00501054U; -} -static inline u32 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) -{ - return 0x00504508U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_r(void) -{ - return 0x00504704U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m(void) -{ - return 0x1U << 3U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_0_r(void) -{ - return 0x00504708U; -} -static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_1_r(void) -{ - return 0x0050470cU; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_0_r(void) -{ - return 0x00504710U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_1_r(void) -{ - return 0x00504714U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_0_r(void) -{ - return 0x00504718U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_1_r(void) -{ - return 0x0050471cU; -} -static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r(void) -{ - return 0x00419e90U; -} -static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_1_r(void) -{ - return 0x00419e94U; -} -static inline u32 gr_gpcs_tpcs_sms_dbgr_status0_r(void) -{ - return 0x00419e80U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_r(void) -{ - return 0x00504700U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_sm_in_trap_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_r(void) -{ - return 0x00504730U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_stack_error_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_api_stack_error_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_pc_wrap_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_pc_f(void) -{ - return 0x5U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_pc_overflow_f(void) -{ - return 0x6U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_reg_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_illegal_instr_encoding_f(void) -{ - return 0x9U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_illegal_instr_param_f(void) -{ - return 0xbU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_oor_reg_f(void) -{ - return 0xdU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_oor_addr_f(void) -{ - return 0xeU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_addr_f(void) -{ - return 0xfU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_invalid_addr_space_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_invalid_const_addr_ldc_f(void) -{ - return 0x12U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_stack_overflow_f(void) -{ - return 0x16U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_fault_f(void) -{ - return 0x17U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_tex_format_f(void) -{ - return 0x18U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_tex_layout_f(void) -{ - return 0x19U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_nack_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m(void) -{ - return 0xffU << 16U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m(void) -{ - return 0xfU << 24U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_r(void) -{ - return 0x0050460cU; -} -static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm0_error_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm1_error_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(void) -{ - return 0x00504738U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_hi_r(void) -{ - return 0x0050473cU; -} -static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) -{ - return 0x005043a0U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) -{ - return 0x00419ba0U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) -{ - return 0x005043b0U; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) -{ - return 0x00419bb0U; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) -{ - return 0x0041be08U; -} -static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) -{ - return 0x4U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map_r(u32 i) -{ - return 0x0041bf00U + i*4U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) -{ - return 0x0041bfd0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) -{ - return (v & 0x7U) << 21U; -} -static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) -{ - return 0x0041bfd4U; -} -static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_r(u32 i) -{ - return 0x0041bfb0U + i*4U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v(void) -{ - return 0x00000005U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gr_bes_zrop_settings_r(void) -{ - return 0x00408850U; -} -static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_be0_crop_debug3_r(void) -{ - return 0x00410108U; -} -static inline u32 gr_bes_crop_debug3_r(void) -{ - return 0x00408908U; -} -static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_bes_crop_debug3_blendopt_fill_override_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_bes_crop_debug3_blendopt_fill_override_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_bes_crop_debug3_blendopt_fill_override_enabled_f(void) -{ - return 0x4U; -} -static inline u32 gr_bes_crop_debug4_r(void) -{ - return 0x0040894cU; -} -static inline u32 gr_bes_crop_debug4_clamp_fp_blend_m(void) -{ - return 0x1U << 18U; -} -static inline u32 gr_bes_crop_debug4_clamp_fp_blend_to_inf_f(void) -{ - return 0x0U; -} -static inline u32 gr_bes_crop_debug4_clamp_fp_blend_to_maxval_f(void) -{ - return 0x40000U; -} -static inline u32 gr_bes_crop_settings_r(void) -{ - return 0x00408958U; -} -static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void) -{ - return 0x000000c0U; -} -static inline u32 gr_zcull_subregion_qty_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_gpcs_tpcs_tex_in_dbg_r(void) -{ - return 0x00419a00U; -} -static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m(void) -{ - return 0x1U << 19U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_r(void) -{ - return 0x00419bf0U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m(void) -{ - return 0x1U << 5U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void) -{ - return 0x1U << 10U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_m(void) -{ - return 0x1U << 28U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_enable_f(void) -{ - return 0x10000000U; -} -static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel0_r(void) -{ - return 0x00584200U; -} -static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel1_r(void) -{ - return 0x00584204U; -} -static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control0_r(void) -{ - return 0x00584208U; -} -static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control1_r(void) -{ - return 0x00584210U; -} -static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control2_r(void) -{ - return 0x00584214U; -} -static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control3_r(void) -{ - return 0x00584218U; -} -static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control4_r(void) -{ - return 0x0058421cU; -} -static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control5_r(void) -{ - return 0x0058420cU; -} -static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter0_control_r(void) -{ - return 0x00584220U; -} -static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter1_control_r(void) -{ - return 0x00584224U; -} -static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter2_control_r(void) -{ - return 0x00584228U; -} -static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter3_control_r(void) -{ - return 0x0058422cU; -} -static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter4_control_r(void) -{ - return 0x00584230U; -} -static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter5_control_r(void) -{ - return 0x00584234U; -} -static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter6_control_r(void) -{ - return 0x00584238U; -} -static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter7_control_r(void) -{ - return 0x0058423cU; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter_status_s0_r(void) -{ - return 0x00584600U; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter_status_s1_r(void) -{ - return 0x00584604U; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s0_r(void) -{ - return 0x00584624U; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s0_r(void) -{ - return 0x00584628U; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s0_r(void) -{ - return 0x0058462cU; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s0_r(void) -{ - return 0x00584630U; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s1_r(void) -{ - return 0x00584634U; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s1_r(void) -{ - return 0x00584638U; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s1_r(void) -{ - return 0x0058463cU; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s1_r(void) -{ - return 0x00584640U; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s2_r(void) -{ - return 0x00584644U; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s2_r(void) -{ - return 0x00584648U; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s2_r(void) -{ - return 0x0058464cU; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s2_r(void) -{ - return 0x00584650U; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s3_r(void) -{ - return 0x00584654U; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s3_r(void) -{ - return 0x00584658U; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s3_r(void) -{ - return 0x0058465cU; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s3_r(void) -{ - return 0x00584660U; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter4_r(void) -{ - return 0x00584614U; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter5_r(void) -{ - return 0x00584618U; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter6_r(void) -{ - return 0x0058461cU; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter7_r(void) -{ - return 0x00584620U; -} -static inline u32 gr_fe_pwr_mode_r(void) -{ - return 0x00404170U; -} -static inline u32 gr_fe_pwr_mode_mode_auto_f(void) -{ - return 0x0U; -} -static inline u32 gr_fe_pwr_mode_mode_force_on_f(void) -{ - return 0x2U; -} -static inline u32 gr_fe_pwr_mode_req_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 gr_fe_pwr_mode_req_send_f(void) -{ - return 0x10U; -} -static inline u32 gr_fe_pwr_mode_req_done_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) -{ - return 0x00418880U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void) -{ - return 0x1U << 11U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void) -{ - return 0x3U << 3U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void) -{ - return 0x3U << 5U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void) -{ - return 0x3U << 28U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void) -{ - return 0x1U << 30U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_atomic_capability_mode_m(void) -{ - return 0x3U << 24U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_atomic_capability_sys_ncoh_mode_m(void) -{ - return 0x1U << 27U; -} -static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) -{ - return 0x00418890U; -} -static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void) -{ - return 0x00418894U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) -{ - return 0x004188b0U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) -{ - return 0x004188b4U; -} -static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void) -{ - return 0x004188b8U; -} -static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) -{ - return 0x004188acU; -} -static inline u32 gr_gpcs_tpcs_sms_dbgr_control0_r(void) -{ - return 0x00419e84U; -} -static inline u32 gr_fe_gfxp_wfi_timeout_r(void) -{ - return 0x004041c0U; -} -static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fe_gfxp_wfi_timeout_count_init_f(void) -{ - return 0x800U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void) -{ - return 0x00419bd8U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void) -{ - return 0x7U << 8U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void) -{ - return 0x00419ba4U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void) -{ - return 0x3U << 11U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void) -{ - return 0x1000U; -} -static inline u32 gr_gpcs_tc_debug0_r(void) -{ - return 0x00418708U; -} -static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) -{ - return 0x1ffU << 0U; -} -static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_r(void) -{ - return 0x00500324U; -} -static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_corrected_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_corrected_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_uncorrected_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_uncorrected_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_r(void) -{ - return 0x00500314U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_sa_data_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_sa_data_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_fa_data_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_fa_data_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_sa_data_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_sa_data_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_fa_data_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_fa_data_m(void) -{ - return 0x1U << 3U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_total_counter_overflow_m(void) -{ - return 0x1U << 18U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_total_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_total_counter_overflow_m(void) -{ - return 0x1U << 16U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_unique_counter_overflow_m(void) -{ - return 0x1U << 19U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_unique_counter_overflow_m(void) -{ - return 0x1U << 17U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_address_r(void) -{ - return 0x00500320U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_address_index_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_r(void) -{ - return 0x00500318U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_s(void) -{ - return 16U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_m(void) -{ - return 0xffffU << 16U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_r(void) -{ - return 0x0050031cU; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_s(void) -{ - return 16U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_m(void) -{ - return 0xffffU << 16U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 gr_gpc0_gpccs_hww_esr_r(void) -{ - return 0x00502c98U; -} -static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_r(void) -{ - return 0x00502678U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_m(void) -{ - return 0x1U << 5U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m(void) -{ - return 0x1U << 10U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_pending_f(void) -{ - return 0x400U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_m(void) -{ - return 0x1U << 8U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_m(void) -{ - return 0x1U << 11U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_pending_f(void) -{ - return 0x800U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 9U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_m(void) -{ - return 0x1U << 9U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_pending_f(void) -{ - return 0x200U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_reset_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_reset_task_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_address_r(void) -{ - return 0x00502684U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_address_index_f(u32 v) -{ - return (v & 0x7fffffU) << 0U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_s(void) -{ - return 20U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_f(u32 v) -{ - return (v & 0xfffffU) << 0U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_m(void) -{ - return 0xfffffU << 0U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_v(u32 r) -{ - return (r >> 0U) & 0xfffffU; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_r(void) -{ - return 0x0050267cU; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_s(void) -{ - return 16U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_m(void) -{ - return 0xffffU << 16U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_r(void) -{ - return 0x00502680U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_s(void) -{ - return 16U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_m(void) -{ - return 0xffffU << 16U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 gr_fecs_falcon_ecc_status_r(void) -{ - return 0x00409678U; -} -static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_m(void) -{ - return 0x1U << 5U; -} -static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m(void) -{ - return 0x1U << 10U; -} -static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_pending_f(void) -{ - return 0x400U; -} -static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_m(void) -{ - return 0x1U << 8U; -} -static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_m(void) -{ - return 0x1U << 11U; -} -static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_pending_f(void) -{ - return 0x800U; -} -static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 9U; -} -static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_m(void) -{ - return 0x1U << 9U; -} -static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_pending_f(void) -{ - return 0x200U; -} -static inline u32 gr_fecs_falcon_ecc_status_reset_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_fecs_falcon_ecc_status_reset_task_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fecs_falcon_ecc_address_r(void) -{ - return 0x00409684U; -} -static inline u32 gr_fecs_falcon_ecc_address_index_f(u32 v) -{ - return (v & 0x7fffffU) << 0U; -} -static inline u32 gr_fecs_falcon_ecc_address_row_address_s(void) -{ - return 20U; -} -static inline u32 gr_fecs_falcon_ecc_address_row_address_f(u32 v) -{ - return (v & 0xfffffU) << 0U; -} -static inline u32 gr_fecs_falcon_ecc_address_row_address_m(void) -{ - return 0xfffffU << 0U; -} -static inline u32 gr_fecs_falcon_ecc_address_row_address_v(u32 r) -{ - return (r >> 0U) & 0xfffffU; -} -static inline u32 gr_fecs_falcon_ecc_corrected_err_count_r(void) -{ - return 0x0040967cU; -} -static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_s(void) -{ - return 16U; -} -static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_m(void) -{ - return 0xffffU << 16U; -} -static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_r(void) -{ - return 0x00409680U; -} -static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_s(void) -{ - return 16U; -} -static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_m(void) -{ - return 0xffffU << 16U; -} -static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 gr_debug_2_r(void) -{ - return 0x00400088U; -} -static inline u32 gr_debug_2_gfxp_wfi_timeout_unit_m(void) -{ - return 0x1U << 27U; -} -static inline u32 gr_debug_2_gfxp_wfi_timeout_unit_usec_f(void) -{ - return 0x0U; -} -static inline u32 gr_debug_2_gfxp_wfi_timeout_unit_sysclk_f(void) -{ - return 0x8000000U; -} -#endif diff --git a/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h b/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h deleted file mode 100644 index 342f90d..0000000 --- a/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h +++ /dev/null @@ -1,815 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ltc_gv11b_h_ -#define _hw_ltc_gv11b_h_ - -static inline u32 ltc_pltcg_base_v(void) -{ - return 0x00140000U; -} -static inline u32 ltc_pltcg_extent_v(void) -{ - return 0x0017ffffU; -} -static inline u32 ltc_ltc0_ltss_v(void) -{ - return 0x00140200U; -} -static inline u32 ltc_ltc0_lts0_v(void) -{ - return 0x00140400U; -} -static inline u32 ltc_ltcs_ltss_v(void) -{ - return 0x0017e200U; -} -static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) -{ - return 0x0014046cU; -} -static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) -{ - return 0x00140518U; -} -static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) -{ - return 0x0017e318U; -} -static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void) -{ - return 0x1U << 15U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) -{ - return 0x00140494U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) -{ - return (r >> 16U) & 0x3U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) -{ - return 0x00000000U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) -{ - return 0x00000002U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) -{ - return 0x0017e26cU; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) -{ - return 0x2U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) -{ - return 0x4U; -} -static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) -{ - return 0x0014046cU; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) -{ - return 0x0017e270U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) -{ - return (v & 0x3ffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) -{ - return 0x0017e274U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) -{ - return (v & 0x3ffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) -{ - return 0x0003ffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_base_r(void) -{ - return 0x0017e278U; -} -static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) -{ - return 0x0000000bU; -} -static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) -{ - return (r >> 0U) & 0x3ffffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) -{ - return 0x0017e27cU; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs__v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_v(u32 r) -{ - return (r >> 25U) & 0x1U; -} -static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) -{ - return 0x0017e000U; -} -static inline u32 ltc_ltcs_ltss_cbc_param_r(void) -{ - return 0x0017e280U; -} -static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r) -{ - return (r >> 24U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r) -{ - return (r >> 28U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_cbc_param2_r(void) -{ - return 0x0017e3f4U; -} -static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) -{ - return 0x0017e2acU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) -{ - return 0x0017e338U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) -{ - return 0x0017e33cU + i*4U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) -{ - return 0x0017e34cU; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) -{ - return 32U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(void) -{ - return 0x0017e204U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_s(void) -{ - return 8U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_m(void) -{ - return 0xffU << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) -{ - return 0x0017e2b0U; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_r(void) -{ - return 0x0017e214U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_r(void) -{ - return 0x00140214U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc1_ltss_g_elpg_r(void) -{ - return 0x00142214U; -} -static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_intr_r(void) -{ - return 0x0017e20cU; -} -static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void) -{ - return 0x100U; -} -static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void) -{ - return 0x200U; -} -static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) -{ - return 0x1U << 20U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_m(void) -{ - return 0x1U << 21U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_disabled_f(void) -{ - return 0x0U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) -{ - return 0x1U << 30U; -} -static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void) -{ - return 0x1000000U; -} -static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void) -{ - return 0x2000000U; -} -static inline u32 ltc_ltc0_lts0_intr_r(void) -{ - return 0x0014040cU; -} -static inline u32 ltc_ltcs_ltss_intr3_r(void) -{ - return 0x0017e388U; -} -static inline u32 ltc_ltcs_ltss_intr3_ecc_corrected_m(void) -{ - return 0x1U << 7U; -} -static inline u32 ltc_ltcs_ltss_intr3_ecc_uncorrected_m(void) -{ - return 0x1U << 8U; -} -static inline u32 ltc_ltc0_lts0_intr3_r(void) -{ - return 0x00140588U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_r(void) -{ - return 0x001404f0U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_m(void) -{ - return 0x1U << 1U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_m(void) -{ - return 0x1U << 3U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_m(void) -{ - return 0x1U << 5U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_m(void) -{ - return 0x1U << 0U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_m(void) -{ - return 0x1U << 2U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_m(void) -{ - return 0x1U << 4U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_m(void) -{ - return 0x1U << 18U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_m(void) -{ - return 0x1U << 16U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_unique_counter_overflow_m(void) -{ - return 0x1U << 19U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_unique_counter_overflow_m(void) -{ - return 0x1U << 17U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_address_r(void) -{ - return 0x001404fcU; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r(void) -{ - return 0x001404f4U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_s(void) -{ - return 16U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_m(void) -{ - return 0xffffU << 16U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_r(void) -{ - return 0x001404f8U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_s(void) -{ - return 16U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_m(void) -{ - return 0xffffU << 16U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void) -{ - return 0x0014051cU; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void) -{ - return 0xffU << 0U; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void) -{ - return 0xffU << 16U; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) -{ - return 0x0017e2a0U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) -{ - return 0x300U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) -{ - return 0x20000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) -{ - return 0x40000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) -{ - return 0x0017e2a4U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) -{ - return 0x300U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) -{ - return 0x10000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) -{ - return 0x20000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) -{ - return 0x40000000U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) -{ - return 0x001402a0U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) -{ - return 0x001402a4U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void) -{ - return 0x001422a0U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void) -{ - return 0x001422a4U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void) -{ - return 0x0014058cU; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -#endif diff --git a/include/nvgpu/hw/gv11b/hw_mc_gv11b.h b/include/nvgpu/hw/gv11b/hw_mc_gv11b.h deleted file mode 100644 index a1bf15b..0000000 --- a/include/nvgpu/hw/gv11b/hw_mc_gv11b.h +++ /dev/null @@ -1,231 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_mc_gv11b_h_ -#define _hw_mc_gv11b_h_ - -static inline u32 mc_boot_0_r(void) -{ - return 0x00000000U; -} -static inline u32 mc_boot_0_architecture_v(u32 r) -{ - return (r >> 24U) & 0x1fU; -} -static inline u32 mc_boot_0_implementation_v(u32 r) -{ - return (r >> 20U) & 0xfU; -} -static inline u32 mc_boot_0_major_revision_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 mc_boot_0_minor_revision_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 mc_intr_r(u32 i) -{ - return 0x00000100U + i*4U; -} -static inline u32 mc_intr_pfifo_pending_f(void) -{ - return 0x100U; -} -static inline u32 mc_intr_hub_pending_f(void) -{ - return 0x200U; -} -static inline u32 mc_intr_pgraph_pending_f(void) -{ - return 0x1000U; -} -static inline u32 mc_intr_pmu_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 mc_intr_ltc_pending_f(void) -{ - return 0x2000000U; -} -static inline u32 mc_intr_priv_ring_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 mc_intr_pbus_pending_f(void) -{ - return 0x10000000U; -} -static inline u32 mc_intr_en_r(u32 i) -{ - return 0x00000140U + i*4U; -} -static inline u32 mc_intr_en_set_r(u32 i) -{ - return 0x00000160U + i*4U; -} -static inline u32 mc_intr_en_clear_r(u32 i) -{ - return 0x00000180U + i*4U; -} -static inline u32 mc_enable_r(void) -{ - return 0x00000200U; -} -static inline u32 mc_enable_xbar_enabled_f(void) -{ - return 0x4U; -} -static inline u32 mc_enable_l2_enabled_f(void) -{ - return 0x8U; -} -static inline u32 mc_enable_pmedia_s(void) -{ - return 1U; -} -static inline u32 mc_enable_pmedia_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 mc_enable_pmedia_m(void) -{ - return 0x1U << 4U; -} -static inline u32 mc_enable_pmedia_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 mc_enable_ce0_m(void) -{ - return 0x1U << 6U; -} -static inline u32 mc_enable_pfifo_enabled_f(void) -{ - return 0x100U; -} -static inline u32 mc_enable_pgraph_enabled_f(void) -{ - return 0x1000U; -} -static inline u32 mc_enable_pwr_v(u32 r) -{ - return (r >> 13U) & 0x1U; -} -static inline u32 mc_enable_pwr_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 mc_enable_pwr_enabled_f(void) -{ - return 0x2000U; -} -static inline u32 mc_enable_pfb_enabled_f(void) -{ - return 0x100000U; -} -static inline u32 mc_enable_ce2_m(void) -{ - return 0x1U << 21U; -} -static inline u32 mc_enable_ce2_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 mc_enable_blg_enabled_f(void) -{ - return 0x8000000U; -} -static inline u32 mc_enable_perfmon_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 mc_enable_hub_enabled_f(void) -{ - return 0x20000000U; -} -static inline u32 mc_intr_ltc_r(void) -{ - return 0x000001c0U; -} -static inline u32 mc_enable_pb_r(void) -{ - return 0x00000204U; -} -static inline u32 mc_enable_pb_0_s(void) -{ - return 1U; -} -static inline u32 mc_enable_pb_0_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 mc_enable_pb_0_m(void) -{ - return 0x1U << 0U; -} -static inline u32 mc_enable_pb_0_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 mc_enable_pb_0_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 mc_enable_pb_sel_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -#endif diff --git a/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h b/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h deleted file mode 100644 index c04d30a..0000000 --- a/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h +++ /dev/null @@ -1,651 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pbdma_gv11b_h_ -#define _hw_pbdma_gv11b_h_ - -static inline u32 pbdma_gp_entry1_r(void) -{ - return 0x10000004U; -} -static inline u32 pbdma_gp_entry1_get_hi_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pbdma_gp_entry1_length_f(u32 v) -{ - return (v & 0x1fffffU) << 10U; -} -static inline u32 pbdma_gp_entry1_length_v(u32 r) -{ - return (r >> 10U) & 0x1fffffU; -} -static inline u32 pbdma_gp_base_r(u32 i) -{ - return 0x00040048U + i*8192U; -} -static inline u32 pbdma_gp_base__size_1_v(void) -{ - return 0x00000003U; -} -static inline u32 pbdma_gp_base_offset_f(u32 v) -{ - return (v & 0x1fffffffU) << 3U; -} -static inline u32 pbdma_gp_base_rsvd_s(void) -{ - return 3U; -} -static inline u32 pbdma_gp_base_hi_r(u32 i) -{ - return 0x0004004cU + i*8192U; -} -static inline u32 pbdma_gp_base_hi_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pbdma_gp_base_hi_limit2_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 pbdma_gp_fetch_r(u32 i) -{ - return 0x00040050U + i*8192U; -} -static inline u32 pbdma_gp_get_r(u32 i) -{ - return 0x00040014U + i*8192U; -} -static inline u32 pbdma_gp_put_r(u32 i) -{ - return 0x00040000U + i*8192U; -} -static inline u32 pbdma_pb_fetch_r(u32 i) -{ - return 0x00040054U + i*8192U; -} -static inline u32 pbdma_pb_fetch_hi_r(u32 i) -{ - return 0x00040058U + i*8192U; -} -static inline u32 pbdma_get_r(u32 i) -{ - return 0x00040018U + i*8192U; -} -static inline u32 pbdma_get_hi_r(u32 i) -{ - return 0x0004001cU + i*8192U; -} -static inline u32 pbdma_put_r(u32 i) -{ - return 0x0004005cU + i*8192U; -} -static inline u32 pbdma_put_hi_r(u32 i) -{ - return 0x00040060U + i*8192U; -} -static inline u32 pbdma_pb_header_r(u32 i) -{ - return 0x00040084U + i*8192U; -} -static inline u32 pbdma_pb_header_priv_user_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_method_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_subchannel_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_level_main_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_first_true_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_pb_header_type_inc_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_pb_header_type_non_inc_f(void) -{ - return 0x60000000U; -} -static inline u32 pbdma_hdr_shadow_r(u32 i) -{ - return 0x00040118U + i*8192U; -} -static inline u32 pbdma_gp_shadow_0_r(u32 i) -{ - return 0x00040110U + i*8192U; -} -static inline u32 pbdma_gp_shadow_1_r(u32 i) -{ - return 0x00040114U + i*8192U; -} -static inline u32 pbdma_subdevice_r(u32 i) -{ - return 0x00040094U + i*8192U; -} -static inline u32 pbdma_subdevice_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 pbdma_subdevice_status_active_f(void) -{ - return 0x10000000U; -} -static inline u32 pbdma_subdevice_channel_dma_enable_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_method0_r(u32 i) -{ - return 0x000400c0U + i*8192U; -} -static inline u32 pbdma_method0_fifo_size_v(void) -{ - return 0x00000004U; -} -static inline u32 pbdma_method0_addr_f(u32 v) -{ - return (v & 0xfffU) << 2U; -} -static inline u32 pbdma_method0_addr_v(u32 r) -{ - return (r >> 2U) & 0xfffU; -} -static inline u32 pbdma_method0_subch_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 pbdma_method0_first_true_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_method0_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_method1_r(u32 i) -{ - return 0x000400c8U + i*8192U; -} -static inline u32 pbdma_method2_r(u32 i) -{ - return 0x000400d0U + i*8192U; -} -static inline u32 pbdma_method3_r(u32 i) -{ - return 0x000400d8U + i*8192U; -} -static inline u32 pbdma_data0_r(u32 i) -{ - return 0x000400c4U + i*8192U; -} -static inline u32 pbdma_acquire_r(u32 i) -{ - return 0x00040030U + i*8192U; -} -static inline u32 pbdma_acquire_retry_man_2_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_acquire_retry_exp_2_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_acquire_timeout_exp_f(u32 v) -{ - return (v & 0xfU) << 11U; -} -static inline u32 pbdma_acquire_timeout_exp_max_v(void) -{ - return 0x0000000fU; -} -static inline u32 pbdma_acquire_timeout_exp_max_f(void) -{ - return 0x7800U; -} -static inline u32 pbdma_acquire_timeout_man_f(u32 v) -{ - return (v & 0xffffU) << 15U; -} -static inline u32 pbdma_acquire_timeout_man_max_v(void) -{ - return 0x0000ffffU; -} -static inline u32 pbdma_acquire_timeout_man_max_f(void) -{ - return 0x7fff8000U; -} -static inline u32 pbdma_acquire_timeout_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_acquire_timeout_en_disable_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_status_r(u32 i) -{ - return 0x00040100U + i*8192U; -} -static inline u32 pbdma_channel_r(u32 i) -{ - return 0x00040120U + i*8192U; -} -static inline u32 pbdma_signature_r(u32 i) -{ - return 0x00040010U + i*8192U; -} -static inline u32 pbdma_signature_hw_valid_f(void) -{ - return 0xfaceU; -} -static inline u32 pbdma_signature_sw_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_userd_r(u32 i) -{ - return 0x00040008U + i*8192U; -} -static inline u32 pbdma_userd_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_userd_target_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 pbdma_userd_addr_f(u32 v) -{ - return (v & 0x7fffffU) << 9U; -} -static inline u32 pbdma_config_r(u32 i) -{ - return 0x000400f4U + i*8192U; -} -static inline u32 pbdma_config_l2_evict_first_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_config_l2_evict_normal_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_config_ce_split_enable_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_config_ce_split_disable_f(void) -{ - return 0x10U; -} -static inline u32 pbdma_config_auth_level_non_privileged_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_config_auth_level_privileged_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_config_userd_writeback_disable_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_config_userd_writeback_enable_f(void) -{ - return 0x1000U; -} -static inline u32 pbdma_userd_hi_r(u32 i) -{ - return 0x0004000cU + i*8192U; -} -static inline u32 pbdma_userd_hi_addr_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pbdma_hce_ctrl_r(u32 i) -{ - return 0x000400e4U + i*8192U; -} -static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void) -{ - return 0x20U; -} -static inline u32 pbdma_intr_0_r(u32 i) -{ - return 0x00040108U + i*8192U; -} -static inline u32 pbdma_intr_0_memreq_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pbdma_intr_0_memreq_pending_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_intr_0_memack_timeout_pending_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_intr_0_memack_extra_pending_f(void) -{ - return 0x4U; -} -static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void) -{ - return 0x8U; -} -static inline u32 pbdma_intr_0_memdat_extra_pending_f(void) -{ - return 0x10U; -} -static inline u32 pbdma_intr_0_memflush_pending_f(void) -{ - return 0x20U; -} -static inline u32 pbdma_intr_0_memop_pending_f(void) -{ - return 0x40U; -} -static inline u32 pbdma_intr_0_lbconnect_pending_f(void) -{ - return 0x80U; -} -static inline u32 pbdma_intr_0_lbreq_pending_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_0_lback_timeout_pending_f(void) -{ - return 0x200U; -} -static inline u32 pbdma_intr_0_lback_extra_pending_f(void) -{ - return 0x400U; -} -static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void) -{ - return 0x800U; -} -static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void) -{ - return 0x1000U; -} -static inline u32 pbdma_intr_0_gpfifo_pending_f(void) -{ - return 0x2000U; -} -static inline u32 pbdma_intr_0_gpptr_pending_f(void) -{ - return 0x4000U; -} -static inline u32 pbdma_intr_0_gpentry_pending_f(void) -{ - return 0x8000U; -} -static inline u32 pbdma_intr_0_gpcrc_pending_f(void) -{ - return 0x10000U; -} -static inline u32 pbdma_intr_0_pbptr_pending_f(void) -{ - return 0x20000U; -} -static inline u32 pbdma_intr_0_pbentry_pending_f(void) -{ - return 0x40000U; -} -static inline u32 pbdma_intr_0_pbcrc_pending_f(void) -{ - return 0x80000U; -} -static inline u32 pbdma_intr_0_clear_faulted_error_pending_f(void) -{ - return 0x100000U; -} -static inline u32 pbdma_intr_0_method_pending_f(void) -{ - return 0x200000U; -} -static inline u32 pbdma_intr_0_methodcrc_pending_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_intr_0_device_pending_f(void) -{ - return 0x800000U; -} -static inline u32 pbdma_intr_0_eng_reset_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 pbdma_intr_0_semaphore_pending_f(void) -{ - return 0x2000000U; -} -static inline u32 pbdma_intr_0_acquire_pending_f(void) -{ - return 0x4000000U; -} -static inline u32 pbdma_intr_0_pri_pending_f(void) -{ - return 0x8000000U; -} -static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_intr_0_pbseg_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 pbdma_intr_0_signature_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_intr_1_r(u32 i) -{ - return 0x00040148U + i*8192U; -} -static inline u32 pbdma_intr_1_ctxnotvalid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 pbdma_intr_1_ctxnotvalid_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_intr_en_0_r(u32 i) -{ - return 0x0004010cU + i*8192U; -} -static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_en_1_r(u32 i) -{ - return 0x0004014cU + i*8192U; -} -static inline u32 pbdma_intr_stall_r(u32 i) -{ - return 0x0004013cU + i*8192U; -} -static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_stall_1_r(u32 i) -{ - return 0x00040140U + i*8192U; -} -static inline u32 pbdma_intr_stall_1_hce_illegal_op_enabled_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_udma_nop_r(void) -{ - return 0x00000008U; -} -static inline u32 pbdma_runlist_timeslice_r(u32 i) -{ - return 0x000400f8U + i*8192U; -} -static inline u32 pbdma_runlist_timeslice_timeout_128_f(void) -{ - return 0x80U; -} -static inline u32 pbdma_runlist_timeslice_timescale_3_f(void) -{ - return 0x3000U; -} -static inline u32 pbdma_runlist_timeslice_enable_true_f(void) -{ - return 0x10000000U; -} -static inline u32 pbdma_target_r(u32 i) -{ - return 0x000400acU + i*8192U; -} -static inline u32 pbdma_target_engine_sw_f(void) -{ - return 0x1fU; -} -static inline u32 pbdma_target_eng_ctx_valid_true_f(void) -{ - return 0x10000U; -} -static inline u32 pbdma_target_eng_ctx_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_target_ce_ctx_valid_true_f(void) -{ - return 0x20000U; -} -static inline u32 pbdma_target_ce_ctx_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_target_host_tsg_event_reason_pbdma_idle_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_target_host_tsg_event_reason_semaphore_acquire_failure_f(void) -{ - return 0x1000000U; -} -static inline u32 pbdma_target_host_tsg_event_reason_tsg_yield_f(void) -{ - return 0x2000000U; -} -static inline u32 pbdma_target_host_tsg_event_reason_host_subchannel_switch_f(void) -{ - return 0x3000000U; -} -static inline u32 pbdma_target_should_send_tsg_event_true_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_target_should_send_tsg_event_false_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_target_needs_host_tsg_event_true_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_target_needs_host_tsg_event_false_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_set_channel_info_r(u32 i) -{ - return 0x000400fcU + i*8192U; -} -static inline u32 pbdma_set_channel_info_veid_f(u32 v) -{ - return (v & 0x3fU) << 8U; -} -static inline u32 pbdma_timeout_r(u32 i) -{ - return 0x0004012cU + i*8192U; -} -static inline u32 pbdma_timeout_period_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 pbdma_timeout_period_max_f(void) -{ - return 0xffffffffU; -} -static inline u32 pbdma_timeout_period_init_f(void) -{ - return 0x10000U; -} -#endif diff --git a/include/nvgpu/hw/gv11b/hw_perf_gv11b.h b/include/nvgpu/hw/gv11b/hw_perf_gv11b.h deleted file mode 100644 index a3341df..0000000 --- a/include/nvgpu/hw/gv11b/hw_perf_gv11b.h +++ /dev/null @@ -1,263 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_perf_gv11b_h_ -#define _hw_perf_gv11b_h_ - -static inline u32 perf_pmmgpc_perdomain_offset_v(void) -{ - return 0x00000200U; -} -static inline u32 perf_pmmsys_perdomain_offset_v(void) -{ - return 0x00000200U; -} -static inline u32 perf_pmmgpc_base_v(void) -{ - return 0x00180000U; -} -static inline u32 perf_pmmgpc_extent_v(void) -{ - return 0x00183fffU; -} -static inline u32 perf_pmmsys_base_v(void) -{ - return 0x00240000U; -} -static inline u32 perf_pmmsys_extent_v(void) -{ - return 0x00243fffU; -} -static inline u32 perf_pmmfbp_base_v(void) -{ - return 0x00200000U; -} -static inline u32 perf_pmasys_control_r(void) -{ - return 0x0024a000U; -} -static inline u32 perf_pmasys_control_membuf_status_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void) -{ - return 0x10U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) -{ - return 0x20U; -} -static inline u32 perf_pmasys_mem_block_r(void) -{ - return 0x0024a070U; -} -static inline u32 perf_pmasys_mem_block_base_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 perf_pmasys_mem_block_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 perf_pmasys_mem_block_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 perf_pmasys_mem_block_target_lfb_v(void) -{ - return 0x00000000U; -} -static inline u32 perf_pmasys_mem_block_target_lfb_f(void) -{ - return 0x0U; -} -static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 perf_pmasys_mem_block_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 perf_pmasys_mem_block_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 perf_pmasys_mem_block_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_mem_block_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 perf_pmasys_mem_block_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 perf_pmasys_mem_block_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 perf_pmasys_outbase_r(void) -{ - return 0x0024a074U; -} -static inline u32 perf_pmasys_outbase_ptr_f(u32 v) -{ - return (v & 0x7ffffffU) << 5U; -} -static inline u32 perf_pmasys_outbaseupper_r(void) -{ - return 0x0024a078U; -} -static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 perf_pmasys_outsize_r(void) -{ - return 0x0024a07cU; -} -static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) -{ - return (v & 0x7ffffffU) << 5U; -} -static inline u32 perf_pmasys_mem_bytes_r(void) -{ - return 0x0024a084U; -} -static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 perf_pmasys_mem_bump_r(void) -{ - return 0x0024a088U; -} -static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 perf_pmasys_enginestatus_r(void) -{ - return 0x0024a0a4U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void) -{ - return 0x10U; -} -static inline u32 perf_pmmsys_engine_sel_r(u32 i) -{ - return 0x0024006cU + i*512U; -} -static inline u32 perf_pmmsys_engine_sel__size_1_v(void) -{ - return 0x00000020U; -} -static inline u32 perf_pmmfbp_engine_sel_r(u32 i) -{ - return 0x0020006cU + i*512U; -} -static inline u32 perf_pmmfbp_engine_sel__size_1_v(void) -{ - return 0x00000020U; -} -static inline u32 perf_pmmgpc_engine_sel_r(u32 i) -{ - return 0x0018006cU + i*512U; -} -static inline u32 perf_pmmgpc_engine_sel__size_1_v(void) -{ - return 0x00000020U; -} -#endif diff --git a/include/nvgpu/hw/gv11b/hw_pram_gv11b.h b/include/nvgpu/hw/gv11b/hw_pram_gv11b.h deleted file mode 100644 index 456d631..0000000 --- a/include/nvgpu/hw/gv11b/hw_pram_gv11b.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pram_gv11b_h_ -#define _hw_pram_gv11b_h_ - -static inline u32 pram_data032_r(u32 i) -{ - return 0x00700000U + i*4U; -} -#endif diff --git a/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h b/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h deleted file mode 100644 index a653681..0000000 --- a/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pri_ringmaster_gv11b_h_ -#define _hw_pri_ringmaster_gv11b_h_ - -static inline u32 pri_ringmaster_command_r(void) -{ - return 0x0012004cU; -} -static inline u32 pri_ringmaster_command_cmd_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 pri_ringmaster_command_cmd_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void) -{ - return 0x00000000U; -} -static inline u32 pri_ringmaster_command_cmd_start_ring_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void) -{ - return 0x2U; -} -static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void) -{ - return 0x3U; -} -static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void) -{ - return 0x0U; -} -static inline u32 pri_ringmaster_command_data_r(void) -{ - return 0x00120048U; -} -static inline u32 pri_ringmaster_start_results_r(void) -{ - return 0x00120050U; -} -static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void) -{ - return 0x00000001U; -} -static inline u32 pri_ringmaster_intr_status0_r(void) -{ - return 0x00120058U; -} -static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status1_r(void) -{ - return 0x0012005cU; -} -static inline u32 pri_ringmaster_global_ctl_r(void) -{ - return 0x00120060U; -} -static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void) -{ - return 0x0U; -} -static inline u32 pri_ringmaster_enum_fbp_r(void) -{ - return 0x00120074U; -} -static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 pri_ringmaster_enum_gpc_r(void) -{ - return 0x00120078U; -} -static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 pri_ringmaster_enum_ltc_r(void) -{ - return 0x0012006cU; -} -static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -#endif diff --git a/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h b/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h deleted file mode 100644 index 47da22c..0000000 --- a/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pri_ringstation_gpc_gv11b_h_ -#define _hw_pri_ringstation_gpc_gv11b_h_ - -static inline u32 pri_ringstation_gpc_master_config_r(u32 i) -{ - return 0x00128300U + i*4U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void) -{ - return 0x00128120U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void) -{ - return 0x00128124U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void) -{ - return 0x00128128U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void) -{ - return 0x0012812cU; -} -#endif diff --git a/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h b/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h deleted file mode 100644 index 622b6d7..0000000 --- a/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pri_ringstation_sys_gv11b_h_ -#define _hw_pri_ringstation_sys_gv11b_h_ - -static inline u32 pri_ringstation_sys_master_config_r(u32 i) -{ - return 0x00122300U + i*4U; -} -static inline u32 pri_ringstation_sys_decode_config_r(void) -{ - return 0x00122204U; -} -static inline u32 pri_ringstation_sys_decode_config_ring_m(void) -{ - return 0x7U << 0U; -} -static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringstation_sys_priv_error_adr_r(void) -{ - return 0x00122120U; -} -static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void) -{ - return 0x00122124U; -} -static inline u32 pri_ringstation_sys_priv_error_info_r(void) -{ - return 0x00122128U; -} -static inline u32 pri_ringstation_sys_priv_error_code_r(void) -{ - return 0x0012212cU; -} -#endif diff --git a/include/nvgpu/hw/gv11b/hw_proj_gv11b.h b/include/nvgpu/hw/gv11b/hw_proj_gv11b.h deleted file mode 100644 index 7283237..0000000 --- a/include/nvgpu/hw/gv11b/hw_proj_gv11b.h +++ /dev/null @@ -1,191 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_proj_gv11b_h_ -#define _hw_proj_gv11b_h_ - -static inline u32 proj_gpc_base_v(void) -{ - return 0x00500000U; -} -static inline u32 proj_gpc_shared_base_v(void) -{ - return 0x00418000U; -} -static inline u32 proj_gpc_stride_v(void) -{ - return 0x00008000U; -} -static inline u32 proj_gpc_priv_stride_v(void) -{ - return 0x00000800U; -} -static inline u32 proj_ltc_stride_v(void) -{ - return 0x00002000U; -} -static inline u32 proj_lts_stride_v(void) -{ - return 0x00000200U; -} -static inline u32 proj_fbpa_stride_v(void) -{ - return 0x00004000U; -} -static inline u32 proj_ppc_in_gpc_base_v(void) -{ - return 0x00003000U; -} -static inline u32 proj_ppc_in_gpc_shared_base_v(void) -{ - return 0x00003e00U; -} -static inline u32 proj_ppc_in_gpc_stride_v(void) -{ - return 0x00000200U; -} -static inline u32 proj_rop_base_v(void) -{ - return 0x00410000U; -} -static inline u32 proj_rop_shared_base_v(void) -{ - return 0x00408800U; -} -static inline u32 proj_rop_stride_v(void) -{ - return 0x00000400U; -} -static inline u32 proj_tpc_in_gpc_base_v(void) -{ - return 0x00004000U; -} -static inline u32 proj_tpc_in_gpc_stride_v(void) -{ - return 0x00000800U; -} -static inline u32 proj_tpc_in_gpc_shared_base_v(void) -{ - return 0x00001800U; -} -static inline u32 proj_smpc_base_v(void) -{ - return 0x00000200U; -} -static inline u32 proj_smpc_shared_base_v(void) -{ - return 0x00000300U; -} -static inline u32 proj_smpc_unique_base_v(void) -{ - return 0x00000600U; -} -static inline u32 proj_smpc_stride_v(void) -{ - return 0x00000100U; -} -static inline u32 proj_host_num_engines_v(void) -{ - return 0x00000004U; -} -static inline u32 proj_host_num_pbdma_v(void) -{ - return 0x00000003U; -} -static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) -{ - return 0x00000004U; -} -static inline u32 proj_scal_litter_num_fbps_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_fbpas_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_gpcs_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) -{ - return 0x00000002U; -} -static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) -{ - return 0x00000002U; -} -static inline u32 proj_scal_litter_num_zcull_banks_v(void) -{ - return 0x00000004U; -} -static inline u32 proj_scal_litter_num_sm_per_tpc_v(void) -{ - return 0x00000002U; -} -static inline u32 proj_scal_max_gpcs_v(void) -{ - return 0x00000020U; -} -static inline u32 proj_scal_max_tpc_per_gpc_v(void) -{ - return 0x00000008U; -} -static inline u32 proj_sm_stride_v(void) -{ - return 0x00000080U; -} -#endif diff --git a/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h b/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h deleted file mode 100644 index 1cda12d..0000000 --- a/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h +++ /dev/null @@ -1,1219 +0,0 @@ -/* - * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pwr_gv11b_h_ -#define _hw_pwr_gv11b_h_ - -static inline u32 pwr_falcon_irqsset_r(void) -{ - return 0x0010a000U; -} -static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 pwr_falcon_irqsclr_r(void) -{ - return 0x0010a004U; -} -static inline u32 pwr_falcon_irqstat_r(void) -{ - return 0x0010a008U; -} -static inline u32 pwr_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 pwr_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 pwr_falcon_irqstat_ext_second_true_f(void) -{ - return 0x800U; -} -static inline u32 pwr_falcon_irqstat_ext_ecc_parity_true_f(void) -{ - return 0x400U; -} -static inline u32 pwr_pmu_ecc_intr_status_r(void) -{ - return 0x0010abfcU; -} -static inline u32 pwr_pmu_ecc_intr_status_corrected_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_pmu_ecc_intr_status_corrected_m(void) -{ - return 0x1U << 0U; -} -static inline u32 pwr_pmu_ecc_intr_status_uncorrected_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_pmu_ecc_intr_status_uncorrected_m(void) -{ - return 0x1U << 1U; -} -static inline u32 pwr_falcon_irqmode_r(void) -{ - return 0x0010a00cU; -} -static inline u32 pwr_falcon_irqmset_r(void) -{ - return 0x0010a010U; -} -static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqmset_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqmset_ext_ctxe_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 pwr_falcon_irqmset_ext_limitv_f(u32 v) -{ - return (v & 0x1U) << 9U; -} -static inline u32 pwr_falcon_irqmset_ext_second_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 pwr_falcon_irqmset_ext_therm_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 pwr_falcon_irqmset_ext_miscio_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 pwr_falcon_irqmset_ext_rttimer_f(u32 v) -{ - return (v & 0x1U) << 14U; -} -static inline u32 pwr_falcon_irqmset_ext_rsvd8_f(u32 v) -{ - return (v & 0x1U) << 15U; -} -static inline u32 pwr_falcon_irqmset_ext_ecc_parity_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 pwr_falcon_irqmclr_r(void) -{ - return 0x0010a014U; -} -static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqmclr_ext_ctxe_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 pwr_falcon_irqmclr_ext_limitv_f(u32 v) -{ - return (v & 0x1U) << 9U; -} -static inline u32 pwr_falcon_irqmclr_ext_second_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 pwr_falcon_irqmclr_ext_therm_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 pwr_falcon_irqmclr_ext_miscio_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 pwr_falcon_irqmclr_ext_rttimer_f(u32 v) -{ - return (v & 0x1U) << 14U; -} -static inline u32 pwr_falcon_irqmclr_ext_rsvd8_f(u32 v) -{ - return (v & 0x1U) << 15U; -} -static inline u32 pwr_falcon_irqmclr_ext_ecc_parity_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 pwr_falcon_irqmask_r(void) -{ - return 0x0010a018U; -} -static inline u32 pwr_falcon_irqdest_r(void) -{ - return 0x0010a01cU; -} -static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqdest_host_ext_ctxe_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 pwr_falcon_irqdest_host_ext_limitv_f(u32 v) -{ - return (v & 0x1U) << 9U; -} -static inline u32 pwr_falcon_irqdest_host_ext_second_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 pwr_falcon_irqdest_host_ext_therm_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 pwr_falcon_irqdest_host_ext_miscio_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 pwr_falcon_irqdest_host_ext_rttimer_f(u32 v) -{ - return (v & 0x1U) << 14U; -} -static inline u32 pwr_falcon_irqdest_host_ext_rsvd8_f(u32 v) -{ - return (v & 0x1U) << 15U; -} -static inline u32 pwr_falcon_irqdest_host_ext_ecc_parity_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 pwr_falcon_irqdest_target_ext_ctxe_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_irqdest_target_ext_limitv_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 pwr_falcon_irqdest_target_ext_second_f(u32 v) -{ - return (v & 0x1U) << 27U; -} -static inline u32 pwr_falcon_irqdest_target_ext_therm_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 pwr_falcon_irqdest_target_ext_miscio_f(u32 v) -{ - return (v & 0x1U) << 29U; -} -static inline u32 pwr_falcon_irqdest_target_ext_rttimer_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 pwr_falcon_irqdest_target_ext_rsvd8_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 pwr_falcon_irqdest_target_ext_ecc_parity_f(u32 v) -{ - return (v & 0x1U) << 26U; -} -static inline u32 pwr_falcon_curctx_r(void) -{ - return 0x0010a050U; -} -static inline u32 pwr_falcon_nxtctx_r(void) -{ - return 0x0010a054U; -} -static inline u32 pwr_falcon_mailbox0_r(void) -{ - return 0x0010a040U; -} -static inline u32 pwr_falcon_mailbox1_r(void) -{ - return 0x0010a044U; -} -static inline u32 pwr_falcon_itfen_r(void) -{ - return 0x0010a048U; -} -static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 pwr_falcon_idlestate_r(void) -{ - return 0x0010a04cU; -} -static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 pwr_falcon_os_r(void) -{ - return 0x0010a080U; -} -static inline u32 pwr_falcon_engctl_r(void) -{ - return 0x0010a0a4U; -} -static inline u32 pwr_falcon_cpuctl_r(void) -{ - return 0x0010a100U; -} -static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) -{ - return 0x1U << 4U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void) -{ - return 0x1U << 6U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 pwr_falcon_cpuctl_alias_r(void) -{ - return 0x0010a130U; -} -static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_pmu_scpctl_stat_r(void) -{ - return 0x0010ac08U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void) -{ - return 0x1U << 20U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 pwr_falcon_imemc_r(u32 i) -{ - return 0x0010a180U + i*16U; -} -static inline u32 pwr_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pwr_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_imemd_r(u32 i) -{ - return 0x0010a184U + i*16U; -} -static inline u32 pwr_falcon_imemt_r(u32 i) -{ - return 0x0010a188U + i*16U; -} -static inline u32 pwr_falcon_sctl_r(void) -{ - return 0x0010a240U; -} -static inline u32 pwr_falcon_mmu_phys_sec_r(void) -{ - return 0x00100ce4U; -} -static inline u32 pwr_falcon_bootvec_r(void) -{ - return 0x0010a104U; -} -static inline u32 pwr_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_falcon_dmactl_r(void) -{ - return 0x0010a10cU; -} -static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) -{ - return 0x1U << 1U; -} -static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) -{ - return 0x1U << 2U; -} -static inline u32 pwr_falcon_hwcfg_r(void) -{ - return 0x0010a108U; -} -static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 pwr_falcon_dmatrfbase_r(void) -{ - return 0x0010a110U; -} -static inline u32 pwr_falcon_dmatrfbase1_r(void) -{ - return 0x0010a128U; -} -static inline u32 pwr_falcon_dmatrfmoffs_r(void) -{ - return 0x0010a114U; -} -static inline u32 pwr_falcon_dmatrfcmd_r(void) -{ - return 0x0010a118U; -} -static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 pwr_falcon_dmatrffboffs_r(void) -{ - return 0x0010a11cU; -} -static inline u32 pwr_falcon_exterraddr_r(void) -{ - return 0x0010a168U; -} -static inline u32 pwr_falcon_exterrstat_r(void) -{ - return 0x0010a16cU; -} -static inline u32 pwr_falcon_exterrstat_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 pwr_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_r(void) -{ - return 0x0010a200U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) -{ - return 0xfU << 0U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 pwr_pmu_falcon_icd_rdata_r(void) -{ - return 0x0010a20cU; -} -static inline u32 pwr_falcon_dmemc_r(u32 i) -{ - return 0x0010a1c0U + i*8U; -} -static inline u32 pwr_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pwr_falcon_dmemc_offs_m(void) -{ - return 0x3fU << 2U; -} -static inline u32 pwr_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_dmemc_blk_m(void) -{ - return 0xffU << 8U; -} -static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 pwr_falcon_dmemd_r(u32 i) -{ - return 0x0010a1c4U + i*8U; -} -static inline u32 pwr_pmu_new_instblk_r(void) -{ - return 0x0010a480U; -} -static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 pwr_pmu_new_instblk_target_fb_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 pwr_pmu_mutex_id_r(void) -{ - return 0x0010a488U; -} -static inline u32 pwr_pmu_mutex_id_value_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pwr_pmu_mutex_id_value_init_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) -{ - return 0x000000ffU; -} -static inline u32 pwr_pmu_mutex_id_release_r(void) -{ - return 0x0010a48cU; -} -static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_id_release_value_m(void) -{ - return 0xffU << 0U; -} -static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_mutex_r(u32 i) -{ - return 0x0010a580U + i*4U; -} -static inline u32 pwr_pmu_mutex__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 pwr_pmu_mutex_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_value_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_queue_head_r(u32 i) -{ - return 0x0010a800U + i*4U; -} -static inline u32 pwr_pmu_queue_head__size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 pwr_pmu_queue_head_address_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_queue_head_address_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_queue_tail_r(u32 i) -{ - return 0x0010a820U + i*4U; -} -static inline u32 pwr_pmu_queue_tail__size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 pwr_pmu_queue_tail_address_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_queue_tail_address_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_msgq_head_r(void) -{ - return 0x0010a4c8U; -} -static inline u32 pwr_pmu_msgq_head_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_msgq_head_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_msgq_tail_r(void) -{ - return 0x0010a4ccU; -} -static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_idle_mask_r(u32 i) -{ - return 0x0010a504U + i*16U; -} -static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) -{ - return 0x1U; -} -static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 pwr_pmu_idle_mask_1_r(u32 i) -{ - return 0x0010aa34U + i*8U; -} -static inline u32 pwr_pmu_idle_mask_2_r(u32 i) -{ - return 0x0010a840U + i*4U; -} -static inline u32 pwr_pmu_idle_count_r(u32 i) -{ - return 0x0010a508U + i*16U; -} -static inline u32 pwr_pmu_idle_count_value_f(u32 v) -{ - return (v & 0x7fffffffU) << 0U; -} -static inline u32 pwr_pmu_idle_count_value_v(u32 r) -{ - return (r >> 0U) & 0x7fffffffU; -} -static inline u32 pwr_pmu_idle_count_reset_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 pwr_pmu_idle_ctrl_r(u32 i) -{ - return 0x0010a50cU + i*16U; -} -static inline u32 pwr_pmu_idle_ctrl_value_m(void) -{ - return 0x3U << 0U; -} -static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) -{ - return 0x2U; -} -static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) -{ - return 0x3U; -} -static inline u32 pwr_pmu_idle_ctrl_filter_m(void) -{ - return 0x1U << 2U; -} -static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_idle_threshold_r(u32 i) -{ - return 0x0010a8a0U + i*4U; -} -static inline u32 pwr_pmu_idle_threshold_value_f(u32 v) -{ - return (v & 0x7fffffffU) << 0U; -} -static inline u32 pwr_pmu_idle_intr_r(void) -{ - return 0x0010a9e8U; -} -static inline u32 pwr_pmu_idle_intr_en_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_en_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_idle_intr_en_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_intr_status_r(void) -{ - return 0x0010a9ecU; -} -static inline u32 pwr_pmu_idle_intr_status_intr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_m(void) -{ - return 0x1U << 0U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) -{ - return 0x0010a9f0U + i*8U; -} -static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) -{ - return 0x0010a9f4U + i*8U; -} -static inline u32 pwr_pmu_idle_mask_2_supp_r(u32 i) -{ - return 0x0010a690U + i*4U; -} -static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) -{ - return 0x0010aa30U + i*8U; -} -static inline u32 pwr_pmu_debug_r(u32 i) -{ - return 0x0010a5c0U + i*4U; -} -static inline u32 pwr_pmu_debug__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 pwr_pmu_mailbox_r(u32 i) -{ - return 0x0010a450U + i*4U; -} -static inline u32 pwr_pmu_mailbox__size_1_v(void) -{ - return 0x0000000cU; -} -static inline u32 pwr_pmu_bar0_addr_r(void) -{ - return 0x0010a7a0U; -} -static inline u32 pwr_pmu_bar0_data_r(void) -{ - return 0x0010a7a4U; -} -static inline u32 pwr_pmu_bar0_ctl_r(void) -{ - return 0x0010a7acU; -} -static inline u32 pwr_pmu_bar0_timeout_r(void) -{ - return 0x0010a7a8U; -} -static inline u32 pwr_pmu_bar0_fecs_error_r(void) -{ - return 0x0010a988U; -} -static inline u32 pwr_pmu_bar0_error_status_r(void) -{ - return 0x0010a7b0U; -} -static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) -{ - return 0x0010a6c0U + i*4U; -} -static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) -{ - return 0x0010a6e8U + i*4U; -} -static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) -{ - return 0x0010a710U + i*4U; -} -static inline u32 pwr_pmu_pg_intren_r(u32 i) -{ - return 0x0010a760U + i*4U; -} -static inline u32 pwr_pmu_falcon_ecc_status_r(void) -{ - return 0x0010a6b0U; -} -static inline u32 pwr_pmu_falcon_ecc_status_corrected_err_imem_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_pmu_falcon_ecc_status_corrected_err_imem_m(void) -{ - return 0x1U << 0U; -} -static inline u32 pwr_pmu_falcon_ecc_status_corrected_err_dmem_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_pmu_falcon_ecc_status_corrected_err_dmem_m(void) -{ - return 0x1U << 1U; -} -static inline u32 pwr_pmu_falcon_ecc_status_uncorrected_err_imem_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 pwr_pmu_falcon_ecc_status_uncorrected_err_imem_m(void) -{ - return 0x1U << 8U; -} -static inline u32 pwr_pmu_falcon_ecc_status_uncorrected_err_dmem_f(u32 v) -{ - return (v & 0x1U) << 9U; -} -static inline u32 pwr_pmu_falcon_ecc_status_uncorrected_err_dmem_m(void) -{ - return 0x1U << 9U; -} -static inline u32 pwr_pmu_falcon_ecc_status_corrected_err_total_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 pwr_pmu_falcon_ecc_status_corrected_err_total_counter_overflow_m(void) -{ - return 0x1U << 16U; -} -static inline u32 pwr_pmu_falcon_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 pwr_pmu_falcon_ecc_status_uncorrected_err_total_counter_overflow_m(void) -{ - return 0x1U << 18U; -} -static inline u32 pwr_pmu_falcon_ecc_status_reset_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 pwr_pmu_falcon_ecc_status_reset_task_f(void) -{ - return 0x80000000U; -} -static inline u32 pwr_pmu_falcon_ecc_address_r(void) -{ - return 0x0010a6b4U; -} -static inline u32 pwr_pmu_falcon_ecc_address_index_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 pwr_pmu_falcon_ecc_address_type_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 pwr_pmu_falcon_ecc_address_type_imem_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_falcon_ecc_address_type_dmem_f(void) -{ - return 0x100000U; -} -static inline u32 pwr_pmu_falcon_ecc_address_row_address_s(void) -{ - return 16U; -} -static inline u32 pwr_pmu_falcon_ecc_address_row_address_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 pwr_pmu_falcon_ecc_address_row_address_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 pwr_pmu_falcon_ecc_address_row_address_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_r(void) -{ - return 0x0010a6b8U; -} -static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_total_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_unique_total_s(void) -{ - return 16U; -} -static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_unique_total_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_unique_total_m(void) -{ - return 0xffffU << 16U; -} -static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_unique_total_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_r(void) -{ - return 0x0010a6bcU; -} -static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_total_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_unique_total_s(void) -{ - return 16U; -} -static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_unique_total_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_unique_total_m(void) -{ - return 0xffffU << 16U; -} -static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 pwr_fbif_transcfg_r(u32 i) -{ - return 0x0010ae00U + i*4U; -} -static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) -{ - return 0x0U; -} -static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) -{ - return 0x1U; -} -static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) -{ - return 0x2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_s(void) -{ - return 1U; -} -static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_m(void) -{ - return 0x1U << 2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) -{ - return 0x0U; -} -static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) -{ - return 0x4U; -} -#endif diff --git a/include/nvgpu/hw/gv11b/hw_ram_gv11b.h b/include/nvgpu/hw/gv11b/hw_ram_gv11b.h deleted file mode 100644 index 59c6d88..0000000 --- a/include/nvgpu/hw/gv11b/hw_ram_gv11b.h +++ /dev/null @@ -1,791 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ram_gv11b_h_ -#define _hw_ram_gv11b_h_ - -static inline u32 ram_in_ramfc_s(void) -{ - return 4096U; -} -static inline u32 ram_in_ramfc_w(void) -{ - return 0U; -} -static inline u32 ram_in_page_dir_base_target_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ram_in_page_dir_base_target_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 ram_in_page_dir_base_vol_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_vol_true_f(void) -{ - return 0x4U; -} -static inline u32 ram_in_page_dir_base_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) -{ - return 0x1U << 4U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) -{ - return 0x10U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) -{ - return 0x1U << 5U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void) -{ - return 0x20U; -} -static inline u32 ram_in_use_ver2_pt_format_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 ram_in_use_ver2_pt_format_m(void) -{ - return 0x1U << 10U; -} -static inline u32 ram_in_use_ver2_pt_format_w(void) -{ - return 128U; -} -static inline u32 ram_in_use_ver2_pt_format_true_f(void) -{ - return 0x400U; -} -static inline u32 ram_in_use_ver2_pt_format_false_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_big_page_size_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 ram_in_big_page_size_m(void) -{ - return 0x1U << 11U; -} -static inline u32 ram_in_big_page_size_w(void) -{ - return 128U; -} -static inline u32 ram_in_big_page_size_128kb_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_big_page_size_64kb_f(void) -{ - return 0x800U; -} -static inline u32 ram_in_page_dir_base_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_page_dir_base_lo_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_hi_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_in_page_dir_base_hi_w(void) -{ - return 129U; -} -static inline u32 ram_in_engine_cs_w(void) -{ - return 132U; -} -static inline u32 ram_in_engine_cs_wfi_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_engine_cs_wfi_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_engine_cs_fg_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_engine_cs_fg_f(void) -{ - return 0x8U; -} -static inline u32 ram_in_engine_wfi_mode_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 ram_in_engine_wfi_mode_w(void) -{ - return 132U; -} -static inline u32 ram_in_engine_wfi_mode_physical_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_engine_wfi_mode_virtual_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_engine_wfi_target_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ram_in_engine_wfi_target_w(void) -{ - return 132U; -} -static inline u32 ram_in_engine_wfi_target_sys_mem_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 ram_in_engine_wfi_target_sys_mem_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 ram_in_engine_wfi_target_local_mem_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_engine_wfi_ptr_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_engine_wfi_ptr_lo_w(void) -{ - return 132U; -} -static inline u32 ram_in_engine_wfi_ptr_hi_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ram_in_engine_wfi_ptr_hi_w(void) -{ - return 133U; -} -static inline u32 ram_in_engine_wfi_veid_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 ram_in_engine_wfi_veid_w(void) -{ - return 134U; -} -static inline u32 ram_in_eng_method_buffer_addr_lo_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_in_eng_method_buffer_addr_lo_w(void) -{ - return 136U; -} -static inline u32 ram_in_eng_method_buffer_addr_hi_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ram_in_eng_method_buffer_addr_hi_w(void) -{ - return 137U; -} -static inline u32 ram_in_sc_page_dir_base_target_f(u32 v, u32 i) -{ - return (v & 0x3U) << (0U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_target__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_target_vid_mem_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_sc_page_dir_base_target_invalid_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_page_dir_base_target_sys_mem_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 ram_in_sc_page_dir_base_vol_f(u32 v, u32 i) -{ - return (v & 0x1U) << (2U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_vol__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_vol_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_page_dir_base_vol_false_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_f(u32 v, u32 i) -{ - return (v & 0x1U) << (4U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_f(u32 v, u32 i) -{ - return (v & 0x1U) << (5U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_sc_use_ver2_pt_format_f(u32 v, u32 i) -{ - return (v & 0x1U) << (10U + i*0U); -} -static inline u32 ram_in_sc_use_ver2_pt_format__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_use_ver2_pt_format_false_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_sc_use_ver2_pt_format_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_big_page_size_f(u32 v, u32 i) -{ - return (v & 0x1U) << (11U + i*0U); -} -static inline u32 ram_in_sc_big_page_size__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_big_page_size_64kb_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_page_dir_base_lo_f(u32 v, u32 i) -{ - return (v & 0xfffffU) << (12U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_lo__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_hi_f(u32 v, u32 i) -{ - return (v & 0xffffffffU) << (0U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_hi__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_target_0_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ram_in_sc_page_dir_base_target_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_page_dir_base_vol_0_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 ram_in_sc_page_dir_base_vol_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_use_ver2_pt_format_0_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 ram_in_sc_use_ver2_pt_format_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_big_page_size_0_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 ram_in_sc_big_page_size_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_page_dir_base_lo_0_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_sc_page_dir_base_lo_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_page_dir_base_hi_0_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_in_sc_page_dir_base_hi_0_w(void) -{ - return 169U; -} -static inline u32 ram_in_base_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 ram_in_alloc_size_v(void) -{ - return 0x00001000U; -} -static inline u32 ram_fc_size_val_v(void) -{ - return 0x00000200U; -} -static inline u32 ram_fc_gp_put_w(void) -{ - return 0U; -} -static inline u32 ram_fc_userd_w(void) -{ - return 2U; -} -static inline u32 ram_fc_userd_hi_w(void) -{ - return 3U; -} -static inline u32 ram_fc_signature_w(void) -{ - return 4U; -} -static inline u32 ram_fc_gp_get_w(void) -{ - return 5U; -} -static inline u32 ram_fc_pb_get_w(void) -{ - return 6U; -} -static inline u32 ram_fc_pb_get_hi_w(void) -{ - return 7U; -} -static inline u32 ram_fc_pb_top_level_get_w(void) -{ - return 8U; -} -static inline u32 ram_fc_pb_top_level_get_hi_w(void) -{ - return 9U; -} -static inline u32 ram_fc_acquire_w(void) -{ - return 12U; -} -static inline u32 ram_fc_sem_addr_hi_w(void) -{ - return 14U; -} -static inline u32 ram_fc_sem_addr_lo_w(void) -{ - return 15U; -} -static inline u32 ram_fc_sem_payload_lo_w(void) -{ - return 16U; -} -static inline u32 ram_fc_sem_payload_hi_w(void) -{ - return 39U; -} -static inline u32 ram_fc_sem_execute_w(void) -{ - return 17U; -} -static inline u32 ram_fc_gp_base_w(void) -{ - return 18U; -} -static inline u32 ram_fc_gp_base_hi_w(void) -{ - return 19U; -} -static inline u32 ram_fc_gp_fetch_w(void) -{ - return 20U; -} -static inline u32 ram_fc_pb_fetch_w(void) -{ - return 21U; -} -static inline u32 ram_fc_pb_fetch_hi_w(void) -{ - return 22U; -} -static inline u32 ram_fc_pb_put_w(void) -{ - return 23U; -} -static inline u32 ram_fc_pb_put_hi_w(void) -{ - return 24U; -} -static inline u32 ram_fc_pb_header_w(void) -{ - return 33U; -} -static inline u32 ram_fc_pb_count_w(void) -{ - return 34U; -} -static inline u32 ram_fc_subdevice_w(void) -{ - return 37U; -} -static inline u32 ram_fc_target_w(void) -{ - return 43U; -} -static inline u32 ram_fc_hce_ctrl_w(void) -{ - return 57U; -} -static inline u32 ram_fc_chid_w(void) -{ - return 58U; -} -static inline u32 ram_fc_chid_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_fc_chid_id_w(void) -{ - return 0U; -} -static inline u32 ram_fc_config_w(void) -{ - return 61U; -} -static inline u32 ram_fc_runlist_timeslice_w(void) -{ - return 62U; -} -static inline u32 ram_fc_set_channel_info_w(void) -{ - return 63U; -} -static inline u32 ram_userd_base_shift_v(void) -{ - return 0x00000009U; -} -static inline u32 ram_userd_chan_size_v(void) -{ - return 0x00000200U; -} -static inline u32 ram_userd_put_w(void) -{ - return 16U; -} -static inline u32 ram_userd_get_w(void) -{ - return 17U; -} -static inline u32 ram_userd_ref_w(void) -{ - return 18U; -} -static inline u32 ram_userd_put_hi_w(void) -{ - return 19U; -} -static inline u32 ram_userd_ref_threshold_w(void) -{ - return 20U; -} -static inline u32 ram_userd_top_level_get_w(void) -{ - return 22U; -} -static inline u32 ram_userd_top_level_get_hi_w(void) -{ - return 23U; -} -static inline u32 ram_userd_get_hi_w(void) -{ - return 24U; -} -static inline u32 ram_userd_gp_get_w(void) -{ - return 34U; -} -static inline u32 ram_userd_gp_put_w(void) -{ - return 35U; -} -static inline u32 ram_userd_gp_top_level_get_w(void) -{ - return 22U; -} -static inline u32 ram_userd_gp_top_level_get_hi_w(void) -{ - return 23U; -} -static inline u32 ram_rl_entry_size_v(void) -{ - return 0x00000010U; -} -static inline u32 ram_rl_entry_type_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ram_rl_entry_type_channel_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_rl_entry_type_tsg_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_rl_entry_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_chan_runqueue_selector_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ram_rl_entry_chan_inst_target_f(u32 v) -{ - return (v & 0x3U) << 4U; -} -static inline u32 ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 ram_rl_entry_chan_inst_target_sys_mem_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 ram_rl_entry_chan_inst_target_vid_mem_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_rl_entry_chan_userd_target_f(u32 v) -{ - return (v & 0x3U) << 6U; -} -static inline u32 ram_rl_entry_chan_userd_target_vid_mem_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_rl_entry_chan_userd_target_vid_mem_nvlink_coh_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_rl_entry_chan_userd_target_sys_mem_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 ram_rl_entry_chan_userd_ptr_lo_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 ram_rl_entry_chan_userd_ptr_hi_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_rl_entry_chid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_chan_inst_ptr_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_rl_entry_chan_inst_ptr_hi_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_rl_entry_tsg_timeslice_scale_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 ram_rl_entry_tsg_timeslice_scale_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ram_rl_entry_tsg_timeslice_timeout_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 ram_rl_entry_tsg_timeslice_timeout_128_v(void) -{ - return 0x00000080U; -} -static inline u32 ram_rl_entry_tsg_length_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ram_rl_entry_tsg_length_init_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_rl_entry_tsg_length_min_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_rl_entry_tsg_length_max_v(void) -{ - return 0x00000080U; -} -static inline u32 ram_rl_entry_tsg_tsgid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_chan_userd_ptr_align_shift_v(void) -{ - return 0x00000008U; -} -static inline u32 ram_rl_entry_chan_userd_align_shift_v(void) -{ - return 0x00000008U; -} -static inline u32 ram_rl_entry_chan_inst_ptr_align_shift_v(void) -{ - return 0x0000000cU; -} -#endif diff --git a/include/nvgpu/hw/gv11b/hw_therm_gv11b.h b/include/nvgpu/hw/gv11b/hw_therm_gv11b.h deleted file mode 100644 index 0050083..0000000 --- a/include/nvgpu/hw/gv11b/hw_therm_gv11b.h +++ /dev/null @@ -1,487 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_therm_gv11b_h_ -#define _hw_therm_gv11b_h_ - -static inline u32 therm_use_a_r(void) -{ - return 0x00020798U; -} -static inline u32 therm_use_a_ext_therm_0_enable_f(void) -{ - return 0x1U; -} -static inline u32 therm_use_a_ext_therm_1_enable_f(void) -{ - return 0x2U; -} -static inline u32 therm_use_a_ext_therm_2_enable_f(void) -{ - return 0x4U; -} -static inline u32 therm_evt_ext_therm_0_r(void) -{ - return 0x00020700U; -} -static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v) -{ - return (v & 0x3fU) << 24U; -} -static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void) -{ - return 0x00000001U; -} -static inline u32 therm_evt_ext_therm_0_mode_f(u32 v) -{ - return (v & 0x3U) << 30U; -} -static inline u32 therm_evt_ext_therm_0_mode_normal_v(void) -{ - return 0x00000000U; -} -static inline u32 therm_evt_ext_therm_0_mode_inverted_v(void) -{ - return 0x00000001U; -} -static inline u32 therm_evt_ext_therm_0_mode_forced_v(void) -{ - return 0x00000002U; -} -static inline u32 therm_evt_ext_therm_0_mode_cleared_v(void) -{ - return 0x00000003U; -} -static inline u32 therm_evt_ext_therm_1_r(void) -{ - return 0x00020704U; -} -static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v) -{ - return (v & 0x3fU) << 24U; -} -static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void) -{ - return 0x00000002U; -} -static inline u32 therm_evt_ext_therm_1_mode_f(u32 v) -{ - return (v & 0x3U) << 30U; -} -static inline u32 therm_evt_ext_therm_1_mode_normal_v(void) -{ - return 0x00000000U; -} -static inline u32 therm_evt_ext_therm_1_mode_inverted_v(void) -{ - return 0x00000001U; -} -static inline u32 therm_evt_ext_therm_1_mode_forced_v(void) -{ - return 0x00000002U; -} -static inline u32 therm_evt_ext_therm_1_mode_cleared_v(void) -{ - return 0x00000003U; -} -static inline u32 therm_evt_ext_therm_2_r(void) -{ - return 0x00020708U; -} -static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v) -{ - return (v & 0x3fU) << 24U; -} -static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void) -{ - return 0x00000003U; -} -static inline u32 therm_evt_ext_therm_2_mode_f(u32 v) -{ - return (v & 0x3U) << 30U; -} -static inline u32 therm_evt_ext_therm_2_mode_normal_v(void) -{ - return 0x00000000U; -} -static inline u32 therm_evt_ext_therm_2_mode_inverted_v(void) -{ - return 0x00000001U; -} -static inline u32 therm_evt_ext_therm_2_mode_forced_v(void) -{ - return 0x00000002U; -} -static inline u32 therm_evt_ext_therm_2_mode_cleared_v(void) -{ - return 0x00000003U; -} -static inline u32 therm_weight_1_r(void) -{ - return 0x00020024U; -} -static inline u32 therm_config1_r(void) -{ - return 0x00020050U; -} -static inline u32 therm_config2_r(void) -{ - return 0x00020130U; -} -static inline u32 therm_config2_grad_step_duration_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 therm_config2_grad_step_duration_m(void) -{ - return 0xfU << 8U; -} -static inline u32 therm_config2_slowdown_factor_extended_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 therm_config2_grad_enable_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 therm_gate_ctrl_r(u32 i) -{ - return 0x00020200U + i*4U; -} -static inline u32 therm_gate_ctrl_eng_clk_m(void) -{ - return 0x3U << 0U; -} -static inline u32 therm_gate_ctrl_eng_clk_run_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) -{ - return 0x1U; -} -static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) -{ - return 0x2U; -} -static inline u32 therm_gate_ctrl_blk_clk_m(void) -{ - return 0x3U << 2U; -} -static inline u32 therm_gate_ctrl_blk_clk_run_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) -{ - return 0x4U; -} -static inline u32 therm_gate_ctrl_idle_holdoff_m(void) -{ - return 0x1U << 4U; -} -static inline u32 therm_gate_ctrl_idle_holdoff_off_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_idle_holdoff_on_f(void) -{ - return 0x10U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) -{ - return 0x1fU << 8U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp__prod_f(void) -{ - return 0x200U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) -{ - return (v & 0x7U) << 13U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) -{ - return 0x7U << 13U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant__prod_f(void) -{ - return 0x2000U; -} -static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 therm_gate_ctrl_eng_delay_before_m(void) -{ - return 0xfU << 16U; -} -static inline u32 therm_gate_ctrl_eng_delay_before__prod_f(void) -{ - return 0x40000U; -} -static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 therm_gate_ctrl_eng_delay_after_m(void) -{ - return 0xfU << 20U; -} -static inline u32 therm_gate_ctrl_eng_delay_after__prod_f(void) -{ - return 0x0U; -} -static inline u32 therm_fecs_idle_filter_r(void) -{ - return 0x00020288U; -} -static inline u32 therm_fecs_idle_filter_value_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 therm_fecs_idle_filter_value__prod_f(void) -{ - return 0x0U; -} -static inline u32 therm_hubmmu_idle_filter_r(void) -{ - return 0x0002028cU; -} -static inline u32 therm_hubmmu_idle_filter_value_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 therm_hubmmu_idle_filter_value__prod_f(void) -{ - return 0x0U; -} -static inline u32 therm_clk_slowdown_r(u32 i) -{ - return 0x00020160U + i*4U; -} -static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) -{ - return (v & 0x3fU) << 16U; -} -static inline u32 therm_clk_slowdown_idle_factor_m(void) -{ - return 0x3fU << 16U; -} -static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) -{ - return (r >> 16U) & 0x3fU; -} -static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) -{ - return 0x0U; -} -static inline u32 therm_clk_slowdown_2_r(u32 i) -{ - return 0x000201a0U + i*4U; -} -static inline u32 therm_clk_slowdown_2_idle_condition_a_select_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 therm_clk_slowdown_2_idle_condition_a_type_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 therm_clk_slowdown_2_idle_condition_a_type_v(u32 r) -{ - return (r >> 4U) & 0x7U; -} -static inline u32 therm_clk_slowdown_2_idle_condition_a_type_never_f(void) -{ - return 0x40U; -} -static inline u32 therm_clk_slowdown_2_idle_condition_b_type_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 therm_clk_slowdown_2_idle_condition_b_type_v(u32 r) -{ - return (r >> 12U) & 0x7U; -} -static inline u32 therm_clk_slowdown_2_idle_condition_b_type_never_f(void) -{ - return 0x4000U; -} -static inline u32 therm_grad_stepping_table_r(u32 i) -{ - return 0x000202c8U + i*4U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1_f(void) -{ - return 0x0U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void) -{ - return 0x1U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void) -{ - return 0x2U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void) -{ - return 0x6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void) -{ - return 0xeU; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by16_f(void) -{ - return 0x1eU; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by32_f(void) -{ - return 0x3eU; -} -static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v) -{ - return (v & 0x3fU) << 6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void) -{ - return 0x3fU << 6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) -{ - return (v & 0x3fU) << 12U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void) -{ - return 0x3fU << 12U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) -{ - return (v & 0x3fU) << 18U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void) -{ - return 0x3fU << 18U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) -{ - return (v & 0x3fU) << 24U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void) -{ - return 0x3fU << 24U; -} -static inline u32 therm_grad_stepping0_r(void) -{ - return 0x000202c0U; -} -static inline u32 therm_grad_stepping0_feature_s(void) -{ - return 1U; -} -static inline u32 therm_grad_stepping0_feature_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 therm_grad_stepping0_feature_m(void) -{ - return 0x1U << 0U; -} -static inline u32 therm_grad_stepping0_feature_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 therm_grad_stepping0_feature_enable_f(void) -{ - return 0x1U; -} -static inline u32 therm_grad_stepping1_r(void) -{ - return 0x000202c4U; -} -static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 therm_clk_timing_r(u32 i) -{ - return 0x000203c0U + i*4U; -} -static inline u32 therm_clk_timing_grad_slowdown_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 therm_clk_timing_grad_slowdown_m(void) -{ - return 0x1U << 16U; -} -static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void) -{ - return 0x10000U; -} -#endif diff --git a/include/nvgpu/hw/gv11b/hw_timer_gv11b.h b/include/nvgpu/hw/gv11b/hw_timer_gv11b.h deleted file mode 100644 index 34285b3..0000000 --- a/include/nvgpu/hw/gv11b/hw_timer_gv11b.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_timer_gv11b_h_ -#define _hw_timer_gv11b_h_ - -static inline u32 timer_pri_timeout_r(void) -{ - return 0x00009080U; -} -static inline u32 timer_pri_timeout_period_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 timer_pri_timeout_period_m(void) -{ - return 0xffffffU << 0U; -} -static inline u32 timer_pri_timeout_period_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 timer_pri_timeout_en_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 timer_pri_timeout_en_m(void) -{ - return 0x1U << 31U; -} -static inline u32 timer_pri_timeout_en_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 timer_pri_timeout_en_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 timer_pri_timeout_en_en_disabled_f(void) -{ - return 0x0U; -} -static inline u32 timer_pri_timeout_save_0_r(void) -{ - return 0x00009084U; -} -static inline u32 timer_pri_timeout_save_0_fecs_tgt_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 timer_pri_timeout_save_0_addr_v(u32 r) -{ - return (r >> 2U) & 0x3fffffU; -} -static inline u32 timer_pri_timeout_save_0_write_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 timer_pri_timeout_save_1_r(void) -{ - return 0x00009088U; -} -static inline u32 timer_pri_timeout_fecs_errcode_r(void) -{ - return 0x0000908cU; -} -static inline u32 timer_time_0_r(void) -{ - return 0x00009400U; -} -static inline u32 timer_time_1_r(void) -{ - return 0x00009410U; -} -#endif diff --git a/include/nvgpu/hw/gv11b/hw_top_gv11b.h b/include/nvgpu/hw/gv11b/hw_top_gv11b.h deleted file mode 100644 index 89e4aeb..0000000 --- a/include/nvgpu/hw/gv11b/hw_top_gv11b.h +++ /dev/null @@ -1,235 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_top_gv11b_h_ -#define _hw_top_gv11b_h_ - -static inline u32 top_num_gpcs_r(void) -{ - return 0x00022430U; -} -static inline u32 top_num_gpcs_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_tpc_per_gpc_r(void) -{ - return 0x00022434U; -} -static inline u32 top_tpc_per_gpc_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_num_fbps_r(void) -{ - return 0x00022438U; -} -static inline u32 top_num_fbps_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_ltc_per_fbp_r(void) -{ - return 0x00022450U; -} -static inline u32 top_ltc_per_fbp_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_slices_per_ltc_r(void) -{ - return 0x0002245cU; -} -static inline u32 top_slices_per_ltc_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_num_ltcs_r(void) -{ - return 0x00022454U; -} -static inline u32 top_num_ces_r(void) -{ - return 0x00022444U; -} -static inline u32 top_num_ces_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_device_info_r(u32 i) -{ - return 0x00022700U + i*4U; -} -static inline u32 top_device_info__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 top_device_info_chain_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 top_device_info_chain_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_engine_enum_v(u32 r) -{ - return (r >> 26U) & 0xfU; -} -static inline u32 top_device_info_runlist_enum_v(u32 r) -{ - return (r >> 21U) & 0xfU; -} -static inline u32 top_device_info_intr_enum_v(u32 r) -{ - return (r >> 15U) & 0x1fU; -} -static inline u32 top_device_info_reset_enum_v(u32 r) -{ - return (r >> 9U) & 0x1fU; -} -static inline u32 top_device_info_type_enum_v(u32 r) -{ - return (r >> 2U) & 0x1fffffffU; -} -static inline u32 top_device_info_type_enum_graphics_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_type_enum_graphics_f(void) -{ - return 0x0U; -} -static inline u32 top_device_info_type_enum_copy2_v(void) -{ - return 0x00000003U; -} -static inline u32 top_device_info_type_enum_copy2_f(void) -{ - return 0xcU; -} -static inline u32 top_device_info_type_enum_lce_v(void) -{ - return 0x00000013U; -} -static inline u32 top_device_info_type_enum_lce_f(void) -{ - return 0x4cU; -} -static inline u32 top_device_info_engine_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 top_device_info_runlist_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 top_device_info_intr_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 top_device_info_reset_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 top_device_info_entry_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 top_device_info_entry_not_valid_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_entry_enum_v(void) -{ - return 0x00000002U; -} -static inline u32 top_device_info_entry_data_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_data_type_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 top_device_info_data_type_enum2_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_data_inst_id_v(u32 r) -{ - return (r >> 26U) & 0xfU; -} -static inline u32 top_device_info_data_pri_base_v(u32 r) -{ - return (r >> 12U) & 0xfffU; -} -static inline u32 top_device_info_data_pri_base_align_v(void) -{ - return 0x0000000cU; -} -static inline u32 top_device_info_data_fault_id_enum_v(u32 r) -{ - return (r >> 3U) & 0x7fU; -} -static inline u32 top_device_info_data_fault_id_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 top_device_info_data_fault_id_valid_v(void) -{ - return 0x00000001U; -} -#endif diff --git a/include/nvgpu/hw/gv11b/hw_usermode_gv11b.h b/include/nvgpu/hw/gv11b/hw_usermode_gv11b.h deleted file mode 100644 index e374969..0000000 --- a/include/nvgpu/hw/gv11b/hw_usermode_gv11b.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_usermode_gv11b_h_ -#define _hw_usermode_gv11b_h_ - -static inline u32 usermode_cfg0_r(void) -{ - return 0x00810000; -} -static inline u32 usermode_cfg0_usermode_class_id_f(u32 v) -{ - return (v & 0xffff) << 0; -} -static inline u32 usermode_cfg0_usermode_class_id_value_v(void) -{ - return 0x0000c361; -} -static inline u32 usermode_time_0_r(void) -{ - return 0x00810080; -} -static inline u32 usermode_time_0_nsec_f(u32 v) -{ - return (v & 0x7ffffff) << 5; -} -static inline u32 usermode_time_1_r(void) -{ - return 0x00810084; -} -static inline u32 usermode_time_1_nsec_f(u32 v) -{ - return (v & 0x1fffffff) << 0; -} -static inline u32 usermode_notify_channel_pending_r(void) -{ - return 0x00810090; -} -static inline u32 usermode_notify_channel_pending_id_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -#endif diff --git a/include/nvgpu/hw_sim.h b/include/nvgpu/hw_sim.h deleted file mode 100644 index 89ce6da..0000000 --- a/include/nvgpu/hw_sim.h +++ /dev/null @@ -1,2153 +0,0 @@ -/* - * Copyright (c) 2012-2018, NVIDIA Corporation. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - - /* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ - -#ifndef __hw_sim_h__ -#define __hw_sim_h__ -/*This file is autogenerated. Do not edit. */ - -static inline u32 sim_send_ring_r(void) -{ - return 0x00000000; -} -static inline u32 sim_send_ring_target_s(void) -{ - return 2; -} -static inline u32 sim_send_ring_target_f(u32 v) -{ - return (v & 0x3) << 0; -} -static inline u32 sim_send_ring_target_m(void) -{ - return 0x3 << 0; -} -static inline u32 sim_send_ring_target_v(u32 r) -{ - return (r >> 0) & 0x3; -} -static inline u32 sim_send_ring_target_phys_init_v(void) -{ - return 0x00000001; -} -static inline u32 sim_send_ring_target_phys_init_f(void) -{ - return 0x1; -} -static inline u32 sim_send_ring_target_phys__init_v(void) -{ - return 0x00000001; -} -static inline u32 sim_send_ring_target_phys__init_f(void) -{ - return 0x1; -} -static inline u32 sim_send_ring_target_phys__prod_v(void) -{ - return 0x00000001; -} -static inline u32 sim_send_ring_target_phys__prod_f(void) -{ - return 0x1; -} -static inline u32 sim_send_ring_target_phys_nvm_v(void) -{ - return 0x00000001; -} -static inline u32 sim_send_ring_target_phys_nvm_f(void) -{ - return 0x1; -} -static inline u32 sim_send_ring_target_phys_pci_v(void) -{ - return 0x00000002; -} -static inline u32 sim_send_ring_target_phys_pci_f(void) -{ - return 0x2; -} -static inline u32 sim_send_ring_target_phys_pci_coherent_v(void) -{ - return 0x00000003; -} -static inline u32 sim_send_ring_target_phys_pci_coherent_f(void) -{ - return 0x3; -} -static inline u32 sim_send_ring_status_s(void) -{ - return 1; -} -static inline u32 sim_send_ring_status_f(u32 v) -{ - return (v & 0x1) << 3; -} -static inline u32 sim_send_ring_status_m(void) -{ - return 0x1 << 3; -} -static inline u32 sim_send_ring_status_v(u32 r) -{ - return (r >> 3) & 0x1; -} -static inline u32 sim_send_ring_status_init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_send_ring_status_init_f(void) -{ - return 0x0; -} -static inline u32 sim_send_ring_status__init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_send_ring_status__init_f(void) -{ - return 0x0; -} -static inline u32 sim_send_ring_status__prod_v(void) -{ - return 0x00000000; -} -static inline u32 sim_send_ring_status__prod_f(void) -{ - return 0x0; -} -static inline u32 sim_send_ring_status_invalid_v(void) -{ - return 0x00000000; -} -static inline u32 sim_send_ring_status_invalid_f(void) -{ - return 0x0; -} -static inline u32 sim_send_ring_status_valid_v(void) -{ - return 0x00000001; -} -static inline u32 sim_send_ring_status_valid_f(void) -{ - return 0x8; -} -static inline u32 sim_send_ring_size_s(void) -{ - return 2; -} -static inline u32 sim_send_ring_size_f(u32 v) -{ - return (v & 0x3) << 4; -} -static inline u32 sim_send_ring_size_m(void) -{ - return 0x3 << 4; -} -static inline u32 sim_send_ring_size_v(u32 r) -{ - return (r >> 4) & 0x3; -} -static inline u32 sim_send_ring_size_init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_send_ring_size_init_f(void) -{ - return 0x0; -} -static inline u32 sim_send_ring_size__init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_send_ring_size__init_f(void) -{ - return 0x0; -} -static inline u32 sim_send_ring_size__prod_v(void) -{ - return 0x00000000; -} -static inline u32 sim_send_ring_size__prod_f(void) -{ - return 0x0; -} -static inline u32 sim_send_ring_size_4kb_v(void) -{ - return 0x00000000; -} -static inline u32 sim_send_ring_size_4kb_f(void) -{ - return 0x0; -} -static inline u32 sim_send_ring_size_8kb_v(void) -{ - return 0x00000001; -} -static inline u32 sim_send_ring_size_8kb_f(void) -{ - return 0x10; -} -static inline u32 sim_send_ring_size_12kb_v(void) -{ - return 0x00000002; -} -static inline u32 sim_send_ring_size_12kb_f(void) -{ - return 0x20; -} -static inline u32 sim_send_ring_size_16kb_v(void) -{ - return 0x00000003; -} -static inline u32 sim_send_ring_size_16kb_f(void) -{ - return 0x30; -} -static inline u32 sim_send_ring_gp_in_ring_s(void) -{ - return 1; -} -static inline u32 sim_send_ring_gp_in_ring_f(u32 v) -{ - return (v & 0x1) << 11; -} -static inline u32 sim_send_ring_gp_in_ring_m(void) -{ - return 0x1 << 11; -} -static inline u32 sim_send_ring_gp_in_ring_v(u32 r) -{ - return (r >> 11) & 0x1; -} -static inline u32 sim_send_ring_gp_in_ring__init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_send_ring_gp_in_ring__init_f(void) -{ - return 0x0; -} -static inline u32 sim_send_ring_gp_in_ring__prod_v(void) -{ - return 0x00000000; -} -static inline u32 sim_send_ring_gp_in_ring__prod_f(void) -{ - return 0x0; -} -static inline u32 sim_send_ring_gp_in_ring_no_v(void) -{ - return 0x00000000; -} -static inline u32 sim_send_ring_gp_in_ring_no_f(void) -{ - return 0x0; -} -static inline u32 sim_send_ring_gp_in_ring_yes_v(void) -{ - return 0x00000001; -} -static inline u32 sim_send_ring_gp_in_ring_yes_f(void) -{ - return 0x800; -} -static inline u32 sim_send_ring_addr_lo_s(void) -{ - return 20; -} -static inline u32 sim_send_ring_addr_lo_f(u32 v) -{ - return (v & 0xfffff) << 12; -} -static inline u32 sim_send_ring_addr_lo_m(void) -{ - return 0xfffff << 12; -} -static inline u32 sim_send_ring_addr_lo_v(u32 r) -{ - return (r >> 12) & 0xfffff; -} -static inline u32 sim_send_ring_addr_lo__init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_send_ring_addr_lo__init_f(void) -{ - return 0x0; -} -static inline u32 sim_send_ring_addr_lo__prod_v(void) -{ - return 0x00000000; -} -static inline u32 sim_send_ring_addr_lo__prod_f(void) -{ - return 0x0; -} -static inline u32 sim_send_ring_hi_r(void) -{ - return 0x00000004; -} -static inline u32 sim_send_ring_hi_addr_s(void) -{ - return 20; -} -static inline u32 sim_send_ring_hi_addr_f(u32 v) -{ - return (v & 0xfffff) << 0; -} -static inline u32 sim_send_ring_hi_addr_m(void) -{ - return 0xfffff << 0; -} -static inline u32 sim_send_ring_hi_addr_v(u32 r) -{ - return (r >> 0) & 0xfffff; -} -static inline u32 sim_send_ring_hi_addr__init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_send_ring_hi_addr__init_f(void) -{ - return 0x0; -} -static inline u32 sim_send_ring_hi_addr__prod_v(void) -{ - return 0x00000000; -} -static inline u32 sim_send_ring_hi_addr__prod_f(void) -{ - return 0x0; -} -static inline u32 sim_send_put_r(void) -{ - return 0x00000008; -} -static inline u32 sim_send_put_pointer_s(void) -{ - return 29; -} -static inline u32 sim_send_put_pointer_f(u32 v) -{ - return (v & 0x1fffffff) << 3; -} -static inline u32 sim_send_put_pointer_m(void) -{ - return 0x1fffffff << 3; -} -static inline u32 sim_send_put_pointer_v(u32 r) -{ - return (r >> 3) & 0x1fffffff; -} -static inline u32 sim_send_get_r(void) -{ - return 0x0000000c; -} -static inline u32 sim_send_get_pointer_s(void) -{ - return 29; -} -static inline u32 sim_send_get_pointer_f(u32 v) -{ - return (v & 0x1fffffff) << 3; -} -static inline u32 sim_send_get_pointer_m(void) -{ - return 0x1fffffff << 3; -} -static inline u32 sim_send_get_pointer_v(u32 r) -{ - return (r >> 3) & 0x1fffffff; -} -static inline u32 sim_recv_ring_r(void) -{ - return 0x00000010; -} -static inline u32 sim_recv_ring_target_s(void) -{ - return 2; -} -static inline u32 sim_recv_ring_target_f(u32 v) -{ - return (v & 0x3) << 0; -} -static inline u32 sim_recv_ring_target_m(void) -{ - return 0x3 << 0; -} -static inline u32 sim_recv_ring_target_v(u32 r) -{ - return (r >> 0) & 0x3; -} -static inline u32 sim_recv_ring_target_phys_init_v(void) -{ - return 0x00000001; -} -static inline u32 sim_recv_ring_target_phys_init_f(void) -{ - return 0x1; -} -static inline u32 sim_recv_ring_target_phys__init_v(void) -{ - return 0x00000001; -} -static inline u32 sim_recv_ring_target_phys__init_f(void) -{ - return 0x1; -} -static inline u32 sim_recv_ring_target_phys__prod_v(void) -{ - return 0x00000001; -} -static inline u32 sim_recv_ring_target_phys__prod_f(void) -{ - return 0x1; -} -static inline u32 sim_recv_ring_target_phys_nvm_v(void) -{ - return 0x00000001; -} -static inline u32 sim_recv_ring_target_phys_nvm_f(void) -{ - return 0x1; -} -static inline u32 sim_recv_ring_target_phys_pci_v(void) -{ - return 0x00000002; -} -static inline u32 sim_recv_ring_target_phys_pci_f(void) -{ - return 0x2; -} -static inline u32 sim_recv_ring_target_phys_pci_coherent_v(void) -{ - return 0x00000003; -} -static inline u32 sim_recv_ring_target_phys_pci_coherent_f(void) -{ - return 0x3; -} -static inline u32 sim_recv_ring_status_s(void) -{ - return 1; -} -static inline u32 sim_recv_ring_status_f(u32 v) -{ - return (v & 0x1) << 3; -} -static inline u32 sim_recv_ring_status_m(void) -{ - return 0x1 << 3; -} -static inline u32 sim_recv_ring_status_v(u32 r) -{ - return (r >> 3) & 0x1; -} -static inline u32 sim_recv_ring_status_init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_recv_ring_status_init_f(void) -{ - return 0x0; -} -static inline u32 sim_recv_ring_status__init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_recv_ring_status__init_f(void) -{ - return 0x0; -} -static inline u32 sim_recv_ring_status__prod_v(void) -{ - return 0x00000000; -} -static inline u32 sim_recv_ring_status__prod_f(void) -{ - return 0x0; -} -static inline u32 sim_recv_ring_status_invalid_v(void) -{ - return 0x00000000; -} -static inline u32 sim_recv_ring_status_invalid_f(void) -{ - return 0x0; -} -static inline u32 sim_recv_ring_status_valid_v(void) -{ - return 0x00000001; -} -static inline u32 sim_recv_ring_status_valid_f(void) -{ - return 0x8; -} -static inline u32 sim_recv_ring_size_s(void) -{ - return 2; -} -static inline u32 sim_recv_ring_size_f(u32 v) -{ - return (v & 0x3) << 4; -} -static inline u32 sim_recv_ring_size_m(void) -{ - return 0x3 << 4; -} -static inline u32 sim_recv_ring_size_v(u32 r) -{ - return (r >> 4) & 0x3; -} -static inline u32 sim_recv_ring_size_init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_recv_ring_size_init_f(void) -{ - return 0x0; -} -static inline u32 sim_recv_ring_size__init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_recv_ring_size__init_f(void) -{ - return 0x0; -} -static inline u32 sim_recv_ring_size__prod_v(void) -{ - return 0x00000000; -} -static inline u32 sim_recv_ring_size__prod_f(void) -{ - return 0x0; -} -static inline u32 sim_recv_ring_size_4kb_v(void) -{ - return 0x00000000; -} -static inline u32 sim_recv_ring_size_4kb_f(void) -{ - return 0x0; -} -static inline u32 sim_recv_ring_size_8kb_v(void) -{ - return 0x00000001; -} -static inline u32 sim_recv_ring_size_8kb_f(void) -{ - return 0x10; -} -static inline u32 sim_recv_ring_size_12kb_v(void) -{ - return 0x00000002; -} -static inline u32 sim_recv_ring_size_12kb_f(void) -{ - return 0x20; -} -static inline u32 sim_recv_ring_size_16kb_v(void) -{ - return 0x00000003; -} -static inline u32 sim_recv_ring_size_16kb_f(void) -{ - return 0x30; -} -static inline u32 sim_recv_ring_gp_in_ring_s(void) -{ - return 1; -} -static inline u32 sim_recv_ring_gp_in_ring_f(u32 v) -{ - return (v & 0x1) << 11; -} -static inline u32 sim_recv_ring_gp_in_ring_m(void) -{ - return 0x1 << 11; -} -static inline u32 sim_recv_ring_gp_in_ring_v(u32 r) -{ - return (r >> 11) & 0x1; -} -static inline u32 sim_recv_ring_gp_in_ring__init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_recv_ring_gp_in_ring__init_f(void) -{ - return 0x0; -} -static inline u32 sim_recv_ring_gp_in_ring__prod_v(void) -{ - return 0x00000000; -} -static inline u32 sim_recv_ring_gp_in_ring__prod_f(void) -{ - return 0x0; -} -static inline u32 sim_recv_ring_gp_in_ring_no_v(void) -{ - return 0x00000000; -} -static inline u32 sim_recv_ring_gp_in_ring_no_f(void) -{ - return 0x0; -} -static inline u32 sim_recv_ring_gp_in_ring_yes_v(void) -{ - return 0x00000001; -} -static inline u32 sim_recv_ring_gp_in_ring_yes_f(void) -{ - return 0x800; -} -static inline u32 sim_recv_ring_addr_lo_s(void) -{ - return 20; -} -static inline u32 sim_recv_ring_addr_lo_f(u32 v) -{ - return (v & 0xfffff) << 12; -} -static inline u32 sim_recv_ring_addr_lo_m(void) -{ - return 0xfffff << 12; -} -static inline u32 sim_recv_ring_addr_lo_v(u32 r) -{ - return (r >> 12) & 0xfffff; -} -static inline u32 sim_recv_ring_addr_lo__init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_recv_ring_addr_lo__init_f(void) -{ - return 0x0; -} -static inline u32 sim_recv_ring_addr_lo__prod_v(void) -{ - return 0x00000000; -} -static inline u32 sim_recv_ring_addr_lo__prod_f(void) -{ - return 0x0; -} -static inline u32 sim_recv_ring_hi_r(void) -{ - return 0x00000014; -} -static inline u32 sim_recv_ring_hi_addr_s(void) -{ - return 20; -} -static inline u32 sim_recv_ring_hi_addr_f(u32 v) -{ - return (v & 0xfffff) << 0; -} -static inline u32 sim_recv_ring_hi_addr_m(void) -{ - return 0xfffff << 0; -} -static inline u32 sim_recv_ring_hi_addr_v(u32 r) -{ - return (r >> 0) & 0xfffff; -} -static inline u32 sim_recv_ring_hi_addr__init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_recv_ring_hi_addr__init_f(void) -{ - return 0x0; -} -static inline u32 sim_recv_ring_hi_addr__prod_v(void) -{ - return 0x00000000; -} -static inline u32 sim_recv_ring_hi_addr__prod_f(void) -{ - return 0x0; -} -static inline u32 sim_recv_put_r(void) -{ - return 0x00000018; -} -static inline u32 sim_recv_put_pointer_s(void) -{ - return 11; -} -static inline u32 sim_recv_put_pointer_f(u32 v) -{ - return (v & 0x7ff) << 3; -} -static inline u32 sim_recv_put_pointer_m(void) -{ - return 0x7ff << 3; -} -static inline u32 sim_recv_put_pointer_v(u32 r) -{ - return (r >> 3) & 0x7ff; -} -static inline u32 sim_recv_get_r(void) -{ - return 0x0000001c; -} -static inline u32 sim_recv_get_pointer_s(void) -{ - return 11; -} -static inline u32 sim_recv_get_pointer_f(u32 v) -{ - return (v & 0x7ff) << 3; -} -static inline u32 sim_recv_get_pointer_m(void) -{ - return 0x7ff << 3; -} -static inline u32 sim_recv_get_pointer_v(u32 r) -{ - return (r >> 3) & 0x7ff; -} -static inline u32 sim_config_r(void) -{ - return 0x00000020; -} -static inline u32 sim_config_mode_s(void) -{ - return 1; -} -static inline u32 sim_config_mode_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 sim_config_mode_m(void) -{ - return 0x1 << 0; -} -static inline u32 sim_config_mode_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 sim_config_mode_disabled_v(void) -{ - return 0x00000000; -} -static inline u32 sim_config_mode_disabled_f(void) -{ - return 0x0; -} -static inline u32 sim_config_mode_enabled_v(void) -{ - return 0x00000001; -} -static inline u32 sim_config_mode_enabled_f(void) -{ - return 0x1; -} -static inline u32 sim_config_channels_s(void) -{ - return 7; -} -static inline u32 sim_config_channels_f(u32 v) -{ - return (v & 0x7f) << 1; -} -static inline u32 sim_config_channels_m(void) -{ - return 0x7f << 1; -} -static inline u32 sim_config_channels_v(u32 r) -{ - return (r >> 1) & 0x7f; -} -static inline u32 sim_config_channels_none_v(void) -{ - return 0x00000000; -} -static inline u32 sim_config_channels_none_f(void) -{ - return 0x0; -} -static inline u32 sim_config_cached_only_s(void) -{ - return 1; -} -static inline u32 sim_config_cached_only_f(u32 v) -{ - return (v & 0x1) << 8; -} -static inline u32 sim_config_cached_only_m(void) -{ - return 0x1 << 8; -} -static inline u32 sim_config_cached_only_v(u32 r) -{ - return (r >> 8) & 0x1; -} -static inline u32 sim_config_cached_only_disabled_v(void) -{ - return 0x00000000; -} -static inline u32 sim_config_cached_only_disabled_f(void) -{ - return 0x0; -} -static inline u32 sim_config_cached_only_enabled_v(void) -{ - return 0x00000001; -} -static inline u32 sim_config_cached_only_enabled_f(void) -{ - return 0x100; -} -static inline u32 sim_config_validity_s(void) -{ - return 2; -} -static inline u32 sim_config_validity_f(u32 v) -{ - return (v & 0x3) << 9; -} -static inline u32 sim_config_validity_m(void) -{ - return 0x3 << 9; -} -static inline u32 sim_config_validity_v(u32 r) -{ - return (r >> 9) & 0x3; -} -static inline u32 sim_config_validity__init_v(void) -{ - return 0x00000001; -} -static inline u32 sim_config_validity__init_f(void) -{ - return 0x200; -} -static inline u32 sim_config_validity_valid_v(void) -{ - return 0x00000001; -} -static inline u32 sim_config_validity_valid_f(void) -{ - return 0x200; -} -static inline u32 sim_config_simulation_s(void) -{ - return 2; -} -static inline u32 sim_config_simulation_f(u32 v) -{ - return (v & 0x3) << 12; -} -static inline u32 sim_config_simulation_m(void) -{ - return 0x3 << 12; -} -static inline u32 sim_config_simulation_v(u32 r) -{ - return (r >> 12) & 0x3; -} -static inline u32 sim_config_simulation_disabled_v(void) -{ - return 0x00000000; -} -static inline u32 sim_config_simulation_disabled_f(void) -{ - return 0x0; -} -static inline u32 sim_config_simulation_fmodel_v(void) -{ - return 0x00000001; -} -static inline u32 sim_config_simulation_fmodel_f(void) -{ - return 0x1000; -} -static inline u32 sim_config_simulation_rtlsim_v(void) -{ - return 0x00000002; -} -static inline u32 sim_config_simulation_rtlsim_f(void) -{ - return 0x2000; -} -static inline u32 sim_config_secondary_display_s(void) -{ - return 1; -} -static inline u32 sim_config_secondary_display_f(u32 v) -{ - return (v & 0x1) << 14; -} -static inline u32 sim_config_secondary_display_m(void) -{ - return 0x1 << 14; -} -static inline u32 sim_config_secondary_display_v(u32 r) -{ - return (r >> 14) & 0x1; -} -static inline u32 sim_config_secondary_display_disabled_v(void) -{ - return 0x00000000; -} -static inline u32 sim_config_secondary_display_disabled_f(void) -{ - return 0x0; -} -static inline u32 sim_config_secondary_display_enabled_v(void) -{ - return 0x00000001; -} -static inline u32 sim_config_secondary_display_enabled_f(void) -{ - return 0x4000; -} -static inline u32 sim_config_num_heads_s(void) -{ - return 8; -} -static inline u32 sim_config_num_heads_f(u32 v) -{ - return (v & 0xff) << 17; -} -static inline u32 sim_config_num_heads_m(void) -{ - return 0xff << 17; -} -static inline u32 sim_config_num_heads_v(u32 r) -{ - return (r >> 17) & 0xff; -} -static inline u32 sim_event_ring_r(void) -{ - return 0x00000030; -} -static inline u32 sim_event_ring_target_s(void) -{ - return 2; -} -static inline u32 sim_event_ring_target_f(u32 v) -{ - return (v & 0x3) << 0; -} -static inline u32 sim_event_ring_target_m(void) -{ - return 0x3 << 0; -} -static inline u32 sim_event_ring_target_v(u32 r) -{ - return (r >> 0) & 0x3; -} -static inline u32 sim_event_ring_target_phys_init_v(void) -{ - return 0x00000001; -} -static inline u32 sim_event_ring_target_phys_init_f(void) -{ - return 0x1; -} -static inline u32 sim_event_ring_target_phys__init_v(void) -{ - return 0x00000001; -} -static inline u32 sim_event_ring_target_phys__init_f(void) -{ - return 0x1; -} -static inline u32 sim_event_ring_target_phys__prod_v(void) -{ - return 0x00000001; -} -static inline u32 sim_event_ring_target_phys__prod_f(void) -{ - return 0x1; -} -static inline u32 sim_event_ring_target_phys_nvm_v(void) -{ - return 0x00000001; -} -static inline u32 sim_event_ring_target_phys_nvm_f(void) -{ - return 0x1; -} -static inline u32 sim_event_ring_target_phys_pci_v(void) -{ - return 0x00000002; -} -static inline u32 sim_event_ring_target_phys_pci_f(void) -{ - return 0x2; -} -static inline u32 sim_event_ring_target_phys_pci_coherent_v(void) -{ - return 0x00000003; -} -static inline u32 sim_event_ring_target_phys_pci_coherent_f(void) -{ - return 0x3; -} -static inline u32 sim_event_ring_status_s(void) -{ - return 1; -} -static inline u32 sim_event_ring_status_f(u32 v) -{ - return (v & 0x1) << 3; -} -static inline u32 sim_event_ring_status_m(void) -{ - return 0x1 << 3; -} -static inline u32 sim_event_ring_status_v(u32 r) -{ - return (r >> 3) & 0x1; -} -static inline u32 sim_event_ring_status_init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_event_ring_status_init_f(void) -{ - return 0x0; -} -static inline u32 sim_event_ring_status__init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_event_ring_status__init_f(void) -{ - return 0x0; -} -static inline u32 sim_event_ring_status__prod_v(void) -{ - return 0x00000000; -} -static inline u32 sim_event_ring_status__prod_f(void) -{ - return 0x0; -} -static inline u32 sim_event_ring_status_invalid_v(void) -{ - return 0x00000000; -} -static inline u32 sim_event_ring_status_invalid_f(void) -{ - return 0x0; -} -static inline u32 sim_event_ring_status_valid_v(void) -{ - return 0x00000001; -} -static inline u32 sim_event_ring_status_valid_f(void) -{ - return 0x8; -} -static inline u32 sim_event_ring_size_s(void) -{ - return 2; -} -static inline u32 sim_event_ring_size_f(u32 v) -{ - return (v & 0x3) << 4; -} -static inline u32 sim_event_ring_size_m(void) -{ - return 0x3 << 4; -} -static inline u32 sim_event_ring_size_v(u32 r) -{ - return (r >> 4) & 0x3; -} -static inline u32 sim_event_ring_size_init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_event_ring_size_init_f(void) -{ - return 0x0; -} -static inline u32 sim_event_ring_size__init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_event_ring_size__init_f(void) -{ - return 0x0; -} -static inline u32 sim_event_ring_size__prod_v(void) -{ - return 0x00000000; -} -static inline u32 sim_event_ring_size__prod_f(void) -{ - return 0x0; -} -static inline u32 sim_event_ring_size_4kb_v(void) -{ - return 0x00000000; -} -static inline u32 sim_event_ring_size_4kb_f(void) -{ - return 0x0; -} -static inline u32 sim_event_ring_size_8kb_v(void) -{ - return 0x00000001; -} -static inline u32 sim_event_ring_size_8kb_f(void) -{ - return 0x10; -} -static inline u32 sim_event_ring_size_12kb_v(void) -{ - return 0x00000002; -} -static inline u32 sim_event_ring_size_12kb_f(void) -{ - return 0x20; -} -static inline u32 sim_event_ring_size_16kb_v(void) -{ - return 0x00000003; -} -static inline u32 sim_event_ring_size_16kb_f(void) -{ - return 0x30; -} -static inline u32 sim_event_ring_gp_in_ring_s(void) -{ - return 1; -} -static inline u32 sim_event_ring_gp_in_ring_f(u32 v) -{ - return (v & 0x1) << 11; -} -static inline u32 sim_event_ring_gp_in_ring_m(void) -{ - return 0x1 << 11; -} -static inline u32 sim_event_ring_gp_in_ring_v(u32 r) -{ - return (r >> 11) & 0x1; -} -static inline u32 sim_event_ring_gp_in_ring__init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_event_ring_gp_in_ring__init_f(void) -{ - return 0x0; -} -static inline u32 sim_event_ring_gp_in_ring__prod_v(void) -{ - return 0x00000000; -} -static inline u32 sim_event_ring_gp_in_ring__prod_f(void) -{ - return 0x0; -} -static inline u32 sim_event_ring_gp_in_ring_no_v(void) -{ - return 0x00000000; -} -static inline u32 sim_event_ring_gp_in_ring_no_f(void) -{ - return 0x0; -} -static inline u32 sim_event_ring_gp_in_ring_yes_v(void) -{ - return 0x00000001; -} -static inline u32 sim_event_ring_gp_in_ring_yes_f(void) -{ - return 0x800; -} -static inline u32 sim_event_ring_addr_lo_s(void) -{ - return 20; -} -static inline u32 sim_event_ring_addr_lo_f(u32 v) -{ - return (v & 0xfffff) << 12; -} -static inline u32 sim_event_ring_addr_lo_m(void) -{ - return 0xfffff << 12; -} -static inline u32 sim_event_ring_addr_lo_v(u32 r) -{ - return (r >> 12) & 0xfffff; -} -static inline u32 sim_event_ring_addr_lo__init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_event_ring_addr_lo__init_f(void) -{ - return 0x0; -} -static inline u32 sim_event_ring_addr_lo__prod_v(void) -{ - return 0x00000000; -} -static inline u32 sim_event_ring_addr_lo__prod_f(void) -{ - return 0x0; -} -static inline u32 sim_event_ring_hi_v(void) -{ - return 0x00000034; -} -static inline u32 sim_event_ring_hi_addr_s(void) -{ - return 20; -} -static inline u32 sim_event_ring_hi_addr_f(u32 v) -{ - return (v & 0xfffff) << 0; -} -static inline u32 sim_event_ring_hi_addr_m(void) -{ - return 0xfffff << 0; -} -static inline u32 sim_event_ring_hi_addr_v(u32 r) -{ - return (r >> 0) & 0xfffff; -} -static inline u32 sim_event_ring_hi_addr__init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_event_ring_hi_addr__init_f(void) -{ - return 0x0; -} -static inline u32 sim_event_ring_hi_addr__prod_v(void) -{ - return 0x00000000; -} -static inline u32 sim_event_ring_hi_addr__prod_f(void) -{ - return 0x0; -} -static inline u32 sim_event_put_r(void) -{ - return 0x00000038; -} -static inline u32 sim_event_put_pointer_s(void) -{ - return 30; -} -static inline u32 sim_event_put_pointer_f(u32 v) -{ - return (v & 0x3fffffff) << 2; -} -static inline u32 sim_event_put_pointer_m(void) -{ - return 0x3fffffff << 2; -} -static inline u32 sim_event_put_pointer_v(u32 r) -{ - return (r >> 2) & 0x3fffffff; -} -static inline u32 sim_event_get_r(void) -{ - return 0x0000003c; -} -static inline u32 sim_event_get_pointer_s(void) -{ - return 30; -} -static inline u32 sim_event_get_pointer_f(u32 v) -{ - return (v & 0x3fffffff) << 2; -} -static inline u32 sim_event_get_pointer_m(void) -{ - return 0x3fffffff << 2; -} -static inline u32 sim_event_get_pointer_v(u32 r) -{ - return (r >> 2) & 0x3fffffff; -} -static inline u32 sim_status_r(void) -{ - return 0x00000028; -} -static inline u32 sim_status_send_put_s(void) -{ - return 1; -} -static inline u32 sim_status_send_put_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 sim_status_send_put_m(void) -{ - return 0x1 << 0; -} -static inline u32 sim_status_send_put_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 sim_status_send_put__init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_status_send_put__init_f(void) -{ - return 0x0; -} -static inline u32 sim_status_send_put_idle_v(void) -{ - return 0x00000000; -} -static inline u32 sim_status_send_put_idle_f(void) -{ - return 0x0; -} -static inline u32 sim_status_send_put_pending_v(void) -{ - return 0x00000001; -} -static inline u32 sim_status_send_put_pending_f(void) -{ - return 0x1; -} -static inline u32 sim_status_send_get_s(void) -{ - return 1; -} -static inline u32 sim_status_send_get_f(u32 v) -{ - return (v & 0x1) << 1; -} -static inline u32 sim_status_send_get_m(void) -{ - return 0x1 << 1; -} -static inline u32 sim_status_send_get_v(u32 r) -{ - return (r >> 1) & 0x1; -} -static inline u32 sim_status_send_get__init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_status_send_get__init_f(void) -{ - return 0x0; -} -static inline u32 sim_status_send_get_idle_v(void) -{ - return 0x00000000; -} -static inline u32 sim_status_send_get_idle_f(void) -{ - return 0x0; -} -static inline u32 sim_status_send_get_pending_v(void) -{ - return 0x00000001; -} -static inline u32 sim_status_send_get_pending_f(void) -{ - return 0x2; -} -static inline u32 sim_status_send_get_clear_v(void) -{ - return 0x00000001; -} -static inline u32 sim_status_send_get_clear_f(void) -{ - return 0x2; -} -static inline u32 sim_status_recv_put_s(void) -{ - return 1; -} -static inline u32 sim_status_recv_put_f(u32 v) -{ - return (v & 0x1) << 2; -} -static inline u32 sim_status_recv_put_m(void) -{ - return 0x1 << 2; -} -static inline u32 sim_status_recv_put_v(u32 r) -{ - return (r >> 2) & 0x1; -} -static inline u32 sim_status_recv_put__init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_status_recv_put__init_f(void) -{ - return 0x0; -} -static inline u32 sim_status_recv_put_idle_v(void) -{ - return 0x00000000; -} -static inline u32 sim_status_recv_put_idle_f(void) -{ - return 0x0; -} -static inline u32 sim_status_recv_put_pending_v(void) -{ - return 0x00000001; -} -static inline u32 sim_status_recv_put_pending_f(void) -{ - return 0x4; -} -static inline u32 sim_status_recv_put_clear_v(void) -{ - return 0x00000001; -} -static inline u32 sim_status_recv_put_clear_f(void) -{ - return 0x4; -} -static inline u32 sim_status_recv_get_s(void) -{ - return 1; -} -static inline u32 sim_status_recv_get_f(u32 v) -{ - return (v & 0x1) << 3; -} -static inline u32 sim_status_recv_get_m(void) -{ - return 0x1 << 3; -} -static inline u32 sim_status_recv_get_v(u32 r) -{ - return (r >> 3) & 0x1; -} -static inline u32 sim_status_recv_get__init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_status_recv_get__init_f(void) -{ - return 0x0; -} -static inline u32 sim_status_recv_get_idle_v(void) -{ - return 0x00000000; -} -static inline u32 sim_status_recv_get_idle_f(void) -{ - return 0x0; -} -static inline u32 sim_status_recv_get_pending_v(void) -{ - return 0x00000001; -} -static inline u32 sim_status_recv_get_pending_f(void) -{ - return 0x8; -} -static inline u32 sim_status_event_put_s(void) -{ - return 1; -} -static inline u32 sim_status_event_put_f(u32 v) -{ - return (v & 0x1) << 4; -} -static inline u32 sim_status_event_put_m(void) -{ - return 0x1 << 4; -} -static inline u32 sim_status_event_put_v(u32 r) -{ - return (r >> 4) & 0x1; -} -static inline u32 sim_status_event_put__init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_status_event_put__init_f(void) -{ - return 0x0; -} -static inline u32 sim_status_event_put_idle_v(void) -{ - return 0x00000000; -} -static inline u32 sim_status_event_put_idle_f(void) -{ - return 0x0; -} -static inline u32 sim_status_event_put_pending_v(void) -{ - return 0x00000001; -} -static inline u32 sim_status_event_put_pending_f(void) -{ - return 0x10; -} -static inline u32 sim_status_event_put_clear_v(void) -{ - return 0x00000001; -} -static inline u32 sim_status_event_put_clear_f(void) -{ - return 0x10; -} -static inline u32 sim_status_event_get_s(void) -{ - return 1; -} -static inline u32 sim_status_event_get_f(u32 v) -{ - return (v & 0x1) << 5; -} -static inline u32 sim_status_event_get_m(void) -{ - return 0x1 << 5; -} -static inline u32 sim_status_event_get_v(u32 r) -{ - return (r >> 5) & 0x1; -} -static inline u32 sim_status_event_get__init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_status_event_get__init_f(void) -{ - return 0x0; -} -static inline u32 sim_status_event_get_idle_v(void) -{ - return 0x00000000; -} -static inline u32 sim_status_event_get_idle_f(void) -{ - return 0x0; -} -static inline u32 sim_status_event_get_pending_v(void) -{ - return 0x00000001; -} -static inline u32 sim_status_event_get_pending_f(void) -{ - return 0x20; -} -static inline u32 sim_control_r(void) -{ - return 0x0000002c; -} -static inline u32 sim_control_send_put_s(void) -{ - return 1; -} -static inline u32 sim_control_send_put_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 sim_control_send_put_m(void) -{ - return 0x1 << 0; -} -static inline u32 sim_control_send_put_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 sim_control_send_put__init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_control_send_put__init_f(void) -{ - return 0x0; -} -static inline u32 sim_control_send_put_disabled_v(void) -{ - return 0x00000000; -} -static inline u32 sim_control_send_put_disabled_f(void) -{ - return 0x0; -} -static inline u32 sim_control_send_put_enabled_v(void) -{ - return 0x00000001; -} -static inline u32 sim_control_send_put_enabled_f(void) -{ - return 0x1; -} -static inline u32 sim_control_send_get_s(void) -{ - return 1; -} -static inline u32 sim_control_send_get_f(u32 v) -{ - return (v & 0x1) << 1; -} -static inline u32 sim_control_send_get_m(void) -{ - return 0x1 << 1; -} -static inline u32 sim_control_send_get_v(u32 r) -{ - return (r >> 1) & 0x1; -} -static inline u32 sim_control_send_get__init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_control_send_get__init_f(void) -{ - return 0x0; -} -static inline u32 sim_control_send_get_disabled_v(void) -{ - return 0x00000000; -} -static inline u32 sim_control_send_get_disabled_f(void) -{ - return 0x0; -} -static inline u32 sim_control_send_get_enabled_v(void) -{ - return 0x00000001; -} -static inline u32 sim_control_send_get_enabled_f(void) -{ - return 0x2; -} -static inline u32 sim_control_recv_put_s(void) -{ - return 1; -} -static inline u32 sim_control_recv_put_f(u32 v) -{ - return (v & 0x1) << 2; -} -static inline u32 sim_control_recv_put_m(void) -{ - return 0x1 << 2; -} -static inline u32 sim_control_recv_put_v(u32 r) -{ - return (r >> 2) & 0x1; -} -static inline u32 sim_control_recv_put__init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_control_recv_put__init_f(void) -{ - return 0x0; -} -static inline u32 sim_control_recv_put_disabled_v(void) -{ - return 0x00000000; -} -static inline u32 sim_control_recv_put_disabled_f(void) -{ - return 0x0; -} -static inline u32 sim_control_recv_put_enabled_v(void) -{ - return 0x00000001; -} -static inline u32 sim_control_recv_put_enabled_f(void) -{ - return 0x4; -} -static inline u32 sim_control_recv_get_s(void) -{ - return 1; -} -static inline u32 sim_control_recv_get_f(u32 v) -{ - return (v & 0x1) << 3; -} -static inline u32 sim_control_recv_get_m(void) -{ - return 0x1 << 3; -} -static inline u32 sim_control_recv_get_v(u32 r) -{ - return (r >> 3) & 0x1; -} -static inline u32 sim_control_recv_get__init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_control_recv_get__init_f(void) -{ - return 0x0; -} -static inline u32 sim_control_recv_get_disabled_v(void) -{ - return 0x00000000; -} -static inline u32 sim_control_recv_get_disabled_f(void) -{ - return 0x0; -} -static inline u32 sim_control_recv_get_enabled_v(void) -{ - return 0x00000001; -} -static inline u32 sim_control_recv_get_enabled_f(void) -{ - return 0x8; -} -static inline u32 sim_control_event_put_s(void) -{ - return 1; -} -static inline u32 sim_control_event_put_f(u32 v) -{ - return (v & 0x1) << 4; -} -static inline u32 sim_control_event_put_m(void) -{ - return 0x1 << 4; -} -static inline u32 sim_control_event_put_v(u32 r) -{ - return (r >> 4) & 0x1; -} -static inline u32 sim_control_event_put__init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_control_event_put__init_f(void) -{ - return 0x0; -} -static inline u32 sim_control_event_put_disabled_v(void) -{ - return 0x00000000; -} -static inline u32 sim_control_event_put_disabled_f(void) -{ - return 0x0; -} -static inline u32 sim_control_event_put_enabled_v(void) -{ - return 0x00000001; -} -static inline u32 sim_control_event_put_enabled_f(void) -{ - return 0x10; -} -static inline u32 sim_control_event_get_s(void) -{ - return 1; -} -static inline u32 sim_control_event_get_f(u32 v) -{ - return (v & 0x1) << 5; -} -static inline u32 sim_control_event_get_m(void) -{ - return 0x1 << 5; -} -static inline u32 sim_control_event_get_v(u32 r) -{ - return (r >> 5) & 0x1; -} -static inline u32 sim_control_event_get__init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_control_event_get__init_f(void) -{ - return 0x0; -} -static inline u32 sim_control_event_get_disabled_v(void) -{ - return 0x00000000; -} -static inline u32 sim_control_event_get_disabled_f(void) -{ - return 0x0; -} -static inline u32 sim_control_event_get_enabled_v(void) -{ - return 0x00000001; -} -static inline u32 sim_control_event_get_enabled_f(void) -{ - return 0x20; -} -static inline u32 sim_dma_r(void) -{ - return 0x00000000; -} -static inline u32 sim_dma_target_s(void) -{ - return 2; -} -static inline u32 sim_dma_target_f(u32 v) -{ - return (v & 0x3) << 0; -} -static inline u32 sim_dma_target_m(void) -{ - return 0x3 << 0; -} -static inline u32 sim_dma_target_v(u32 r) -{ - return (r >> 0) & 0x3; -} -static inline u32 sim_dma_target_phys_init_v(void) -{ - return 0x00000001; -} -static inline u32 sim_dma_target_phys_init_f(void) -{ - return 0x1; -} -static inline u32 sim_dma_target_phys__init_v(void) -{ - return 0x00000001; -} -static inline u32 sim_dma_target_phys__init_f(void) -{ - return 0x1; -} -static inline u32 sim_dma_target_phys__prod_v(void) -{ - return 0x00000001; -} -static inline u32 sim_dma_target_phys__prod_f(void) -{ - return 0x1; -} -static inline u32 sim_dma_target_phys_nvm_v(void) -{ - return 0x00000001; -} -static inline u32 sim_dma_target_phys_nvm_f(void) -{ - return 0x1; -} -static inline u32 sim_dma_target_phys_pci_v(void) -{ - return 0x00000002; -} -static inline u32 sim_dma_target_phys_pci_f(void) -{ - return 0x2; -} -static inline u32 sim_dma_target_phys_pci_coherent_v(void) -{ - return 0x00000003; -} -static inline u32 sim_dma_target_phys_pci_coherent_f(void) -{ - return 0x3; -} -static inline u32 sim_dma_status_s(void) -{ - return 1; -} -static inline u32 sim_dma_status_f(u32 v) -{ - return (v & 0x1) << 3; -} -static inline u32 sim_dma_status_m(void) -{ - return 0x1 << 3; -} -static inline u32 sim_dma_status_v(u32 r) -{ - return (r >> 3) & 0x1; -} -static inline u32 sim_dma_status_init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_dma_status_init_f(void) -{ - return 0x0; -} -static inline u32 sim_dma_status__init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_dma_status__init_f(void) -{ - return 0x0; -} -static inline u32 sim_dma_status__prod_v(void) -{ - return 0x00000000; -} -static inline u32 sim_dma_status__prod_f(void) -{ - return 0x0; -} -static inline u32 sim_dma_status_invalid_v(void) -{ - return 0x00000000; -} -static inline u32 sim_dma_status_invalid_f(void) -{ - return 0x0; -} -static inline u32 sim_dma_status_valid_v(void) -{ - return 0x00000001; -} -static inline u32 sim_dma_status_valid_f(void) -{ - return 0x8; -} -static inline u32 sim_dma_size_s(void) -{ - return 2; -} -static inline u32 sim_dma_size_f(u32 v) -{ - return (v & 0x3) << 4; -} -static inline u32 sim_dma_size_m(void) -{ - return 0x3 << 4; -} -static inline u32 sim_dma_size_v(u32 r) -{ - return (r >> 4) & 0x3; -} -static inline u32 sim_dma_size_init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_dma_size_init_f(void) -{ - return 0x0; -} -static inline u32 sim_dma_size__init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_dma_size__init_f(void) -{ - return 0x0; -} -static inline u32 sim_dma_size__prod_v(void) -{ - return 0x00000000; -} -static inline u32 sim_dma_size__prod_f(void) -{ - return 0x0; -} -static inline u32 sim_dma_size_4kb_v(void) -{ - return 0x00000000; -} -static inline u32 sim_dma_size_4kb_f(void) -{ - return 0x0; -} -static inline u32 sim_dma_size_8kb_v(void) -{ - return 0x00000001; -} -static inline u32 sim_dma_size_8kb_f(void) -{ - return 0x10; -} -static inline u32 sim_dma_size_12kb_v(void) -{ - return 0x00000002; -} -static inline u32 sim_dma_size_12kb_f(void) -{ - return 0x20; -} -static inline u32 sim_dma_size_16kb_v(void) -{ - return 0x00000003; -} -static inline u32 sim_dma_size_16kb_f(void) -{ - return 0x30; -} -static inline u32 sim_dma_addr_lo_s(void) -{ - return 20; -} -static inline u32 sim_dma_addr_lo_f(u32 v) -{ - return (v & 0xfffff) << 12; -} -static inline u32 sim_dma_addr_lo_m(void) -{ - return 0xfffff << 12; -} -static inline u32 sim_dma_addr_lo_v(u32 r) -{ - return (r >> 12) & 0xfffff; -} -static inline u32 sim_dma_addr_lo__init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_dma_addr_lo__init_f(void) -{ - return 0x0; -} -static inline u32 sim_dma_addr_lo__prod_v(void) -{ - return 0x00000000; -} -static inline u32 sim_dma_addr_lo__prod_f(void) -{ - return 0x0; -} -static inline u32 sim_dma_hi_r(void) -{ - return 0x00000004; -} -static inline u32 sim_dma_hi_addr_s(void) -{ - return 20; -} -static inline u32 sim_dma_hi_addr_f(u32 v) -{ - return (v & 0xfffff) << 0; -} -static inline u32 sim_dma_hi_addr_m(void) -{ - return 0xfffff << 0; -} -static inline u32 sim_dma_hi_addr_v(u32 r) -{ - return (r >> 0) & 0xfffff; -} -static inline u32 sim_dma_hi_addr__init_v(void) -{ - return 0x00000000; -} -static inline u32 sim_dma_hi_addr__init_f(void) -{ - return 0x0; -} -static inline u32 sim_dma_hi_addr__prod_v(void) -{ - return 0x00000000; -} -static inline u32 sim_dma_hi_addr__prod_f(void) -{ - return 0x0; -} -static inline u32 sim_msg_signature_r(void) -{ - return 0x00000000; -} -static inline u32 sim_msg_signature_valid_v(void) -{ - return 0x43505256; -} -static inline u32 sim_msg_length_r(void) -{ - return 0x00000004; -} -static inline u32 sim_msg_function_r(void) -{ - return 0x00000008; -} -static inline u32 sim_msg_function_sim_escape_read_v(void) -{ - return 0x00000023; -} -static inline u32 sim_msg_function_sim_escape_write_v(void) -{ - return 0x00000024; -} -static inline u32 sim_msg_result_r(void) -{ - return 0x0000000c; -} -static inline u32 sim_msg_result_success_v(void) -{ - return 0x00000000; -} -static inline u32 sim_msg_result_rpc_pending_v(void) -{ - return 0xFFFFFFFF; -} -static inline u32 sim_msg_sequence_r(void) -{ - return 0x00000010; -} -static inline u32 sim_msg_spare_r(void) -{ - return 0x00000014; -} -static inline u32 sim_msg_spare__init_v(void) -{ - return 0x00000000; -} - -#endif /* __hw_sim__ */ diff --git a/include/nvgpu/hw_sim_pci.h b/include/nvgpu/hw_sim_pci.h deleted file mode 100644 index 32dbeb4..0000000 --- a/include/nvgpu/hw_sim_pci.h +++ /dev/null @@ -1,2169 +0,0 @@ -/* - * Copyright (c) 2012-2018, NVIDIA Corporation. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - - /* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ - -#ifndef __hw_sim_pci_h__ -#define __hw_sim_pci_h__ -/*This file is autogenerated. Do not edit. */ - -static inline u32 sim_r(void) -{ - return 0x0008f000U; -} -static inline u32 sim_send_ring_r(void) -{ - return 0x00000000U; -} -static inline u32 sim_send_ring_target_s(void) -{ - return 2U; -} -static inline u32 sim_send_ring_target_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 sim_send_ring_target_m(void) -{ - return 0x3U << 0U; -} -static inline u32 sim_send_ring_target_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 sim_send_ring_target_phys_init_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_send_ring_target_phys_init_f(void) -{ - return 0x1U; -} -static inline u32 sim_send_ring_target_phys__init_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_send_ring_target_phys__init_f(void) -{ - return 0x1U; -} -static inline u32 sim_send_ring_target_phys__prod_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_send_ring_target_phys__prod_f(void) -{ - return 0x1U; -} -static inline u32 sim_send_ring_target_phys_nvm_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_send_ring_target_phys_nvm_f(void) -{ - return 0x1U; -} -static inline u32 sim_send_ring_target_phys_pci_v(void) -{ - return 0x00000002U; -} -static inline u32 sim_send_ring_target_phys_pci_f(void) -{ - return 0x2U; -} -static inline u32 sim_send_ring_target_phys_pci_coherent_v(void) -{ - return 0x00000003U; -} -static inline u32 sim_send_ring_target_phys_pci_coherent_f(void) -{ - return 0x3U; -} -static inline u32 sim_send_ring_status_s(void) -{ - return 1U; -} -static inline u32 sim_send_ring_status_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 sim_send_ring_status_m(void) -{ - return 0x1U << 3U; -} -static inline u32 sim_send_ring_status_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 sim_send_ring_status_init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_send_ring_status_init_f(void) -{ - return 0x0U; -} -static inline u32 sim_send_ring_status__init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_send_ring_status__init_f(void) -{ - return 0x0U; -} -static inline u32 sim_send_ring_status__prod_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_send_ring_status__prod_f(void) -{ - return 0x0U; -} -static inline u32 sim_send_ring_status_invalid_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_send_ring_status_invalid_f(void) -{ - return 0x0U; -} -static inline u32 sim_send_ring_status_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_send_ring_status_valid_f(void) -{ - return 0x8U; -} -static inline u32 sim_send_ring_size_s(void) -{ - return 2U; -} -static inline u32 sim_send_ring_size_f(u32 v) -{ - return (v & 0x3U) << 4U; -} -static inline u32 sim_send_ring_size_m(void) -{ - return 0x3U << 4U; -} -static inline u32 sim_send_ring_size_v(u32 r) -{ - return (r >> 4U) & 0x3U; -} -static inline u32 sim_send_ring_size_init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_send_ring_size_init_f(void) -{ - return 0x0U; -} -static inline u32 sim_send_ring_size__init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_send_ring_size__init_f(void) -{ - return 0x0U; -} -static inline u32 sim_send_ring_size__prod_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_send_ring_size__prod_f(void) -{ - return 0x0U; -} -static inline u32 sim_send_ring_size_4kb_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_send_ring_size_4kb_f(void) -{ - return 0x0U; -} -static inline u32 sim_send_ring_size_8kb_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_send_ring_size_8kb_f(void) -{ - return 0x10U; -} -static inline u32 sim_send_ring_size_12kb_v(void) -{ - return 0x00000002U; -} -static inline u32 sim_send_ring_size_12kb_f(void) -{ - return 0x20U; -} -static inline u32 sim_send_ring_size_16kb_v(void) -{ - return 0x00000003U; -} -static inline u32 sim_send_ring_size_16kb_f(void) -{ - return 0x30U; -} -static inline u32 sim_send_ring_gp_in_ring_s(void) -{ - return 1U; -} -static inline u32 sim_send_ring_gp_in_ring_f(u32 v) -{ - return (v & 0x1) << 11U; -} -static inline u32 sim_send_ring_gp_in_ring_m(void) -{ - return 0x1 << 11U; -} -static inline u32 sim_send_ring_gp_in_ring_v(u32 r) -{ - return (r >> 11) & 0x1U; -} -static inline u32 sim_send_ring_gp_in_ring__init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_send_ring_gp_in_ring__init_f(void) -{ - return 0x0U; -} -static inline u32 sim_send_ring_gp_in_ring__prod_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_send_ring_gp_in_ring__prod_f(void) -{ - return 0x0U; -} -static inline u32 sim_send_ring_gp_in_ring_no_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_send_ring_gp_in_ring_no_f(void) -{ - return 0x0U; -} -static inline u32 sim_send_ring_gp_in_ring_yes_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_send_ring_gp_in_ring_yes_f(void) -{ - return 0x800U; -} -static inline u32 sim_send_ring_addr_lo_s(void) -{ - return 20U; -} -static inline u32 sim_send_ring_addr_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 sim_send_ring_addr_lo_m(void) -{ - return 0xfffffU << 12U; -} -static inline u32 sim_send_ring_addr_lo_v(u32 r) -{ - return (r >> 12U) & 0xfffffU; -} -static inline u32 sim_send_ring_addr_lo__init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_send_ring_addr_lo__init_f(void) -{ - return 0x0U; -} -static inline u32 sim_send_ring_addr_lo__prod_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_send_ring_addr_lo__prod_f(void) -{ - return 0x0U; -} -static inline u32 sim_send_ring_hi_r(void) -{ - return 0x00000004U; -} -static inline u32 sim_send_ring_hi_addr_s(void) -{ - return 20U; -} -static inline u32 sim_send_ring_hi_addr_f(u32 v) -{ - return (v & 0xfffffU) << 0U; -} -static inline u32 sim_send_ring_hi_addr_m(void) -{ - return 0xfffffU << 0U; -} -static inline u32 sim_send_ring_hi_addr_v(u32 r) -{ - return (r >> 0U) & 0xfffffU; -} -static inline u32 sim_send_ring_hi_addr__init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_send_ring_hi_addr__init_f(void) -{ - return 0x0U; -} -static inline u32 sim_send_ring_hi_addr__prod_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_send_ring_hi_addr__prod_f(void) -{ - return 0x0U; -} -static inline u32 sim_send_put_r(void) -{ - return 0x00000008U; -} -static inline u32 sim_send_put_pointer_s(void) -{ - return 29U; -} -static inline u32 sim_send_put_pointer_f(u32 v) -{ - return (v & 0x1fffffffU) << 3U; -} -static inline u32 sim_send_put_pointer_m(void) -{ - return 0x1fffffffU << 3U; -} -static inline u32 sim_send_put_pointer_v(u32 r) -{ - return (r >> 3U) & 0x1fffffffU; -} -static inline u32 sim_send_get_r(void) -{ - return 0x0000000cU; -} -static inline u32 sim_send_get_pointer_s(void) -{ - return 29U; -} -static inline u32 sim_send_get_pointer_f(u32 v) -{ - return (v & 0x1fffffffU) << 3U; -} -static inline u32 sim_send_get_pointer_m(void) -{ - return 0x1fffffffU << 3U; -} -static inline u32 sim_send_get_pointer_v(u32 r) -{ - return (r >> 3U) & 0x1fffffffU; -} -static inline u32 sim_recv_ring_r(void) -{ - return 0x00000010U; -} -static inline u32 sim_recv_ring_target_s(void) -{ - return 2U; -} -static inline u32 sim_recv_ring_target_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 sim_recv_ring_target_m(void) -{ - return 0x3U << 0U; -} -static inline u32 sim_recv_ring_target_v(u32 r) -{ - return (r >> 0) & 0x3U; -} -static inline u32 sim_recv_ring_target_phys_init_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_recv_ring_target_phys_init_f(void) -{ - return 0x1U; -} -static inline u32 sim_recv_ring_target_phys__init_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_recv_ring_target_phys__init_f(void) -{ - return 0x1U; -} -static inline u32 sim_recv_ring_target_phys__prod_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_recv_ring_target_phys__prod_f(void) -{ - return 0x1U; -} -static inline u32 sim_recv_ring_target_phys_nvm_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_recv_ring_target_phys_nvm_f(void) -{ - return 0x1U; -} -static inline u32 sim_recv_ring_target_phys_pci_v(void) -{ - return 0x00000002U; -} -static inline u32 sim_recv_ring_target_phys_pci_f(void) -{ - return 0x2U; -} -static inline u32 sim_recv_ring_target_phys_pci_coherent_v(void) -{ - return 0x00000003U; -} -static inline u32 sim_recv_ring_target_phys_pci_coherent_f(void) -{ - return 0x3U; -} -static inline u32 sim_recv_ring_status_s(void) -{ - return 1U; -} -static inline u32 sim_recv_ring_status_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 sim_recv_ring_status_m(void) -{ - return 0x1U << 3U; -} -static inline u32 sim_recv_ring_status_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 sim_recv_ring_status_init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_recv_ring_status_init_f(void) -{ - return 0x0U; -} -static inline u32 sim_recv_ring_status__init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_recv_ring_status__init_f(void) -{ - return 0x0U; -} -static inline u32 sim_recv_ring_status__prod_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_recv_ring_status__prod_f(void) -{ - return 0x0U; -} -static inline u32 sim_recv_ring_status_invalid_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_recv_ring_status_invalid_f(void) -{ - return 0x0U; -} -static inline u32 sim_recv_ring_status_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_recv_ring_status_valid_f(void) -{ - return 0x8U; -} -static inline u32 sim_recv_ring_size_s(void) -{ - return 2U; -} -static inline u32 sim_recv_ring_size_f(u32 v) -{ - return (v & 0x3U) << 4U; -} -static inline u32 sim_recv_ring_size_m(void) -{ - return 0x3U << 4U; -} -static inline u32 sim_recv_ring_size_v(u32 r) -{ - return (r >> 4U) & 0x3U; -} -static inline u32 sim_recv_ring_size_init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_recv_ring_size_init_f(void) -{ - return 0x0U; -} -static inline u32 sim_recv_ring_size__init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_recv_ring_size__init_f(void) -{ - return 0x0U; -} -static inline u32 sim_recv_ring_size__prod_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_recv_ring_size__prod_f(void) -{ - return 0x0U; -} -static inline u32 sim_recv_ring_size_4kb_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_recv_ring_size_4kb_f(void) -{ - return 0x0U; -} -static inline u32 sim_recv_ring_size_8kb_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_recv_ring_size_8kb_f(void) -{ - return 0x10U; -} -static inline u32 sim_recv_ring_size_12kb_v(void) -{ - return 0x00000002U; -} -static inline u32 sim_recv_ring_size_12kb_f(void) -{ - return 0x20U; -} -static inline u32 sim_recv_ring_size_16kb_v(void) -{ - return 0x00000003U; -} -static inline u32 sim_recv_ring_size_16kb_f(void) -{ - return 0x30U; -} -static inline u32 sim_recv_ring_gp_in_ring_s(void) -{ - return 1U; -} -static inline u32 sim_recv_ring_gp_in_ring_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 sim_recv_ring_gp_in_ring_m(void) -{ - return 0x1U << 11U; -} -static inline u32 sim_recv_ring_gp_in_ring_v(u32 r) -{ - return (r >> 11U) & 0x1U; -} -static inline u32 sim_recv_ring_gp_in_ring__init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_recv_ring_gp_in_ring__init_f(void) -{ - return 0x0U; -} -static inline u32 sim_recv_ring_gp_in_ring__prod_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_recv_ring_gp_in_ring__prod_f(void) -{ - return 0x0U; -} -static inline u32 sim_recv_ring_gp_in_ring_no_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_recv_ring_gp_in_ring_no_f(void) -{ - return 0x0U; -} -static inline u32 sim_recv_ring_gp_in_ring_yes_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_recv_ring_gp_in_ring_yes_f(void) -{ - return 0x800U; -} -static inline u32 sim_recv_ring_addr_lo_s(void) -{ - return 20U; -} -static inline u32 sim_recv_ring_addr_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 sim_recv_ring_addr_lo_m(void) -{ - return 0xfffffU << 12U; -} -static inline u32 sim_recv_ring_addr_lo_v(u32 r) -{ - return (r >> 12U) & 0xfffffU; -} -static inline u32 sim_recv_ring_addr_lo__init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_recv_ring_addr_lo__init_f(void) -{ - return 0x0U; -} -static inline u32 sim_recv_ring_addr_lo__prod_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_recv_ring_addr_lo__prod_f(void) -{ - return 0x0U; -} -static inline u32 sim_recv_ring_hi_r(void) -{ - return 0x00000014U; -} -static inline u32 sim_recv_ring_hi_addr_s(void) -{ - return 20U; -} -static inline u32 sim_recv_ring_hi_addr_f(u32 v) -{ - return (v & 0xfffffU) << 0U; -} -static inline u32 sim_recv_ring_hi_addr_m(void) -{ - return 0xfffffU << 0U; -} -static inline u32 sim_recv_ring_hi_addr_v(u32 r) -{ - return (r >> 0U) & 0xfffffU; -} -static inline u32 sim_recv_ring_hi_addr__init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_recv_ring_hi_addr__init_f(void) -{ - return 0x0U; -} -static inline u32 sim_recv_ring_hi_addr__prod_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_recv_ring_hi_addr__prod_f(void) -{ - return 0x0U; -} -static inline u32 sim_recv_put_r(void) -{ - return 0x00000018U; -} -static inline u32 sim_recv_put_pointer_s(void) -{ - return 11U; -} -static inline u32 sim_recv_put_pointer_f(u32 v) -{ - return (v & 0x7ffU) << 3U; -} -static inline u32 sim_recv_put_pointer_m(void) -{ - return 0x7ffU << 3U; -} -static inline u32 sim_recv_put_pointer_v(u32 r) -{ - return (r >> 3U) & 0x7ffU; -} -static inline u32 sim_recv_get_r(void) -{ - return 0x0000001cU; -} -static inline u32 sim_recv_get_pointer_s(void) -{ - return 11U; -} -static inline u32 sim_recv_get_pointer_f(u32 v) -{ - return (v & 0x7ffU) << 3U; -} -static inline u32 sim_recv_get_pointer_m(void) -{ - return 0x7ffU << 3U; -} -static inline u32 sim_recv_get_pointer_v(u32 r) -{ - return (r >> 3U) & 0x7ffU; -} -static inline u32 sim_config_r(void) -{ - return 0x00000020U; -} -static inline u32 sim_config_mode_s(void) -{ - return 1U; -} -static inline u32 sim_config_mode_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 sim_config_mode_m(void) -{ - return 0x1U << 0U; -} -static inline u32 sim_config_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 sim_config_mode_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_config_mode_disabled_f(void) -{ - return 0x0U; -} -static inline u32 sim_config_mode_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_config_mode_enabled_f(void) -{ - return 0x1U; -} -static inline u32 sim_config_channels_s(void) -{ - return 7U; -} -static inline u32 sim_config_channels_f(u32 v) -{ - return (v & 0x7fU) << 1U; -} -static inline u32 sim_config_channels_m(void) -{ - return 0x7fU << 1U; -} -static inline u32 sim_config_channels_v(u32 r) -{ - return (r >> 1U) & 0x7fU; -} -static inline u32 sim_config_channels_none_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_config_channels_none_f(void) -{ - return 0x0U; -} -static inline u32 sim_config_cached_only_s(void) -{ - return 1U; -} -static inline u32 sim_config_cached_only_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 sim_config_cached_only_m(void) -{ - return 0x1U << 8U; -} -static inline u32 sim_config_cached_only_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 sim_config_cached_only_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_config_cached_only_disabled_f(void) -{ - return 0x0U; -} -static inline u32 sim_config_cached_only_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_config_cached_only_enabled_f(void) -{ - return 0x100U; -} -static inline u32 sim_config_validity_s(void) -{ - return 2U; -} -static inline u32 sim_config_validity_f(u32 v) -{ - return (v & 0x3U) << 9U; -} -static inline u32 sim_config_validity_m(void) -{ - return 0x3U << 9U; -} -static inline u32 sim_config_validity_v(u32 r) -{ - return (r >> 9U) & 0x3U; -} -static inline u32 sim_config_validity__init_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_config_validity__init_f(void) -{ - return 0x200U; -} -static inline u32 sim_config_validity_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_config_validity_valid_f(void) -{ - return 0x200U; -} -static inline u32 sim_config_simulation_s(void) -{ - return 2U; -} -static inline u32 sim_config_simulation_f(u32 v) -{ - return (v & 0x3U) << 12U; -} -static inline u32 sim_config_simulation_m(void) -{ - return 0x3U << 12U; -} -static inline u32 sim_config_simulation_v(u32 r) -{ - return (r >> 12U) & 0x3U; -} -static inline u32 sim_config_simulation_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_config_simulation_disabled_f(void) -{ - return 0x0U; -} -static inline u32 sim_config_simulation_fmodel_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_config_simulation_fmodel_f(void) -{ - return 0x1000U; -} -static inline u32 sim_config_simulation_rtlsim_v(void) -{ - return 0x00000002U; -} -static inline u32 sim_config_simulation_rtlsim_f(void) -{ - return 0x2000U; -} -static inline u32 sim_config_secondary_display_s(void) -{ - return 1U; -} -static inline u32 sim_config_secondary_display_f(u32 v) -{ - return (v & 0x1U) << 14U; -} -static inline u32 sim_config_secondary_display_m(void) -{ - return 0x1U << 14U; -} -static inline u32 sim_config_secondary_display_v(u32 r) -{ - return (r >> 14U) & 0x1U; -} -static inline u32 sim_config_secondary_display_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_config_secondary_display_disabled_f(void) -{ - return 0x0U; -} -static inline u32 sim_config_secondary_display_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_config_secondary_display_enabled_f(void) -{ - return 0x4000U; -} -static inline u32 sim_config_num_heads_s(void) -{ - return 8U; -} -static inline u32 sim_config_num_heads_f(u32 v) -{ - return (v & 0xffU) << 17U; -} -static inline u32 sim_config_num_heads_m(void) -{ - return 0xffU << 17U; -} -static inline u32 sim_config_num_heads_v(u32 r) -{ - return (r >> 17U) & 0xffU; -} -static inline u32 sim_event_ring_r(void) -{ - return 0x00000030U; -} -static inline u32 sim_event_ring_target_s(void) -{ - return 2U; -} -static inline u32 sim_event_ring_target_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 sim_event_ring_target_m(void) -{ - return 0x3U << 0U; -} -static inline u32 sim_event_ring_target_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 sim_event_ring_target_phys_init_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_event_ring_target_phys_init_f(void) -{ - return 0x1U; -} -static inline u32 sim_event_ring_target_phys__init_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_event_ring_target_phys__init_f(void) -{ - return 0x1U; -} -static inline u32 sim_event_ring_target_phys__prod_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_event_ring_target_phys__prod_f(void) -{ - return 0x1U; -} -static inline u32 sim_event_ring_target_phys_nvm_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_event_ring_target_phys_nvm_f(void) -{ - return 0x1U; -} -static inline u32 sim_event_ring_target_phys_pci_v(void) -{ - return 0x00000002U; -} -static inline u32 sim_event_ring_target_phys_pci_f(void) -{ - return 0x2U; -} -static inline u32 sim_event_ring_target_phys_pci_coherent_v(void) -{ - return 0x00000003U; -} -static inline u32 sim_event_ring_target_phys_pci_coherent_f(void) -{ - return 0x3U; -} -static inline u32 sim_event_ring_status_s(void) -{ - return 1U; -} -static inline u32 sim_event_ring_status_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 sim_event_ring_status_m(void) -{ - return 0x1U << 3U; -} -static inline u32 sim_event_ring_status_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 sim_event_ring_status_init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_event_ring_status_init_f(void) -{ - return 0x0U; -} -static inline u32 sim_event_ring_status__init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_event_ring_status__init_f(void) -{ - return 0x0U; -} -static inline u32 sim_event_ring_status__prod_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_event_ring_status__prod_f(void) -{ - return 0x0U; -} -static inline u32 sim_event_ring_status_invalid_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_event_ring_status_invalid_f(void) -{ - return 0x0U; -} -static inline u32 sim_event_ring_status_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_event_ring_status_valid_f(void) -{ - return 0x8U; -} -static inline u32 sim_event_ring_size_s(void) -{ - return 2U; -} -static inline u32 sim_event_ring_size_f(u32 v) -{ - return (v & 0x3U) << 4U; -} -static inline u32 sim_event_ring_size_m(void) -{ - return 0x3U << 4U; -} -static inline u32 sim_event_ring_size_v(u32 r) -{ - return (r >> 4U) & 0x3U; -} -static inline u32 sim_event_ring_size_init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_event_ring_size_init_f(void) -{ - return 0x0U; -} -static inline u32 sim_event_ring_size__init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_event_ring_size__init_f(void) -{ - return 0x0U; -} -static inline u32 sim_event_ring_size__prod_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_event_ring_size__prod_f(void) -{ - return 0x0U; -} -static inline u32 sim_event_ring_size_4kb_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_event_ring_size_4kb_f(void) -{ - return 0x0U; -} -static inline u32 sim_event_ring_size_8kb_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_event_ring_size_8kb_f(void) -{ - return 0x10U; -} -static inline u32 sim_event_ring_size_12kb_v(void) -{ - return 0x00000002U; -} -static inline u32 sim_event_ring_size_12kb_f(void) -{ - return 0x20U; -} -static inline u32 sim_event_ring_size_16kb_v(void) -{ - return 0x00000003U; -} -static inline u32 sim_event_ring_size_16kb_f(void) -{ - return 0x30U; -} -static inline u32 sim_event_ring_gp_in_ring_s(void) -{ - return 1U; -} -static inline u32 sim_event_ring_gp_in_ring_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 sim_event_ring_gp_in_ring_m(void) -{ - return 0x1U << 11U; -} -static inline u32 sim_event_ring_gp_in_ring_v(u32 r) -{ - return (r >> 11U) & 0x1U; -} -static inline u32 sim_event_ring_gp_in_ring__init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_event_ring_gp_in_ring__init_f(void) -{ - return 0x0U; -} -static inline u32 sim_event_ring_gp_in_ring__prod_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_event_ring_gp_in_ring__prod_f(void) -{ - return 0x0U; -} -static inline u32 sim_event_ring_gp_in_ring_no_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_event_ring_gp_in_ring_no_f(void) -{ - return 0x0U; -} -static inline u32 sim_event_ring_gp_in_ring_yes_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_event_ring_gp_in_ring_yes_f(void) -{ - return 0x800U; -} -static inline u32 sim_event_ring_addr_lo_s(void) -{ - return 20U; -} -static inline u32 sim_event_ring_addr_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 sim_event_ring_addr_lo_m(void) -{ - return 0xfffffU << 12U; -} -static inline u32 sim_event_ring_addr_lo_v(u32 r) -{ - return (r >> 12U) & 0xfffffU; -} -static inline u32 sim_event_ring_addr_lo__init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_event_ring_addr_lo__init_f(void) -{ - return 0x0U; -} -static inline u32 sim_event_ring_addr_lo__prod_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_event_ring_addr_lo__prod_f(void) -{ - return 0x0U; -} -static inline u32 sim_event_ring_hi_v(void) -{ - return 0x00000034U; -} -static inline u32 sim_event_ring_hi_addr_s(void) -{ - return 20U; -} -static inline u32 sim_event_ring_hi_addr_f(u32 v) -{ - return (v & 0xfffffU) << 0U; -} -static inline u32 sim_event_ring_hi_addr_m(void) -{ - return 0xfffffU << 0U; -} -static inline u32 sim_event_ring_hi_addr_v(u32 r) -{ - return (r >> 0U) & 0xfffffU; -} -static inline u32 sim_event_ring_hi_addr__init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_event_ring_hi_addr__init_f(void) -{ - return 0x0U; -} -static inline u32 sim_event_ring_hi_addr__prod_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_event_ring_hi_addr__prod_f(void) -{ - return 0x0U; -} -static inline u32 sim_event_put_r(void) -{ - return 0x00000038U; -} -static inline u32 sim_event_put_pointer_s(void) -{ - return 30U; -} -static inline u32 sim_event_put_pointer_f(u32 v) -{ - return (v & 0x3fffffffU) << 2U; -} -static inline u32 sim_event_put_pointer_m(void) -{ - return 0x3fffffffU << 2U; -} -static inline u32 sim_event_put_pointer_v(u32 r) -{ - return (r >> 2U) & 0x3fffffffU; -} -static inline u32 sim_event_get_r(void) -{ - return 0x0000003cU; -} -static inline u32 sim_event_get_pointer_s(void) -{ - return 30U; -} -static inline u32 sim_event_get_pointer_f(u32 v) -{ - return (v & 0x3fffffffU) << 2U; -} -static inline u32 sim_event_get_pointer_m(void) -{ - return 0x3fffffffU << 2U; -} -static inline u32 sim_event_get_pointer_v(u32 r) -{ - return (r >> 2U) & 0x3fffffffU; -} -static inline u32 sim_status_r(void) -{ - return 0x00000028U; -} -static inline u32 sim_status_send_put_s(void) -{ - return 1U; -} -static inline u32 sim_status_send_put_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 sim_status_send_put_m(void) -{ - return 0x1 << 0U; -} -static inline u32 sim_status_send_put_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 sim_status_send_put__init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_status_send_put__init_f(void) -{ - return 0x0U; -} -static inline u32 sim_status_send_put_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_status_send_put_idle_f(void) -{ - return 0x0U; -} -static inline u32 sim_status_send_put_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_status_send_put_pending_f(void) -{ - return 0x1U; -} -static inline u32 sim_status_send_get_s(void) -{ - return 1U; -} -static inline u32 sim_status_send_get_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 sim_status_send_get_m(void) -{ - return 0x1U << 1U; -} -static inline u32 sim_status_send_get_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 sim_status_send_get__init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_status_send_get__init_f(void) -{ - return 0x0U; -} -static inline u32 sim_status_send_get_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_status_send_get_idle_f(void) -{ - return 0x0U; -} -static inline u32 sim_status_send_get_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_status_send_get_pending_f(void) -{ - return 0x2U; -} -static inline u32 sim_status_send_get_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_status_send_get_clear_f(void) -{ - return 0x2U; -} -static inline u32 sim_status_recv_put_s(void) -{ - return 1U; -} -static inline u32 sim_status_recv_put_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 sim_status_recv_put_m(void) -{ - return 0x1U << 2U; -} -static inline u32 sim_status_recv_put_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 sim_status_recv_put__init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_status_recv_put__init_f(void) -{ - return 0x0U; -} -static inline u32 sim_status_recv_put_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_status_recv_put_idle_f(void) -{ - return 0x0U; -} -static inline u32 sim_status_recv_put_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_status_recv_put_pending_f(void) -{ - return 0x4U; -} -static inline u32 sim_status_recv_put_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_status_recv_put_clear_f(void) -{ - return 0x4U; -} -static inline u32 sim_status_recv_get_s(void) -{ - return 1U; -} -static inline u32 sim_status_recv_get_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 sim_status_recv_get_m(void) -{ - return 0x1U << 3U; -} -static inline u32 sim_status_recv_get_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 sim_status_recv_get__init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_status_recv_get__init_f(void) -{ - return 0x0U; -} -static inline u32 sim_status_recv_get_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_status_recv_get_idle_f(void) -{ - return 0x0U; -} -static inline u32 sim_status_recv_get_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_status_recv_get_pending_f(void) -{ - return 0x8U; -} -static inline u32 sim_status_event_put_s(void) -{ - return 1U; -} -static inline u32 sim_status_event_put_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 sim_status_event_put_m(void) -{ - return 0x1U << 4U; -} -static inline u32 sim_status_event_put_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 sim_status_event_put__init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_status_event_put__init_f(void) -{ - return 0x0U; -} -static inline u32 sim_status_event_put_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_status_event_put_idle_f(void) -{ - return 0x0U; -} -static inline u32 sim_status_event_put_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_status_event_put_pending_f(void) -{ - return 0x10U; -} -static inline u32 sim_status_event_put_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_status_event_put_clear_f(void) -{ - return 0x10U; -} -static inline u32 sim_status_event_get_s(void) -{ - return 1U; -} -static inline u32 sim_status_event_get_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 sim_status_event_get_m(void) -{ - return 0x1U << 5U; -} -static inline u32 sim_status_event_get_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 sim_status_event_get__init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_status_event_get__init_f(void) -{ - return 0x0U; -} -static inline u32 sim_status_event_get_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_status_event_get_idle_f(void) -{ - return 0x0U; -} -static inline u32 sim_status_event_get_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_status_event_get_pending_f(void) -{ - return 0x20U; -} -static inline u32 sim_control_r(void) -{ - return 0x0000002cU; -} -static inline u32 sim_control_send_put_s(void) -{ - return 1U; -} -static inline u32 sim_control_send_put_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 sim_control_send_put_m(void) -{ - return 0x1U << 0U; -} -static inline u32 sim_control_send_put_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 sim_control_send_put__init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_control_send_put__init_f(void) -{ - return 0x0U; -} -static inline u32 sim_control_send_put_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_control_send_put_disabled_f(void) -{ - return 0x0U; -} -static inline u32 sim_control_send_put_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_control_send_put_enabled_f(void) -{ - return 0x1U; -} -static inline u32 sim_control_send_get_s(void) -{ - return 1U; -} -static inline u32 sim_control_send_get_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 sim_control_send_get_m(void) -{ - return 0x1U << 1U; -} -static inline u32 sim_control_send_get_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 sim_control_send_get__init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_control_send_get__init_f(void) -{ - return 0x0U; -} -static inline u32 sim_control_send_get_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_control_send_get_disabled_f(void) -{ - return 0x0U; -} -static inline u32 sim_control_send_get_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_control_send_get_enabled_f(void) -{ - return 0x2U; -} -static inline u32 sim_control_recv_put_s(void) -{ - return 1U; -} -static inline u32 sim_control_recv_put_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 sim_control_recv_put_m(void) -{ - return 0x1U << 2U; -} -static inline u32 sim_control_recv_put_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 sim_control_recv_put__init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_control_recv_put__init_f(void) -{ - return 0x0U; -} -static inline u32 sim_control_recv_put_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_control_recv_put_disabled_f(void) -{ - return 0x0U; -} -static inline u32 sim_control_recv_put_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_control_recv_put_enabled_f(void) -{ - return 0x4U; -} -static inline u32 sim_control_recv_get_s(void) -{ - return 1U; -} -static inline u32 sim_control_recv_get_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 sim_control_recv_get_m(void) -{ - return 0x1U << 3U; -} -static inline u32 sim_control_recv_get_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 sim_control_recv_get__init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_control_recv_get__init_f(void) -{ - return 0x0U; -} -static inline u32 sim_control_recv_get_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_control_recv_get_disabled_f(void) -{ - return 0x0U; -} -static inline u32 sim_control_recv_get_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_control_recv_get_enabled_f(void) -{ - return 0x8U; -} -static inline u32 sim_control_event_put_s(void) -{ - return 1U; -} -static inline u32 sim_control_event_put_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 sim_control_event_put_m(void) -{ - return 0x1U << 4U; -} -static inline u32 sim_control_event_put_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 sim_control_event_put__init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_control_event_put__init_f(void) -{ - return 0x0U; -} -static inline u32 sim_control_event_put_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_control_event_put_disabled_f(void) -{ - return 0x0U; -} -static inline u32 sim_control_event_put_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_control_event_put_enabled_f(void) -{ - return 0x10U; -} -static inline u32 sim_control_event_get_s(void) -{ - return 1U; -} -static inline u32 sim_control_event_get_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 sim_control_event_get_m(void) -{ - return 0x1U << 5U; -} -static inline u32 sim_control_event_get_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 sim_control_event_get__init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_control_event_get__init_f(void) -{ - return 0x0U; -} -static inline u32 sim_control_event_get_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_control_event_get_disabled_f(void) -{ - return 0x0U; -} -static inline u32 sim_control_event_get_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_control_event_get_enabled_f(void) -{ - return 0x20U; -} -static inline u32 sim_dma_r(void) -{ - return 0x00000000U; -} -static inline u32 sim_dma_target_s(void) -{ - return 2U; -} -static inline u32 sim_dma_target_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 sim_dma_target_m(void) -{ - return 0x3U << 0U; -} -static inline u32 sim_dma_target_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 sim_dma_target_phys_init_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_dma_target_phys_init_f(void) -{ - return 0x1U; -} -static inline u32 sim_dma_target_phys__init_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_dma_target_phys__init_f(void) -{ - return 0x1U; -} -static inline u32 sim_dma_target_phys__prod_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_dma_target_phys__prod_f(void) -{ - return 0x1U; -} -static inline u32 sim_dma_target_phys_nvm_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_dma_target_phys_nvm_f(void) -{ - return 0x1U; -} -static inline u32 sim_dma_target_phys_pci_v(void) -{ - return 0x00000002U; -} -static inline u32 sim_dma_target_phys_pci_f(void) -{ - return 0x2U; -} -static inline u32 sim_dma_target_phys_pci_coherent_v(void) -{ - return 0x00000003U; -} -static inline u32 sim_dma_target_phys_pci_coherent_f(void) -{ - return 0x3U; -} -static inline u32 sim_dma_status_s(void) -{ - return 1U; -} -static inline u32 sim_dma_status_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 sim_dma_status_m(void) -{ - return 0x1U << 3U; -} -static inline u32 sim_dma_status_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 sim_dma_status_init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_dma_status_init_f(void) -{ - return 0x0U; -} -static inline u32 sim_dma_status__init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_dma_status__init_f(void) -{ - return 0x0U; -} -static inline u32 sim_dma_status__prod_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_dma_status__prod_f(void) -{ - return 0x0U; -} -static inline u32 sim_dma_status_invalid_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_dma_status_invalid_f(void) -{ - return 0x0U; -} -static inline u32 sim_dma_status_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_dma_status_valid_f(void) -{ - return 0x8U; -} -static inline u32 sim_dma_size_s(void) -{ - return 2U; -} -static inline u32 sim_dma_size_f(u32 v) -{ - return (v & 0x3U) << 4U; -} -static inline u32 sim_dma_size_m(void) -{ - return 0x3U << 4U; -} -static inline u32 sim_dma_size_v(u32 r) -{ - return (r >> 4U) & 0x3U; -} -static inline u32 sim_dma_size_init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_dma_size_init_f(void) -{ - return 0x0U; -} -static inline u32 sim_dma_size__init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_dma_size__init_f(void) -{ - return 0x0U; -} -static inline u32 sim_dma_size__prod_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_dma_size__prod_f(void) -{ - return 0x0U; -} -static inline u32 sim_dma_size_4kb_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_dma_size_4kb_f(void) -{ - return 0x0U; -} -static inline u32 sim_dma_size_8kb_v(void) -{ - return 0x00000001U; -} -static inline u32 sim_dma_size_8kb_f(void) -{ - return 0x10U; -} -static inline u32 sim_dma_size_12kb_v(void) -{ - return 0x00000002U; -} -static inline u32 sim_dma_size_12kb_f(void) -{ - return 0x20U; -} -static inline u32 sim_dma_size_16kb_v(void) -{ - return 0x00000003U; -} -static inline u32 sim_dma_size_16kb_f(void) -{ - return 0x30U; -} -static inline u32 sim_dma_addr_lo_s(void) -{ - return 20U; -} -static inline u32 sim_dma_addr_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 sim_dma_addr_lo_m(void) -{ - return 0xfffffU << 12U; -} -static inline u32 sim_dma_addr_lo_v(u32 r) -{ - return (r >> 12U) & 0xfffffU; -} -static inline u32 sim_dma_addr_lo__init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_dma_addr_lo__init_f(void) -{ - return 0x0U; -} -static inline u32 sim_dma_addr_lo__prod_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_dma_addr_lo__prod_f(void) -{ - return 0x0U; -} -static inline u32 sim_dma_hi_r(void) -{ - return 0x00000004U; -} -static inline u32 sim_dma_hi_addr_s(void) -{ - return 20U; -} -static inline u32 sim_dma_hi_addr_f(u32 v) -{ - return (v & 0xfffffU) << 0U; -} -static inline u32 sim_dma_hi_addr_m(void) -{ - return 0xfffffU << 0U; -} -static inline u32 sim_dma_hi_addr_v(u32 r) -{ - return (r >> 0U) & 0xfffffU; -} -static inline u32 sim_dma_hi_addr__init_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_dma_hi_addr__init_f(void) -{ - return 0x0U; -} -static inline u32 sim_dma_hi_addr__prod_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_dma_hi_addr__prod_f(void) -{ - return 0x0U; -} -static inline u32 sim_msg_header_version_r(void) -{ - return 0x00000000U; -} -static inline u32 sim_msg_header_version_major_tot_v(void) -{ - return 0x03000000U; -} -static inline u32 sim_msg_header_version_minor_tot_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_msg_signature_r(void) -{ - return 0x00000004U; -} -static inline u32 sim_msg_signature_valid_v(void) -{ - return 0x43505256U; -} -static inline u32 sim_msg_length_r(void) -{ - return 0x00000008U; -} -static inline u32 sim_msg_function_r(void) -{ - return 0x0000000cU; -} -static inline u32 sim_msg_function_sim_escape_read_v(void) -{ - return 0x00000023U; -} -static inline u32 sim_msg_function_sim_escape_write_v(void) -{ - return 0x00000024U; -} -static inline u32 sim_msg_result_r(void) -{ - return 0x00000010U; -} -static inline u32 sim_msg_result_success_v(void) -{ - return 0x00000000U; -} -static inline u32 sim_msg_result_rpc_pending_v(void) -{ - return 0xFFFFFFFFU; -} -static inline u32 sim_msg_sequence_r(void) -{ - return 0x00000018U; -} -static inline u32 sim_msg_spare_r(void) -{ - return 0x0000001cU; -} -static inline u32 sim_msg_spare__init_v(void) -{ - return 0x00000000U; -} - -#endif /* __hw_sim_pci_h__ */ diff --git a/include/nvgpu/io.h b/include/nvgpu/io.h deleted file mode 100644 index d6cc16e..0000000 --- a/include/nvgpu/io.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_IO_H -#define NVGPU_IO_H - -#include - -/* Legacy defines - should be removed once everybody uses nvgpu_* */ -#define gk20a_writel nvgpu_writel -#define gk20a_readl nvgpu_readl -#define gk20a_writel_check nvgpu_writel_check -#define gk20a_bar1_writel nvgpu_bar1_writel -#define gk20a_bar1_readl nvgpu_bar1_readl -#define gk20a_io_exists nvgpu_io_exists -#define gk20a_io_valid_reg nvgpu_io_valid_reg - -struct gk20a; - -void nvgpu_writel(struct gk20a *g, u32 r, u32 v); -void nvgpu_writel_relaxed(struct gk20a *g, u32 r, u32 v); -u32 nvgpu_readl(struct gk20a *g, u32 r); -u32 __nvgpu_readl(struct gk20a *g, u32 r); -void nvgpu_writel_check(struct gk20a *g, u32 r, u32 v); -void nvgpu_writel_loop(struct gk20a *g, u32 r, u32 v); -void nvgpu_bar1_writel(struct gk20a *g, u32 b, u32 v); -u32 nvgpu_bar1_readl(struct gk20a *g, u32 b); -bool nvgpu_io_exists(struct gk20a *g); -bool nvgpu_io_valid_reg(struct gk20a *g, u32 r); - -#endif /* NVGPU_IO_H */ diff --git a/include/nvgpu/io_usermode.h b/include/nvgpu/io_usermode.h deleted file mode 100644 index f56062b..0000000 --- a/include/nvgpu/io_usermode.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_IO_USERMODE_H -#define NVGPU_IO_USERMODE_H - -void nvgpu_usermode_writel(struct gk20a *g, u32 r, u32 v); - -#endif /* NVGPU_IO_USERMODE_H */ diff --git a/include/nvgpu/kmem.h b/include/nvgpu/kmem.h deleted file mode 100644 index 61f90bf..0000000 --- a/include/nvgpu/kmem.h +++ /dev/null @@ -1,285 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_KMEM_H -#define NVGPU_KMEM_H - -#include -#include - -struct gk20a; - -/* - * When there's other implementations make sure they are included instead of - * Linux when not compiling on Linux! - */ -#ifdef __KERNEL__ -#include -#elif defined(__NVGPU_POSIX__) -#include -#else -#include -#endif - -/** - * DOC: Kmem cache support - * - * In Linux there is support for the notion of a kmem_cache. It gives better - * memory usage characteristics for lots of allocations of the same size. Think - * structs that get allocated over and over. Normal kmalloc() type routines - * typically round to the next power-of-2 since that's easy. - * - * But if we know the size ahead of time the packing for the allocations can be - * much better. This is the benefit of a slab allocator. This type hides the - * underlying kmem_cache (or absense thereof). - */ -struct nvgpu_kmem_cache; - -#ifdef CONFIG_NVGPU_TRACK_MEM_USAGE -/* - * Uncomment this if you want to enable stack traces in the memory profiling. - * Since this is a fairly high overhead operation and is only necessary for - * debugging actual bugs it's left here for developers to enable. - */ -/* #define __NVGPU_SAVE_KALLOC_STACK_TRACES */ - -/* - * Defined per-OS. - */ -struct nvgpu_mem_alloc_tracker; -#endif - - -/** - * nvgpu_kmem_cache_create - create an nvgpu kernel memory cache. - * - * @g The GPU driver struct using this cache. - * @size Size of the object allocated by the cache. - * - * This cache can be used to allocate objects of size @size. Common usage would - * be for a struct that gets allocated a lot. In that case @size should be - * sizeof(struct my_struct). - * - * A given implementation of this need not do anything special. The allocation - * routines can simply be passed on to nvgpu_kzalloc() if desired so packing - * and alignment of the structs cannot be assumed. - */ -struct nvgpu_kmem_cache *nvgpu_kmem_cache_create(struct gk20a *g, size_t size); - -/** - * nvgpu_kmem_cache_destroy - destroy a cache created by - * nvgpu_kmem_cache_create(). - * - * @cache The cache to destroy. - */ -void nvgpu_kmem_cache_destroy(struct nvgpu_kmem_cache *cache); - -/** - * nvgpu_kmem_cache_alloc - Allocate an object from the cache - * - * @cache The cache to alloc from. - */ -void *nvgpu_kmem_cache_alloc(struct nvgpu_kmem_cache *cache); - -/** - * nvgpu_kmem_cache_free - Free an object back to a cache - * - * @cache The cache to return the object to. - * @ptr Pointer to the object to free. - */ -void nvgpu_kmem_cache_free(struct nvgpu_kmem_cache *cache, void *ptr); - -/** - * nvgpu_kmalloc - Allocate from the kernel's allocator. - * - * @g: Current GPU. - * @size: Size of the allocation. - * - * Allocate a chunk of system memory from the kernel. Allocations larger than 1 - * page may fail even when there may appear to be enough memory. - * - * This function may sleep so cannot be used in IRQs. - */ -#define nvgpu_kmalloc(g, size) __nvgpu_kmalloc(g, size, _NVGPU_GET_IP_) - -/** - * nvgpu_kzalloc - Allocate from the kernel's allocator. - * - * @g: Current GPU. - * @size: Size of the allocation. - * - * Identical to nvgpu_kalloc() except the memory will be zeroed before being - * returned. - */ -#define nvgpu_kzalloc(g, size) __nvgpu_kzalloc(g, size, _NVGPU_GET_IP_) - -/** - * nvgpu_kcalloc - Allocate from the kernel's allocator. - * - * @g: Current GPU. - * @n: Number of objects. - * @size: Size of each object. - * - * Identical to nvgpu_kalloc() except the size of the memory chunk returned is - * @n * @size. - */ -#define nvgpu_kcalloc(g, n, size) \ - __nvgpu_kcalloc(g, n, size, _NVGPU_GET_IP_) - -/** - * nvgpu_vmalloc - Allocate memory and return a map to it. - * - * @g: Current GPU. - * @size: Size of the allocation. - * - * Allocate some memory and return a pointer to a virtual memory mapping of - * that memory in the kernel's virtual address space. The underlying physical - * memory is not guaranteed to be contiguous (and indeed likely isn't). This - * allows for much larger allocations to be done without worrying about as much - * about physical memory fragmentation. - * - * This function may sleep. - */ -#define nvgpu_vmalloc(g, size) __nvgpu_vmalloc(g, size, _NVGPU_GET_IP_) - -/** - * nvgpu_vzalloc - Allocate memory and return a map to it. - * - * @g: Current GPU. - * @size: Size of the allocation. - * - * Identical to nvgpu_vmalloc() except this will return zero'ed memory. - */ -#define nvgpu_vzalloc(g, size) __nvgpu_vzalloc(g, size, _NVGPU_GET_IP_) - -/** - * nvgpu_kfree - Frees an alloc from nvgpu_kmalloc, nvgpu_kzalloc, - * nvgpu_kcalloc. - * - * @g: Current GPU. - * @addr: Address of object to free. - */ -#define nvgpu_kfree(g, addr) __nvgpu_kfree(g, addr) - -/** - * nvgpu_vfree - Frees an alloc from nvgpu_vmalloc, nvgpu_vzalloc. - * - * @g: Current GPU. - * @addr: Address of object to free. - */ -#define nvgpu_vfree(g, addr) __nvgpu_vfree(g, addr) - -#define kmem_dbg(g, fmt, args...) \ - nvgpu_log(g, gpu_dbg_kmem, fmt, ##args) - -/** - * nvgpu_kmem_init - Initialize the kmem tracking stuff. - * - *@g: The driver to init. - * - * Returns non-zero on failure. - */ -int nvgpu_kmem_init(struct gk20a *g); - -/** - * nvgpu_kmem_fini - Finalize the kmem tracking code - * - * @g - The GPU. - * @flags - Flags that control operation of this finalization. - * - * Cleanup resources used by nvgpu_kmem. Available flags for cleanup are: - * - * %NVGPU_KMEM_FINI_DO_NOTHING - * %NVGPU_KMEM_FINI_FORCE_CLEANUP - * %NVGPU_KMEM_FINI_DUMP_ALLOCS - * %NVGPU_KMEM_FINI_WARN - * %NVGPU_KMEM_FINI_BUG - * - * %NVGPU_KMEM_FINI_DO_NOTHING will be overridden by anything else specified. - * Put another way don't just add %NVGPU_KMEM_FINI_DO_NOTHING and expect that - * to suppress other flags from doing anything. - */ -void nvgpu_kmem_fini(struct gk20a *g, int flags); - -/* - * These will simply be ignored if CONFIG_NVGPU_TRACK_MEM_USAGE is not defined. - */ -#define NVGPU_KMEM_FINI_DO_NOTHING 0 -#define NVGPU_KMEM_FINI_FORCE_CLEANUP (1 << 0) -#define NVGPU_KMEM_FINI_DUMP_ALLOCS (1 << 1) -#define NVGPU_KMEM_FINI_WARN (1 << 2) -#define NVGPU_KMEM_FINI_BUG (1 << 3) - -/* - * Implemented by the OS interface. - */ -void *__nvgpu_big_alloc(struct gk20a *g, size_t size, bool clear); - -/** - * nvgpu_big_malloc - Pick virtual or physical alloc based on @size - * - * @g - The GPU. - * @size - Size of the allocation. - * - * On some platforms (i.e Linux) it is possible to allocate memory directly - * mapped into the kernel's address space (kmalloc) or allocate discontiguous - * pages which are then mapped into a special kernel address range. Each type - * of allocation has pros and cons. kmalloc() for instance lets you allocate - * small buffers more space efficiently but vmalloc() allows you to successfully - * allocate much larger buffers without worrying about fragmentation as much - * (but will allocate in multiples of page size). - * - * This function aims to provide the right allocation for when buffers are of - * variable size. In some cases the code doesn't know ahead of time if the - * buffer is going to be big or small so this does the check for you and - * provides the right type of memory allocation. - * - * Returns a pointer to a virtual address range that the kernel can access or - * %NULL on failure. - */ -static inline void *nvgpu_big_malloc(struct gk20a *g, size_t size) -{ - return __nvgpu_big_alloc(g, size, false); -} - -/** - * nvgpu_big_malloc - Pick virtual or physical alloc based on @size - * - * @g - The GPU. - * @size - Size of the allocation. - * - * Zeroed memory version of nvgpu_big_malloc(). - */ -static inline void *nvgpu_big_zalloc(struct gk20a *g, size_t size) -{ - return __nvgpu_big_alloc(g, size, true); -} - -/** - * nvgpu_big_free - Free and alloc from nvgpu_big_zalloc() or - * nvgpu_big_malloc(). - * @g - The GPU. - * @p - A pointer allocated by nvgpu_big_zalloc() or nvgpu_big_malloc(). - */ -void nvgpu_big_free(struct gk20a *g, void *p); - -#endif /* NVGPU_KMEM_H */ diff --git a/include/nvgpu/kref.h b/include/nvgpu/kref.h deleted file mode 100644 index 486040e..0000000 --- a/include/nvgpu/kref.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -/* - * The following structure is used for reference counting of objects in nvgpu. - */ -#ifndef NVGPU_KREF_H -#define NVGPU_KREF_H - -#include - -struct nvgpu_ref { - nvgpu_atomic_t refcount; -}; - -/* - * Initialize object. - * @ref: the nvgpu_ref object to initialize - */ -static inline void nvgpu_ref_init(struct nvgpu_ref *ref) -{ - nvgpu_atomic_set(&ref->refcount, 1); -} - -/* - * Increment reference count for the object - * @ref: the nvgpu_ref object - */ -static inline void nvgpu_ref_get(struct nvgpu_ref *ref) -{ - nvgpu_atomic_inc(&ref->refcount); -} - -/* - * Decrement reference count for the object and call release() if it becomes - * zero. - * @ref: the nvgpu_ref object - * @release: pointer to the function that would be invoked to clean up the - * object when the reference count becomes zero, i.e. the last - * reference corresponding to this object is removed. - * Return 1 if object was removed, otherwise return 0. The user should not - * make any assumptions about the status of the object in the memory when - * the function returns 0 and should only use it to know that there are no - * further references to this object. - */ -static inline int nvgpu_ref_put(struct nvgpu_ref *ref, - void (*release)(struct nvgpu_ref *r)) -{ - if (nvgpu_atomic_sub_and_test(1, &ref->refcount)) { - if (release != NULL) { - release(ref); - } - return 1; - } - return 0; -} - -/* - * Increment reference count for the object unless it is zero. - * @ref: the nvgpu_ref object - * Return non-zero if the increment succeeds, Otherwise return 0. - */ -static inline int __must_check nvgpu_ref_get_unless_zero(struct nvgpu_ref *ref) -{ - return nvgpu_atomic_add_unless(&ref->refcount, 1, 0); -} - -#endif /* NVGPU_KREF_H */ diff --git a/include/nvgpu/linux/atomic.h b/include/nvgpu/linux/atomic.h deleted file mode 100644 index 0734672..0000000 --- a/include/nvgpu/linux/atomic.h +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#ifndef __NVGPU_ATOMIC_LINUX_H__ -#define __NVGPU_ATOMIC_LINUX_H__ - -#ifdef __KERNEL__ -#include -#endif - -typedef struct nvgpu_atomic { - atomic_t atomic_var; -} nvgpu_atomic_t; - -typedef struct nvgpu_atomic64 { - atomic64_t atomic_var; -} nvgpu_atomic64_t; - -#define __nvgpu_atomic_init(i) { ATOMIC_INIT(i) } -#define __nvgpu_atomic64_init(i) { ATOMIC64_INIT(i) } - -static inline void __nvgpu_atomic_set(nvgpu_atomic_t *v, int i) -{ - atomic_set(&v->atomic_var, i); -} - -static inline int __nvgpu_atomic_read(nvgpu_atomic_t *v) -{ - return atomic_read(&v->atomic_var); -} - -static inline void __nvgpu_atomic_inc(nvgpu_atomic_t *v) -{ - atomic_inc(&v->atomic_var); -} - -static inline int __nvgpu_atomic_inc_return(nvgpu_atomic_t *v) -{ - return atomic_inc_return(&v->atomic_var); -} - -static inline void __nvgpu_atomic_dec(nvgpu_atomic_t *v) -{ - atomic_dec(&v->atomic_var); -} - -static inline int __nvgpu_atomic_dec_return(nvgpu_atomic_t *v) -{ - return atomic_dec_return(&v->atomic_var); -} - -static inline int __nvgpu_atomic_cmpxchg(nvgpu_atomic_t *v, int old, int new) -{ - return atomic_cmpxchg(&v->atomic_var, old, new); -} - -static inline int __nvgpu_atomic_xchg(nvgpu_atomic_t *v, int new) -{ - return atomic_xchg(&v->atomic_var, new); -} - -static inline bool __nvgpu_atomic_inc_and_test(nvgpu_atomic_t *v) -{ - return atomic_inc_and_test(&v->atomic_var); -} - -static inline bool __nvgpu_atomic_dec_and_test(nvgpu_atomic_t *v) -{ - return atomic_dec_and_test(&v->atomic_var); -} - -static inline bool __nvgpu_atomic_sub_and_test(int i, nvgpu_atomic_t *v) -{ - return atomic_sub_and_test(i, &v->atomic_var); -} - -static inline int __nvgpu_atomic_add_return(int i, nvgpu_atomic_t *v) -{ - return atomic_add_return(i, &v->atomic_var); -} - -static inline int __nvgpu_atomic_add_unless(nvgpu_atomic_t *v, int a, int u) -{ - return atomic_add_unless(&v->atomic_var, a, u); -} - -static inline void __nvgpu_atomic64_set(nvgpu_atomic64_t *v, long i) -{ - atomic64_set(&v->atomic_var, i); -} - -static inline long __nvgpu_atomic64_read(nvgpu_atomic64_t *v) -{ - return atomic64_read(&v->atomic_var); -} - -static inline void __nvgpu_atomic64_add(long x, nvgpu_atomic64_t *v) -{ - atomic64_add(x, &v->atomic_var); -} - -static inline void __nvgpu_atomic64_inc(nvgpu_atomic64_t *v) -{ - atomic64_inc(&v->atomic_var); -} - -static inline long __nvgpu_atomic64_inc_return(nvgpu_atomic64_t *v) -{ - return atomic64_inc_return(&v->atomic_var); -} - -static inline void __nvgpu_atomic64_dec(nvgpu_atomic64_t *v) -{ - atomic64_dec(&v->atomic_var); -} - -static inline void __nvgpu_atomic64_dec_return(nvgpu_atomic64_t *v) -{ - atomic64_dec_return(&v->atomic_var); -} - -static inline long __nvgpu_atomic64_cmpxchg(nvgpu_atomic64_t *v, - long old, long new) -{ - return atomic64_cmpxchg(&v->atomic_var, old, new); -} - -static inline void __nvgpu_atomic64_sub(long x, nvgpu_atomic64_t *v) -{ - atomic64_sub(x, &v->atomic_var); -} - -static inline long __nvgpu_atomic64_sub_return(long x, nvgpu_atomic64_t *v) -{ - return atomic64_sub_return(x, &v->atomic_var); -} -#endif /*__NVGPU_ATOMIC_LINUX_H__ */ diff --git a/include/nvgpu/linux/barrier.h b/include/nvgpu/linux/barrier.h deleted file mode 100644 index ef867c4..0000000 --- a/include/nvgpu/linux/barrier.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef __NVGPU_BARRIER_LINUX_H__ -#define __NVGPU_BARRIER_LINUX_H__ - -#include - -#define __nvgpu_mb() mb() -#define __nvgpu_rmb() rmb() -#define __nvgpu_wmb() wmb() - -#define __nvgpu_smp_mb() smp_mb() -#define __nvgpu_smp_rmb() smp_rmb() -#define __nvgpu_smp_wmb() smp_wmb() - -#define __nvgpu_read_barrier_depends() read_barrier_depends() -#define __nvgpu_smp_read_barrier_depends() smp_read_barrier_depends() - -#define __NV_ACCESS_ONCE(x) ACCESS_ONCE(x) - -#define __nvgpu_speculation_barrier() speculation_barrier() - -#endif /* __NVGPU_BARRIER_LINUX_H__ */ diff --git a/include/nvgpu/linux/cond.h b/include/nvgpu/linux/cond.h deleted file mode 100644 index b53ada3..0000000 --- a/include/nvgpu/linux/cond.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef __NVGPU_COND_LINUX_H__ -#define __NVGPU_COND_LINUX_H__ - -#include -#include - -struct nvgpu_cond { - bool initialized; - wait_queue_head_t wq; -}; - -/** - * NVGPU_COND_WAIT - Wait for a condition to be true - * - * @c - The condition variable to sleep on - * @condition - The condition that needs to be true - * @timeout_ms - Timeout in milliseconds, or 0 for infinite wait - * - * Wait for a condition to become true. Returns -ETIMEOUT if - * the wait timed out with condition false. - */ -#define NVGPU_COND_WAIT(c, condition, timeout_ms) \ -({\ - int ret = 0; \ - long _timeout_ms = timeout_ms;\ - if (_timeout_ms > 0) { \ - long _ret = wait_event_timeout((c)->wq, condition, \ - msecs_to_jiffies(_timeout_ms)); \ - if (_ret == 0) \ - ret = -ETIMEDOUT; \ - } else { \ - wait_event((c)->wq, condition); \ - } \ - ret;\ -}) - -/** - * NVGPU_COND_WAIT_INTERRUPTIBLE - Wait for a condition to be true - * - * @c - The condition variable to sleep on - * @condition - The condition that needs to be true - * @timeout_ms - Timeout in milliseconds, or 0 for infinite wait - * - * Wait for a condition to become true. Returns -ETIMEOUT if - * the wait timed out with condition false or -ERESTARTSYS on - * signal. - */ -#define NVGPU_COND_WAIT_INTERRUPTIBLE(c, condition, timeout_ms) \ -({ \ - int ret = 0; \ - long _timeout_ms = timeout_ms;\ - if (_timeout_ms > 0) { \ - long _ret = wait_event_interruptible_timeout((c)->wq, condition, \ - msecs_to_jiffies(_timeout_ms)); \ - if (_ret == 0) \ - ret = -ETIMEDOUT; \ - else if (_ret == -ERESTARTSYS) \ - ret = -ERESTARTSYS; \ - } else { \ - ret = wait_event_interruptible((c)->wq, condition); \ - } \ - ret; \ -}) - -#endif /* __NVGPU_LOCK_LINUX_H__ */ diff --git a/include/nvgpu/linux/dma.h b/include/nvgpu/linux/dma.h deleted file mode 100644 index 342b278..0000000 --- a/include/nvgpu/linux/dma.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef __NVGPU_LINUX_DMA_H__ -#define __NVGPU_LINUX_DMA_H__ - -/** - * Functions used internally for building the backing SGTs for nvgpu_mems. - */ - - -int nvgpu_get_sgtable_attrs(struct gk20a *g, struct sg_table **sgt, - void *cpuva, u64 iova, - size_t size, unsigned long flags); - -int nvgpu_get_sgtable(struct gk20a *g, struct sg_table **sgt, - void *cpuva, u64 iova, size_t size); - -int nvgpu_get_sgtable_from_pages(struct gk20a *g, struct sg_table **sgt, - struct page **pages, u64 iova, - size_t size); - -void nvgpu_free_sgtable(struct gk20a *g, struct sg_table **sgt); - -#endif diff --git a/include/nvgpu/linux/kmem.h b/include/nvgpu/linux/kmem.h deleted file mode 100644 index 660aac9..0000000 --- a/include/nvgpu/linux/kmem.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef __NVGPU_KMEM_LINUX_H__ -#define __NVGPU_KMEM_LINUX_H__ - -struct gk20a; -struct device; - -#ifdef CONFIG_NVGPU_TRACK_MEM_USAGE -void *__nvgpu_track_vmalloc(struct gk20a *g, unsigned long size, void *ip); -void *__nvgpu_track_vzalloc(struct gk20a *g, unsigned long size, void *ip); -void *__nvgpu_track_kmalloc(struct gk20a *g, size_t size, void *ip); -void *__nvgpu_track_kzalloc(struct gk20a *g, size_t size, void *ip); -void *__nvgpu_track_kcalloc(struct gk20a *g, size_t n, size_t size, void *ip); -void __nvgpu_track_vfree(struct gk20a *g, void *addr); -void __nvgpu_track_kfree(struct gk20a *g, void *addr); -#endif - -/** - * DOC: Linux pass through kmem implementation. - * - * These are the Linux implementations of the various kmem functions defined by - * nvgpu. This should not be included directly - instead include . - */ -void *__nvgpu_kmalloc(struct gk20a *g, size_t size, void *ip); -void *__nvgpu_kzalloc(struct gk20a *g, size_t size, void *ip); -void *__nvgpu_kcalloc(struct gk20a *g, size_t n, size_t size, void *ip); -void *__nvgpu_vmalloc(struct gk20a *g, unsigned long size, void *ip); -void *__nvgpu_vzalloc(struct gk20a *g, unsigned long size, void *ip); -void __nvgpu_kfree(struct gk20a *g, void *addr); -void __nvgpu_vfree(struct gk20a *g, void *addr); - -#endif diff --git a/include/nvgpu/linux/lock.h b/include/nvgpu/linux/lock.h deleted file mode 100644 index fbf26e9..0000000 --- a/include/nvgpu/linux/lock.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef NVGPU_LOCK_LINUX_H -#define NVGPU_LOCK_LINUX_H - -#include -#include - -struct nvgpu_mutex { - struct mutex mutex; -}; -struct nvgpu_spinlock { - spinlock_t spinlock; -}; -struct nvgpu_raw_spinlock { - raw_spinlock_t spinlock; -}; - -static inline int nvgpu_mutex_init(struct nvgpu_mutex *mutex) -{ - mutex_init(&mutex->mutex); - return 0; -}; -static inline void nvgpu_mutex_acquire(struct nvgpu_mutex *mutex) -{ - mutex_lock(&mutex->mutex); -}; -static inline void nvgpu_mutex_release(struct nvgpu_mutex *mutex) -{ - mutex_unlock(&mutex->mutex); -}; -static inline int nvgpu_mutex_tryacquire(struct nvgpu_mutex *mutex) -{ - return mutex_trylock(&mutex->mutex); -}; -static inline void nvgpu_mutex_destroy(struct nvgpu_mutex *mutex) -{ - mutex_destroy(&mutex->mutex); -}; - -static inline void nvgpu_spinlock_init(struct nvgpu_spinlock *spinlock) -{ - spin_lock_init(&spinlock->spinlock); -}; -static inline void nvgpu_spinlock_acquire(struct nvgpu_spinlock *spinlock) -{ - spin_lock(&spinlock->spinlock); -}; -static inline void nvgpu_spinlock_release(struct nvgpu_spinlock *spinlock) -{ - spin_unlock(&spinlock->spinlock); -}; - -static inline void nvgpu_raw_spinlock_init(struct nvgpu_raw_spinlock *spinlock) -{ - raw_spin_lock_init(&spinlock->spinlock); -}; -static inline void nvgpu_raw_spinlock_acquire(struct nvgpu_raw_spinlock *spinlock) -{ - raw_spin_lock(&spinlock->spinlock); -}; -static inline void nvgpu_raw_spinlock_release(struct nvgpu_raw_spinlock *spinlock) -{ - raw_spin_unlock(&spinlock->spinlock); -}; - -#endif /* NVGPU_LOCK_LINUX_H */ diff --git a/include/nvgpu/linux/nvgpu_mem.h b/include/nvgpu/linux/nvgpu_mem.h deleted file mode 100644 index e5f5031..0000000 --- a/include/nvgpu/linux/nvgpu_mem.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef __NVGPU_LINUX_NVGPU_MEM_H__ -#define __NVGPU_LINUX_NVGPU_MEM_H__ - -struct page; -struct sg_table; -struct scatterlist; -struct nvgpu_sgt; - -struct gk20a; -struct nvgpu_mem; -struct nvgpu_gmmu_attrs; - -struct nvgpu_mem_priv { - struct page **pages; - struct sg_table *sgt; - unsigned long flags; -}; - -u64 nvgpu_mem_get_addr_sgl(struct gk20a *g, struct scatterlist *sgl); -struct nvgpu_sgt *nvgpu_mem_linux_sgt_create(struct gk20a *g, - struct sg_table *sgt); -void nvgpu_mem_linux_sgt_free(struct gk20a *g, struct nvgpu_sgt *sgt); -struct nvgpu_sgt *nvgpu_linux_sgt_create(struct gk20a *g, - struct sg_table *sgt); -/** - * __nvgpu_mem_create_from_pages - Create an nvgpu_mem from physical pages. - * - * @g - The GPU. - * @dest - nvgpu_mem to initialize. - * @pages - A list of page pointers. - * @nr_pages - The number of pages in @pages. - * - * Create a new nvgpu_mem struct from a pre-existing list of physical pages. The - * pages need not be contiguous (the underlying scatter gather list will help - * with that). However, note, this API will explicitly make it so that the GMMU - * mapping code bypasses SMMU access for the passed pages. This allows one to - * make mem_descs that describe MMIO regions or other non-DRAM things. - * - * This only works for SYSMEM (or other things like SYSMEM - basically just not - * VIDMEM). Also, this API is only available for Linux as it heavily depends on - * the notion of struct %page. - * - * The resulting nvgpu_mem should be released with the nvgpu_dma_free() or the - * nvgpu_dma_unmap_free() function depending on whether or not the resulting - * nvgpu_mem has been mapped. The underlying pages themselves must be cleaned up - * by the caller of this API. - * - * Returns 0 on success, or a relevant error otherwise. - */ -int __nvgpu_mem_create_from_pages(struct gk20a *g, struct nvgpu_mem *dest, - struct page **pages, int nr_pages); - -/** - * __nvgpu_mem_create_from_phys - Create an nvgpu_mem from physical mem. - * - * @g - The GPU. - * @dest - nvgpu_mem to initialize. - * @src_phys - start address of physical mem - * @nr_pages - The number of pages in phys. - * - * Create a new nvgpu_mem struct from a physical memory aperure. The physical - * memory aperture needs to be contiguous for requested @nr_pages. This API - * only works for SYSMEM. - * - * The resulting nvgpu_mem should be released with the nvgpu_dma_free() or the - * nvgpu_dma_unmap_free() function depending on whether or not the resulting - * nvgpu_mem has been mapped. - * - * Returns 0 on success, or a relevant error otherwise. - */ -int __nvgpu_mem_create_from_phys(struct gk20a *g, struct nvgpu_mem *dest, - u64 src_phys, int nr_pages); -#endif diff --git a/include/nvgpu/linux/nvlink.h b/include/nvgpu/linux/nvlink.h deleted file mode 100644 index 550a897..0000000 --- a/include/nvgpu/linux/nvlink.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NVGPU_LINUX_NVLINK_H__ -#define __NVGPU_LINUX_NVLINK_H__ - -#ifdef CONFIG_TEGRA_NVLINK -#include -#include -#endif - -#endif diff --git a/include/nvgpu/linux/os_fence_android.h b/include/nvgpu/linux/os_fence_android.h deleted file mode 100644 index 201b530..0000000 --- a/include/nvgpu/linux/os_fence_android.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NVGPU_OS_FENCE_ANDROID_H__ -#define __NVGPU_OS_FENCE_ANDROID_H__ - -struct gk20a; -struct nvgpu_os_fence; -struct sync_fence; -struct channel_gk20a; - -struct sync_fence *nvgpu_get_sync_fence(struct nvgpu_os_fence *s); - -void nvgpu_os_fence_android_drop_ref(struct nvgpu_os_fence *s); - -int nvgpu_os_fence_sema_fdget(struct nvgpu_os_fence *fence_out, - struct channel_gk20a *c, int fd); - -void nvgpu_os_fence_init(struct nvgpu_os_fence *fence_out, - struct gk20a *g, const struct nvgpu_os_fence_ops *fops, - struct sync_fence *fence); - -void nvgpu_os_fence_android_install_fd(struct nvgpu_os_fence *s, int fd); - -int nvgpu_os_fence_syncpt_fdget( - struct nvgpu_os_fence *fence_out, - struct channel_gk20a *c, int fd); - -#endif /* __NVGPU_OS_FENCE_ANDROID_H__ */ \ No newline at end of file diff --git a/include/nvgpu/linux/rwsem.h b/include/nvgpu/linux/rwsem.h deleted file mode 100644 index 7d073d3..0000000 --- a/include/nvgpu/linux/rwsem.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef __NVGPU_RWSEM_LINUX_H__ -#define __NVGPU_RWSEM_LINUX_H__ - -#include - -struct nvgpu_rwsem { - struct rw_semaphore rwsem; -}; - -#endif diff --git a/include/nvgpu/linux/sim.h b/include/nvgpu/linux/sim.h deleted file mode 100644 index 99c6348..0000000 --- a/include/nvgpu/linux/sim.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * - * nvgpu sim support - * - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef __SIM_LINUX_H__ -#define __SIM_LINUX_H__ - -struct platform_device; - -struct sim_nvgpu_linux { - struct sim_nvgpu sim; - struct resource *reg_mem; - void __iomem *regs; - void (*remove_support_linux)(struct gk20a *g); -}; - -void sim_writel(struct sim_nvgpu *sim, u32 r, u32 v); -u32 sim_readl(struct sim_nvgpu *sim, u32 r); - -int nvgpu_init_sim_support_linux(struct gk20a *g, - struct platform_device *dev); -void nvgpu_remove_sim_support_linux(struct gk20a *g); -#endif diff --git a/include/nvgpu/linux/sim_pci.h b/include/nvgpu/linux/sim_pci.h deleted file mode 100644 index b248f07..0000000 --- a/include/nvgpu/linux/sim_pci.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * - * nvgpu sim support pci - * - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef __SIM_PCI_LINUX_H__ -#define __SIM_PCI_LINUX_H__ - -int nvgpu_init_sim_support_linux_pci(struct gk20a *g); -void nvgpu_remove_sim_support_linux_pci(struct gk20a *g); - -#endif diff --git a/include/nvgpu/linux/thread.h b/include/nvgpu/linux/thread.h deleted file mode 100644 index 1355319..0000000 --- a/include/nvgpu/linux/thread.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef __NVGPU_THREAD_LINUX_H__ -#define __NVGPU_THREAD_LINUX_H__ - -struct task_struct; - -struct nvgpu_thread { - struct task_struct *task; - bool running; - int (*fn)(void *); - void *data; -}; - -#endif /* __NVGPU_THREAD_LINUX_H__ */ diff --git a/include/nvgpu/linux/vm.h b/include/nvgpu/linux/vm.h deleted file mode 100644 index 6f3beaa..0000000 --- a/include/nvgpu/linux/vm.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef __COMMON_LINUX_VM_PRIV_H__ -#define __COMMON_LINUX_VM_PRIV_H__ - -#include - -#include - -/* - * Couple of places explicitly flush caches still. Any DMA buffer we allocate - * from within the GPU is writecombine and as a result does not need this but - * there seem to be exceptions. - */ -#ifdef CONFIG_ARM64 -#define outer_flush_range(a, b) -#define __cpuc_flush_dcache_area __flush_dcache_area -#endif - -struct sg_table; -struct dma_buf; -struct device; - -struct vm_gk20a; -struct vm_gk20a_mapping_batch; -struct nvgpu_vm_area; - -struct nvgpu_os_buffer { - struct dma_buf *dmabuf; - struct dma_buf_attachment *attachment; - struct device *dev; -}; - -struct nvgpu_mapped_buf_priv { - struct dma_buf *dmabuf; - struct dma_buf_attachment *attachment; - struct sg_table *sgt; -}; - -/* NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL must be set */ -int nvgpu_vm_map_linux(struct vm_gk20a *vm, - struct dma_buf *dmabuf, - u64 map_addr, - u32 flags, - u32 page_size, - s16 compr_kind, - s16 incompr_kind, - int rw_flag, - u64 buffer_offset, - u64 mapping_size, - struct vm_gk20a_mapping_batch *mapping_batch, - u64 *gpu_va); - -/* - * Notes: - * - Batch may be NULL if map op is not part of a batch. - * - NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL must be set - */ -int nvgpu_vm_map_buffer(struct vm_gk20a *vm, - int dmabuf_fd, - u64 *map_addr, - u32 flags, /* NVGPU_AS_MAP_BUFFER_FLAGS_ */ - u32 page_size, - s16 compr_kind, - s16 incompr_kind, - u64 buffer_offset, - u64 mapping_size, - struct vm_gk20a_mapping_batch *batch); - -/* find buffer corresponding to va */ -int nvgpu_vm_find_buf(struct vm_gk20a *vm, u64 gpu_va, - struct dma_buf **dmabuf, - u64 *offset); - -enum nvgpu_aperture gk20a_dmabuf_aperture(struct gk20a *g, - struct dma_buf *dmabuf); - -#endif diff --git a/include/nvgpu/list.h b/include/nvgpu/list.h deleted file mode 100644 index 1608035..0000000 --- a/include/nvgpu/list.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_LIST_H -#define NVGPU_LIST_H -#include - -struct nvgpu_list_node { - struct nvgpu_list_node *prev; - struct nvgpu_list_node *next; -}; - -static inline void nvgpu_init_list_node(struct nvgpu_list_node *node) -{ - node->prev = node; - node->next = node; -} - -static inline void nvgpu_list_add(struct nvgpu_list_node *new_node, struct nvgpu_list_node *head) -{ - new_node->next = head->next; - new_node->next->prev = new_node; - new_node->prev = head; - head->next = new_node; -} - -static inline void nvgpu_list_add_tail(struct nvgpu_list_node *new_node, struct nvgpu_list_node *head) -{ - new_node->prev = head->prev; - new_node->prev->next = new_node; - new_node->next = head; - head->prev = new_node; -} - -static inline void nvgpu_list_del(struct nvgpu_list_node *node) -{ - node->prev->next = node->next; - node->next->prev = node->prev; - nvgpu_init_list_node(node); -} - -static inline bool nvgpu_list_empty(struct nvgpu_list_node *head) -{ - return head->next == head; -} - -static inline void nvgpu_list_move(struct nvgpu_list_node *node, struct nvgpu_list_node *head) -{ - nvgpu_list_del(node); - nvgpu_list_add(node, head); -} - -static inline void nvgpu_list_replace_init(struct nvgpu_list_node *old_node, struct nvgpu_list_node *new_node) -{ - new_node->next = old_node->next; - new_node->next->prev = new_node; - new_node->prev = old_node->prev; - new_node->prev->next = new_node; - nvgpu_init_list_node(old_node); -} - -#define nvgpu_list_entry(ptr, type, member) \ - type ## _from_ ## member(ptr) - -#define nvgpu_list_next_entry(pos, type, member) \ - nvgpu_list_entry((pos)->member.next, type, member) - -#define nvgpu_list_first_entry(ptr, type, member) \ - nvgpu_list_entry((ptr)->next, type, member) - -#define nvgpu_list_last_entry(ptr, type, member) \ - nvgpu_list_entry((ptr)->prev, type, member) - -#define nvgpu_list_for_each_entry(pos, head, type, member) \ - for (pos = nvgpu_list_first_entry(head, type, member); \ - &pos->member != (head); \ - pos = nvgpu_list_next_entry(pos, type, member)) - -#define nvgpu_list_for_each_entry_safe(pos, n, head, type, member) \ - for (pos = nvgpu_list_first_entry(head, type, member), \ - n = nvgpu_list_next_entry(pos, type, member); \ - &pos->member != (head); \ - pos = n, n = nvgpu_list_next_entry(n, type, member)) - -#endif /* NVGPU_LIST_H */ diff --git a/include/nvgpu/lock.h b/include/nvgpu/lock.h deleted file mode 100644 index 7e4b2ac..0000000 --- a/include/nvgpu/lock.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_LOCK_H -#define NVGPU_LOCK_H - -#ifdef __KERNEL__ -#include -#elif defined(__NVGPU_POSIX__) -#include -#else -#include -#endif - -/* - * struct nvgpu_mutex - * - * Should be implemented per-OS in a separate library - * But implementation should adhere to mutex implementation - * as specified in Linux Documentation - */ -struct nvgpu_mutex; - -/* - * struct nvgpu_spinlock - * - * Should be implemented per-OS in a separate library - * But implementation should adhere to spinlock implementation - * as specified in Linux Documentation - */ -struct nvgpu_spinlock; - -/* - * struct nvgpu_raw_spinlock - * - * Should be implemented per-OS in a separate library - * But implementation should adhere to raw_spinlock implementation - * as specified in Linux Documentation - */ -struct nvgpu_raw_spinlock; - -int nvgpu_mutex_init(struct nvgpu_mutex *mutex); -void nvgpu_mutex_acquire(struct nvgpu_mutex *mutex); -void nvgpu_mutex_release(struct nvgpu_mutex *mutex); -int nvgpu_mutex_tryacquire(struct nvgpu_mutex *mutex); -void nvgpu_mutex_destroy(struct nvgpu_mutex *mutex); - -void nvgpu_spinlock_init(struct nvgpu_spinlock *spinlock); -void nvgpu_spinlock_acquire(struct nvgpu_spinlock *spinlock); -void nvgpu_spinlock_release(struct nvgpu_spinlock *spinlock); - -void nvgpu_raw_spinlock_init(struct nvgpu_raw_spinlock *spinlock); -void nvgpu_raw_spinlock_acquire(struct nvgpu_raw_spinlock *spinlock); -void nvgpu_raw_spinlock_release(struct nvgpu_raw_spinlock *spinlock); - -#endif /* NVGPU_LOCK_H */ diff --git a/include/nvgpu/log.h b/include/nvgpu/log.h deleted file mode 100644 index 2bcca33..0000000 --- a/include/nvgpu/log.h +++ /dev/null @@ -1,184 +0,0 @@ -/* - * Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_LOG_H -#define NVGPU_LOG_H - -#include -#include - -struct gk20a; - -enum nvgpu_log_type { - NVGPU_ERROR, - NVGPU_WARNING, - NVGPU_DEBUG, - NVGPU_INFO, -}; - -/* - * Each OS must implement these functions. They handle the OS specific nuances - * of printing data to a UART, log, whatever. - */ -__attribute__((format (printf, 5, 6))) -void __nvgpu_log_msg(struct gk20a *g, const char *func_name, int line, - enum nvgpu_log_type type, const char *fmt, ...); - -__attribute__((format (printf, 5, 6))) -void __nvgpu_log_dbg(struct gk20a *g, u64 log_mask, - const char *func_name, int line, - const char *fmt, ...); - -/* - * Use this define to set a default mask. - */ -#define NVGPU_DEFAULT_DBG_MASK (0) - -#define gpu_dbg_info BIT(0) /* Lightly verbose info. */ -#define gpu_dbg_fn BIT(1) /* Function name tracing. */ -#define gpu_dbg_reg BIT(2) /* Register accesses; very verbose. */ -#define gpu_dbg_pte BIT(3) /* GMMU PTEs. */ -#define gpu_dbg_intr BIT(4) /* Interrupts. */ -#define gpu_dbg_pmu BIT(5) /* gk20a pmu. */ -#define gpu_dbg_clk BIT(6) /* gk20a clk. */ -#define gpu_dbg_map BIT(7) /* Memory mappings. */ -#define gpu_dbg_map_v BIT(8) /* Verbose mem mappings. */ -#define gpu_dbg_gpu_dbg BIT(9) /* GPU debugger/profiler. */ -#define gpu_dbg_cde BIT(10) /* cde info messages. */ -#define gpu_dbg_cde_ctx BIT(11) /* cde context usage messages. */ -#define gpu_dbg_ctxsw BIT(12) /* ctxsw tracing. */ -#define gpu_dbg_sched BIT(13) /* Sched control tracing. */ -#define gpu_dbg_sema BIT(14) /* Semaphore debugging. */ -#define gpu_dbg_sema_v BIT(15) /* Verbose semaphore debugging. */ -#define gpu_dbg_pmu_pstate BIT(16) /* p state controlled by pmu. */ -#define gpu_dbg_xv BIT(17) /* XVE debugging. */ -#define gpu_dbg_shutdown BIT(18) /* GPU shutdown tracing. */ -#define gpu_dbg_kmem BIT(19) /* Kmem tracking debugging. */ -#define gpu_dbg_pd_cache BIT(20) /* PD cache traces. */ -#define gpu_dbg_alloc BIT(21) /* Allocator debugging. */ -#define gpu_dbg_dma BIT(22) /* DMA allocation prints. */ -#define gpu_dbg_sgl BIT(23) /* SGL related traces. */ -#define gpu_dbg_vidmem BIT(24) /* VIDMEM tracing. */ -#define gpu_dbg_nvlink BIT(25) /* nvlink Operation tracing. */ -#define gpu_dbg_clk_arb BIT(26) /* Clk arbiter debugging. */ -#define gpu_dbg_ecc BIT(27) /* Print ECC Info Logs. */ -#define gpu_dbg_mem BIT(31) /* memory accesses; very verbose. */ - -/** - * nvgpu_log_mask_enabled - Check if logging is enabled - * - * @g - The GPU. - * @log_mask - The mask the check against. - * - * Check if, given the passed mask, logging would actually happen. This is - * useful for avoiding calling the logging function many times when we know that - * said prints would not happen. For example for-loops of log statements in - * critical paths. - */ -int nvgpu_log_mask_enabled(struct gk20a *g, u64 log_mask); - -/** - * nvgpu_log - Print a debug message - * - * @g - The GPU. - * @log_mask - A mask defining when the print should happen. See enum - * %nvgpu_log_categories. - * @fmt - A format string (printf style). - * @arg... - Arguments for the format string. - * - * Print a message if the log_mask matches the enabled debugging. - */ -#define nvgpu_log(g, log_mask, fmt, arg...) \ - __nvgpu_log_dbg(g, (u32)log_mask, __func__, __LINE__, fmt, ##arg) - -/** - * nvgpu_err - Print an error - * - * @g - The GPU. - * @fmt - A format string (printf style). - * @arg... - Arguments for the format string. - * - * Uncondtionally print an error message. - */ -#define nvgpu_err(g, fmt, arg...) \ - __nvgpu_log_msg(g, __func__, __LINE__, NVGPU_ERROR, fmt, ##arg) - -/** - * nvgpu_err - Print a warning - * - * @g - The GPU. - * @fmt - A format string (printf style). - * @arg... - Arguments for the format string. - * - * Uncondtionally print a warming message. - */ -#define nvgpu_warn(g, fmt, arg...) \ - __nvgpu_log_msg(g, __func__, __LINE__, NVGPU_WARNING, fmt, ##arg) - -/** - * nvgpu_info - Print an info message - * - * @g - The GPU. - * @fmt - A format string (printf style). - * @arg... - Arguments for the format string. - * - * Unconditionally print an information message. - */ -#define nvgpu_info(g, fmt, arg...) \ - __nvgpu_log_msg(g, __func__, __LINE__, NVGPU_INFO, fmt, ##arg) - -/* - * Some convenience macros. - */ -#define nvgpu_log_fn(g, fmt, arg...) nvgpu_log(g, gpu_dbg_fn, fmt, ##arg) -#define nvgpu_log_info(g, fmt, arg...) nvgpu_log(g, gpu_dbg_info, fmt, ##arg) - -/****************************************************************************** - * The old legacy debugging API minus some parts that are unnecessary. * - * Please, please, please do not use this!!! This is still around to aid * - * transitioning to the new API. * - * * - * This changes up the print formats to be closer to the new APIs formats. * - * Also it removes the dev_warn() and dev_err() usage. Those arguments are * - * ignored now. * - ******************************************************************************/ - -/* - * This exist for backwards compatibility with the old debug/logging API. If you - * want ftrace support use the new API! - */ -extern u64 nvgpu_dbg_mask; - -#define gk20a_dbg(log_mask, fmt, arg...) \ - do { \ - if (((log_mask) & nvgpu_dbg_mask) != 0) \ - __nvgpu_log_msg(NULL, __func__, __LINE__, \ - NVGPU_DEBUG, fmt "\n", ##arg); \ - } while (0) - -/* - * Some convenience macros. - */ -#define gk20a_dbg_fn(fmt, arg...) gk20a_dbg(gpu_dbg_fn, fmt, ##arg) -#define gk20a_dbg_info(fmt, arg...) gk20a_dbg(gpu_dbg_info, fmt, ##arg) - -#endif /* NVGPU_LOG_H */ diff --git a/include/nvgpu/log2.h b/include/nvgpu/log2.h deleted file mode 100644 index 98db1ec..0000000 --- a/include/nvgpu/log2.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_LOG2_H -#define NVGPU_LOG2_H - -#ifdef __KERNEL__ -#include -#elif defined(__NVGPU_POSIX__) -#include -#endif - -#endif /* NVGPU_LOG2_H */ diff --git a/include/nvgpu/ltc.h b/include/nvgpu/ltc.h deleted file mode 100644 index a674a29..0000000 --- a/include/nvgpu/ltc.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_LTC_H -#define NVGPU_LTC_H - -#include - -struct gk20a; - -int nvgpu_init_ltc_support(struct gk20a *g); -void nvgpu_ltc_sync_enabled(struct gk20a *g); -int nvgpu_ltc_alloc_cbc(struct gk20a *g, size_t compbit_backing_size, - bool vidmem_alloc); - -#endif /* NVGPU_LTC_H */ diff --git a/include/nvgpu/mc.h b/include/nvgpu/mc.h deleted file mode 100644 index 3c012f9..0000000 --- a/include/nvgpu/mc.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_MC_H -#define NVGPU_MC_H - -#include - -struct gk20a; - -#define NVGPU_MC_INTR_STALLING 0U -#define NVGPU_MC_INTR_NONSTALLING 1U - -u32 nvgpu_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev); - -#endif diff --git a/include/nvgpu/mm.h b/include/nvgpu/mm.h deleted file mode 100644 index 01063bc..0000000 --- a/include/nvgpu/mm.h +++ /dev/null @@ -1,223 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_MM_H -#define NVGPU_MM_H - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -struct gk20a; -struct vm_gk20a; -struct nvgpu_mem; -struct nvgpu_pd_cache; - -#define NVGPU_MM_MMU_FAULT_TYPE_OTHER_AND_NONREPLAY 0 -#define NVGPU_MM_MMU_FAULT_TYPE_REPLAY 1 - -#define FAULT_TYPE_NUM 2 /* replay and nonreplay faults */ - -struct mmu_fault_info { - u64 inst_ptr; - u32 inst_aperture; - u64 fault_addr; - u32 fault_addr_aperture; - u32 timestamp_lo; - u32 timestamp_hi; - u32 mmu_engine_id; - u32 gpc_id; - u32 client_type; - u32 client_id; - u32 fault_type; - u32 access_type; - u32 protected_mode; - u32 replayable_fault; - u32 replay_fault_en; - u32 valid; - u32 faulted_pbdma; - u32 faulted_engine; - u32 faulted_subid; - u32 chid; - struct channel_gk20a *refch; - const char *client_type_desc; - const char *fault_type_desc; - const char *client_id_desc; -}; - -enum nvgpu_flush_op { - NVGPU_FLUSH_DEFAULT, - NVGPU_FLUSH_FB, - NVGPU_FLUSH_L2_INV, - NVGPU_FLUSH_L2_FLUSH, - NVGPU_FLUSH_CBC_CLEAN, -}; - -struct mm_gk20a { - struct gk20a *g; - - /* GPU VA default sizes address spaces for channels */ - struct { - u64 user_size; /* userspace-visible GPU VA region */ - u64 kernel_size; /* kernel-only GPU VA region */ - } channel; - - struct { - u32 aperture_size; - struct vm_gk20a *vm; - struct nvgpu_mem inst_block; - } bar1; - - struct { - u32 aperture_size; - struct vm_gk20a *vm; - struct nvgpu_mem inst_block; - } bar2; - - struct { - u32 aperture_size; - struct vm_gk20a *vm; - struct nvgpu_mem inst_block; - } pmu; - - struct { - /* using pmu vm currently */ - struct nvgpu_mem inst_block; - } hwpm; - - struct { - struct vm_gk20a *vm; - struct nvgpu_mem inst_block; - } perfbuf; - - struct { - struct vm_gk20a *vm; - } cde; - - struct { - struct vm_gk20a *vm; - } ce; - - struct nvgpu_pd_cache *pd_cache; - - struct nvgpu_mutex l2_op_lock; - struct nvgpu_mutex tlb_lock; - struct nvgpu_mutex priv_lock; - - struct nvgpu_mem bar2_desc; - - struct nvgpu_mem hw_fault_buf[FAULT_TYPE_NUM]; - struct mmu_fault_info fault_info[FAULT_TYPE_NUM]; - struct nvgpu_mutex hub_isr_mutex; - - /* - * Separate function to cleanup the CE since it requires a channel to - * be closed which must happen before fifo cleanup. - */ - void (*remove_ce_support)(struct mm_gk20a *mm); - void (*remove_support)(struct mm_gk20a *mm); - bool sw_ready; - int physical_bits; - bool use_full_comp_tag_line; - bool ltc_enabled_current; - bool ltc_enabled_target; - bool disable_bigpage; - - struct nvgpu_mem sysmem_flush; - - u32 pramin_window; - struct nvgpu_spinlock pramin_window_lock; - - struct { - size_t size; - u64 base; - size_t bootstrap_size; - u64 bootstrap_base; - - struct nvgpu_allocator allocator; - struct nvgpu_allocator bootstrap_allocator; - - u32 ce_ctx_id; - volatile bool cleared; - struct nvgpu_mutex first_clear_mutex; - - struct nvgpu_list_node clear_list_head; - struct nvgpu_mutex clear_list_mutex; - - struct nvgpu_cond clearing_thread_cond; - struct nvgpu_thread clearing_thread; - struct nvgpu_mutex clearing_thread_lock; - nvgpu_atomic_t pause_count; - - nvgpu_atomic64_t bytes_pending; - } vidmem; - - struct nvgpu_mem mmu_wr_mem; - struct nvgpu_mem mmu_rd_mem; -}; - -#define gk20a_from_mm(mm) ((mm)->g) -#define gk20a_from_vm(vm) ((vm)->mm->g) - -static inline int bar1_aperture_size_mb_gk20a(void) -{ - return 16; /* 16MB is more than enough atm. */ -} - -/* The maximum GPU VA range supported */ -#define NV_GMMU_VA_RANGE 38 - -/* The default userspace-visible GPU VA size */ -#define NV_MM_DEFAULT_USER_SIZE (1ULL << 37) - -/* The default kernel-reserved GPU VA size */ -#define NV_MM_DEFAULT_KERNEL_SIZE (1ULL << 32) - -/* - * When not using unified address spaces, the bottom 56GB of the space are used - * for small pages, and the remaining high memory is used for large pages. - */ -static inline u64 nvgpu_gmmu_va_small_page_limit(void) -{ - return ((u64)SZ_1G * 56U); -} - -u32 nvgpu_vm_get_pte_size(struct vm_gk20a *vm, u64 base, u64 size); - -void nvgpu_init_mm_ce_context(struct gk20a *g); -int nvgpu_init_mm_support(struct gk20a *g); -int nvgpu_init_mm_setup_hw(struct gk20a *g); - -u64 nvgpu_inst_block_addr(struct gk20a *g, struct nvgpu_mem *mem); -void nvgpu_free_inst_block(struct gk20a *g, struct nvgpu_mem *inst_block); - -int nvgpu_mm_suspend(struct gk20a *g); -u32 nvgpu_mm_get_default_big_page_size(struct gk20a *g); -u32 nvgpu_mm_get_available_big_page_sizes(struct gk20a *g); - -#endif /* NVGPU_MM_H */ diff --git a/include/nvgpu/nvgpu_common.h b/include/nvgpu/nvgpu_common.h deleted file mode 100644 index 3466051..0000000 --- a/include/nvgpu/nvgpu_common.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_COMMON_H -#define NVGPU_COMMON_H - -struct gk20a; -struct class; - -int nvgpu_probe(struct gk20a *g, - const char *debugfs_symlink, - const char *interface_name, - struct class *class); - -void nvgpu_kernel_restart(void *cmd); - -#endif diff --git a/include/nvgpu/nvgpu_err.h b/include/nvgpu/nvgpu_err.h deleted file mode 100644 index 0595faf..0000000 --- a/include/nvgpu/nvgpu_err.h +++ /dev/null @@ -1,359 +0,0 @@ -/* - * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_NVGPU_ERR_H -#define NVGPU_NVGPU_ERR_H - -/** - * @file - * - * Define indices for HW units and errors. Define structures used to carry error - * information. Declare prototype for APIs that are used to report GPU HW errors - * to the Safety_Services framework. - */ - -#include -#include - -struct gk20a; - -/** - * @defgroup INDICES_FOR_GPU_HW_UNITS - * Macros used to assign unique index to GPU HW units. - * @{ - */ -#define NVGPU_ERR_MODULE_SM (0U) -#define NVGPU_ERR_MODULE_FECS (1U) -#define NVGPU_ERR_MODULE_PMU (2U) -/** - * @} - */ - -/** - * @defgroup LIST_OF_ERRORS_REPORTED_FROM_SM - * Macros used to assign unique index to errors reported from the SM unit. - * @{ - */ -#define GPU_SM_L1_TAG_ECC_CORRECTED (0U) -#define GPU_SM_L1_TAG_ECC_UNCORRECTED (1U) -#define GPU_SM_CBU_ECC_UNCORRECTED (3U) -#define GPU_SM_LRF_ECC_UNCORRECTED (5U) -#define GPU_SM_L1_DATA_ECC_UNCORRECTED (7U) -#define GPU_SM_ICACHE_L0_DATA_ECC_UNCORRECTED (9U) -#define GPU_SM_ICACHE_L1_DATA_ECC_UNCORRECTED (11U) -#define GPU_SM_ICACHE_L0_PREDECODE_ECC_UNCORRECTED (13U) -#define GPU_SM_L1_TAG_MISS_FIFO_ECC_UNCORRECTED (15U) -#define GPU_SM_L1_TAG_S2R_PIXPRF_ECC_UNCORRECTED (17U) -#define GPU_SM_ICACHE_L1_PREDECODE_ECC_UNCORRECTED (20U) -/** - * @} - */ - -/** - * @defgroup LIST_OF_ERRORS_REPORTED_FROM_FECS - * Macros used to assign unique index to errors reported from the FECS unit. - * @{ - */ -#define GPU_FECS_FALCON_IMEM_ECC_CORRECTED (0U) -#define GPU_FECS_FALCON_IMEM_ECC_UNCORRECTED (1U) -#define GPU_FECS_FALCON_DMEM_ECC_UNCORRECTED (3U) -/** - * @} - */ - -/** - * @defgroup LIST_OF_ERRORS_REPORTED_FROM_GPCCS - * Macros used to assign unique index to errors reported from the GPCCS unit. - * @{ - */ -#define GPU_GPCCS_FALCON_IMEM_ECC_CORRECTED (0U) -#define GPU_GPCCS_FALCON_IMEM_ECC_UNCORRECTED (1U) -#define GPU_GPCCS_FALCON_DMEM_ECC_UNCORRECTED (3U) -/** - * @} - */ - -/** - * @defgroup LIST_OF_ERRORS_REPORTED_FROM_MMU - * Macros used to assign unique index to errors reported from the MMU unit. - * @{ - */ -#define GPU_MMU_L1TLB_SA_DATA_ECC_UNCORRECTED (1U) -#define GPU_MMU_L1TLB_FA_DATA_ECC_UNCORRECTED (3U) -/** - * @} - */ - -/** - * @defgroup LIST_OF_ERRORS_REPORTED_FROM_GCC - * Macros used to assign unique index to errors reported from the GCC unit. - * @{ - */ -#define GPU_GCC_L15_ECC_UNCORRECTED (1U) -/** - * @} - */ - - -/** - * @defgroup LIST_OF_ERRORS_REPORTED_FROM_PMU - * Macros used to assign unique index to errors reported from the PMU unit. - * @{ - */ -#define GPU_PMU_FALCON_IMEM_ECC_CORRECTED (0U) -#define GPU_PMU_FALCON_IMEM_ECC_UNCORRECTED (1U) -#define GPU_PMU_FALCON_DMEM_ECC_UNCORRECTED (3U) -/** - * @} - */ - -/** - * @defgroup LIST_OF_ERRORS_REPORTED_FROM_LTC - * Macros used to assign unique index to errors reported from the LTC unit. - * @{ - */ -#define GPU_LTC_CACHE_DSTG_ECC_CORRECTED (0U) -#define GPU_LTC_CACHE_DSTG_ECC_UNCORRECTED (1U) -#define GPU_LTC_CACHE_TSTG_ECC_UNCORRECTED (3U) -#define GPU_LTC_CACHE_DSTG_BE_ECC_UNCORRECTED (7U) -/** - * @} - */ - -/** - * @defgroup LIST_OF_ERRORS_REPORTED_FROM_HUBMMU - * Macros used to assign unique index to errors reported from the HUBMMU unit. - * @{ - */ -#define GPU_HUBMMU_L2TLB_SA_DATA_ECC_UNCORRECTED (1U) -#define GPU_HUBMMU_TLB_SA_DATA_ECC_UNCORRECTED (3U) -#define GPU_HUBMMU_PTE_DATA_ECC_UNCORRECTED (5U) -#define GPU_HUBMMU_PDE0_DATA_ECC_UNCORRECTED (7U) -#define GPU_HUBMMU_PAGE_FAULT_ERROR (8U) - - -#ifdef CONFIG_NVGPU_SUPPORT_LINUX_ECC_ERROR_REPORTING -/** - * @} - */ - -/** - * nvgpu_err_desc structure holds fields which describe an error along with - * function callback which can be used to inject the error. - */ -struct nvgpu_err_desc { - /** String representation of error. */ - const char *name; - - /** Flag to classify an error as critical or non-critical. */ - bool is_critical; - - /** - * Error Threshold: once this threshold value is reached, then the - * corresponding error counter will be reset to 0 and the error will be - * propagated to Safety_Services. - */ - int err_threshold; - - /** - * Total number of times an error has occurred (since its last reset). - */ - nvgpu_atomic_t err_count; - - /** Error ID. */ - u8 error_id; -}; - -/** - * gpu_err_header structure holds fields which are required to identify the - * version of header, sub-error type, sub-unit id, error address and time stamp. - */ -struct gpu_err_header { - /** Version of GPU error header. */ - struct { - /** Major version number. */ - u16 major; - /** Minor version number. */ - u16 minor; - } version; - - /** Sub error type corresponding to the error that is being reported. */ - u32 sub_err_type; - - /** ID of the sub-unit in a HW unit which encountered an error. */ - u64 sub_unit_id; - - /** Location of the error. */ - u64 address; - - /** Timestamp in nano seconds. */ - u64 timestamp_ns; -}; - -struct gpu_ecc_error_info { - struct gpu_err_header header; - - /** Number of ECC errors. */ - u64 err_cnt; -}; - -/** - * nvgpu_err_hw_module structure holds fields which describe the h/w modules - * error reporting capabilities. - */ -struct nvgpu_err_hw_module { - /** String representation of a given HW unit. */ - const char *name; - - /** HW unit ID. */ - u32 hw_unit; - - /** Total number of errors reported from a given HW unit. */ - u32 num_errs; - - u32 base_ecc_service_id; - - /** Used to get error description from look-up table. */ - struct nvgpu_err_desc *errs; -}; - -struct nvgpu_ecc_reporting_ops { - void (*report_ecc_err)(struct gk20a *g, u32 hw_unit, u32 inst, - u32 err_id, u64 err_addr, u64 err_count); -}; - -struct nvgpu_ecc_reporting { - struct nvgpu_spinlock lock; - /* This flag is protected by the above spinlock */ - bool ecc_reporting_service_enabled; - const struct nvgpu_ecc_reporting_ops *ops; -}; - - /** - * This macro is used to initialize the members of nvgpu_err_desc struct. - */ -#define GPU_ERR(err, critical, id, threshold, ecount) \ -{ \ - .name = (err), \ - .is_critical = (critical), \ - .error_id = (id), \ - .err_threshold = (threshold), \ - .err_count = NVGPU_ATOMIC_INIT(ecount), \ -} - -/** - * This macro is used to initialize critical errors. - */ -#define GPU_CRITERR(err, id, threshold, ecount) \ - GPU_ERR(err, true, id, threshold, ecount) - -/** - * This macro is used to initialize non-critical errors. - */ -#define GPU_NONCRITERR(err, id, threshold, ecount) \ - GPU_ERR(err, false, id, threshold, ecount) - -/** - * @brief GPU HW errors need to be reported to Safety_Services via SDL unit. - * This function provides an interface to report ECC erros to SDL unit. - * - * @param g [in] - The GPU driver struct. - * @param hw_unit [in] - Index of HW unit. - * - List of valid HW unit IDs - * - NVGPU_ERR_MODULE_SM - * - NVGPU_ERR_MODULE_FECS - * - NVGPU_ERR_MODULE_GPCCS - * - NVGPU_ERR_MODULE_MMU - * - NVGPU_ERR_MODULE_GCC - * - NVGPU_ERR_MODULE_PMU - * - NVGPU_ERR_MODULE_LTC - * - NVGPU_ERR_MODULE_HUBMMU - * @param inst [in] - Instance ID. - * - In case of multiple instances of the same HW - * unit (e.g., there are multiple instances of - * SM), it is used to identify the instance - * that encountered a fault. - * @param err_id [in] - Error index. - * - For SM: - * - Min: GPU_SM_L1_TAG_ECC_CORRECTED - * - Max: GPU_SM_ICACHE_L1_PREDECODE_ECC_UNCORRECTED - * - For FECS: - * - Min: GPU_FECS_FALCON_IMEM_ECC_CORRECTED - * - Max: GPU_FECS_INVALID_ERROR - * - For GPCCS: - * - Min: GPU_GPCCS_FALCON_IMEM_ECC_CORRECTED - * - Max: GPU_GPCCS_FALCON_DMEM_ECC_UNCORRECTED - * - For MMU: - * - Min: GPU_MMU_L1TLB_SA_DATA_ECC_UNCORRECTED - * - Max: GPU_MMU_L1TLB_FA_DATA_ECC_UNCORRECTED - * - For GCC: - * - Min: GPU_GCC_L15_ECC_UNCORRECTED - * - Max: GPU_GCC_L15_ECC_UNCORRECTED - * - For PMU: - * - Min: GPU_PMU_FALCON_IMEM_ECC_CORRECTED - * - Max: GPU_PMU_FALCON_DMEM_ECC_UNCORRECTED - * - For LTC: - * - Min: GPU_LTC_CACHE_DSTG_ECC_CORRECTED - * - Max: GPU_LTC_CACHE_DSTG_BE_ECC_UNCORRECTED - * - For HUBMMU: - * - Min: GPU_HUBMMU_L2TLB_SA_DATA_ECC_UNCORRECTED - * - Max: GPU_HUBMMU_PDE0_DATA_ECC_UNCORRECTED - * @param err_addr [in] - Error address. - * - This is the location at which correctable or - * uncorrectable error has occurred. - * @param err_count [in] - Error count. - * - * - Checks whether SDL is supported in the current GPU platform. If SDL is not - * supported, it simply returns. - * - Validates both \a hw_unit and \a err_id indices. In case of a failure, - * invokes #nvgpu_sdl_handle_report_failure() api. - * - Gets the current time of a clock. In case of a failure, invokes - * #nvgpu_sdl_handle_report_failure() api. - * - Gets error description from internal look-up table using \a hw_unit and - * \a err_id indices. - * - Forms error packet using details such as time-stamp, \a hw_unit, \a err_id, - * criticality of the error, \a inst, \a err_addr, \a err_count, error - * description, and size of the error packet. - * - Performs compile-time assert check to ensure that the size of the error - * packet does not exceed the maximum allowable size specified in - * #MAX_ERR_MSG_SIZE. - * - * @return None - */ -void nvgpu_report_ecc_err(struct gk20a *g, u32 hw_unit, u32 inst, - u32 err_id, u64 err_addr, u64 err_count); - -void nvgpu_init_ecc_reporting(struct gk20a *g); -void nvgpu_enable_ecc_reporting(struct gk20a *g); -void nvgpu_disable_ecc_reporting(struct gk20a *g); -void nvgpu_deinit_ecc_reporting(struct gk20a *g); - -#else - -static inline void nvgpu_report_ecc_err(struct gk20a *g, u32 hw_unit, u32 inst, - u32 err_id, u64 err_addr, u64 err_count) { - -} - -#endif /* CONFIG_NVGPU_SUPPORT_LINUX_ECC_ERROR_REPORTING */ - -#endif /* NVGPU_NVGPU_ERR_H */ \ No newline at end of file diff --git a/include/nvgpu/nvgpu_mem.h b/include/nvgpu/nvgpu_mem.h deleted file mode 100644 index 4e84f2a..0000000 --- a/include/nvgpu/nvgpu_mem.h +++ /dev/null @@ -1,359 +0,0 @@ -/* - * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_MEM_H -#define NVGPU_MEM_H - -#include -#include -#include - -#ifdef __KERNEL__ -#include -#elif defined(__NVGPU_POSIX__) -#include -#else -#include -#endif - -struct page; -struct sg_table; -struct nvgpu_sgt; - -struct gk20a; -struct nvgpu_allocator; -struct nvgpu_gmmu_attrs; -struct nvgpu_page_alloc; - -#define NVGPU_MEM_DMA_ERROR (~0ULL) - -/* - * Real location of a buffer - nvgpu_aperture_mask() will deduce what will be - * told to the gpu about the aperture, but this flag designates where the - * memory actually was allocated from. - */ -enum nvgpu_aperture { - APERTURE_INVALID = 0, /* unallocated or N/A */ - APERTURE_SYSMEM, - - /* Don't use directly. Use APERTURE_SYSMEM, this is used internally. */ - APERTURE_SYSMEM_COH, - - APERTURE_VIDMEM -}; - -/* - * Forward declared opaque placeholder type that does not really exist, but - * helps the compiler help us about getting types right. In reality, - * implementors of nvgpu_sgt_ops will have some concrete type in place of this. - */ -struct nvgpu_sgl; - -struct nvgpu_sgt_ops { - struct nvgpu_sgl *(*sgl_next)(struct nvgpu_sgl *sgl); - u64 (*sgl_phys)(struct gk20a *g, struct nvgpu_sgl *sgl); - u64 (*sgl_dma)(struct nvgpu_sgl *sgl); - u64 (*sgl_length)(struct nvgpu_sgl *sgl); - u64 (*sgl_gpu_addr)(struct gk20a *g, struct nvgpu_sgl *sgl, - struct nvgpu_gmmu_attrs *attrs); - /* - * If left NULL then iommuable is assumed to be false. - */ - bool (*sgt_iommuable)(struct gk20a *g, struct nvgpu_sgt *sgt); - - /* - * Note: this operates on the whole SGT not a specific SGL entry. - */ - void (*sgt_free)(struct gk20a *g, struct nvgpu_sgt *sgt); -}; - -/* - * Scatter gather table: this is a list of scatter list entries and the ops for - * interacting with those entries. - */ -struct nvgpu_sgt { - /* - * Ops for interacting with the underlying scatter gather list entries. - */ - const struct nvgpu_sgt_ops *ops; - - /* - * The first node in the scatter gather list. - */ - struct nvgpu_sgl *sgl; -}; - -/* - * This struct holds the necessary information for describing a struct - * nvgpu_mem's scatter gather list. - * - * This is one underlying implementation for nvgpu_sgl. Not all nvgpu_sgt's use - * this particular implementation. Nor is a given OS required to use this at - * all. - */ -struct nvgpu_mem_sgl { - /* - * Internally this is implemented as a singly linked list. - */ - struct nvgpu_mem_sgl *next; - - /* - * There is both a phys address and a DMA address since some systems, - * for example ones with an IOMMU, may see these as different addresses. - */ - u64 phys; - u64 dma; - u64 length; -}; - -/* - * Iterate over the SGL entries in an SGT. - */ -#define nvgpu_sgt_for_each_sgl(__sgl__, __sgt__) \ - for ((__sgl__) = (__sgt__)->sgl; \ - (__sgl__) != NULL; \ - (__sgl__) = nvgpu_sgt_get_next(__sgt__, __sgl__)) - -struct nvgpu_mem { - /* - * Populated for all nvgpu_mem structs - vidmem or system. - */ - enum nvgpu_aperture aperture; - size_t size; - size_t aligned_size; - u64 gpu_va; - bool skip_wmb; - bool free_gpu_va; - - /* - * Set when a nvgpu_mem struct is not a "real" nvgpu_mem struct. Instead - * the struct is just a copy of another nvgpu_mem struct. - */ -#define NVGPU_MEM_FLAG_SHADOW_COPY (1 << 0) - - /* - * Specify that the GVA mapping is a fixed mapping - that is the caller - * chose the GPU VA, not the GMMU mapping function. Only relevant for - * VIDMEM. - */ -#define NVGPU_MEM_FLAG_FIXED (1 << 1) - - /* - * Set for user generated VIDMEM allocations. This triggers a special - * cleanup path that clears the vidmem on free. Given that the VIDMEM is - * zeroed on boot this means that all user vidmem allocations are - * therefor zeroed (to prevent leaking information in VIDMEM buffers). - */ -#define NVGPU_MEM_FLAG_USER_MEM (1 << 2) - - /* - * Internal flag that specifies this struct has not been made with DMA - * memory and as a result should not try to use the DMA routines for - * freeing the backing memory. - * - * However, this will not stop the DMA API from freeing other parts of - * nvgpu_mem in a system specific way. - */ -#define __NVGPU_MEM_FLAG_NO_DMA (1 << 3) - /* - * Some nvgpu_mem objects act as facades to memory buffers owned by - * someone else. This internal flag specifies that the sgt field is - * "borrowed", and it must not be freed by us. - * - * Of course the caller will have to make sure that the sgt owner - * outlives the nvgpu_mem. - */ -#define NVGPU_MEM_FLAG_FOREIGN_SGT (1 << 4) - unsigned long mem_flags; - - /* - * Only populated for a sysmem allocation. - */ - void *cpu_va; - - /* - * Fields only populated for vidmem allocations. - */ - struct nvgpu_page_alloc *vidmem_alloc; - struct nvgpu_allocator *allocator; - struct nvgpu_list_node clear_list_entry; - - /* - * This is defined by the system specific header. It can be empty if - * there's no system specific stuff for a given system. - */ - struct nvgpu_mem_priv priv; -}; - -static inline struct nvgpu_mem * -nvgpu_mem_from_clear_list_entry(struct nvgpu_list_node *node) -{ - return (struct nvgpu_mem *) - ((uintptr_t)node - offsetof(struct nvgpu_mem, - clear_list_entry)); -}; - -static inline const char *nvgpu_aperture_str(struct gk20a *g, - enum nvgpu_aperture aperture) -{ - switch (aperture) { - case APERTURE_INVALID: - return "INVAL"; - case APERTURE_SYSMEM: - return "SYSMEM"; - case APERTURE_SYSMEM_COH: - return "SYSCOH"; - case APERTURE_VIDMEM: - return "VIDMEM"; - }; - return "UNKNOWN"; -} - -bool nvgpu_aperture_is_sysmem(enum nvgpu_aperture ap); -bool nvgpu_mem_is_sysmem(struct nvgpu_mem *mem); - -/* - * Returns true if the passed nvgpu_mem has been allocated (i.e it's valid for - * subsequent use). - */ -static inline bool nvgpu_mem_is_valid(struct nvgpu_mem *mem) -{ - /* - * Internally the DMA APIs must set/unset the aperture flag when - * allocating/freeing the buffer. So check that to see if the *mem - * has been allocated or not. - * - * This relies on mem_descs being zeroed before being initialized since - * APERTURE_INVALID is equal to 0. - */ - return mem->aperture != APERTURE_INVALID; - -} - -/** - * nvgpu_mem_sgt_create_from_mem - Create a scatter list from an nvgpu_mem. - * - * @g - The GPU. - * @mem - The source memory allocation to use. - * - * Create a scatter gather table from the passed @mem struct. This list lets the - * calling code iterate across each chunk of a DMA allocation for when that DMA - * allocation is not completely contiguous. - */ -struct nvgpu_sgt *nvgpu_sgt_create_from_mem(struct gk20a *g, - struct nvgpu_mem *mem); - -struct nvgpu_sgl *nvgpu_sgt_get_next(struct nvgpu_sgt *sgt, - struct nvgpu_sgl *sgl); -u64 nvgpu_sgt_get_phys(struct gk20a *g, struct nvgpu_sgt *sgt, - struct nvgpu_sgl *sgl); -u64 nvgpu_sgt_get_dma(struct nvgpu_sgt *sgt, struct nvgpu_sgl *sgl); -u64 nvgpu_sgt_get_length(struct nvgpu_sgt *sgt, struct nvgpu_sgl *sgl); -u64 nvgpu_sgt_get_gpu_addr(struct gk20a *g, struct nvgpu_sgt *sgt, - struct nvgpu_sgl *sgl, - struct nvgpu_gmmu_attrs *attrs); -void nvgpu_sgt_free(struct gk20a *g, struct nvgpu_sgt *sgt); - -bool nvgpu_sgt_iommuable(struct gk20a *g, struct nvgpu_sgt *sgt); -u64 nvgpu_sgt_alignment(struct gk20a *g, struct nvgpu_sgt *sgt); - -/** - * nvgpu_mem_create_from_mem - Create a new nvgpu_mem struct from an old one. - * - * @g - The GPU. - * @dest - Destination nvgpu_mem to hold resulting memory description. - * @src - Source memory. Must be valid. - * @start_page - Starting page to use. - * @nr_pages - Number of pages to place in the new nvgpu_mem. - * - * Create a new nvgpu_mem struct describing a subsection of the @src nvgpu_mem. - * This will create an nvpgu_mem object starting at @start_page and is @nr_pages - * long. This currently only works on SYSMEM nvgpu_mems. If this is called on a - * VIDMEM nvgpu_mem then this will return an error. - * - * There is a _major_ caveat to this API: if the source buffer is freed before - * the copy is freed then the copy will become invalid. This is a result from - * how typical DMA APIs work: we can't call free on the buffer multiple times. - * Nor can we call free on parts of a buffer. Thus the only way to ensure that - * the entire buffer is actually freed is to call free once on the source - * buffer. Since these nvgpu_mem structs are not ref-counted in anyway it is up - * to the caller of this API to _ensure_ that the resulting nvgpu_mem buffer - * from this API is freed before the source buffer. Otherwise there can and will - * be memory corruption. - * - * The resulting nvgpu_mem should be released with the nvgpu_dma_free() or the - * nvgpu_dma_unmap_free() function depending on whether or not the resulting - * nvgpu_mem has been mapped. - * - * This will return 0 on success. An error is returned if the resulting - * nvgpu_mem would not make sense or if a new scatter gather table cannot be - * created. - */ -int nvgpu_mem_create_from_mem(struct gk20a *g, - struct nvgpu_mem *dest, struct nvgpu_mem *src, - u64 start_page, int nr_pages); - -/* - * Really free a vidmem buffer. There's a fair amount of work involved in - * freeing vidmem buffers in the DMA API. This handles none of that - it only - * frees the underlying vidmem specific structures used in vidmem buffers. - * - * This is implemented in the OS specific code. If it's not necessary it can - * be a noop. But the symbol must at least be present. - */ -void __nvgpu_mem_free_vidmem_alloc(struct gk20a *g, struct nvgpu_mem *vidmem); - -/* - * Buffer accessors. Sysmem buffers always have a CPU mapping and vidmem - * buffers are accessed via PRAMIN. - */ - -/* word-indexed offset */ -u32 nvgpu_mem_rd32(struct gk20a *g, struct nvgpu_mem *mem, u32 w); -/* byte offset (32b-aligned) */ -u32 nvgpu_mem_rd(struct gk20a *g, struct nvgpu_mem *mem, u32 offset); -/* memcpy to cpu, offset and size in bytes (32b-aligned) */ -void nvgpu_mem_rd_n(struct gk20a *g, struct nvgpu_mem *mem, u32 offset, - void *dest, u32 size); - -/* word-indexed offset */ -void nvgpu_mem_wr32(struct gk20a *g, struct nvgpu_mem *mem, u32 w, u32 data); -/* byte offset (32b-aligned) */ -void nvgpu_mem_wr(struct gk20a *g, struct nvgpu_mem *mem, u32 offset, u32 data); -/* memcpy from cpu, offset and size in bytes (32b-aligned) */ -void nvgpu_mem_wr_n(struct gk20a *g, struct nvgpu_mem *mem, u32 offset, - void *src, u32 size); -/* size and offset in bytes (32b-aligned), filled with the constant byte c */ -void nvgpu_memset(struct gk20a *g, struct nvgpu_mem *mem, u32 offset, - u32 c, u32 size); - -u64 nvgpu_mem_get_addr(struct gk20a *g, struct nvgpu_mem *mem); -u64 nvgpu_mem_get_phys_addr(struct gk20a *g, struct nvgpu_mem *mem); - -u32 nvgpu_aperture_mask_raw(struct gk20a *g, enum nvgpu_aperture aperture, - u32 sysmem_mask, u32 sysmem_coh_mask, u32 vidmem_mask); -u32 nvgpu_aperture_mask(struct gk20a *g, struct nvgpu_mem *mem, - u32 sysmem_mask, u32 sysmem_coh_mask, u32 vidmem_mask); - -u64 nvgpu_mem_iommu_translate(struct gk20a *g, u64 phys); - -#endif /* NVGPU_MEM_H */ diff --git a/include/nvgpu/nvhost.h b/include/nvgpu/nvhost.h deleted file mode 100644 index 74dc48b..0000000 --- a/include/nvgpu/nvhost.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_NVHOST_H -#define NVGPU_NVHOST_H - -#ifdef CONFIG_TEGRA_GK20A_NVHOST - -#include - -struct nvgpu_nvhost_dev; -struct gk20a; -struct sync_pt; -struct sync_fence; -struct timespec; - -int nvgpu_get_nvhost_dev(struct gk20a *g); -void nvgpu_free_nvhost_dev(struct gk20a *g); - -int nvgpu_nvhost_module_busy_ext(struct nvgpu_nvhost_dev *nvhost_dev); -void nvgpu_nvhost_module_idle_ext(struct nvgpu_nvhost_dev *nvhost_dev); - -void nvgpu_nvhost_debug_dump_device(struct nvgpu_nvhost_dev *nvhost_dev); - -int nvgpu_nvhost_syncpt_is_expired_ext(struct nvgpu_nvhost_dev *nvhost_dev, - u32 id, u32 thresh); -int nvgpu_nvhost_syncpt_wait_timeout_ext(struct nvgpu_nvhost_dev *nvhost_dev, - u32 id, u32 thresh, u32 timeout, u32 *value, struct timespec *ts); - -u32 nvgpu_nvhost_syncpt_incr_max_ext(struct nvgpu_nvhost_dev *nvhost_dev, - u32 id, u32 incrs); -void nvgpu_nvhost_syncpt_set_min_eq_max_ext(struct nvgpu_nvhost_dev *nvhost_dev, - u32 id); -int nvgpu_nvhost_syncpt_read_ext_check(struct nvgpu_nvhost_dev *nvhost_dev, - u32 id, u32 *val); -u32 nvgpu_nvhost_syncpt_read_maxval(struct nvgpu_nvhost_dev *nvhost_dev, - u32 id); -void nvgpu_nvhost_syncpt_set_safe_state( - struct nvgpu_nvhost_dev *nvhost_dev, u32 id); - -int nvgpu_nvhost_intr_register_notifier(struct nvgpu_nvhost_dev *nvhost_dev, - u32 id, u32 thresh, void (*callback)(void *, int), void *private_data); - -const char *nvgpu_nvhost_syncpt_get_name(struct nvgpu_nvhost_dev *nvhost_dev, - int id); -bool nvgpu_nvhost_syncpt_is_valid_pt_ext(struct nvgpu_nvhost_dev *nvhost_dev, - u32 id); -void nvgpu_nvhost_syncpt_put_ref_ext(struct nvgpu_nvhost_dev *nvhost_dev, - u32 id); -u32 nvgpu_nvhost_get_syncpt_host_managed(struct nvgpu_nvhost_dev *nvhost_dev, - u32 param, - const char *syncpt_name); -u32 nvgpu_nvhost_get_syncpt_client_managed(struct nvgpu_nvhost_dev *nvhost_dev, - const char *syncpt_name); - -int nvgpu_nvhost_create_symlink(struct gk20a *g); -void nvgpu_nvhost_remove_symlink(struct gk20a *g); - -#ifdef CONFIG_SYNC -u32 nvgpu_nvhost_sync_pt_id(struct sync_pt *pt); -u32 nvgpu_nvhost_sync_pt_thresh(struct sync_pt *pt); -int nvgpu_nvhost_sync_num_pts(struct sync_fence *fence); - -struct sync_fence *nvgpu_nvhost_sync_fdget(int fd); -struct sync_fence *nvgpu_nvhost_sync_create_fence( - struct nvgpu_nvhost_dev *nvhost_dev, - u32 id, u32 thresh, const char *name); -#endif /* CONFIG_SYNC */ - -#ifdef CONFIG_TEGRA_T19X_GRHOST -int nvgpu_nvhost_syncpt_unit_interface_get_aperture( - struct nvgpu_nvhost_dev *nvhost_dev, - u64 *base, size_t *size); -u32 nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(u32 syncpt_id); -int nvgpu_nvhost_syncpt_init(struct gk20a *g); -#else -static inline int nvgpu_nvhost_syncpt_unit_interface_get_aperture( - struct nvgpu_nvhost_dev *nvhost_dev, - u64 *base, size_t *size) -{ - return -EINVAL; -} -static inline u32 nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(u32 syncpt_id) -{ - return 0; -} -static inline int nvgpu_nvhost_syncpt_init(struct gk20a *g) -{ - return 0; -} -#endif -#endif /* CONFIG_TEGRA_GK20A_NVHOST */ -#endif /* NVGPU_NVHOST_H */ diff --git a/include/nvgpu/nvlink.h b/include/nvgpu/nvlink.h deleted file mode 100644 index a74111c..0000000 --- a/include/nvgpu/nvlink.h +++ /dev/null @@ -1,237 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_NVLINK_H -#define NVGPU_NVLINK_H - -#include - -#ifdef __KERNEL__ -#include -#elif defined(__NVGPU_POSIX__) -#include -#else -#include -#endif - -#define NV_NVLINK_REG_POLL_TIMEOUT_MS 3000 -#define NV_NVLINK_TIMEOUT_DELAY_US 5 - -#define MINION_REG_RD32(g, off) gk20a_readl(g, g->nvlink.minion_base + (off)) -#define MINION_REG_WR32(g, off, v) gk20a_writel(g, g->nvlink.minion_base + (off), (v)) -#define IOCTRL_REG_RD32(g, off) gk20a_readl(g, g->nvlink.ioctrl_base + (off)) -#define IOCTRL_REG_WR32(g, off, v) gk20a_writel(g, g->nvlink.ioctrl_base + (off), (v)) -#define MIF_REG_RD32(g, id, off) gk20a_readl(g, g->nvlink.links[(id)].mif_base + (off)) -#define MIF_REG_WR32(g, id, off, v) gk20a_writel(g, g->nvlink.links[(id)].mif_base + (off), (v)) -#define IPT_REG_RD32(g, off) gk20a_readl(g, g->nvlink.ipt_base + (off)) -#define IPT_REG_WR32(g, off, v) gk20a_writel(g, g->nvlink.ipt_base + (off), (v)) -#define TLC_REG_RD32(g, id, off) gk20a_readl(g, g->nvlink.links[(id)].tl_base + (off)) -#define TLC_REG_WR32(g, id, off, v) gk20a_writel(g, g->nvlink.links[(id)].tl_base + (off), (v)) -#define DLPL_REG_RD32(g, id, off) gk20a_readl(g, g->nvlink.links[(id)].dlpl_base + (off)) -#define DLPL_REG_WR32(g, id, off, v) gk20a_writel(g, g->nvlink.links[(id)].dlpl_base + (off), (v)) - -struct gk20a; - -struct nvgpu_nvlink_ioctrl_list { - bool valid; - u32 pri_base_addr; - u8 intr_enum; - u8 reset_enum; -}; - -struct nvgpu_nvlink_device_list { - bool valid; - u8 device_type; - u8 device_id; - u8 device_version; - u32 pri_base_addr; - u8 intr_enum; - u8 reset_enum; - u8 num_tx; - u8 num_rx; - u8 pll_master; - u8 pll_master_id; -}; - -enum nvgpu_nvlink_endp { - nvgpu_nvlink_endp_gpu, - nvgpu_nvlink_endp_tegra, - nvgpu_nvlink_endp__last, -}; - -enum nvgpu_nvlink_link_mode { - nvgpu_nvlink_link_off, - nvgpu_nvlink_link_hs, - nvgpu_nvlink_link_safe, - nvgpu_nvlink_link_fault, - nvgpu_nvlink_link_rcvy_ac, - nvgpu_nvlink_link_rcvy_sw, - nvgpu_nvlink_link_rcvy_rx, - nvgpu_nvlink_link_detect, - nvgpu_nvlink_link_reset, - nvgpu_nvlink_link_enable_pm, - nvgpu_nvlink_link_disable_pm, - nvgpu_nvlink_link_disable_err_detect, - nvgpu_nvlink_link_lane_disable, - nvgpu_nvlink_link_lane_shutdown, - nvgpu_nvlink_link__last, -}; - -enum nvgpu_nvlink_sublink_mode { - nvgpu_nvlink_sublink_tx_hs, - nvgpu_nvlink_sublink_tx_enable_pm, - nvgpu_nvlink_sublink_tx_disable_pm, - nvgpu_nvlink_sublink_tx_single_lane, - nvgpu_nvlink_sublink_tx_safe, - nvgpu_nvlink_sublink_tx_off, - nvgpu_nvlink_sublink_tx_common, - nvgpu_nvlink_sublink_tx_common_disable, - nvgpu_nvlink_sublink_tx_data_ready, - nvgpu_nvlink_sublink_tx_prbs_en, - nvgpu_nvlink_sublink_tx__last, - /* RX */ - nvgpu_nvlink_sublink_rx_hs, - nvgpu_nvlink_sublink_rx_enable_pm, - nvgpu_nvlink_sublink_rx_disable_pm, - nvgpu_nvlink_sublink_rx_single_lane, - nvgpu_nvlink_sublink_rx_safe, - nvgpu_nvlink_sublink_rx_off, - nvgpu_nvlink_sublink_rx_rxcal, - nvgpu_nvlink_sublink_rx__last, -}; - -struct nvgpu_nvlink_conn_info { - enum nvgpu_nvlink_endp device_type; - u32 link_number; - bool is_connected; -}; - -struct nvgpu_nvlink_link { - bool valid; - struct gk20a *g; - u8 link_id; - - u32 dlpl_base; - u8 dlpl_version; - - u32 tl_base; - u8 tl_version; - - u32 mif_base; - u8 mif_version; - - u8 intr_enum; - u8 reset_enum; - - bool dl_init_done; - - u8 pll_master_link_id; - u8 pll_slave_link_id; - - struct nvgpu_nvlink_conn_info remote_info; - void *priv; -}; - -#define NVLINK_MAX_LINKS_SW 6 - -enum nvgpu_nvlink_speed { - nvgpu_nvlink_speed_25G, - nvgpu_nvlink_speed_20G, - nvgpu_nvlink_speed__last, -}; - -struct nvgpu_nvlink_dev { - struct nvgpu_nvlink_ioctrl_list *ioctrl_table; - u32 io_num_entries; - - struct nvgpu_nvlink_device_list *device_table; - u32 num_devices; - - struct nvgpu_nvlink_link links[NVLINK_MAX_LINKS_SW]; - - u8 dlpl_type; - u32 dlpl_base[NVLINK_MAX_LINKS_SW]; - - u8 tl_type; - u32 tl_base[NVLINK_MAX_LINKS_SW]; - - u8 mif_type; - u32 mif_base[NVLINK_MAX_LINKS_SW]; - - u8 ipt_type; - u32 ipt_base; - u8 ipt_version; - - u8 dlpl_multicast_type; - u8 dlpl_multicast_version; - u32 dlpl_multicast_base; - - u8 tl_multicast_type; - u8 tl_multicast_version; - u32 tl_multicast_base; - - u8 mif_multicast_type; - u8 mif_multicast_version; - u32 mif_multicast_base; - - u8 ioctrl_type; - u32 ioctrl_base; - - u8 minion_type; - u32 minion_base; - u8 minion_version; - - u32 discovered_links; - - /* VBIOS settings */ - u32 link_disable_mask; - u32 link_mode_mask; - u32 link_refclk_mask; - u8 train_at_boot; - u32 ac_coupling_mask; - - u32 connected_links; - u32 initialized_links; - u32 enabled_links; - u32 init_pll_done; - - enum nvgpu_nvlink_speed speed; - - /* tlc cached errors */ - u32 tlc_rx_err_status_0[NVLINK_MAX_LINKS_SW]; - u32 tlc_rx_err_status_1[NVLINK_MAX_LINKS_SW]; - u32 tlc_tx_err_status_0[NVLINK_MAX_LINKS_SW]; - - /* priv struct */ - void *priv; -}; - -int nvgpu_nvlink_enumerate(struct gk20a *g); -int nvgpu_nvlink_train(struct gk20a *g, u32 link_id, bool from_off); -int nvgpu_nvlink_read_dt_props(struct gk20a *g); - -int nvgpu_nvlink_probe(struct gk20a *g); -int nvgpu_nvlink_remove(struct gk20a *g); - -void nvgpu_mss_nvlink_init_credits(struct gk20a *g); - -#endif /* NVGPU_NVLINK_H */ diff --git a/include/nvgpu/os_fence.h b/include/nvgpu/os_fence.h deleted file mode 100644 index 272b076..0000000 --- a/include/nvgpu/os_fence.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * nvgpu os fence - * - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_OS_FENCE_H -#define NVGPU_OS_FENCE_H - -#include - -struct nvgpu_semaphore; -struct channel_gk20a; -struct priv_cmd_entry; -struct nvgpu_nvhost_dev; - -/* - * struct nvgpu_os_fence adds an abstraction to the earlier Android Sync - * Framework, specifically the sync-fence mechanism and the newer DMA sync - * APIs from linux-4.9. This abstraction provides the high-level definition - * as well as APIs that can be used by other OSes in future to have their own - * alternatives for the sync-framework. - */ -struct nvgpu_os_fence; - -/* - * struct nvgpu_os_fence depends on the following ops structure - */ -struct nvgpu_os_fence_ops { - /* - * This API is used to iterate through multiple fence points within the - * fence and program the pushbuffer method for wait command. - */ - int (*program_waits)(struct nvgpu_os_fence *s, - struct priv_cmd_entry *wait_cmd, - struct channel_gk20a *c, - int max_wait_cmds); - - /* - * This should be the last operation on the OS fence. The - * OS fence acts as a place-holder for the underlying fence - * implementation e.g. sync_fences. For each construct/fdget call - * there needs to be a drop_ref call. This reduces a reference count - * for the underlying sync_fence. - */ - void (*drop_ref)(struct nvgpu_os_fence *s); - - /* - * Used to install the fd in the corresponding OS. The underlying - * implementation varies from OS to OS. - */ - void (*install_fence)(struct nvgpu_os_fence *s, int fd); -}; - -/* - * The priv structure here is used to contain the struct sync_fence - * for LINUX_VERSION <= 4.9 and dma_fence for LINUX_VERSION > 4.9 - */ -struct nvgpu_os_fence { - void *priv; - struct gk20a *g; - const struct nvgpu_os_fence_ops *ops; -}; - -/* - * This API is used to validate the nvgpu_os_fence - */ -static inline int nvgpu_os_fence_is_initialized(struct nvgpu_os_fence *fence) -{ - return (fence->ops != NULL); -} - -#ifdef CONFIG_SYNC - -int nvgpu_os_fence_sema_create( - struct nvgpu_os_fence *fence_out, - struct channel_gk20a *c, - struct nvgpu_semaphore *sema); - -int nvgpu_os_fence_fdget( - struct nvgpu_os_fence *fence_out, - struct channel_gk20a *c, int fd); - -#else - -static inline int nvgpu_os_fence_sema_create( - struct nvgpu_os_fence *fence_out, - struct channel_gk20a *c, - struct nvgpu_semaphore *sema) -{ - return -ENOSYS; -} -static inline int nvgpu_os_fence_fdget( - struct nvgpu_os_fence *fence_out, - struct channel_gk20a *c, int fd) -{ - return -ENOSYS; -} - -#endif /* CONFIG_SYNC */ - -#if defined(CONFIG_TEGRA_GK20A_NVHOST) && defined(CONFIG_SYNC) - -int nvgpu_os_fence_syncpt_create(struct nvgpu_os_fence *fence_out, - struct channel_gk20a *c, struct nvgpu_nvhost_dev *nvhost_dev, - u32 id, u32 thresh); - -#else - -static inline int nvgpu_os_fence_syncpt_create( - struct nvgpu_os_fence *fence_out, struct channel_gk20a *c, - struct nvgpu_nvhost_dev *nvhost_dev, - u32 id, u32 thresh) -{ - return -ENOSYS; -} - -#endif /* CONFIG_TEGRA_GK20A_NVHOST && CONFIG_SYNC */ - -#endif /* NVGPU_OS_FENCE_H */ diff --git a/include/nvgpu/os_sched.h b/include/nvgpu/os_sched.h deleted file mode 100644 index c8843b1..0000000 --- a/include/nvgpu/os_sched.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_OS_SCHED_H -#define NVGPU_OS_SCHED_H - -#include - -struct gk20a; - -/** - * nvgpu_current_tid - Query the id of current thread - * - */ -int nvgpu_current_tid(struct gk20a *g); - -/** - * nvgpu_current_pid - Query the id of current process - * - */ -int nvgpu_current_pid(struct gk20a *g); - -void __nvgpu_print_current(struct gk20a *g, const char *func_name, int line, - void *ctx, enum nvgpu_log_type type); -/** - * nvgpu_print_current - print the name of current calling process - * - */ -#define nvgpu_print_current(g, ctx, type) \ - __nvgpu_print_current(g, __func__, __LINE__, ctx, type) - -#endif /* NVGPU_OS_SCHED_H */ diff --git a/include/nvgpu/page_allocator.h b/include/nvgpu/page_allocator.h deleted file mode 100644 index a6e0205..0000000 --- a/include/nvgpu/page_allocator.h +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef PAGE_ALLOCATOR_PRIV_H -#define PAGE_ALLOCATOR_PRIV_H - -#include -#include -#include -#include -#include - -struct nvgpu_allocator; - -/* - * This allocator implements the ability to do SLAB style allocation since the - * GPU has two page sizes available - 4k and 64k/128k. When the default - * granularity is the large page size (64k/128k) small allocations become very - * space inefficient. This is most notable in PDE and PTE blocks which are 4k - * in size. - * - * Thus we need the ability to suballocate in 64k pages. The way we do this for - * the GPU is as follows. We have several buckets for sub-64K allocations: - * - * B0 - 4k - * B1 - 8k - * B3 - 16k - * B4 - 32k - * B5 - 64k (for when large pages are 128k) - * - * When an allocation comes in for less than the large page size (from now on - * assumed to be 64k) the allocation is satisfied by one of the buckets. - */ -struct page_alloc_slab { - struct nvgpu_list_node empty; - struct nvgpu_list_node partial; - struct nvgpu_list_node full; - - int nr_empty; - int nr_partial; - int nr_full; - - u32 slab_size; -}; - -enum slab_page_state { - SP_EMPTY, - SP_PARTIAL, - SP_FULL, - SP_NONE -}; - -struct page_alloc_slab_page { - unsigned long bitmap; - u64 page_addr; - u32 slab_size; - - u32 nr_objects; - u32 nr_objects_alloced; - - enum slab_page_state state; - - struct page_alloc_slab *owner; - struct nvgpu_list_node list_entry; -}; - -static inline struct page_alloc_slab_page * -page_alloc_slab_page_from_list_entry(struct nvgpu_list_node *node) -{ - return (struct page_alloc_slab_page *) - ((uintptr_t)node - offsetof(struct page_alloc_slab_page, list_entry)); -}; - -/* - * Struct to handle internal management of page allocation. It holds a list - * of the chunks of pages that make up the overall allocation - much like a - * scatter gather table. - */ -struct nvgpu_page_alloc { - /* - * nvgpu_sgt for describing the actual allocation. Convenient for - * GMMU mapping. - */ - struct nvgpu_sgt sgt; - - int nr_chunks; - u64 length; - - /* - * Only useful for the RB tree - since the alloc may have discontiguous - * pages the base is essentially irrelevant except for the fact that it - * is guarenteed to be unique. - */ - u64 base; - - struct nvgpu_rbtree_node tree_entry; - - /* - * Set if this is a slab alloc. Points back to the slab page that owns - * this particular allocation. nr_chunks will always be 1 if this is - * set. - */ - struct page_alloc_slab_page *slab_page; -}; - -static inline struct nvgpu_page_alloc * -nvgpu_page_alloc_from_rbtree_node(struct nvgpu_rbtree_node *node) -{ - return (struct nvgpu_page_alloc *) - ((uintptr_t)node - offsetof(struct nvgpu_page_alloc, tree_entry)); -}; - -struct nvgpu_page_allocator { - struct nvgpu_allocator *owner; /* Owner of this allocator. */ - - /* - * Use a buddy allocator to manage the allocation of the underlying - * pages. This lets us abstract the discontiguous allocation handling - * out of the annoyingly complicated buddy allocator. - */ - struct nvgpu_allocator source_allocator; - - /* - * Page params. - */ - u64 base; - u64 length; - u64 page_size; - u32 page_shift; - - struct nvgpu_rbtree_node *allocs; /* Outstanding allocations. */ - - struct page_alloc_slab *slabs; - int nr_slabs; - - struct nvgpu_kmem_cache *alloc_cache; - struct nvgpu_kmem_cache *slab_page_cache; - - u64 flags; - - /* - * Stat tracking. - */ - u64 nr_allocs; - u64 nr_frees; - u64 nr_fixed_allocs; - u64 nr_fixed_frees; - u64 nr_slab_allocs; - u64 nr_slab_frees; - u64 pages_alloced; - u64 pages_freed; -}; - -static inline struct nvgpu_page_allocator *page_allocator( - struct nvgpu_allocator *a) -{ - return (struct nvgpu_page_allocator *)(a)->priv; -} - -static inline struct nvgpu_allocator *palloc_owner( - struct nvgpu_page_allocator *a) -{ - return a->owner; -} - -#endif diff --git a/include/nvgpu/pci.h b/include/nvgpu/pci.h deleted file mode 100644 index b38465a..0000000 --- a/include/nvgpu/pci.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_PCI_H -#define NVGPU_PCI_H - -#ifdef __KERNEL__ -#include -#elif defined(__NVGPU_POSIX__) -#include -#elif defined(__QNX__) -#include -#else -/* - * In case someone tries to use this without implementing support! - */ -#error "Build bug: need PCI headers!" -#endif - -#endif /* NVGPU_PCI_H */ diff --git a/include/nvgpu/pmu.h b/include/nvgpu/pmu.h deleted file mode 100644 index fb1b016..0000000 --- a/include/nvgpu/pmu.h +++ /dev/null @@ -1,545 +0,0 @@ -/* - * Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_PMU_H -#define NVGPU_PMU_H - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define nvgpu_pmu_dbg(g, fmt, args...) \ - nvgpu_log(g, gpu_dbg_pmu, fmt, ##args) - -/* defined by pmu hw spec */ -#define GK20A_PMU_VA_SIZE (512 * 1024 * 1024) -#define GK20A_PMU_UCODE_SIZE_MAX (256 * 1024) -#define GK20A_PMU_SEQ_BUF_SIZE 4096 - -#define GK20A_PMU_TRACE_BUFSIZE 0x4000 /* 4K */ -#define GK20A_PMU_DMEM_BLKSIZE2 8 - -#define PMU_MODE_MISMATCH_STATUS_MAILBOX_R 6 -#define PMU_MODE_MISMATCH_STATUS_VAL 0xDEADDEAD - -/* Falcon Register index */ -#define PMU_FALCON_REG_R0 (0) -#define PMU_FALCON_REG_R1 (1) -#define PMU_FALCON_REG_R2 (2) -#define PMU_FALCON_REG_R3 (3) -#define PMU_FALCON_REG_R4 (4) -#define PMU_FALCON_REG_R5 (5) -#define PMU_FALCON_REG_R6 (6) -#define PMU_FALCON_REG_R7 (7) -#define PMU_FALCON_REG_R8 (8) -#define PMU_FALCON_REG_R9 (9) -#define PMU_FALCON_REG_R10 (10) -#define PMU_FALCON_REG_R11 (11) -#define PMU_FALCON_REG_R12 (12) -#define PMU_FALCON_REG_R13 (13) -#define PMU_FALCON_REG_R14 (14) -#define PMU_FALCON_REG_R15 (15) -#define PMU_FALCON_REG_IV0 (16) -#define PMU_FALCON_REG_IV1 (17) -#define PMU_FALCON_REG_UNDEFINED (18) -#define PMU_FALCON_REG_EV (19) -#define PMU_FALCON_REG_SP (20) -#define PMU_FALCON_REG_PC (21) -#define PMU_FALCON_REG_IMB (22) -#define PMU_FALCON_REG_DMB (23) -#define PMU_FALCON_REG_CSW (24) -#define PMU_FALCON_REG_CCR (25) -#define PMU_FALCON_REG_SEC (26) -#define PMU_FALCON_REG_CTX (27) -#define PMU_FALCON_REG_EXCI (28) -#define PMU_FALCON_REG_RSVD0 (29) -#define PMU_FALCON_REG_RSVD1 (30) -#define PMU_FALCON_REG_RSVD2 (31) -#define PMU_FALCON_REG_SIZE (32) - -/* Choices for pmu_state */ -#define PMU_STATE_OFF 0U /* PMU is off */ -#define PMU_STATE_STARTING 1U /* PMU is on, but not booted */ -#define PMU_STATE_INIT_RECEIVED 2U /* PMU init message received */ -#define PMU_STATE_ELPG_BOOTING 3U /* PMU is booting */ -#define PMU_STATE_ELPG_BOOTED 4U /* ELPG is initialized */ -#define PMU_STATE_LOADING_PG_BUF 5U /* Loading PG buf */ -#define PMU_STATE_LOADING_ZBC 6U /* Loading ZBC buf */ -#define PMU_STATE_STARTED 7U /* Fully unitialized */ -#define PMU_STATE_EXIT 8U /* Exit PMU state machine */ - -/* state transition : - * OFF => [OFF_ON_PENDING optional] => ON_PENDING => ON => OFF - * ON => OFF is always synchronized - */ -/* elpg is off */ -#define PMU_ELPG_STAT_OFF 0U -/* elpg is on */ -#define PMU_ELPG_STAT_ON 1U -/* elpg is off, ALLOW cmd has been sent, wait for ack */ -#define PMU_ELPG_STAT_ON_PENDING 2U -/* elpg is on, DISALLOW cmd has been sent, wait for ack */ -#define PMU_ELPG_STAT_OFF_PENDING 3U -/* elpg is off, caller has requested on, but ALLOW - * cmd hasn't been sent due to ENABLE_ALLOW delay - */ -#define PMU_ELPG_STAT_OFF_ON_PENDING 4U - -#define GK20A_PMU_UCODE_NB_MAX_OVERLAY 32U -#define GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH 64U - -#define PMU_MAX_NUM_SEQUENCES (256U) -#define PMU_SEQ_BIT_SHIFT (5U) -#define PMU_SEQ_TBL_SIZE \ - (PMU_MAX_NUM_SEQUENCES >> PMU_SEQ_BIT_SHIFT) - -#define PMU_INVALID_SEQ_DESC (~0) - -enum { - GK20A_PMU_DMAIDX_UCODE = 0, - GK20A_PMU_DMAIDX_VIRT = 1, - GK20A_PMU_DMAIDX_PHYS_VID = 2, - GK20A_PMU_DMAIDX_PHYS_SYS_COH = 3, - GK20A_PMU_DMAIDX_PHYS_SYS_NCOH = 4, - GK20A_PMU_DMAIDX_RSVD = 5, - GK20A_PMU_DMAIDX_PELPG = 6, - GK20A_PMU_DMAIDX_END = 7 -}; - -enum { - PMU_SEQ_STATE_FREE = 0, - PMU_SEQ_STATE_PENDING, - PMU_SEQ_STATE_USED, - PMU_SEQ_STATE_CANCELLED -}; - -/*PG defines used by nvpgu-pmu*/ -#define PMU_PG_IDLE_THRESHOLD_SIM 1000 -#define PMU_PG_POST_POWERUP_IDLE_THRESHOLD_SIM 4000000 -/* TBD: QT or else ? */ -#define PMU_PG_IDLE_THRESHOLD 15000 -#define PMU_PG_POST_POWERUP_IDLE_THRESHOLD 1000000 - -#define PMU_PG_LPWR_FEATURE_RPPG 0x0 -#define PMU_PG_LPWR_FEATURE_MSCG 0x1 - -#define PMU_MSCG_DISABLED 0U -#define PMU_MSCG_ENABLED 1U - -/* Default Sampling Period of AELPG */ -#define APCTRL_SAMPLING_PERIOD_PG_DEFAULT_US (1000000) - -/* Default values of APCTRL parameters */ -#define APCTRL_MINIMUM_IDLE_FILTER_DEFAULT_US (100) -#define APCTRL_MINIMUM_TARGET_SAVING_DEFAULT_US (10000) -#define APCTRL_POWER_BREAKEVEN_DEFAULT_US (2000) -#define APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT (200) - -/* pmu load const defines */ -#define PMU_BUSY_CYCLES_NORM_MAX (1000U) - -/* RPC */ -#define PMU_RPC_EXECUTE(_stat, _pmu, _unit, _func, _prpc, _size)\ - do { \ - memset(&((_prpc)->hdr), 0, sizeof((_prpc)->hdr));\ - \ - (_prpc)->hdr.unit_id = PMU_UNIT_##_unit; \ - (_prpc)->hdr.function = NV_PMU_RPC_ID_##_unit##_##_func;\ - (_prpc)->hdr.flags = 0x0; \ - \ - _stat = nvgpu_pmu_rpc_execute(_pmu, &((_prpc)->hdr), \ - (sizeof(*(_prpc)) - sizeof((_prpc)->scratch)),\ - (_size), NULL, NULL, false); \ - } while (0) - -/* RPC blocking call to copy back data from PMU to _prpc */ -#define PMU_RPC_EXECUTE_CPB(_stat, _pmu, _unit, _func, _prpc, _size)\ - do { \ - memset(&((_prpc)->hdr), 0, sizeof((_prpc)->hdr));\ - \ - (_prpc)->hdr.unit_id = PMU_UNIT_##_unit; \ - (_prpc)->hdr.function = NV_PMU_RPC_ID_##_unit##_##_func;\ - (_prpc)->hdr.flags = 0x0; \ - \ - _stat = nvgpu_pmu_rpc_execute(_pmu, &((_prpc)->hdr), \ - (sizeof(*(_prpc)) - sizeof((_prpc)->scratch)),\ - (_size), NULL, NULL, true); \ - } while (0) - -/* RPC non-blocking with call_back handler option */ -#define PMU_RPC_EXECUTE_CB(_stat, _pmu, _unit, _func, _prpc, _size, _cb, _cbp)\ - do { \ - memset(&((_prpc)->hdr), 0, sizeof((_prpc)->hdr));\ - \ - (_prpc)->hdr.unit_id = PMU_UNIT_##_unit; \ - (_prpc)->hdr.function = NV_PMU_RPC_ID_##_unit##_##_func;\ - (_prpc)->hdr.flags = 0x0; \ - \ - _stat = nvgpu_pmu_rpc_execute(_pmu, &((_prpc)->hdr), \ - (sizeof(*(_prpc)) - sizeof((_prpc)->scratch)),\ - (_size), _cb, _cbp, false); \ - } while (0) - -typedef void (*pmu_callback)(struct gk20a *, struct pmu_msg *, void *, u32, - u32); - -struct rpc_handler_payload { - void *rpc_buff; - bool is_mem_free_set; - bool complete; -}; - -struct pmu_rpc_desc { - void *prpc; - u16 size_rpc; - u16 size_scratch; -}; - -struct pmu_payload { - struct { - void *buf; - u32 offset; - u32 size; - u32 fb_size; - } in, out; - struct pmu_rpc_desc rpc; -}; - -struct pmu_ucode_desc { - u32 descriptor_size; - u32 image_size; - u32 tools_version; - u32 app_version; - char date[GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH]; - u32 bootloader_start_offset; - u32 bootloader_size; - u32 bootloader_imem_offset; - u32 bootloader_entry_point; - u32 app_start_offset; - u32 app_size; - u32 app_imem_offset; - u32 app_imem_entry; - u32 app_dmem_offset; - /* Offset from appStartOffset */ - u32 app_resident_code_offset; - /* Exact size of the resident code - * ( potentially contains CRC inside at the end ) - */ - u32 app_resident_code_size; - /* Offset from appStartOffset */ - u32 app_resident_data_offset; - /* Exact size of the resident code - * ( potentially contains CRC inside at the end ) - */ - u32 app_resident_data_size; - u32 nb_overlays; - struct {u32 start; u32 size; } load_ovl[GK20A_PMU_UCODE_NB_MAX_OVERLAY]; - u32 compressed; -}; - -struct pmu_ucode_desc_v1 { - u32 descriptor_size; - u32 image_size; - u32 tools_version; - u32 app_version; - char date[GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH]; - u32 bootloader_start_offset; - u32 bootloader_size; - u32 bootloader_imem_offset; - u32 bootloader_entry_point; - u32 app_start_offset; - u32 app_size; - u32 app_imem_offset; - u32 app_imem_entry; - u32 app_dmem_offset; - u32 app_resident_code_offset; - u32 app_resident_code_size; - u32 app_resident_data_offset; - u32 app_resident_data_size; - u32 nb_imem_overlays; - u32 nb_dmem_overlays; - struct {u32 start; u32 size; } load_ovl[64]; - u32 compressed; -}; - -struct pmu_mutex { - u32 id; - u32 index; - u32 ref_cnt; -}; - -struct pmu_sequence { - u8 id; - u32 state; - u32 desc; - struct pmu_msg *msg; - union { - struct pmu_allocation_v1 in_v1; - struct pmu_allocation_v2 in_v2; - struct pmu_allocation_v3 in_v3; - }; - struct nvgpu_mem *in_mem; - union { - struct pmu_allocation_v1 out_v1; - struct pmu_allocation_v2 out_v2; - struct pmu_allocation_v3 out_v3; - }; - struct nvgpu_mem *out_mem; - u8 *out_payload; - pmu_callback callback; - void *cb_params; -}; - -struct nvgpu_pg_init { - bool state_change; - bool state_destroy; - struct nvgpu_cond wq; - struct nvgpu_thread state_task; -}; - -struct nvgpu_pmu { - struct gk20a *g; - struct nvgpu_falcon *flcn; - - union { - struct pmu_ucode_desc *desc; - struct pmu_ucode_desc_v1 *desc_v1; - }; - struct nvgpu_mem ucode; - - struct nvgpu_mem pg_buf; - - /* TBD: remove this if ZBC seq is fixed */ - struct nvgpu_mem seq_buf; - struct nvgpu_mem trace_buf; - struct nvgpu_mem super_surface_buf; - - bool buf_loaded; - - struct pmu_sha1_gid gid_info; - - struct nvgpu_falcon_queue queue[PMU_QUEUE_COUNT]; - - struct pmu_sequence *seq; - unsigned long pmu_seq_tbl[PMU_SEQ_TBL_SIZE]; - u32 next_seq_desc; - - struct pmu_mutex *mutex; - u32 mutex_cnt; - - struct nvgpu_mutex pmu_copy_lock; - struct nvgpu_mutex pmu_seq_lock; - - struct nvgpu_allocator dmem; - - u32 *ucode_image; - bool pmu_ready; - - u32 perfmon_query; - - u32 zbc_save_done; - - u32 stat_dmem_offset[PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE]; - - u32 elpg_stat; - u32 disallow_state; - - u32 mscg_stat; - u32 mscg_transition_state; - - u32 pmu_state; - -#define PMU_ELPG_ENABLE_ALLOW_DELAY_MSEC 1 /* msec */ - struct nvgpu_pg_init pg_init; - struct nvgpu_mutex pg_mutex; /* protect pg-RPPG/MSCG enable/disable */ - struct nvgpu_mutex elpg_mutex; /* protect elpg enable/disable */ - /* disable -1, enable +1, <=0 elpg disabled, > 0 elpg enabled */ - int elpg_refcnt; - - union { - struct pmu_perfmon_counter_v2 perfmon_counter_v2; - }; - u32 perfmon_state_id[PMU_DOMAIN_GROUP_NUM]; - - bool initialized; - - void (*remove_support)(struct nvgpu_pmu *pmu); - bool sw_ready; - bool perfmon_ready; - - u32 sample_buffer; - u32 load_shadow; - u32 load_avg; - u32 load; - - struct nvgpu_mutex isr_mutex; - bool isr_enabled; - - bool zbc_ready; - union { - struct pmu_cmdline_args_v3 args_v3; - struct pmu_cmdline_args_v4 args_v4; - struct pmu_cmdline_args_v5 args_v5; - struct pmu_cmdline_args_v6 args_v6; - }; - unsigned long perfmon_events_cnt; - bool perfmon_sampling_enabled; - u8 pmu_mode; /*Added for GM20b, and ACR*/ - u32 falcon_id; - u32 aelpg_param[5]; - u32 override_done; - - struct nvgpu_firmware *fw; -}; - -struct pmu_surface { - struct nvgpu_mem vidmem_desc; - struct nvgpu_mem sysmem_desc; - struct flcn_mem_desc_v0 params; -}; - -/*PG defines used by nvpgu-pmu*/ -struct pmu_pg_stats_data { - u32 gating_cnt; - u32 ingating_time; - u32 ungating_time; - u32 avg_entry_latency_us; - u32 avg_exit_latency_us; -}; - -/*! - * Structure/object which single register write need to be done during PG init - * sequence to set PROD values. - */ -struct pg_init_sequence_list { - u32 regaddr; - u32 writeval; -}; - -/* PMU IPC Methods */ -void nvgpu_pmu_seq_init(struct nvgpu_pmu *pmu); - -int nvgpu_pmu_mutex_acquire(struct nvgpu_pmu *pmu, u32 id, u32 *token); -int nvgpu_pmu_mutex_release(struct nvgpu_pmu *pmu, u32 id, u32 *token); - -int nvgpu_pmu_queue_init(struct nvgpu_pmu *pmu, u32 id, - union pmu_init_msg_pmu *init); - -/* send a cmd to pmu */ -int nvgpu_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd, - struct pmu_msg *msg, struct pmu_payload *payload, - u32 queue_id, pmu_callback callback, void *cb_param, - u32 *seq_desc, unsigned long timeout); - -int nvgpu_pmu_process_message(struct nvgpu_pmu *pmu); - -/* perfmon */ -int nvgpu_pmu_init_perfmon(struct nvgpu_pmu *pmu); -int nvgpu_pmu_perfmon_start_sampling(struct nvgpu_pmu *pmu); -int nvgpu_pmu_perfmon_stop_sampling(struct nvgpu_pmu *pmu); -int nvgpu_pmu_perfmon_start_sampling_rpc(struct nvgpu_pmu *pmu); -int nvgpu_pmu_perfmon_stop_sampling_rpc(struct nvgpu_pmu *pmu); -int nvgpu_pmu_perfmon_get_samples_rpc(struct nvgpu_pmu *pmu); -int nvgpu_pmu_handle_perfmon_event(struct nvgpu_pmu *pmu, - struct pmu_perfmon_msg *msg); -int nvgpu_pmu_init_perfmon_rpc(struct nvgpu_pmu *pmu); -int nvgpu_pmu_load_norm(struct gk20a *g, u32 *load); -int nvgpu_pmu_load_update(struct gk20a *g); -int nvgpu_pmu_busy_cycles_norm(struct gk20a *g, u32 *norm); -void nvgpu_pmu_reset_load_counters(struct gk20a *g); -void nvgpu_pmu_get_load_counters(struct gk20a *g, u32 *busy_cycles, - u32 *total_cycles); - -int nvgpu_pmu_handle_therm_event(struct nvgpu_pmu *pmu, - struct nv_pmu_therm_msg *msg); - -/* PMU init */ -int nvgpu_init_pmu_support(struct gk20a *g); -int nvgpu_pmu_destroy(struct gk20a *g); -int nvgpu_pmu_process_init_msg(struct nvgpu_pmu *pmu, - struct pmu_msg *msg); -int nvgpu_pmu_super_surface_alloc(struct gk20a *g, - struct nvgpu_mem *mem_surface, u32 size); - -void nvgpu_pmu_state_change(struct gk20a *g, u32 pmu_state, - bool post_change_event); -void nvgpu_kill_task_pg_init(struct gk20a *g); - -/* NVGPU-PMU MEM alloc */ -void nvgpu_pmu_surface_free(struct gk20a *g, struct nvgpu_mem *mem); -void nvgpu_pmu_surface_describe(struct gk20a *g, struct nvgpu_mem *mem, - struct flcn_mem_desc_v0 *fb); -int nvgpu_pmu_vidmem_surface_alloc(struct gk20a *g, struct nvgpu_mem *mem, - u32 size); -int nvgpu_pmu_sysmem_surface_alloc(struct gk20a *g, struct nvgpu_mem *mem, - u32 size); - -/* PMU F/W support */ -int nvgpu_init_pmu_fw_support(struct nvgpu_pmu *pmu); -int nvgpu_pmu_prepare_ns_ucode_blob(struct gk20a *g); - -/* PG init*/ -int nvgpu_pmu_init_powergating(struct gk20a *g); -int nvgpu_pmu_init_bind_fecs(struct gk20a *g); -void nvgpu_pmu_setup_hw_load_zbc(struct gk20a *g); - -/* PMU reset */ -int nvgpu_pmu_reset(struct gk20a *g); - -/* PG enable/disable */ -int nvgpu_pmu_reenable_elpg(struct gk20a *g); -int nvgpu_pmu_enable_elpg(struct gk20a *g); -int nvgpu_pmu_disable_elpg(struct gk20a *g); -int nvgpu_pmu_pg_global_enable(struct gk20a *g, u32 enable_pg); - -int nvgpu_pmu_get_pg_stats(struct gk20a *g, u32 pg_engine_id, - struct pmu_pg_stats_data *pg_stat_data); - -/* AELPG */ -int nvgpu_aelpg_init(struct gk20a *g); -int nvgpu_aelpg_init_and_enable(struct gk20a *g, u8 ctrl_id); -int nvgpu_pmu_ap_send_command(struct gk20a *g, - union pmu_ap_cmd *p_ap_cmd, bool b_block); - -/* PMU debug */ -void nvgpu_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu); -void nvgpu_pmu_dump_elpg_stats(struct nvgpu_pmu *pmu); -bool nvgpu_find_hex_in_string(char *strings, struct gk20a *g, u32 *hex_pos); - -/* PMU RPC */ -int nvgpu_pmu_rpc_execute(struct nvgpu_pmu *pmu, struct nv_pmu_rpc_header *rpc, - u16 size_rpc, u16 size_scratch, pmu_callback callback, void *cb_param, - bool is_copy_back); - -/* PMU wait*/ -int pmu_wait_message_cond(struct nvgpu_pmu *pmu, u32 timeout_ms, - void *var, u8 val); - -struct gk20a *gk20a_from_pmu(struct nvgpu_pmu *pmu); -#endif /* NVGPU_PMU_H */ diff --git a/include/nvgpu/pmuif/gpmu_super_surf_if.h b/include/nvgpu/pmuif/gpmu_super_surf_if.h deleted file mode 100644 index b0f9e10..0000000 --- a/include/nvgpu/pmuif/gpmu_super_surf_if.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_PMUIF_GPMU_SUPER_SURF_IF_H -#define NVGPU_PMUIF_GPMU_SUPER_SURF_IF_H - -struct nv_pmu_super_surface_hdr { - u32 memberMask; - u16 dmemBufferSizeMax; -}; - -NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_super_surface_hdr, - sizeof(struct nv_pmu_super_surface_hdr)); - -/* - * Global Super Surface structure for combined INIT data required by PMU. - * NOTE: Any new substructures or entries must be aligned. - */ -struct nv_pmu_super_surface { - union nv_pmu_super_surface_hdr_aligned hdr; - - struct { - struct nv_pmu_volt_volt_device_boardobj_grp_set volt_device_grp_set; - struct nv_pmu_volt_volt_policy_boardobj_grp_set volt_policy_grp_set; - struct nv_pmu_volt_volt_rail_boardobj_grp_set volt_rail_grp_set; - - struct nv_pmu_volt_volt_policy_boardobj_grp_get_status volt_policy_grp_get_status; - struct nv_pmu_volt_volt_rail_boardobj_grp_get_status volt_rail_grp_get_status; - struct nv_pmu_volt_volt_device_boardobj_grp_get_status volt_device_grp_get_status; - } volt; - struct { - struct nv_pmu_clk_clk_vin_device_boardobj_grp_set clk_vin_device_grp_set; - struct nv_pmu_clk_clk_domain_boardobj_grp_set clk_domain_grp_set; - struct nv_pmu_clk_clk_freq_controller_boardobj_grp_set clk_freq_controller_grp_set; - u8 clk_rsvd2[0x200]; - struct nv_pmu_clk_clk_fll_device_boardobj_grp_set clk_fll_device_grp_set; - struct nv_pmu_clk_clk_prog_boardobj_grp_set clk_prog_grp_set; - struct nv_pmu_clk_clk_vf_point_boardobj_grp_set clk_vf_point_grp_set; - struct nv_pmu_clk_clk_vin_device_boardobj_grp_get_status clk_vin_device_grp_get_status; - struct nv_pmu_clk_clk_fll_device_boardobj_grp_get_status clk_fll_device_grp_get_status; - struct nv_pmu_clk_clk_vf_point_boardobj_grp_get_status clk_vf_point_grp_get_status; - u8 clk_rsvd[0x4660]; - } clk; - struct { - struct nv_pmu_perf_vfe_equ_boardobj_grp_set vfe_equ_grp_set; - struct nv_pmu_perf_vfe_var_boardobj_grp_set vfe_var_grp_set; - - struct nv_pmu_perf_vfe_var_boardobj_grp_get_status vfe_var_grp_get_status; - u8 perf_rsvd[0x40790]; - u8 perfcf_rsvd[0x1eb0]; - } perf; - struct { - struct nv_pmu_therm_therm_channel_boardobj_grp_set therm_channel_grp_set; - struct nv_pmu_therm_therm_device_boardobj_grp_set therm_device_grp_set; - u8 therm_rsvd[0x1460]; - } therm; -}; - -#endif /* NVGPU_PMUIF_GPMU_SUPER_SURF_IF_H */ diff --git a/include/nvgpu/pmuif/gpmuif_acr.h b/include/nvgpu/pmuif/gpmuif_acr.h deleted file mode 100644 index c305589..0000000 --- a/include/nvgpu/pmuif/gpmuif_acr.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_PMUIF_GPMUIF_ACR_H -#define NVGPU_PMUIF_GPMUIF_ACR_H - -/* ACR Commands/Message structures */ - -enum { - PMU_ACR_CMD_ID_INIT_WPR_REGION = 0x0, - PMU_ACR_CMD_ID_BOOTSTRAP_FALCON, - PMU_ACR_CMD_ID_RESERVED, - PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS, -}; - -/* - * Initializes the WPR region details - */ -struct pmu_acr_cmd_init_wpr_details { - u8 cmd_type; - u32 regionid; - u32 wproffset; - -}; - -/* - * falcon ID to bootstrap - */ -struct pmu_acr_cmd_bootstrap_falcon { - u8 cmd_type; - u32 flags; - u32 falconid; -}; - -/* - * falcon ID to bootstrap - */ -struct pmu_acr_cmd_bootstrap_multiple_falcons { - u8 cmd_type; - u32 flags; - u32 falconidmask; - u32 usevamask; - struct falc_u64 wprvirtualbase; -}; - -#define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_NO 1 -#define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0 - - -struct pmu_acr_cmd { - union { - u8 cmd_type; - struct pmu_acr_cmd_bootstrap_falcon bootstrap_falcon; - struct pmu_acr_cmd_init_wpr_details init_wpr; - struct pmu_acr_cmd_bootstrap_multiple_falcons boot_falcons; - }; -}; - -/* acr messages */ - -/* - * returns the WPR region init information - */ -#define PMU_ACR_MSG_ID_INIT_WPR_REGION 0 - -/* - * Returns the Bootstrapped falcon ID to RM - */ -#define PMU_ACR_MSG_ID_BOOTSTRAP_FALCON 1 - -/* - * Returns the WPR init status - */ -#define PMU_ACR_SUCCESS 0 -#define PMU_ACR_ERROR 1 - -/* - * PMU notifies about bootstrap status of falcon - */ -struct pmu_acr_msg_bootstrap_falcon { - u8 msg_type; - union { - u32 errorcode; - u32 falconid; - }; -}; - -struct pmu_acr_msg { - union { - u8 msg_type; - struct pmu_acr_msg_bootstrap_falcon acrmsg; - }; -}; - -/* ACR RPC */ -#define NV_PMU_RPC_ID_ACR_INIT_WPR_REGION 0x00 -#define NV_PMU_RPC_ID_ACR_WRITE_CBC_BASE 0x01 -#define NV_PMU_RPC_ID_ACR_BOOTSTRAP_FALCON 0x02 -#define NV_PMU_RPC_ID_ACR_BOOTSTRAP_GR_FALCONS 0x03 -#define NV_PMU_RPC_ID_ACR__COUNT 0x04 - -/* - * structure that holds data used - * to execute INIT_WPR_REGION RPC. - */ -struct nv_pmu_rpc_struct_acr_init_wpr_region { - /*[IN/OUT] Must be first field in RPC structure */ - struct nv_pmu_rpc_header hdr; - /*[IN] ACR region ID of WPR region */ - u32 wpr_regionId; - /* [IN] WPR offset from startAddress */ - u32 wpr_offset; - u32 scratch[1]; -}; - -/* - * structure that holds data used to - * execute BOOTSTRAP_GR_FALCONS RPC. - */ -struct nv_pmu_rpc_struct_acr_bootstrap_gr_falcons { - /*[IN/OUT] Must be first field in RPC structure */ - struct nv_pmu_rpc_header hdr; - /* [IN] Mask of falcon IDs @ref LSF_FALCON_ID_ */ - u32 falcon_id_mask; - /* - * [IN] Boostrapping flags @ref - * PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_ - */ - u32 flags; - /* [IN] Indicate whether the particular falon uses VA */ - u32 falcon_va_mask; - /* - * [IN] WPR Base Address in VA. The Inst Block containing - * this VA should be bound to both PMU and GR falcons - * during the falcon boot - */ - struct falc_u64 wpr_base_virtual; - u32 scratch[1]; -}; - -#endif /* NVGPU_PMUIF_GPMUIF_ACR_H */ diff --git a/include/nvgpu/pmuif/gpmuif_ap.h b/include/nvgpu/pmuif/gpmuif_ap.h deleted file mode 100644 index 776fce8..0000000 --- a/include/nvgpu/pmuif/gpmuif_ap.h +++ /dev/null @@ -1,256 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_PMUIF_GPMUIF_AP_H -#define NVGPU_PMUIF_GPMUIF_AP_H - -/* PMU Command/Message Interfaces for Adaptive Power */ -/* Macro to get Histogram index */ -#define PMU_AP_HISTOGRAM(idx) (idx) -#define PMU_AP_HISTOGRAM_CONT (4) - -/* Total number of histogram bins */ -#define PMU_AP_CFG_HISTOGRAM_BIN_N (16) - -/* Mapping between Idle counters and histograms */ -#define PMU_AP_IDLE_MASK_HIST_IDX_0 (2) -#define PMU_AP_IDLE_MASK_HIST_IDX_1 (3) -#define PMU_AP_IDLE_MASK_HIST_IDX_2 (5) -#define PMU_AP_IDLE_MASK_HIST_IDX_3 (6) - - -/* Mapping between AP_CTRLs and Histograms */ -#define PMU_AP_HISTOGRAM_IDX_GRAPHICS (PMU_AP_HISTOGRAM(1)) - -/* Mapping between AP_CTRLs and Idle counters */ -#define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1) - -/* Adaptive Power Controls (AP_CTRL) */ -enum { - PMU_AP_CTRL_ID_GRAPHICS = 0x0, - PMU_AP_CTRL_ID_MAX, -}; - -/* AP_CTRL Statistics */ -struct pmu_ap_ctrl_stat { - /* - * Represents whether AP is active or not - */ - u8 b_active; - - /* Idle filter represented by histogram bin index */ - u8 idle_filter_x; - u8 rsvd[2]; - - /* Total predicted power saving cycles. */ - s32 power_saving_h_cycles; - - /* Counts how many times AP gave us -ve power benefits. */ - u32 bad_decision_count; - - /* - * Number of times ap structure needs to skip AP iterations - * KICK_CTRL from kernel updates this parameter. - */ - u32 skip_count; - u8 bin[PMU_AP_CFG_HISTOGRAM_BIN_N]; -}; - -/* Parameters initialized by INITn APCTRL command */ -struct pmu_ap_ctrl_init_params { - /* Minimum idle filter value in Us */ - u32 min_idle_filter_us; - - /* - * Minimum Targeted Saving in Us. AP will update idle thresholds only - * if power saving achieved by updating idle thresholds is greater than - * Minimum targeted saving. - */ - u32 min_target_saving_us; - - /* Minimum targeted residency of power feature in Us */ - u32 power_break_even_us; - - /* - * Maximum number of allowed power feature cycles per sample. - * - * We are allowing at max "pgPerSampleMax" cycles in one iteration of AP - * AKA pgPerSampleMax in original algorithm. - */ - u32 cycles_per_sample_max; -}; - -/* AP Commands/Message structures */ - -/* - * Structure for Generic AP Commands - */ -struct pmu_ap_cmd_common { - u8 cmd_type; - u16 cmd_id; -}; - -/* - * Structure for INIT AP command - */ -struct pmu_ap_cmd_init { - u8 cmd_type; - u16 cmd_id; - u8 rsvd; - u32 pg_sampling_period_us; -}; - -/* - * Structure for Enable/Disable ApCtrl Commands - */ -struct pmu_ap_cmd_enable_ctrl { - u8 cmd_type; - u16 cmd_id; - - u8 ctrl_id; -}; - -struct pmu_ap_cmd_disable_ctrl { - u8 cmd_type; - u16 cmd_id; - - u8 ctrl_id; -}; - -/* - * Structure for INIT command - */ -struct pmu_ap_cmd_init_ctrl { - u8 cmd_type; - u16 cmd_id; - u8 ctrl_id; - struct pmu_ap_ctrl_init_params params; -}; - -struct pmu_ap_cmd_init_and_enable_ctrl { - u8 cmd_type; - u16 cmd_id; - u8 ctrl_id; - struct pmu_ap_ctrl_init_params params; -}; - -/* - * Structure for KICK_CTRL command - */ -struct pmu_ap_cmd_kick_ctrl { - u8 cmd_type; - u16 cmd_id; - u8 ctrl_id; - - u32 skip_count; -}; - -/* - * Structure for PARAM command - */ -struct pmu_ap_cmd_param { - u8 cmd_type; - u16 cmd_id; - u8 ctrl_id; - - u32 data; -}; - -/* - * Defines for AP commands - */ -enum { - PMU_AP_CMD_ID_INIT = 0x0, - PMU_AP_CMD_ID_INIT_AND_ENABLE_CTRL, - PMU_AP_CMD_ID_ENABLE_CTRL, - PMU_AP_CMD_ID_DISABLE_CTRL, - PMU_AP_CMD_ID_KICK_CTRL, -}; - -/* - * AP Command - */ -union pmu_ap_cmd { - u8 cmd_type; - struct pmu_ap_cmd_common cmn; - struct pmu_ap_cmd_init init; - struct pmu_ap_cmd_init_and_enable_ctrl init_and_enable_ctrl; - struct pmu_ap_cmd_enable_ctrl enable_ctrl; - struct pmu_ap_cmd_disable_ctrl disable_ctrl; - struct pmu_ap_cmd_kick_ctrl kick_ctrl; -}; - -/* - * Structure for generic AP Message - */ -struct pmu_ap_msg_common { - u8 msg_type; - u16 msg_id; -}; - -/* - * Structure for INIT_ACK Message - */ -struct pmu_ap_msg_init_ack { - u8 msg_type; - u16 msg_id; - u8 ctrl_id; - u32 stats_dmem_offset; -}; - -/* - * Defines for AP messages - */ -enum { - PMU_AP_MSG_ID_INIT_ACK = 0x0, -}; - -/* - * AP Message - */ -union pmu_ap_msg { - u8 msg_type; - struct pmu_ap_msg_common cmn; - struct pmu_ap_msg_init_ack init_ack; -}; - -/* - * Adaptive Power Controller - */ -struct ap_ctrl { - u32 stats_dmem_offset; - u32 disable_reason_mask; - struct pmu_ap_ctrl_stat stat_cache; - u8 b_ready; -}; - -/* - * Adaptive Power structure - * - * ap structure provides generic infrastructure to make any power feature - * adaptive. - */ -struct pmu_ap { - u32 supported_mask; - struct ap_ctrl ap_ctrl[PMU_AP_CTRL_ID_MAX]; -}; - -#endif /* NVGPU_PMUIF_GPMUIF_AP_H*/ diff --git a/include/nvgpu/pmuif/gpmuif_cmn.h b/include/nvgpu/pmuif/gpmuif_cmn.h deleted file mode 100644 index 0989754..0000000 --- a/include/nvgpu/pmuif/gpmuif_cmn.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_PMUIF_GPMUIF_CMN_H -#define NVGPU_PMUIF_GPMUIF_CMN_H - -/* - * Defines the logical queue IDs that must be used when submitting - * commands to the PMU - */ -/* write by sw, read by pmu, protected by sw mutex lock */ -#define PMU_COMMAND_QUEUE_HPQ 0U -/* write by sw, read by pmu, protected by sw mutex lock */ -#define PMU_COMMAND_QUEUE_LPQ 1U -/* write by pmu, read by sw, accessed by interrupt handler, no lock */ -#define PMU_MESSAGE_QUEUE 4U -#define PMU_QUEUE_COUNT 5U - -#define PMU_IS_COMMAND_QUEUE(id) \ - ((id) < PMU_MESSAGE_QUEUE) - -#define PMU_IS_SW_COMMAND_QUEUE(id) \ - (((id) == PMU_COMMAND_QUEUE_HPQ) || \ - ((id) == PMU_COMMAND_QUEUE_LPQ)) - -#define PMU_IS_MESSAGE_QUEUE(id) \ - ((id) == PMU_MESSAGE_QUEUE) - -#define OFLAG_READ 0U -#define OFLAG_WRITE 1U - -#define QUEUE_SET (true) -#define QUEUE_GET (false) - -#define QUEUE_ALIGNMENT (4U) - -/* An enumeration containing all valid logical mutex identifiers */ -enum { - PMU_MUTEX_ID_RSVD1 = 0, - PMU_MUTEX_ID_GPUSER, - PMU_MUTEX_ID_QUEUE_BIOS, - PMU_MUTEX_ID_QUEUE_SMI, - PMU_MUTEX_ID_GPMUTEX, - PMU_MUTEX_ID_I2C, - PMU_MUTEX_ID_RMLOCK, - PMU_MUTEX_ID_MSGBOX, - PMU_MUTEX_ID_FIFO, - PMU_MUTEX_ID_PG, - PMU_MUTEX_ID_GR, - PMU_MUTEX_ID_CLK, - PMU_MUTEX_ID_RSVD6, - PMU_MUTEX_ID_RSVD7, - PMU_MUTEX_ID_RSVD8, - PMU_MUTEX_ID_RSVD9, - PMU_MUTEX_ID_INVALID -}; - -#define PMU_MUTEX_ID_IS_VALID(id) \ - ((id) < PMU_MUTEX_ID_INVALID) - -#define PMU_INVALID_MUTEX_OWNER_ID (0) - -/* - * The PMU's frame-buffer interface block has several slots/indices - * which can be bound to support DMA to various surfaces in memory - */ -enum { - PMU_DMAIDX_UCODE = 0, - PMU_DMAIDX_VIRT = 1, - PMU_DMAIDX_PHYS_VID = 2, - PMU_DMAIDX_PHYS_SYS_COH = 3, - PMU_DMAIDX_PHYS_SYS_NCOH = 4, - PMU_DMAIDX_RSVD = 5, - PMU_DMAIDX_PELPG = 6, - PMU_DMAIDX_END = 7 -}; - -/* - * Falcon PMU DMA's minimum size in bytes. - */ -#define PMU_DMA_MIN_READ_SIZE_BYTES 16 -#define PMU_DMA_MIN_WRITE_SIZE_BYTES 4 - -#define PMU_FB_COPY_RW_ALIGNMENT \ - ((PMU_DMA_MIN_READ_SIZE_BYTES > PMU_DMA_MIN_WRITE_SIZE_BYTES) ? \ - PMU_DMA_MIN_READ_SIZE_BYTES : PMU_DMA_MIN_WRITE_SIZE_BYTES) - -/* - * Macros to make aligned versions of RM_PMU_XXX structures. PMU needs aligned - * data structures to issue DMA read/write operations. - */ -#define NV_PMU_MAKE_ALIGNED_STRUCT(name, size) \ -union name##_aligned { \ - struct name data; \ - u8 pad[ALIGN_UP(sizeof(struct name), \ - (PMU_FB_COPY_RW_ALIGNMENT))]; \ -} - -#define NV_PMU_MAKE_ALIGNED_UNION(name, size) \ -union name##_aligned { \ - union name data; \ - u8 pad[ALIGN_UP(sizeof(union name), \ - (PMU_FB_COPY_RW_ALIGNMENT))]; \ -} - -/* RPC (Remote Procedure Call) header structure */ -#define NV_PMU_RPC_FLAGS_TYPE_SYNC 0x00000000 - -struct nv_pmu_rpc_header { - /* Identifies the unit servicing requested RPC*/ - u8 unit_id; - /* Identifies the requested RPC (within the unit)*/ - u8 function; - /* RPC call flags (@see PMU_RPC_FLAGS) */ - u8 flags; - /* Falcon's status code to describe failures*/ - u8 flcn_status; - /* RPC's total exec. time (measured on nvgpu driver side)*/ - u32 exec_time_nv_ns; - /* RPC's actual exec. time (measured on PMU side)*/ - u32 exec_time_pmu_ns; -}; - -#endif /* NVGPU_PMUIF_GPMUIF_CMN_H*/ diff --git a/include/nvgpu/pmuif/gpmuif_perfmon.h b/include/nvgpu/pmuif/gpmuif_perfmon.h deleted file mode 100644 index 8324e36..0000000 --- a/include/nvgpu/pmuif/gpmuif_perfmon.h +++ /dev/null @@ -1,241 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_PMUIF_GPMUIF_PERFMON_H -#define NVGPU_PMUIF_GPMUIF_PERFMON_H - -/*perfmon task defines*/ - -#define PMU_DOMAIN_GROUP_PSTATE 0 -#define PMU_DOMAIN_GROUP_GPC2CLK 1 -#define PMU_DOMAIN_GROUP_NUM 2 - -#define PMU_PERFMON_FLAG_ENABLE_INCREASE (0x00000001) -#define PMU_PERFMON_FLAG_ENABLE_DECREASE (0x00000002) -#define PMU_PERFMON_FLAG_CLEAR_PREV (0x00000004) - -#define NV_PMU_PERFMON_MAX_COUNTERS 10U - -enum pmu_perfmon_cmd_start_fields { - COUNTER_ALLOC -}; - -enum { - PMU_PERFMON_CMD_ID_START = 0, - PMU_PERFMON_CMD_ID_STOP = 1, - PMU_PERFMON_CMD_ID_INIT = 2 -}; - -struct pmu_perfmon_counter_v2 { - u8 index; - u8 flags; - u8 group_id; - u8 valid; - u16 upper_threshold; /* units of 0.01% */ - u16 lower_threshold; /* units of 0.01% */ - u32 scale; -}; - -struct pmu_perfmon_counter_v3 { - u8 index; - u8 group_id; - u16 flags; - u16 upper_threshold; /* units of 0.01% */ - u16 lower_threshold; /* units of 0.01% */ - u32 scale; -}; - -struct pmu_perfmon_cmd_start_v3 { - u8 cmd_type; - u8 group_id; - u8 state_id; - u8 flags; - struct pmu_allocation_v3 counter_alloc; -}; - -struct pmu_perfmon_cmd_start_v2 { - u8 cmd_type; - u8 group_id; - u8 state_id; - u8 flags; - struct pmu_allocation_v2 counter_alloc; -}; - -struct pmu_perfmon_cmd_start_v1 { - u8 cmd_type; - u8 group_id; - u8 state_id; - u8 flags; - struct pmu_allocation_v1 counter_alloc; -}; - -struct pmu_perfmon_cmd_stop { - u8 cmd_type; -}; - -struct pmu_perfmon_cmd_init_v3 { - u8 cmd_type; - u8 to_decrease_count; - u8 base_counter_id; - u32 sample_period_us; - struct pmu_allocation_v3 counter_alloc; - u8 num_counters; - u8 samples_in_moving_avg; - u16 sample_buffer; -}; - -struct pmu_perfmon_cmd_init_v2 { - u8 cmd_type; - u8 to_decrease_count; - u8 base_counter_id; - u32 sample_period_us; - struct pmu_allocation_v2 counter_alloc; - u8 num_counters; - u8 samples_in_moving_avg; - u16 sample_buffer; -}; - -struct pmu_perfmon_cmd_init_v1 { - u8 cmd_type; - u8 to_decrease_count; - u8 base_counter_id; - u32 sample_period_us; - struct pmu_allocation_v1 counter_alloc; - u8 num_counters; - u8 samples_in_moving_avg; - u16 sample_buffer; -}; - -struct pmu_perfmon_cmd { - union { - u8 cmd_type; - struct pmu_perfmon_cmd_start_v1 start_v1; - struct pmu_perfmon_cmd_start_v2 start_v2; - struct pmu_perfmon_cmd_start_v3 start_v3; - struct pmu_perfmon_cmd_stop stop; - struct pmu_perfmon_cmd_init_v1 init_v1; - struct pmu_perfmon_cmd_init_v2 init_v2; - struct pmu_perfmon_cmd_init_v3 init_v3; - }; -}; - -struct pmu_zbc_cmd { - u8 cmd_type; - u8 pad; - u16 entry_mask; -}; - -/* PERFMON MSG */ -enum { - PMU_PERFMON_MSG_ID_INCREASE_EVENT = 0, - PMU_PERFMON_MSG_ID_DECREASE_EVENT = 1, - PMU_PERFMON_MSG_ID_INIT_EVENT = 2, - PMU_PERFMON_MSG_ID_ACK = 3 -}; - -struct pmu_perfmon_msg_generic { - u8 msg_type; - u8 state_id; - u8 group_id; - u8 data; -}; - -struct pmu_perfmon_msg { - union { - u8 msg_type; - struct pmu_perfmon_msg_generic gen; - }; -}; - -/* PFERMON RPC interface*/ -/* - * RPC calls serviced by PERFMON unit. - */ -#define NV_PMU_RPC_ID_PERFMON_T18X_INIT 0x00 -#define NV_PMU_RPC_ID_PERFMON_T18X_DEINIT 0x01 -#define NV_PMU_RPC_ID_PERFMON_T18X_START 0x02 -#define NV_PMU_RPC_ID_PERFMON_T18X_STOP 0x03 -#define NV_PMU_RPC_ID_PERFMON_T18X_QUERY 0x04 -#define NV_PMU_RPC_ID_PERFMON_T18X__COUNT 0x05 - -/* - * structure that holds data used to - * execute Perfmon INIT RPC. - * hdr - RPC header - * sample_periodus - Desired period in between samples. - * to_decrease_count - Consecutive samples before decrease event. - * base_counter_id - Index of the base counter. - * samples_in_moving_avg - Number of values in moving average. - * num_counters - Num of counters PMU should use. - * counter - Counters. - */ -struct nv_pmu_rpc_struct_perfmon_init { - struct nv_pmu_rpc_header hdr; - u32 sample_periodus; - u8 to_decrease_count; - u8 base_counter_id; - u8 samples_in_moving_avg; - u8 num_counters; - struct pmu_perfmon_counter_v3 counter[NV_PMU_PERFMON_MAX_COUNTERS]; - u32 scratch[1]; -}; - -/* - * structure that holds data used to - * execute Perfmon START RPC. - * hdr - RPC header - * group_id - NV group ID - * state_id - NV state ID - * flags - PMU_PERFON flags - * counters - Counters. - */ -struct nv_pmu_rpc_struct_perfmon_start { - struct nv_pmu_rpc_header hdr; - u8 group_id; - u8 state_id; - u8 flags; - struct pmu_perfmon_counter_v3 counter[NV_PMU_PERFMON_MAX_COUNTERS]; - u32 scratch[1]; -}; - -/* - * structure that holds data used to - * execute Perfmon STOP RPC. - * hdr - RPC header - */ -struct nv_pmu_rpc_struct_perfmon_stop { - struct nv_pmu_rpc_header hdr; - u32 scratch[1]; -}; - -/* - * structure that holds data used to - * execute QUERY RPC. - * hdr - RPC header - * sample_buffer - Output buffer from pmu containing utilization samples. - */ -struct nv_pmu_rpc_struct_perfmon_query { - struct nv_pmu_rpc_header hdr; - u16 sample_buffer[NV_PMU_PERFMON_MAX_COUNTERS]; - u32 scratch[1]; -}; - -#endif /* NVGPU_PMUIF_GPMUIF_PERFMON_H */ diff --git a/include/nvgpu/pmuif/gpmuif_pg.h b/include/nvgpu/pmuif/gpmuif_pg.h deleted file mode 100644 index 58311ae..0000000 --- a/include/nvgpu/pmuif/gpmuif_pg.h +++ /dev/null @@ -1,424 +0,0 @@ -/* - * Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_PMUIF_GPMUIF_PG_H -#define NVGPU_PMUIF_GPMUIF_PG_H - -#include "gpmuif_ap.h" -#include "gpmuif_pg_rppg.h" - -/*PG defines*/ - -/* Identifier for each PG */ -#define PMU_PG_ELPG_ENGINE_ID_GRAPHICS (0x00000000U) -#define PMU_PG_ELPG_ENGINE_ID_MS (0x00000004U) -#define PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE (0x00000005U) -#define PMU_PG_ELPG_ENGINE_MAX PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE - -/* Async PG message IDs */ -enum { - PMU_PG_MSG_ASYNC_CMD_DISALLOW, -}; - -/* PG message */ -enum { - PMU_PG_ELPG_MSG_INIT_ACK, - PMU_PG_ELPG_MSG_DISALLOW_ACK, - PMU_PG_ELPG_MSG_ALLOW_ACK, - PMU_PG_ELPG_MSG_FREEZE_ACK, - PMU_PG_ELPG_MSG_FREEZE_ABORT, - PMU_PG_ELPG_MSG_UNFREEZE_ACK, -}; - -struct pmu_pg_msg_elpg_msg { - u8 msg_type; - u8 engine_id; - u16 msg; -}; - -enum { - PMU_PG_STAT_MSG_RESP_DMEM_OFFSET = 0, -}; - -struct pmu_pg_msg_stat { - u8 msg_type; - u8 engine_id; - u16 sub_msg_id; - u32 data; -}; - -enum { - PMU_PG_MSG_ENG_BUF_LOADED, - PMU_PG_MSG_ENG_BUF_UNLOADED, - PMU_PG_MSG_ENG_BUF_FAILED, -}; - -struct pmu_pg_msg_eng_buf_stat { - u8 msg_type; - u8 engine_id; - u8 buf_idx; - u8 status; -}; - -struct pmu_pg_msg_async_cmd_resp { - u8 msg_type; - u8 ctrl_id; - u8 msg_id; -}; - -struct pmu_pg_msg { - union { - u8 msg_type; - struct pmu_pg_msg_elpg_msg elpg_msg; - struct pmu_pg_msg_stat stat; - struct pmu_pg_msg_eng_buf_stat eng_buf_stat; - struct pmu_pg_msg_async_cmd_resp async_cmd_resp; - /* TBD: other pg messages */ - union pmu_ap_msg ap_msg; - struct nv_pmu_rppg_msg rppg_msg; - }; -}; - -/* PG commands */ -enum { - PMU_PG_ELPG_CMD_INIT, - PMU_PG_ELPG_CMD_DISALLOW, - PMU_PG_ELPG_CMD_ALLOW, - PMU_PG_ELPG_CMD_FREEZE, - PMU_PG_ELPG_CMD_UNFREEZE, -}; - -enum { - PMU_PG_CMD_ID_ELPG_CMD = 0, - PMU_PG_CMD_ID_ENG_BUF_LOAD, - PMU_PG_CMD_ID_ENG_BUF_UNLOAD, - PMU_PG_CMD_ID_PG_STAT, - PMU_PG_CMD_ID_PG_LOG_INIT, - PMU_PG_CMD_ID_PG_LOG_FLUSH, - PMU_PG_CMD_ID_PG_PARAM, - PMU_PG_CMD_ID_ELPG_INIT, - PMU_PG_CMD_ID_ELPG_POLL_CTXSAVE, - PMU_PG_CMD_ID_ELPG_ABORT_POLL, - PMU_PG_CMD_ID_ELPG_PWR_UP, - PMU_PG_CMD_ID_ELPG_DISALLOW, - PMU_PG_CMD_ID_ELPG_ALLOW, - PMU_PG_CMD_ID_AP, - RM_PMU_PG_CMD_ID_PSI, - RM_PMU_PG_CMD_ID_CG, - PMU_PG_CMD_ID_ZBC_TABLE_UPDATE, - PMU_PG_CMD_ID_PWR_RAIL_GATE_DISABLE = 0x20, - PMU_PG_CMD_ID_PWR_RAIL_GATE_ENABLE, - PMU_PG_CMD_ID_PWR_RAIL_SMU_MSG_DISABLE, - PMU_PMU_PG_CMD_ID_RPPG = 0x24, -}; - -enum { - PMU_PG_STAT_CMD_ALLOC_DMEM = 0, -}; - -enum { - SLOWDOWN_FACTOR_FPDIV_BY1 = 0, - SLOWDOWN_FACTOR_FPDIV_BY1P5, - SLOWDOWN_FACTOR_FPDIV_BY2, - SLOWDOWN_FACTOR_FPDIV_BY2P5, - SLOWDOWN_FACTOR_FPDIV_BY3, - SLOWDOWN_FACTOR_FPDIV_BY3P5, - SLOWDOWN_FACTOR_FPDIV_BY4, - SLOWDOWN_FACTOR_FPDIV_BY4P5, - SLOWDOWN_FACTOR_FPDIV_BY5, - SLOWDOWN_FACTOR_FPDIV_BY5P5, - SLOWDOWN_FACTOR_FPDIV_BY6, - SLOWDOWN_FACTOR_FPDIV_BY6P5, - SLOWDOWN_FACTOR_FPDIV_BY7, - SLOWDOWN_FACTOR_FPDIV_BY7P5, - SLOWDOWN_FACTOR_FPDIV_BY8, - SLOWDOWN_FACTOR_FPDIV_BY8P5, - SLOWDOWN_FACTOR_FPDIV_BY9, - SLOWDOWN_FACTOR_FPDIV_BY9P5, - SLOWDOWN_FACTOR_FPDIV_BY10, - SLOWDOWN_FACTOR_FPDIV_BY10P5, - SLOWDOWN_FACTOR_FPDIV_BY11, - SLOWDOWN_FACTOR_FPDIV_BY11P5, - SLOWDOWN_FACTOR_FPDIV_BY12, - SLOWDOWN_FACTOR_FPDIV_BY12P5, - SLOWDOWN_FACTOR_FPDIV_BY13, - SLOWDOWN_FACTOR_FPDIV_BY13P5, - SLOWDOWN_FACTOR_FPDIV_BY14, - SLOWDOWN_FACTOR_FPDIV_BY14P5, - SLOWDOWN_FACTOR_FPDIV_BY15, - SLOWDOWN_FACTOR_FPDIV_BY15P5, - SLOWDOWN_FACTOR_FPDIV_BY16, - SLOWDOWN_FACTOR_FPDIV_BY16P5, - SLOWDOWN_FACTOR_FPDIV_BY17 = 0x20, - SLOWDOWN_FACTOR_FPDIV_BY18 = 0x22, - SLOWDOWN_FACTOR_FPDIV_BY19 = 0x24, - SLOWDOWN_FACTOR_FPDIV_BY20 = 0x26, - SLOWDOWN_FACTOR_FPDIV_BY21 = 0x28, - SLOWDOWN_FACTOR_FPDIV_BY22 = 0x2a, - SLOWDOWN_FACTOR_FPDIV_BY23 = 0x2c, - SLOWDOWN_FACTOR_FPDIV_BY24 = 0x2e, - SLOWDOWN_FACTOR_FPDIV_BY25 = 0x30, - SLOWDOWN_FACTOR_FPDIV_BY26 = 0x32, - SLOWDOWN_FACTOR_FPDIV_BY27 = 0x34, - SLOWDOWN_FACTOR_FPDIV_BY28 = 0x36, - SLOWDOWN_FACTOR_FPDIV_BY29 = 0x38, - SLOWDOWN_FACTOR_FPDIV_BY30 = 0x3a, - SLOWDOWN_FACTOR_FPDIV_BY31 = 0x3c, - SLOWDOWN_FACTOR_FPDIV_BYMAX, -}; - -#define PMU_PG_PARAM_CMD_GR_INIT_PARAM 0x0U -#define PMU_PG_PARAM_CMD_MS_INIT_PARAM 0x01U -#define PMU_PG_PARAM_CMD_MCLK_CHANGE 0x04U -#define PMU_PG_PARAM_CMD_POST_INIT 0x06U -#define PMU_PG_PARAM_CMD_SUB_FEATURE_MASK_UPDATE 0x07U - -#define NVGPU_PMU_GR_FEATURE_MASK_SDIV_SLOWDOWN BIT32(0) -#define NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING BIT32(2) -#define NVGPU_PMU_GR_FEATURE_MASK_RPPG BIT32(3) -#define NVGPU_PMU_GR_FEATURE_MASK_PRIV_RING BIT32(5) -#define NVGPU_PMU_GR_FEATURE_MASK_UNBIND BIT32(6) -#define NVGPU_PMU_GR_FEATURE_MASK_SAVE_GLOBAL_STATE BIT32(7) -#define NVGPU_PMU_GR_FEATURE_MASK_RESET_ENTRY BIT32(8) -#define NVGPU_PMU_GR_FEATURE_MASK_HW_SEQUENCE BIT32(9) -#define NVGPU_PMU_GR_FEATURE_MASK_ELPG_SRAM BIT32(10) -#define NVGPU_PMU_GR_FEATURE_MASK_ELPG_LOGIC BIT32(11) -#define NVGPU_PMU_GR_FEATURE_MASK_ELPG_L2RPPG BIT32(12) - -#define NVGPU_PMU_GR_FEATURE_MASK_ALL \ - ( \ - NVGPU_PMU_GR_FEATURE_MASK_SDIV_SLOWDOWN |\ - NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING |\ - NVGPU_PMU_GR_FEATURE_MASK_RPPG |\ - NVGPU_PMU_GR_FEATURE_MASK_PRIV_RING |\ - NVGPU_PMU_GR_FEATURE_MASK_UNBIND |\ - NVGPU_PMU_GR_FEATURE_MASK_SAVE_GLOBAL_STATE |\ - NVGPU_PMU_GR_FEATURE_MASK_RESET_ENTRY |\ - NVGPU_PMU_GR_FEATURE_MASK_HW_SEQUENCE |\ - NVGPU_PMU_GR_FEATURE_MASK_ELPG_SRAM |\ - NVGPU_PMU_GR_FEATURE_MASK_ELPG_LOGIC |\ - NVGPU_PMU_GR_FEATURE_MASK_ELPG_L2RPPG \ - ) - -#define NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING BIT32(0) -#define NVGPU_PMU_MS_FEATURE_MASK_SW_ASR BIT32(1) -#define NVGPU_PMU_MS_FEATURE_MASK_RPPG BIT32(8) -#define NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING BIT32(5) - -#define NVGPU_PMU_MS_FEATURE_MASK_ALL \ - ( \ - NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING |\ - NVGPU_PMU_MS_FEATURE_MASK_SW_ASR |\ - NVGPU_PMU_MS_FEATURE_MASK_RPPG |\ - NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING \ - ) - - -struct pmu_pg_cmd_elpg_cmd { - u8 cmd_type; - u8 engine_id; - u16 cmd; -}; - -struct pmu_pg_cmd_eng_buf_load_v0 { - u8 cmd_type; - u8 engine_id; - u8 buf_idx; - u8 pad; - u16 buf_size; - u32 dma_base; - u8 dma_offset; - u8 dma_idx; -}; - -struct pmu_pg_cmd_eng_buf_load_v1 { - u8 cmd_type; - u8 engine_id; - u8 buf_idx; - u8 pad; - struct flcn_mem_desc { - struct falc_u64 dma_addr; - u16 dma_size; - u8 dma_idx; - } dma_desc; -}; - -struct pmu_pg_cmd_eng_buf_load_v2 { - u8 cmd_type; - u8 engine_id; - u8 buf_idx; - u8 pad; - struct flcn_mem_desc_v0 dma_desc; -}; - -struct pmu_pg_cmd_gr_init_param { - u8 cmd_type; - u16 sub_cmd_id; - u8 featuremask; -}; - -struct pmu_pg_cmd_gr_init_param_v2 { - u8 cmd_type; - u16 sub_cmd_id; - u8 featuremask; - u8 ldiv_slowdown_factor; -}; - -struct pmu_pg_cmd_gr_init_param_v1 { - u8 cmd_type; - u16 sub_cmd_id; - u32 featuremask; -}; - -struct pmu_pg_cmd_sub_feature_mask_update { - u8 cmd_type; - u16 sub_cmd_id; - u8 ctrl_id; - u32 enabled_mask; -}; - -struct pmu_pg_cmd_ms_init_param { - u8 cmd_type; - u16 cmd_id; - u8 psi; - u8 idle_flipped_test_enabled; - u16 psiSettleTimeUs; - u8 rsvd[2]; - u32 support_mask; - u32 abort_timeout_us; -}; - -struct pmu_pg_cmd_mclk_change { - u8 cmd_type; - u16 cmd_id; - u8 rsvd; - u32 data; -}; - -#define PG_VOLT_RAIL_IDX_MAX 2 - -struct pmu_pg_volt_rail { - u8 volt_rail_idx; - u8 sleep_volt_dev_idx; - u8 sleep_vfe_idx; - u32 sleep_voltage_uv; - u32 therm_vid0_cache; - u32 therm_vid1_cache; -}; - -struct pmu_pg_cmd_post_init_param { - u8 cmd_type; - u16 cmd_id; - struct pmu_pg_volt_rail pg_volt_rail[PG_VOLT_RAIL_IDX_MAX]; -}; - -struct pmu_pg_cmd_stat { - u8 cmd_type; - u8 engine_id; - u16 sub_cmd_id; - u32 data; -}; - -struct pmu_pg_cmd { - union { - u8 cmd_type; - struct pmu_pg_cmd_elpg_cmd elpg_cmd; - struct pmu_pg_cmd_eng_buf_load_v0 eng_buf_load_v0; - struct pmu_pg_cmd_eng_buf_load_v1 eng_buf_load_v1; - struct pmu_pg_cmd_eng_buf_load_v2 eng_buf_load_v2; - struct pmu_pg_cmd_stat stat; - struct pmu_pg_cmd_gr_init_param gr_init_param; - struct pmu_pg_cmd_gr_init_param_v1 gr_init_param_v1; - struct pmu_pg_cmd_gr_init_param_v2 gr_init_param_v2; - struct pmu_pg_cmd_ms_init_param ms_init_param; - struct pmu_pg_cmd_mclk_change mclk_change; - struct pmu_pg_cmd_post_init_param post_init; - /* TBD: other pg commands */ - union pmu_ap_cmd ap_cmd; - struct nv_pmu_rppg_cmd rppg_cmd; - struct pmu_pg_cmd_sub_feature_mask_update sf_mask_update; - }; -}; - -/* Statistics structure for PG features */ -struct pmu_pg_stats_v2 { - u32 entry_count; - u32 exit_count; - u32 abort_count; - u32 detection_count; - u32 prevention_activate_count; - u32 prevention_deactivate_count; - u32 powered_up_time_us; - u32 entry_latency_us; - u32 exit_latency_us; - u32 resident_time_us; - u32 entry_latency_avg_us; - u32 exit_latency_avg_us; - u32 entry_latency_max_us; - u32 exit_latency_max_us; - u32 total_sleep_time_us; - u32 total_non_sleep_time_us; -}; - -struct pmu_pg_stats_v1 { - /* Number of time PMU successfully engaged sleep state */ - u32 entry_count; - /* Number of time PMU exit sleep state */ - u32 exit_count; - /* Number of time PMU aborted in entry sequence */ - u32 abort_count; - /* - * Time for which GPU was neither in Sleep state not - * executing sleep sequence. - */ - u32 poweredup_timeus; - /* Entry and exit latency of current sleep cycle */ - u32 entry_latency_us; - u32 exitlatencyus; - /* Resident time for current sleep cycle. */ - u32 resident_timeus; - /* Rolling average entry and exit latencies */ - u32 entrylatency_avgus; - u32 exitlatency_avgus; - /* Max entry and exit latencies */ - u32 entrylatency_maxus; - u32 exitlatency_maxus; - /* Total time spent in sleep and non-sleep state */ - u32 total_sleep_timeus; - u32 total_nonsleep_timeus; -}; - -struct pmu_pg_stats { - u64 pg_entry_start_timestamp; - u64 pg_ingating_start_timestamp; - u64 pg_exit_start_timestamp; - u64 pg_ungating_start_timestamp; - u32 pg_avg_entry_time_us; - u32 pg_ingating_cnt; - u32 pg_ingating_time_us; - u32 pg_avg_exit_time_us; - u32 pg_ungating_count; - u32 pg_ungating_time_us; - u32 pg_gating_cnt; - u32 pg_gating_deny_cnt; -}; - -#endif /* NVGPU_PMUIF_GPMUIF_PG_H*/ diff --git a/include/nvgpu/pmuif/gpmuif_pg_rppg.h b/include/nvgpu/pmuif/gpmuif_pg_rppg.h deleted file mode 100644 index 05445f6..0000000 --- a/include/nvgpu/pmuif/gpmuif_pg_rppg.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_PMUIF_GPMUIF_PG_RPPG_H -#define NVGPU_PMUIF_GPMUIF_PG_RPPG_H - -#define NV_PMU_RPPG_CTRL_ID_GR (0x0000) -#define NV_PMU_RPPG_CTRL_ID_MS (0x0001) -#define NV_PMU_RPPG_CTRL_ID_DI (0x0002) -#define NV_PMU_RPPG_CTRL_ID_MAX (0x0003) - -#define NV_PMU_RPPG_CTRL_MASK_ENABLE_ALL (BIT(NV_PMU_RPPG_CTRL_ID_GR) |\ - BIT(NV_PMU_RPPG_CTRL_ID_MS) |\ - BIT(NV_PMU_RPPG_CTRL_ID_DI)) - -#define NV_PMU_RPPG_CTRL_MASK_DISABLE_ALL 0 - -enum { - NV_PMU_RPPG_DOMAIN_ID_GFX = 0x0, - NV_PMU_RPPG_DOMAIN_ID_NON_GFX, -}; - -struct nv_pmu_rppg_ctrl_stats { - u32 entry_count; - u32 exit_count; -}; - -struct nv_pmu_rppg_cmd_common { - u8 cmd_type; - u8 cmd_id; -}; - -struct nv_pmu_rppg_cmd_init { - u8 cmd_type; - u8 cmd_id; -}; - -struct nv_pmu_rppg_cmd_init_ctrl { - u8 cmd_type; - u8 cmd_id; - u8 ctrl_id; - u8 domain_id; -}; - -struct nv_pmu_rppg_cmd_stats_reset { - u8 cmd_type; - u8 cmd_id; - u8 ctrl_id; -}; - -struct nv_pmu_rppg_cmd { - union { - u8 cmd_type; - struct nv_pmu_rppg_cmd_common cmn; - struct nv_pmu_rppg_cmd_init init; - struct nv_pmu_rppg_cmd_init_ctrl init_ctrl; - struct nv_pmu_rppg_cmd_stats_reset stats_reset; - }; -}; - -enum { - NV_PMU_RPPG_CMD_ID_INIT = 0x0, - NV_PMU_RPPG_CMD_ID_INIT_CTRL, - NV_PMU_RPPG_CMD_ID_STATS_RESET, -}; - - -struct nv_pmu_rppg_msg_common { - u8 msg_type; - u8 msg_id; -}; - -struct nv_pmu_rppg_msg_init_ctrl_ack { - u8 msg_type; - u8 msg_id; - u8 ctrl_id; - u32 stats_dmem_offset; -}; - -struct nv_pmu_rppg_msg { - union { - u8 msg_type; - struct nv_pmu_rppg_msg_common cmn; - struct nv_pmu_rppg_msg_init_ctrl_ack init_ctrl_ack; - }; -}; - -enum { - NV_PMU_RPPG_MSG_ID_INIT_CTRL_ACK = 0x0, -}; - -#endif /* NVGPU_PMUIF_GPMUIF_PG_RPPG_H */ diff --git a/include/nvgpu/pmuif/gpmuif_pmu.h b/include/nvgpu/pmuif/gpmuif_pmu.h deleted file mode 100644 index 0528bd6..0000000 --- a/include/nvgpu/pmuif/gpmuif_pmu.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_PMUIF_GPMUIF_PMU_H -#define NVGPU_PMUIF_GPMUIF_PMU_H - -#include -#include "gpmuif_cmn.h" - -/* Make sure size of this structure is a multiple of 4 bytes */ -struct pmu_cmdline_args_v3 { - u32 reserved; - u32 cpu_freq_hz; - u32 falc_trace_size; - u32 falc_trace_dma_base; - u32 falc_trace_dma_idx; - u8 secure_mode; - u8 raise_priv_sec; - struct pmu_mem_v1 gc6_ctx; -}; - -struct pmu_cmdline_args_v4 { - u32 reserved; - u32 cpu_freq_hz; - u32 falc_trace_size; - struct falc_dma_addr dma_addr; - u32 falc_trace_dma_idx; - u8 secure_mode; - u8 raise_priv_sec; - struct pmu_mem_desc_v0 gc6_ctx; - u8 pad; -}; - -struct pmu_cmdline_args_v5 { - u32 cpu_freq_hz; - struct flcn_mem_desc_v0 trace_buf; - u8 secure_mode; - u8 raise_priv_sec; - struct flcn_mem_desc_v0 gc6_ctx; - struct flcn_mem_desc_v0 init_data_dma_info; - u32 dummy; -}; - -struct pmu_cmdline_args_v6 { - u32 cpu_freq_hz; - struct flcn_mem_desc_v0 trace_buf; - u8 secure_mode; - u8 raise_priv_sec; - struct flcn_mem_desc_v0 gc6_ctx; - struct flcn_mem_desc_v0 gc6_bsod_ctx; - struct flcn_mem_desc_v0 super_surface; - u32 flags; -}; - -/* GPU ID */ -#define PMU_SHA1_GID_SIGNATURE 0xA7C66AD2 -#define PMU_SHA1_GID_SIGNATURE_SIZE 4 - -#define PMU_SHA1_GID_SIZE 16 - -struct pmu_sha1_gid { - bool valid; - u8 gid[PMU_SHA1_GID_SIZE]; -}; - -struct pmu_sha1_gid_data { - u8 signature[PMU_SHA1_GID_SIGNATURE_SIZE]; - u8 gid[PMU_SHA1_GID_SIZE]; -}; - -/* PMU INIT MSG */ -enum { - PMU_INIT_MSG_TYPE_PMU_INIT = 0, -}; - -struct pmu_init_msg_pmu_v1 { - u8 msg_type; - u8 pad; - u16 os_debug_entry_point; - - struct { - u16 size; - u16 offset; - u8 index; - u8 pad; - } queue_info[PMU_QUEUE_COUNT]; - - u16 sw_managed_area_offset; - u16 sw_managed_area_size; -}; - -#define PMU_QUEUE_COUNT_FOR_V5 4 -#define PMU_QUEUE_COUNT_FOR_V4 5 -#define PMU_QUEUE_COUNT_FOR_V3 3 -#define PMU_QUEUE_HPQ_IDX_FOR_V3 0 -#define PMU_QUEUE_LPQ_IDX_FOR_V3 1 -#define PMU_QUEUE_MSG_IDX_FOR_V3 2 -#define PMU_QUEUE_MSG_IDX_FOR_V5 3 -struct pmu_init_msg_pmu_v3 { - u8 msg_type; - u8 queue_index[PMU_QUEUE_COUNT_FOR_V3]; - u16 queue_size[PMU_QUEUE_COUNT_FOR_V3]; - u16 queue_offset; - - u16 sw_managed_area_offset; - u16 sw_managed_area_size; - - u16 os_debug_entry_point; - - u8 dummy[18]; -}; - -struct pmu_init_msg_pmu_v4 { - u8 msg_type; - u8 queue_index[PMU_QUEUE_COUNT_FOR_V4]; - u16 queue_size[PMU_QUEUE_COUNT_FOR_V4]; - u16 queue_offset; - - u16 sw_managed_area_offset; - u16 sw_managed_area_size; - - u16 os_debug_entry_point; - - u8 dummy[18]; -}; - -struct pmu_init_msg_pmu_v5 { - u8 msg_type; - u8 flcn_status; - u8 queue_index[PMU_QUEUE_COUNT_FOR_V5]; - u16 queue_size[PMU_QUEUE_COUNT_FOR_V5]; - u16 queue_offset; - - u16 sw_managed_area_offset; - u16 sw_managed_area_size; - - u16 os_debug_entry_point; - - u8 dummy[18]; - u8 pad; -}; - -union pmu_init_msg_pmu { - struct pmu_init_msg_pmu_v1 v1; - struct pmu_init_msg_pmu_v3 v3; - struct pmu_init_msg_pmu_v4 v4; - struct pmu_init_msg_pmu_v5 v5; -}; - -struct pmu_init_msg { - union { - u8 msg_type; - struct pmu_init_msg_pmu_v1 pmu_init_v1; - struct pmu_init_msg_pmu_v3 pmu_init_v3; - struct pmu_init_msg_pmu_v4 pmu_init_v4; - struct pmu_init_msg_pmu_v5 pmu_init_v5; - }; -}; - -/* robust channel (RC) messages */ -enum { - PMU_RC_MSG_TYPE_UNHANDLED_CMD = 0, -}; - -struct pmu_rc_msg_unhandled_cmd { - u8 msg_type; - u8 unit_id; -}; - -struct pmu_rc_msg { - u8 msg_type; - struct pmu_rc_msg_unhandled_cmd unhandled_cmd; -}; - -#endif /* NVGPU_PMUIF_GPMUIF_PMU_H*/ diff --git a/include/nvgpu/pmuif/gpmuifbios.h b/include/nvgpu/pmuif/gpmuifbios.h deleted file mode 100644 index e89fbc3..0000000 --- a/include/nvgpu/pmuif/gpmuifbios.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_PMUIF_GPMUIFBIOS_H -#define NVGPU_PMUIF_GPMUIFBIOS_H - -struct nv_pmu_bios_vfield_register_segment_super { - u8 type; - u8 low_bit; - u8 high_bit; -}; - -struct nv_pmu_bios_vfield_register_segment_reg { - struct nv_pmu_bios_vfield_register_segment_super super; - u32 addr; -}; - -struct nv_pmu_bios_vfield_register_segment_index_reg { - struct nv_pmu_bios_vfield_register_segment_super super; - u32 addr; - u32 reg_index; - u32 index; -}; - -union nv_pmu_bios_vfield_register_segment { - struct nv_pmu_bios_vfield_register_segment_super super; - struct nv_pmu_bios_vfield_register_segment_reg reg; - struct nv_pmu_bios_vfield_register_segment_index_reg index_reg; -}; - - -#endif /* NVGPU_PMUIF_GPMUIFBIOS_H*/ diff --git a/include/nvgpu/pmuif/gpmuifboardobj.h b/include/nvgpu/pmuif/gpmuifboardobj.h deleted file mode 100644 index 47226aa..0000000 --- a/include/nvgpu/pmuif/gpmuifboardobj.h +++ /dev/null @@ -1,234 +0,0 @@ -/* -* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. -* - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. -*/ -#ifndef NVGPU_PMUIF_GPMUIFBOARDOBJ_H -#define NVGPU_PMUIF_GPMUIFBOARDOBJ_H - -#include -#include "ctrl/ctrlboardobj.h" - -/* board object group command id's. */ -#define NV_PMU_BOARDOBJGRP_CMD_SET 0x00U -#define NV_PMU_BOARDOBJGRP_CMD_GET_STATUS 0x01U - -#define NV_PMU_RPC_ID_CLK_BOARD_OBJ_GRP_CMD 0x00U -#define NV_PMU_RPC_ID_FAN_BOARD_OBJ_GRP_CMD 0x00U -#define NV_PMU_RPC_ID_PERF_BOARD_OBJ_GRP_CMD 0x00U -#define NV_PMU_RPC_ID_PERF_CF_BOARD_OBJ_GRP_CMD 0x00U -#define NV_PMU_RPC_ID_PMGR_BOARD_OBJ_GRP_CMD 0x00U -#define NV_PMU_RPC_ID_THERM_BOARD_OBJ_GRP_CMD 0x00U -#define NV_PMU_RPC_ID_VOLT_BOARD_OBJ_GRP_CMD 0x00U - -/* - * Base structure describing a BOARDOBJ for communication between Kernel and - * PMU. - */ -struct nv_pmu_boardobj { - u8 type; - u8 grp_idx; -}; - -/* - * Base structure describing a BOARDOBJ for Query interface between Kernel and - * PMU. - */ -struct nv_pmu_boardobj_query { - u8 type; - u8 grp_idx; -}; - -/* - * Virtual base structure describing a BOARDOBJGRP interface between Kernel and - * PMU. - */ -struct nv_pmu_boardobjgrp_super { - u8 type; - u8 class_id; - u8 obj_slots; - u8 flags; -}; - -struct nv_pmu_boardobjgrp { - struct nv_pmu_boardobjgrp_super super; - u32 obj_mask; -}; - -struct nv_pmu_boardobjgrp_e32 { - struct nv_pmu_boardobjgrp_super super; - struct ctrl_boardobjgrp_mask_e32 obj_mask; -}; - -struct nv_pmu_boardobjgrp_e255 { - struct nv_pmu_boardobjgrp_super super; - struct ctrl_boardobjgrp_mask_e255 obj_mask; -}; - -struct nv_pmu_boardobj_cmd_grp_payload { - struct pmu_allocation_v3 dmem_buf; - struct flcn_mem_desc_v0 fb; - u8 hdr_size; - u8 entry_size; -}; - -struct nv_pmu_boardobj_cmd_grp { - u8 cmd_type; - u8 pad[2]; - u8 class_id; - struct nv_pmu_boardobj_cmd_grp_payload grp; -}; - -#define NV_PMU_BOARDOBJ_GRP_ALLOC_OFFSET \ - (NV_OFFSETOF(NV_PMU_BOARDOBJ_CMD_GRP, grp)) - -struct nv_pmu_boardobj_cmd { - union { - u8 cmd_type; - struct nv_pmu_boardobj_cmd_grp grp; - struct nv_pmu_boardobj_cmd_grp grp_set; - struct nv_pmu_boardobj_cmd_grp grp_get_status; - }; -}; - -struct nv_pmu_boardobj_msg_grp { - u8 msg_type; - bool b_success; - flcn_status flcn_status; - u8 class_id; -}; - -struct nv_pmu_boardobj_msg { - union { - u8 msg_type; - struct nv_pmu_boardobj_msg_grp grp; - struct nv_pmu_boardobj_msg_grp grp_set; - struct nv_pmu_boardobj_msg_grp grp_get_status; - }; -}; - -/* -* Macro generating structures describing classes which implement -* NV_PMU_BOARDOBJGRP via the NV_PMU_BOARDBOBJ_CMD_GRP SET interface. -* -* @para _eng Name of implementing engine in which this structure is -* found. -* @param _class Class ID of Objects within Board Object Group. -* @param _slots Max number of elements this group can contain. -*/ -#define NV_PMU_BOARDOBJ_GRP_SET_MAKE(_eng, _class, _slots) \ - NV_PMU_MAKE_ALIGNED_STRUCT( \ - nv_pmu_##_eng##_##_class##_boardobjgrp_set_header, one_structure); \ - NV_PMU_MAKE_ALIGNED_UNION( \ - nv_pmu_##_eng##_##_class##_boardobj_set_union, one_union); \ - struct nv_pmu_##_eng##_##_class##_boardobj_grp_set { \ - union nv_pmu_##_eng##_##_class##_boardobjgrp_set_header_aligned hdr; \ - union nv_pmu_##_eng##_##_class##_boardobj_set_union_aligned objects[(_slots)];\ - } - -/* -* Macro generating structures describing classes which implement -* NV_PMU_BOARDOBJGRP_E32 via the NV_PMU_BOARDBOBJ_CMD_GRP SET interface. -* -* @para _eng Name of implementing engine in which this structure is -* found. -* @param _class Class ID of Objects within Board Object Group. -*/ -#define NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(_eng, _class) \ - NV_PMU_BOARDOBJ_GRP_SET_MAKE(_eng, _class, \ - CTRL_BOARDOBJGRP_E32_MAX_OBJECTS) - -/* -* Macro generating structures describing classes which implement -* NV_PMU_BOARDOBJGRP_E255 via the NV_PMU_BOARDBOBJ_CMD_GRP SET interface. -* -* @para _eng Name of implementing engine in which this structure is -* found. -* @param _class Class ID of Objects within Board Object Group. -*/ -#define NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(_eng, _class) \ - NV_PMU_BOARDOBJ_GRP_SET_MAKE(_eng, _class, \ - CTRL_BOARDOBJGRP_E255_MAX_OBJECTS) - -/* -* Macro generating structures for querying dynamic state for classes which -* implement NV_PMU_BOARDOBJGRP via the NV_PMU_BOARDOBJ_CMD_GRP GET_STATUS -* interface. -* -* @para _eng Name of implementing engine in which this structure is -* found. -* @param _class Class ID of Objects within Board Object Group. -* @param _slots Max number of elements this group can contain. -*/ -#define NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE(_eng, _class, _slots) \ - NV_PMU_MAKE_ALIGNED_STRUCT( \ - nv_pmu_##_eng##_##_class##_boardobjgrp_get_status_header, struct); \ - NV_PMU_MAKE_ALIGNED_UNION( \ - nv_pmu_##_eng##_##_class##_boardobj_get_status_union, union); \ - struct nv_pmu_##_eng##_##_class##_boardobj_grp_get_status { \ - union nv_pmu_##_eng##_##_class##_boardobjgrp_get_status_header_aligned \ - hdr; \ - union nv_pmu_##_eng##_##_class##_boardobj_get_status_union_aligned \ - objects[(_slots)]; \ - } - -/* -* Macro generating structures for querying dynamic state for classes which -* implement NV_PMU_BOARDOBJGRP_E32 via the NV_PMU_BOARDOBJ_CMD_GRP GET_STATUS -* interface. -* -* @para _eng Name of implementing engine in which this structure is -* found. -* @param _class Class ID of Objects within Board Object Group. -*/ -#define NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(_eng, _class) \ - NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE(_eng, _class, \ - CTRL_BOARDOBJGRP_E32_MAX_OBJECTS) - -/* -* Macro generating structures for querying dynamic state for classes which -* implement NV_PMU_BOARDOBJGRP_E255 via the NV_PMU_BOARDOBJ_CMD_GRP GET_STATUS -* interface. -* -* @para _eng Name of implementing engine in which this structure is -* found. -* @param _class Class ID of Objects within Board Object Group. -*/ -#define NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E255(_eng, _class) \ - NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE(_eng, _class, \ - CTRL_BOARDOBJGRP_E255_MAX_OBJECTS) - -/* RPC */ - -/* - * structure that holds data used to - * execute BOARD_OBJ_GRP_CMD RPC. - */ -struct nv_pmu_rpc_struct_board_obj_grp_cmd -{ - /* [IN/OUT] Must be first field in RPC structure */ - struct nv_pmu_rpc_header hdr; - /* [IN] BOARDOBJGRP class IDs. */ - u8 class_id; - /* [IN] Requested command ID (@ref NV_PMU_BOARDOBJGRP_CMD_***)*/ - u8 command_id; - u32 scratch[1]; -}; - -#endif /* NVGPU_PMUIF_GPMUIFBOARDOBJ_H */ diff --git a/include/nvgpu/pmuif/gpmuifclk.h b/include/nvgpu/pmuif/gpmuifclk.h deleted file mode 100644 index 70a913b..0000000 --- a/include/nvgpu/pmuif/gpmuifclk.h +++ /dev/null @@ -1,573 +0,0 @@ -/* -* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. -* - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. -*/ - -#ifndef NVGPU_PMUIF_GPMUIFCLK_H -#define NVGPU_PMUIF_GPMUIFCLK_H - -#include "ctrl/ctrlboardobj.h" -#include "ctrl/ctrlvolt.h" -#include "ctrl/ctrlperf.h" -#include "ctrl/ctrlclk.h" -#include "gpmuifboardobj.h" -#include "gpmuifvolt.h" -#include - - -/* - * Try to get gpc2clk, mclk, sys2clk, xbar2clk work for Pascal - * - * mclk is same for both - * gpc2clk is 17 for Pascal and 13 for Volta, making it 17 - * as volta uses gpcclk - * sys2clk is 20 in Pascal and 15 in Volta. - * Changing for Pascal would break nvdclk of Volta - * xbar2clk is 19 in Pascal and 14 in Volta - * Changing for Pascal would break pwrclk of Volta - */ -enum nv_pmu_clk_clkwhich { - clkwhich_gpcclk = 1, - clkwhich_xbarclk = 2, - clkwhich_sysclk = 3, - clkwhich_hubclk = 4, - clkwhich_mclk = 5, - clkwhich_hostclk = 6, - clkwhich_dispclk = 7, - clkwhich_xclk = 12, - clkwhich_gpc2clk = 17, - clkwhich_xbar2clk = 14, - clkwhich_sys2clk = 15, - clkwhich_hub2clk = 16, - clkwhich_pwrclk = 19, - clkwhich_nvdclk = 20, - clkwhich_pciegenclk = 26, -}; - -/* - * Enumeration of BOARDOBJGRP class IDs within OBJCLK. Used as "classId" - * argument for communications between Kernel and PMU via the various generic - * BOARDOBJGRP interfaces. - */ -#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_DOMAIN 0x00 -#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_PROG 0x01 -#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_VIN_DEVICE 0x02 -#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_FLL_DEVICE 0x03 -#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_VF_POINT 0x04 -#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_FREQ_CONTROLLER 0x05 - -/*! -* CLK_DOMAIN BOARDOBJGRP Header structure. Describes global state about the -* CLK_DOMAIN feature. -*/ -struct nv_pmu_clk_clk_domain_boardobjgrp_set_header { - struct nv_pmu_boardobjgrp_e32 super; - u32 vbios_domains; - struct ctrl_boardobjgrp_mask_e32 prog_domains_mask; - struct ctrl_boardobjgrp_mask_e32 master_domains_mask; - u16 cntr_sampling_periodms; - u8 version; - bool b_override_o_v_o_c; - bool b_debug_mode; - bool b_enforce_vf_monotonicity; - bool b_enforce_vf_smoothening; - u8 volt_rails_max; - struct ctrl_clk_clk_delta deltas; -}; - -struct nv_pmu_clk_clk_domain_boardobj_set { - struct nv_pmu_boardobj super; - enum nv_pmu_clk_clkwhich domain; - u32 api_domain; - u8 perf_domain_grp_idx; -}; - -struct nv_pmu_clk_clk_domain_3x_boardobj_set { - struct nv_pmu_clk_clk_domain_boardobj_set super; - bool b_noise_aware_capable; -}; - -struct nv_pmu_clk_clk_domain_3x_fixed_boardobj_set { - struct nv_pmu_clk_clk_domain_3x_boardobj_set super; - u16 freq_mhz; -}; - -struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set { - struct nv_pmu_clk_clk_domain_3x_boardobj_set super; - u8 clk_prog_idx_first; - u8 clk_prog_idx_last; - bool b_force_noise_unaware_ordering; - struct ctrl_clk_freq_delta factory_delta; - short freq_delta_min_mhz; - short freq_delta_max_mhz; - struct ctrl_clk_clk_delta deltas; -}; - -struct nv_pmu_clk_clk_domain_30_prog_boardobj_set { - struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super; - u8 noise_unaware_ordering_index; - u8 noise_aware_ordering_index; -}; - -struct nv_pmu_clk_clk_domain_3x_master_boardobj_set { - u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */ - u32 slave_idxs_mask; -}; - -struct nv_pmu_clk_clk_domain_30_master_boardobj_set { - struct nv_pmu_clk_clk_domain_30_prog_boardobj_set super; - struct nv_pmu_clk_clk_domain_3x_master_boardobj_set master; -}; - -struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set { - u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */ - u8 master_idx; -}; - -struct nv_pmu_clk_clk_domain_30_slave_boardobj_set { - struct nv_pmu_clk_clk_domain_30_prog_boardobj_set super; - struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set slave; -}; - -struct nv_pmu_clk_clk_domain_35_prog_boardobj_set { - struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super; - u8 pre_volt_ordering_index; - u8 post_volt_ordering_index; - u8 clk_pos; - u8 clk_vf_curve_count; -}; - -struct nv_pmu_clk_clk_domain_35_master_boardobj_set { - struct nv_pmu_clk_clk_domain_35_prog_boardobj_set super; - struct nv_pmu_clk_clk_domain_3x_master_boardobj_set master; - u32 master_slave_domains_grp_mask; -}; - - -struct nv_pmu_clk_clk_domain_35_slave_boardobj_set { - struct nv_pmu_clk_clk_domain_35_prog_boardobj_set super; - struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set slave; -}; - -union nv_pmu_clk_clk_domain_boardobj_set_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_clk_clk_domain_boardobj_set super; - struct nv_pmu_clk_clk_domain_3x_boardobj_set v3x; - struct nv_pmu_clk_clk_domain_3x_fixed_boardobj_set v3x_fixed; - struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set v3x_prog; - struct nv_pmu_clk_clk_domain_30_prog_boardobj_set v30_prog; - struct nv_pmu_clk_clk_domain_30_master_boardobj_set v30_master; - struct nv_pmu_clk_clk_domain_30_slave_boardobj_set v30_slave; - struct nv_pmu_clk_clk_domain_35_prog_boardobj_set v35_prog; - struct nv_pmu_clk_clk_domain_35_master_boardobj_set v35_master; - struct nv_pmu_clk_clk_domain_35_slave_boardobj_set v35_slave; -}; - -NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_domain); - -struct nv_pmu_clk_clk_prog_boardobjgrp_set_header { - struct nv_pmu_boardobjgrp_e255 super; - u8 slave_entry_count; - u8 vf_entry_count; -}; - -struct nv_pmu_clk_clk_prog_boardobj_set { - struct nv_pmu_boardobj super; -}; - -struct nv_pmu_clk_clk_prog_1x_boardobj_set { - struct nv_pmu_clk_clk_prog_boardobj_set super; - u8 source; - u16 freq_max_mhz; - union ctrl_clk_clk_prog_1x_source_data source_data; -}; - -struct nv_pmu_clk_clk_prog_1x_master_boardobj_set { - struct nv_pmu_clk_clk_prog_1x_boardobj_set super; - u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */ - bool b_o_c_o_v_enabled; - struct ctrl_clk_clk_prog_1x_master_vf_entry vf_entries[ - CTRL_CLK_CLK_PROG_1X_MASTER_VF_ENTRY_MAX_ENTRIES]; - struct ctrl_clk_clk_delta deltas; - union ctrl_clk_clk_prog_1x_master_source_data source_data; -}; - -struct nv_pmu_clk_clk_prog_1x_master_ratio_boardobj_set { - struct nv_pmu_clk_clk_prog_1x_master_boardobj_set super; - u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */ - struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry slave_entries[ - CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES]; -}; - -struct nv_pmu_clk_clk_prog_1x_master_table_boardobj_set { - struct nv_pmu_clk_clk_prog_1x_master_boardobj_set super; - u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */ - struct ctrl_clk_clk_prog_1x_master_table_slave_entry - slave_entries[CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES]; -}; - -union nv_pmu_clk_clk_prog_boardobj_set_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_clk_clk_prog_boardobj_set super; - struct nv_pmu_clk_clk_prog_1x_boardobj_set v1x; - struct nv_pmu_clk_clk_prog_1x_master_boardobj_set v1x_master; - struct nv_pmu_clk_clk_prog_1x_master_ratio_boardobj_set v1x_master_ratio; - struct nv_pmu_clk_clk_prog_1x_master_table_boardobj_set v1x_master_table; -}; - -NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(clk, clk_prog); - -struct nv_pmu_clk_lut_device_desc { - u8 vselect_mode; - u16 hysteresis_threshold; -}; - -struct nv_pmu_clk_regime_desc { - u8 regime_id; - u8 target_regime_id_override; - u16 fixed_freq_regime_limit_mhz; -}; - -struct nv_pmu_clk_clk_fll_device_boardobjgrp_set_header { - struct nv_pmu_boardobjgrp_e32 super; - struct ctrl_boardobjgrp_mask_e32 lut_prog_master_mask; - u32 lut_step_size_uv; - u32 lut_min_voltage_uv; - u8 lut_num_entries; - u16 max_min_freq_mhz; -}; - -struct nv_pmu_clk_clk_fll_device_boardobj_set { - struct nv_pmu_boardobj super; - u8 id; - u8 mdiv; - u8 vin_idx_logic; - u8 vin_idx_sram; - u8 rail_idx_for_lut; - u16 input_freq_mhz; - u32 clk_domain; - struct nv_pmu_clk_lut_device_desc lut_device; - struct nv_pmu_clk_regime_desc regime_desc; - u8 min_freq_vfe_idx; - u8 freq_ctrl_idx; - bool b_skip_pldiv_below_dvco_min; - bool b_dvco_1x; - struct ctrl_boardobjgrp_mask_e32 lut_prog_broadcast_slave_mask; -}; - -union nv_pmu_clk_clk_fll_device_boardobj_set_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_clk_clk_fll_device_boardobj_set super; -}; - -NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_fll_device); - -struct nv_pmu_clk_clk_vin_device_boardobjgrp_set_header { - struct nv_pmu_boardobjgrp_e32 super; - bool b_vin_is_disable_allowed; -}; - -struct nv_pmu_clk_clk_vin_device_boardobj_set { - struct nv_pmu_boardobj super; - u8 id; - u8 volt_domain; - u32 flls_shared_mask; -}; - -struct nv_pmu_clk_clk_vin_device_v10_boardobj_set { - struct nv_pmu_clk_clk_vin_device_boardobj_set super; - struct ctrl_clk_vin_device_info_data_v10 data; -}; - -struct nv_pmu_clk_clk_vin_device_v20_boardobj_set { - struct nv_pmu_clk_clk_vin_device_boardobj_set super; - struct ctrl_clk_vin_device_info_data_v20 data; -}; - -union nv_pmu_clk_clk_vin_device_boardobj_set_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_clk_clk_vin_device_boardobj_set super; - struct nv_pmu_clk_clk_vin_device_v10_boardobj_set v10; - struct nv_pmu_clk_clk_vin_device_v20_boardobj_set v20; -}; - -NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_vin_device); - -struct nv_pmu_clk_clk_vf_point_boardobjgrp_set_header { - struct nv_pmu_boardobjgrp_e255 super; -}; - -struct nv_pmu_clk_clk_vf_point_boardobj_set { - struct nv_pmu_boardobj super; - u8 vfe_equ_idx; - u8 volt_rail_idx; -}; - -struct nv_pmu_clk_clk_vf_point_freq_boardobj_set { - struct nv_pmu_clk_clk_vf_point_boardobj_set super; - u16 freq_mhz; - int volt_delta_uv; -}; - -struct nv_pmu_clk_clk_vf_point_volt_boardobj_set { - struct nv_pmu_clk_clk_vf_point_boardobj_set super; - u32 source_voltage_uv; - struct ctrl_clk_freq_delta freq_delta; -}; - -union nv_pmu_clk_clk_vf_point_boardobj_set_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_clk_clk_vf_point_boardobj_set super; - struct nv_pmu_clk_clk_vf_point_freq_boardobj_set freq; - struct nv_pmu_clk_clk_vf_point_volt_boardobj_set volt; -}; - -NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(clk, clk_vf_point); - -struct nv_pmu_clk_clk_vf_point_boardobjgrp_get_status_header { - struct nv_pmu_boardobjgrp_e255 super; - u32 vf_points_cahce_counter; -}; - -struct nv_pmu_clk_clk_vf_point_boardobj_get_status { - struct nv_pmu_boardobj super; - struct ctrl_clk_vf_pair pair; - u8 dummy[38]; -}; - -struct nv_pmu_clk_clk_vf_point_volt_boardobj_get_status { - struct nv_pmu_clk_clk_vf_point_boardobj_get_status super; - u16 vf_gain_value; -}; - -union nv_pmu_clk_clk_vf_point_boardobj_get_status_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_clk_clk_vf_point_boardobj_get_status super; - struct nv_pmu_clk_clk_vf_point_volt_boardobj_get_status volt; -}; - -NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E255(clk, clk_vf_point); - -#define NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS (12) - -struct nv_pmu_clk_clk_domain_list { - u8 num_domains; - struct ctrl_clk_clk_domain_list_item clk_domains[ - NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS]; -}; - -struct nv_pmu_clk_clk_domain_list_v1 { - u8 num_domains; - struct ctrl_clk_clk_domain_list_item_v1 clk_domains[ - NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS]; -}; - -struct nv_pmu_clk_vf_change_inject { - u8 flags; - struct nv_pmu_clk_clk_domain_list clk_list; - struct nv_pmu_volt_volt_rail_list volt_list; -}; - -struct nv_pmu_clk_vf_change_inject_v1 { - u8 flags; - struct nv_pmu_clk_clk_domain_list_v1 clk_list; - struct nv_pmu_volt_volt_rail_list_v1 volt_list; -}; - -#define NV_NV_PMU_CLK_LOAD_FEATURE_VIN (0x00000002) -#define NV_NV_PMU_CLK_LOAD_ACTION_MASK_VIN_HW_CAL_PROGRAM_YES (0x00000001) - -struct nv_pmu_clk_load_payload_freq_controllers { - struct ctrl_boardobjgrp_mask_e32 load_mask; -}; - -struct nv_pmu_clk_load { - u8 feature; - u32 action_mask; - union { - struct nv_pmu_clk_load_payload_freq_controllers freq_controllers; - } payload; -}; - -struct nv_pmu_clk_freq_effective_avg { - u32 clkDomainMask; - u32 freqkHz[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS]; -}; - -/* CLK_FREQ_CONTROLLER */ -#define NV_NV_PMU_CLK_LOAD_FEATURE_FREQ_CONTROLLER (0x00000003) - -#define NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_CONTROLLER_CALLBACK_NO (0x00000000) -#define NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_CONTROLLER_CALLBACK_YES (0x00000002) - -struct nv_pmu_clk_clk_freq_controller_boardobjgrp_set_header { - struct nv_pmu_boardobjgrp_e32 super; - u32 sampling_period_ms; - u8 volt_policy_idx; -}; - -struct nv_pmu_clk_clk_freq_controller_boardobj_set { - struct nv_pmu_boardobj super; - u8 controller_id; - u8 parts_freq_mode; - bool bdisable; - u32 clk_domain; - s16 freq_cap_noise_unaware_vmin_above; - s16 freq_cap_noise_unaware_vmin_below; - s16 freq_hyst_pos_mhz; - s16 freq_hyst_neg_mhz; -}; - -struct nv_pmu_clk_clk_freq_controller_pi_boardobj_set { - struct nv_pmu_clk_clk_freq_controller_boardobj_set super; - s32 prop_gain; - s32 integ_gain; - s32 integ_decay; - s32 volt_delta_min; - s32 volt_delta_max; - u8 slowdown_pct_min; - bool bpoison; -}; - -union nv_pmu_clk_clk_freq_controller_boardobj_set_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_clk_clk_freq_controller_boardobj_set super; - struct nv_pmu_clk_clk_freq_controller_pi_boardobj_set pi; -}; - -NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_freq_controller); - -#define NV_NV_PMU_CLK_LOAD_FEATURE_FREQ_EFFECTIVE_AVG (0x00000004) -#define NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_EFFECTIVE_AVG_CALLBACK_NO (0x00000000) -#define NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_EFFECTIVE_AVG_CALLBACK_YES (0x00000004) - -/* CLK CMD ID definitions. */ -#define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_SET (0x00000001) -#define NV_PMU_CLK_CMD_ID_RPC (0x00000000) -#define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002) - -#define NV_PMU_CLK_RPC_ID_LOAD (0x00000001) -#define NV_PMU_CLK_RPC_ID_CLK_VF_CHANGE_INJECT (0x00000000) -#define NV_PMU_CLK_RPC_ID_CLK_FREQ_EFF_AVG (0x00000002) - -struct nv_pmu_clk_cmd_rpc { - u8 cmd_type; - u8 pad[3]; - struct nv_pmu_allocation request; -}; - -struct nv_pmu_clk_cmd_generic { - u8 cmd_type; - bool b_perf_daemon_cmd; - u8 pad[2]; -}; - -#define NV_PMU_CLK_CMD_RPC_ALLOC_OFFSET \ - (offsetof(struct nv_pmu_clk_cmd_rpc, request)) - -struct nv_pmu_clk_cmd { - union { - u8 cmd_type; - struct nv_pmu_boardobj_cmd_grp grp_set; - struct nv_pmu_clk_cmd_generic generic; - struct nv_pmu_clk_cmd_rpc rpc; - struct nv_pmu_boardobj_cmd_grp grp_get_status; - }; -}; - -struct nv_pmu_clk_rpc { - u8 function; - bool b_supported; - bool b_success; - flcn_status flcn_status; - union { - struct nv_pmu_clk_vf_change_inject clk_vf_change_inject; - struct nv_pmu_clk_vf_change_inject_v1 clk_vf_change_inject_v1; - struct nv_pmu_clk_load clk_load; - struct nv_pmu_clk_freq_effective_avg clk_freq_effective_avg; - } params; -}; - -/* CLK MSG ID definitions */ -#define NV_PMU_CLK_MSG_ID_BOARDOBJ_GRP_SET (0x00000001) -#define NV_PMU_CLK_MSG_ID_RPC (0x00000000) -#define NV_PMU_CLK_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002) - -struct nv_pmu_clk_msg_rpc { - u8 msg_type; - u8 rsvd[3]; - struct nv_pmu_allocation response; -}; - -#define NV_PMU_CLK_MSG_RPC_ALLOC_OFFSET \ - offsetof(struct nv_pmu_clk_msg_rpc, response) - -struct nv_pmu_clk_msg { - union { - u8 msg_type; - struct nv_pmu_boardobj_msg_grp grp_set; - struct nv_pmu_clk_msg_rpc rpc; - struct nv_pmu_boardobj_msg_grp grp_get_status; - }; -}; - -struct nv_pmu_clk_clk_vin_device_boardobjgrp_get_status_header { - struct nv_pmu_boardobjgrp_e32 super; -}; - -struct nv_pmu_clk_clk_vin_device_boardobj_get_status { - struct nv_pmu_boardobj_query super; - u32 actual_voltage_uv; - u32 corrected_voltage_uv; - u8 sampled_code; - u8 override_code; -}; - -union nv_pmu_clk_clk_vin_device_boardobj_get_status_union { - struct nv_pmu_boardobj_query board_obj; - struct nv_pmu_clk_clk_vin_device_boardobj_get_status super; -}; - -NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(clk, clk_vin_device); - -struct nv_pmu_clk_lut_vf_entry { - u32 entry; -}; - -struct nv_pmu_clk_clk_fll_device_boardobjgrp_get_status_header { - struct nv_pmu_boardobjgrp_e32 super; -}; - -struct nv_pmu_clk_clk_fll_device_boardobj_get_status { - struct nv_pmu_boardobj_query super; - u8 current_regime_id; - bool b_dvco_min_reached; - u16 min_freq_mhz; - struct nv_pmu_clk_lut_vf_entry lut_vf_curve[NV_UNSIGNED_ROUNDED_DIV(CTRL_CLK_LUT_NUM_ENTRIES_MAX, 2)]; -}; - -union nv_pmu_clk_clk_fll_device_boardobj_get_status_union { - struct nv_pmu_boardobj_query board_obj; - struct nv_pmu_clk_clk_fll_device_boardobj_get_status super; -}; - -NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(clk, clk_fll_device); - -#endif /*NVGPU_PMUIF_GPMUIFCLK_H*/ diff --git a/include/nvgpu/pmuif/gpmuifperf.h b/include/nvgpu/pmuif/gpmuifperf.h deleted file mode 100644 index 70b93e1..0000000 --- a/include/nvgpu/pmuif/gpmuifperf.h +++ /dev/null @@ -1,154 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_PMUIF_GPMUIFPERF_H -#define NVGPU_PMUIF_GPMUIFPERF_H - -#include "gpmuifvolt.h" -#include "gpmuifperfvfe.h" - -/* -* Enumeration of BOARDOBJGRP class IDs within OBJPERF. Used as "classId" -* argument for communications between Kernel and PMU via the various generic -* BOARDOBJGRP interfaces. -*/ -#define NV_PMU_PERF_BOARDOBJGRP_CLASS_ID_VFE_VAR 0x00U -#define NV_PMU_PERF_BOARDOBJGRP_CLASS_ID_VFE_EQU 0x01U - -#define NV_PMU_PERF_CMD_ID_RPC (0x00000002U) -#define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_SET (0x00000003U) -#define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000004U) - -/*! - * RPC calls serviced by PERF unit. - */ -#define NV_PMU_RPC_ID_PERF_BOARD_OBJ_GRP_CMD 0x00U -#define NV_PMU_RPC_ID_PERF_LOAD 0x01U -#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_INFO_GET 0x02U -#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_INFO_SET 0x03U -#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_SET_CONTROL 0x04U -#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_QUEUE_CHANGE 0x05U -#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_LOCK 0x06U -#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_LOAD 0x07U -#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_QUERY 0x08U -#define NV_PMU_RPC_ID_PERF_PERF_LIMITS_INVALIDATE 0x09U -#define NV_PMU_RPC_ID_PERF_VFE_EQU_EVAL 0x0AU -#define NV_PMU_RPC_ID_PERF_VFE_INVALIDATE 0x0BU -#define NV_PMU_RPC_ID_PERF_VFE_EQU_MONITOR_SET 0x0CU -#define NV_PMU_RPC_ID_PERF_VFE_EQU_MONITOR_GET 0x0DU -#define NV_PMU_RPC_ID_PERF__COUNT 0x0EU -/* - * Defines the structure that holds data - * used to execute LOAD RPC. - */ -struct nv_pmu_rpc_struct_perf_load { - /*[IN/OUT] Must be first field in RPC structure */ - struct nv_pmu_rpc_header hdr; - u32 scratch[1]; -}; - -struct nv_pmu_perf_cmd_set_object { - u8 cmd_type; - u8 pad[2]; - u8 object_type; - struct nv_pmu_allocation object; -}; - -#define NV_PMU_PERF_SET_OBJECT_ALLOC_OFFSET \ - (offsetof(struct nv_pmu_perf_cmd_set_object, object)) - -/* RPC IDs */ -#define NV_PMU_PERF_RPC_ID_VFE_LOAD (0x00000001U) - -/*! -* Command requesting execution of the perf RPC. -*/ -struct nv_pmu_perf_cmd_rpc { - u8 cmd_type; - u8 pad[3]; - struct nv_pmu_allocation request; -}; - -#define NV_PMU_PERF_CMD_RPC_ALLOC_OFFSET \ - offsetof(struct nv_pmu_perf_cmd_rpc, request) - -/*! -* Simply a union of all specific PERF commands. Forms the general packet -* exchanged between the Kernel and PMU when sending and receiving PERF commands -* (respectively). -*/ -struct nv_pmu_perf_cmd { - union { - u8 cmd_type; - struct nv_pmu_perf_cmd_set_object set_object; - struct nv_pmu_boardobj_cmd_grp grp_set; - struct nv_pmu_boardobj_cmd_grp grp_get_status; - }; -}; - -/*! -* Defines the data structure used to invoke PMU perf RPCs. Same structure is -* used to return the result of the RPC execution. -*/ -struct nv_pmu_perf_rpc { - u8 function; - bool b_supported; - bool b_success; - flcn_status flcn_status; - union { - struct nv_pmu_perf_rpc_vfe_equ_eval vfe_equ_eval; - struct nv_pmu_perf_rpc_vfe_load vfe_load; - } params; -}; - - -/* PERF Message-type Definitions */ -#define NV_PMU_PERF_MSG_ID_RPC (0x00000003U) -#define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_SET (0x00000004U) -#define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000006U) -#define NV_PMU_PERF_MSG_ID_VFE_CALLBACK (0x00000005U) - -/*! -* Message carrying the result of the perf RPC execution. -*/ -struct nv_pmu_perf_msg_rpc { - u8 msg_type; - u8 rsvd[3]; - struct nv_pmu_allocation response; -}; - -#define NV_PMU_PERF_MSG_RPC_ALLOC_OFFSET \ - (offsetof(struct nv_pmu_perf_msg_rpc, response)) - -/*! -* Simply a union of all specific PERF messages. Forms the general packet -* exchanged between the Kernel and PMU when sending and receiving PERF messages -* (respectively). -*/ -struct nv_pmu_perf_msg { - union { - u8 msg_type; - struct nv_pmu_perf_msg_rpc rpc; - struct nv_pmu_boardobj_msg_grp grp_set; - }; -}; - -#endif /* NVGPU_PMUIF_GPMUIFPERF_H*/ diff --git a/include/nvgpu/pmuif/gpmuifperfvfe.h b/include/nvgpu/pmuif/gpmuifperfvfe.h deleted file mode 100644 index d128c32..0000000 --- a/include/nvgpu/pmuif/gpmuifperfvfe.h +++ /dev/null @@ -1,206 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_PMUIF_GPMUIFPERFVFE_H -#define NVGPU_PMUIF_GPMUIFPERFVFE_H - -#include "gpmuifbios.h" -#include "gpmuifboardobj.h" -#include "ctrl/ctrlperf.h" - -#define CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT 0x03 -#define NV_PMU_PERF_RPC_VFE_EQU_EVAL_VAR_COUNT_MAX 2 -#define NV_PMU_PERF_RPC_VFE_EQU_MONITOR_COUNT_MAX 16 - -struct nv_pmu_perf_vfe_var_value { - u8 var_type; - u8 reserved[3]; - u32 var_value; -}; - -union nv_pmu_perf_vfe_equ_result { - u32 freq_m_hz; - u32 voltu_v; - u32 vf_gain; - int volt_deltau_v; -}; - -struct nv_pmu_perf_rpc_vfe_equ_eval { - u8 equ_idx; - u8 var_count; - u8 output_type; - struct nv_pmu_perf_vfe_var_value var_values[ - NV_PMU_PERF_RPC_VFE_EQU_EVAL_VAR_COUNT_MAX]; - union nv_pmu_perf_vfe_equ_result result; -}; - -struct nv_pmu_perf_rpc_vfe_load { - bool b_load; -}; - -struct nv_pmu_perf_vfe_var_boardobjgrp_get_status_header { - struct nv_pmu_boardobjgrp_e32 super; -}; - -struct nv_pmu_perf_vfe_var_get_status_super { - struct nv_pmu_boardobj_query board_obj; -}; - -struct nv_pmu_perf_vfe_var_single_sensed_fuse_get_status { - struct nv_pmu_perf_vfe_var_get_status_super super; - struct ctrl_perf_vfe_var_single_sensed_fuse_value fuse_value_integer; - struct ctrl_perf_vfe_var_single_sensed_fuse_value fuse_value_hw_integer; - u8 fuse_version; - bool b_version_check_failed; -}; - -union nv_pmu_perf_vfe_var_boardobj_get_status_union { - struct nv_pmu_boardobj_query board_obj; - struct nv_pmu_perf_vfe_var_get_status_super super; - struct nv_pmu_perf_vfe_var_single_sensed_fuse_get_status fuse_status; -}; - -NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(perf, vfe_var); - -struct nv_pmu_vfe_var { - struct nv_pmu_boardobj super; - u32 out_range_min; - u32 out_range_max; - struct ctrl_boardobjgrp_mask_e32 mask_dependent_vars; - struct ctrl_boardobjgrp_mask_e255 mask_dependent_equs; -}; - -struct nv_pmu_vfe_var_derived { - struct nv_pmu_vfe_var super; -}; - -struct nv_pmu_vfe_var_derived_product { - struct nv_pmu_vfe_var_derived super; - u8 var_idx0; - u8 var_idx1; -}; - -struct nv_pmu_vfe_var_derived_sum { - struct nv_pmu_vfe_var_derived super; - u8 var_idx0; - u8 var_idx1; -}; - -struct nv_pmu_vfe_var_single { - struct nv_pmu_vfe_var super; - u8 override_type; - u32 override_value; -}; - -struct nv_pmu_vfe_var_single_frequency { - struct nv_pmu_vfe_var_single super; -}; - -struct nv_pmu_vfe_var_single_sensed { - struct nv_pmu_vfe_var_single super; -}; - -struct nv_pmu_vfe_var_single_sensed_fuse { - struct nv_pmu_vfe_var_single_sensed super; - struct ctrl_perf_vfe_var_single_sensed_fuse_override_info override_info; - struct ctrl_perf_vfe_var_single_sensed_fuse_vfield_info vfield_info; - struct ctrl_perf_vfe_var_single_sensed_fuse_ver_vfield_info vfield_ver_info; - struct ctrl_perf_vfe_var_single_sensed_fuse_value fuse_val_default; - bool b_fuse_value_signed; -}; - -struct nv_pmu_vfe_var_single_sensed_temp { - struct nv_pmu_vfe_var_single_sensed super; - u8 therm_channel_index; - int temp_hysteresis_positive; - int temp_hysteresis_negative; - int temp_default; -}; - -struct nv_pmu_vfe_var_single_voltage { - struct nv_pmu_vfe_var_single super; -}; - -struct nv_pmu_perf_vfe_var_boardobjgrp_set_header { - struct nv_pmu_boardobjgrp_e32 super; - u8 polling_periodms; -}; - -union nv_pmu_perf_vfe_var_boardobj_set_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_vfe_var var; - struct nv_pmu_vfe_var_derived var_derived; - struct nv_pmu_vfe_var_derived_product var_derived_product; - struct nv_pmu_vfe_var_derived_sum var_derived_sum; - struct nv_pmu_vfe_var_single var_single; - struct nv_pmu_vfe_var_single_frequency var_single_frequiency; - struct nv_pmu_vfe_var_single_sensed var_single_sensed; - struct nv_pmu_vfe_var_single_sensed_fuse var_single_sensed_fuse; - struct nv_pmu_vfe_var_single_sensed_temp var_single_sensed_temp; - struct nv_pmu_vfe_var_single_voltage var_single_voltage; -}; - -NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(perf, vfe_var); - -struct nv_pmu_vfe_equ { - struct nv_pmu_boardobj super; - u8 var_idx; - u8 equ_idx_next; - u8 output_type; - u32 out_range_min; - u32 out_range_max; -}; - -struct nv_pmu_vfe_equ_compare { - struct nv_pmu_vfe_equ super; - u8 func_id; - u8 equ_idx_true; - u8 equ_idx_false; - u32 criteria; -}; - -struct nv_pmu_vfe_equ_minmax { - struct nv_pmu_vfe_equ super; - bool b_max; - u8 equ_idx0; - u8 equ_idx1; -}; - -struct nv_pmu_vfe_equ_quadratic { - struct nv_pmu_vfe_equ super; - u32 coeffs[CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT]; -}; - -struct nv_pmu_perf_vfe_equ_boardobjgrp_set_header { - struct nv_pmu_boardobjgrp_e255 super; -}; - -union nv_pmu_perf_vfe_equ_boardobj_set_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_vfe_equ equ; - struct nv_pmu_vfe_equ_compare equ_comapre; - struct nv_pmu_vfe_equ_minmax equ_minmax; - struct nv_pmu_vfe_equ_quadratic equ_quadratic; -}; - -NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(perf, vfe_equ); - -#endif /* NVGPU_PMUIF_GPMUIFPERFVFE_H*/ diff --git a/include/nvgpu/pmuif/gpmuifpmgr.h b/include/nvgpu/pmuif/gpmuifpmgr.h deleted file mode 100644 index a0e6c82..0000000 --- a/include/nvgpu/pmuif/gpmuifpmgr.h +++ /dev/null @@ -1,443 +0,0 @@ -/* -* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. -* - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. -*/ - -#ifndef NVGPU_PMUIF_GPMUIFPMGR_H -#define NVGPU_PMUIF_GPMUIFPMGR_H - -#include "ctrl/ctrlpmgr.h" -#include "gpmuifboardobj.h" -#include - -struct nv_pmu_pmgr_i2c_device_desc { - struct nv_pmu_boardobj super; - u8 dcb_index; - u16 i2c_address; - u32 i2c_flags; - u8 i2c_port; -}; - -#define NV_PMU_PMGR_I2C_DEVICE_DESC_TABLE_MAX_DEVICES (32U) - -struct nv_pmu_pmgr_i2c_device_desc_table { - u32 dev_mask; - struct nv_pmu_pmgr_i2c_device_desc - devices[NV_PMU_PMGR_I2C_DEVICE_DESC_TABLE_MAX_DEVICES]; -}; - -struct nv_pmu_pmgr_pwr_device_desc { - struct nv_pmu_boardobj super; - u32 power_corr_factor; -}; - -#define NV_PMU_PMGR_PWR_DEVICE_INA3221_CH_NUM 0x03U - -struct nv_pmu_pmgr_pwr_device_desc_ina3221 { - struct nv_pmu_pmgr_pwr_device_desc super; - u8 i2c_dev_idx; - struct ctrl_pmgr_pwr_device_info_rshunt - r_shuntm_ohm[NV_PMU_PMGR_PWR_DEVICE_INA3221_CH_NUM]; - u16 configuration; - u16 mask_enable; - u32 event_mask; - u16 curr_correct_m; - s16 curr_correct_b; -}; - -union nv_pmu_pmgr_pwr_device_desc_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_pmgr_pwr_device_desc pwr_dev; - struct nv_pmu_pmgr_pwr_device_desc_ina3221 ina3221; -}; - -struct nv_pmu_pmgr_pwr_device_ba_info { - bool b_initialized_and_used; -}; - -struct nv_pmu_pmgr_pwr_device_desc_table_header { - struct nv_pmu_boardobjgrp_e32 super; - struct nv_pmu_pmgr_pwr_device_ba_info ba_info; -}; - -NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_device_desc_table_header, - sizeof(struct nv_pmu_pmgr_pwr_device_desc_table_header)); -NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_device_desc_union, - sizeof(union nv_pmu_pmgr_pwr_device_desc_union)); - -struct nv_pmu_pmgr_pwr_device_desc_table { - union nv_pmu_pmgr_pwr_device_desc_table_header_aligned hdr; - union nv_pmu_pmgr_pwr_device_desc_union_aligned - devices[CTRL_PMGR_PWR_DEVICES_MAX_DEVICES]; -}; - -union nv_pmu_pmgr_pwr_device_dmem_size { - union nv_pmu_pmgr_pwr_device_desc_table_header_aligned pwr_device_hdr; - union nv_pmu_pmgr_pwr_device_desc_union_aligned pwr_device; -}; - -struct nv_pmu_pmgr_pwr_channel { - struct nv_pmu_boardobj super; - u8 pwr_rail; - u8 ch_idx; - u32 volt_fixedu_v; - u32 pwr_corr_slope; - s32 pwr_corr_offsetm_w; - u32 curr_corr_slope; - s32 curr_corr_offsetm_a; - u32 dependent_ch_mask; -}; - -#define NV_PMU_PMGR_PWR_CHANNEL_MAX_CHANNELS 16U - -#define NV_PMU_PMGR_PWR_CHANNEL_MAX_CHRELATIONSHIPS 16U - -struct nv_pmu_pmgr_pwr_channel_sensor { - struct nv_pmu_pmgr_pwr_channel super; - u8 pwr_dev_idx; - u8 pwr_dev_prov_idx; -}; - -struct nv_pmu_pmgr_pwr_channel_pmu_compactible { - u8 pmu_compactible_data[56]; -}; - -union nv_pmu_pmgr_pwr_channel_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_pmgr_pwr_channel pwr_channel; - struct nv_pmu_pmgr_pwr_channel_sensor sensor; - struct nv_pmu_pmgr_pwr_channel_pmu_compactible pmu_pwr_channel; -}; - -#define NV_PMU_PMGR_PWR_MONITOR_TYPE_NO_POLLING 0x02U - -struct nv_pmu_pmgr_pwr_monitor_pstate { - u32 hw_channel_mask; -}; - -union nv_pmu_pmgr_pwr_monitor_type_specific { - struct nv_pmu_pmgr_pwr_monitor_pstate pstate; -}; - -struct nv_pmu_pmgr_pwr_chrelationship_pmu_compactible { - u8 pmu_compactible_data[28]; -}; - -union nv_pmu_pmgr_pwr_chrelationship_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_pmgr_pwr_chrelationship_pmu_compactible pmu_pwr_chrelationship; -}; - -struct nv_pmu_pmgr_pwr_channel_header { - struct nv_pmu_boardobjgrp_e32 super; - u8 type; - union nv_pmu_pmgr_pwr_monitor_type_specific type_specific; - u8 sample_count; - u16 sampling_periodms; - u16 sampling_period_low_powerms; - u32 total_gpu_power_channel_mask; - u32 physical_channel_mask; -}; - -struct nv_pmu_pmgr_pwr_chrelationship_header { - struct nv_pmu_boardobjgrp_e32 super; -}; - -NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_channel_header, - sizeof(struct nv_pmu_pmgr_pwr_channel_header)); -NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_chrelationship_header, - sizeof(struct nv_pmu_pmgr_pwr_chrelationship_header)); -NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_chrelationship_union, - sizeof(union nv_pmu_pmgr_pwr_chrelationship_union)); -NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_channel_union, - sizeof(union nv_pmu_pmgr_pwr_channel_union)); - -struct nv_pmu_pmgr_pwr_channel_desc { - union nv_pmu_pmgr_pwr_channel_header_aligned hdr; - union nv_pmu_pmgr_pwr_channel_union_aligned - channels[NV_PMU_PMGR_PWR_CHANNEL_MAX_CHANNELS]; -}; - -struct nv_pmu_pmgr_pwr_chrelationship_desc { - union nv_pmu_pmgr_pwr_chrelationship_header_aligned hdr; - union nv_pmu_pmgr_pwr_chrelationship_union_aligned - ch_rels[NV_PMU_PMGR_PWR_CHANNEL_MAX_CHRELATIONSHIPS]; -}; - -union nv_pmu_pmgr_pwr_monitor_dmem_size { - union nv_pmu_pmgr_pwr_channel_header_aligned channel_hdr; - union nv_pmu_pmgr_pwr_channel_union_aligned channel; - union nv_pmu_pmgr_pwr_chrelationship_header_aligned ch_rels_hdr; - union nv_pmu_pmgr_pwr_chrelationship_union_aligned ch_rels; -}; - -struct nv_pmu_pmgr_pwr_monitor_pack { - struct nv_pmu_pmgr_pwr_channel_desc channels; - struct nv_pmu_pmgr_pwr_chrelationship_desc ch_rels; -}; - -#define NV_PMU_PMGR_PWR_POLICY_MAX_POLICIES 32U - -#define NV_PMU_PMGR_PWR_POLICY_MAX_POLICY_RELATIONSHIPS 32U - -struct nv_pmu_pmgr_pwr_policy { - struct nv_pmu_boardobj super; - u8 ch_idx; - u8 num_limit_inputs; - u8 limit_unit; - u8 sample_mult; - u32 limit_curr; - u32 limit_min; - u32 limit_max; - struct ctrl_pmgr_pwr_policy_info_integral integral; - enum ctrl_pmgr_pwr_policy_filter_type filter_type; - union ctrl_pmgr_pwr_policy_filter_param filter_param; -}; - -struct nv_pmu_pmgr_pwr_policy_hw_threshold { - struct nv_pmu_pmgr_pwr_policy super; - u8 threshold_idx; - u8 low_threshold_idx; - bool b_use_low_threshold; - u16 low_threshold_value; -}; - -struct nv_pmu_pmgr_pwr_policy_sw_threshold { - struct nv_pmu_pmgr_pwr_policy super; - u8 threshold_idx; - u8 low_threshold_idx; - bool b_use_low_threshold; - u16 low_threshold_value; - u8 event_id; -}; - -struct nv_pmu_pmgr_pwr_policy_pmu_compactible { - u8 pmu_compactible_data[68]; -}; - -union nv_pmu_pmgr_pwr_policy_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_pmgr_pwr_policy pwr_policy; - struct nv_pmu_pmgr_pwr_policy_hw_threshold hw_threshold; - struct nv_pmu_pmgr_pwr_policy_sw_threshold sw_threshold; - struct nv_pmu_pmgr_pwr_policy_pmu_compactible pmu_pwr_policy; -}; - -struct nv_pmu_pmgr_pwr_policy_relationship_pmu_compactible { - u8 pmu_compactible_data[24]; -}; - -union nv_pmu_pmgr_pwr_policy_relationship_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_pmgr_pwr_policy_relationship_pmu_compactible pmu_pwr_relationship; -}; - -struct nv_pmu_pmgr_pwr_violation_pmu_compactible { - u8 pmu_compactible_data[16]; -}; - -union nv_pmu_pmgr_pwr_violation_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_pmgr_pwr_violation_pmu_compactible violation; -}; - -#define NV_PMU_PMGR_PWR_POLICY_DESC_TABLE_VERSION_3X 0x30U - -NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_policy_union, - sizeof(union nv_pmu_pmgr_pwr_policy_union)); -NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_policy_relationship_union, - sizeof(union nv_pmu_pmgr_pwr_policy_relationship_union)); - -#define NV_PMU_PERF_DOMAIN_GROUP_MAX_GROUPS 2U - -struct nv_pmu_perf_domain_group_limits -{ - u32 values[NV_PMU_PERF_DOMAIN_GROUP_MAX_GROUPS]; -} ; - -#define NV_PMU_PMGR_RESERVED_PWR_POLICY_MASK_COUNT 0x6U - -struct nv_pmu_pmgr_pwr_policy_desc_header { - struct nv_pmu_boardobjgrp_e32 super; - u8 version; - bool b_enabled; - u8 low_sampling_mult; - u8 semantic_policy_tbl[CTRL_PMGR_PWR_POLICY_IDX_NUM_INDEXES]; - u16 base_sample_period; - u16 min_client_sample_period; - u32 reserved_pmu_policy_mask[NV_PMU_PMGR_RESERVED_PWR_POLICY_MASK_COUNT]; - struct nv_pmu_perf_domain_group_limits global_ceiling; -}; - -NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_policy_desc_header , - sizeof(struct nv_pmu_pmgr_pwr_policy_desc_header )); - -struct nv_pmu_pmgr_pwr_policyrel_desc_header { - struct nv_pmu_boardobjgrp_e32 super; -}; - -NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_policyrel_desc_header, - sizeof(struct nv_pmu_pmgr_pwr_policyrel_desc_header)); - -struct nv_pmu_pmgr_pwr_violation_desc_header { - struct nv_pmu_boardobjgrp_e32 super; -}; - -NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_violation_desc_header, - sizeof(struct nv_pmu_pmgr_pwr_violation_desc_header)); -NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_violation_union, - sizeof(union nv_pmu_pmgr_pwr_violation_union)); - -struct nv_pmu_pmgr_pwr_policy_desc { - union nv_pmu_pmgr_pwr_policy_desc_header_aligned hdr; - union nv_pmu_pmgr_pwr_policy_union_aligned - policies[NV_PMU_PMGR_PWR_POLICY_MAX_POLICIES]; -}; - -struct nv_pmu_pmgr_pwr_policyrel_desc { - union nv_pmu_pmgr_pwr_policyrel_desc_header_aligned hdr; - union nv_pmu_pmgr_pwr_policy_relationship_union_aligned - policy_rels[NV_PMU_PMGR_PWR_POLICY_MAX_POLICY_RELATIONSHIPS]; -}; - -struct nv_pmu_pmgr_pwr_violation_desc { - union nv_pmu_pmgr_pwr_violation_desc_header_aligned hdr; - union nv_pmu_pmgr_pwr_violation_union_aligned - violations[CTRL_PMGR_PWR_VIOLATION_MAX]; -}; - -union nv_pmu_pmgr_pwr_policy_dmem_size { - union nv_pmu_pmgr_pwr_policy_desc_header_aligned policy_hdr; - union nv_pmu_pmgr_pwr_policy_union_aligned policy; - union nv_pmu_pmgr_pwr_policyrel_desc_header_aligned policy_rels_hdr; - union nv_pmu_pmgr_pwr_policy_relationship_union_aligned policy_rels; - union nv_pmu_pmgr_pwr_violation_desc_header_aligned violation_hdr; - union nv_pmu_pmgr_pwr_violation_union_aligned violation; -}; - -struct nv_pmu_pmgr_pwr_policy_pack { - struct nv_pmu_pmgr_pwr_policy_desc policies; - struct nv_pmu_pmgr_pwr_policyrel_desc policy_rels; - struct nv_pmu_pmgr_pwr_violation_desc violations; -}; - -#define NV_PMU_PMGR_CMD_ID_SET_OBJECT (0x00000000U) - -#define NV_PMU_PMGR_MSG_ID_QUERY (0x00000002U) - -#define NV_PMU_PMGR_CMD_ID_PWR_DEVICES_QUERY (0x00000001U) - -#define NV_PMU_PMGR_CMD_ID_LOAD (0x00000006U) - -#define NV_PMU_PMGR_CMD_ID_UNLOAD (0x00000007U) - -struct nv_pmu_pmgr_cmd_set_object { - u8 cmd_type; - u8 pad[2]; - u8 object_type; - struct nv_pmu_allocation object; -}; - -#define NV_PMU_PMGR_SET_OBJECT_ALLOC_OFFSET (0x04U) - -#define NV_PMU_PMGR_OBJECT_I2C_DEVICE_DESC_TABLE (0x00000000U) - -#define NV_PMU_PMGR_OBJECT_PWR_DEVICE_DESC_TABLE (0x00000001U) - -#define NV_PMU_PMGR_OBJECT_PWR_MONITOR (0x00000002U) - -#define NV_PMU_PMGR_OBJECT_PWR_POLICY (0x00000005U) - -struct nv_pmu_pmgr_pwr_devices_query_payload { - struct { - u32 powerm_w; - u32 voltageu_v; - u32 currentm_a; - } devices[CTRL_PMGR_PWR_DEVICES_MAX_DEVICES]; -}; - -struct nv_pmu_pmgr_cmd_pwr_devices_query { - u8 cmd_type; - u8 pad[3]; - u32 dev_mask; - struct nv_pmu_allocation payload; -}; - -#define NV_PMU_PMGR_PWR_DEVICES_QUERY_ALLOC_OFFSET (0x08U) - -struct nv_pmu_pmgr_cmd_load { - u8 cmd_type; -}; - -struct nv_pmu_pmgr_cmd_unload { - u8 cmd_type; -}; - -struct nv_pmu_pmgr_cmd { - union { - u8 cmd_type; - struct nv_pmu_pmgr_cmd_set_object set_object; - struct nv_pmu_pmgr_cmd_pwr_devices_query pwr_dev_query; - struct nv_pmu_pmgr_cmd_load load; - struct nv_pmu_pmgr_cmd_unload unload; - }; -}; - -#define NV_PMU_PMGR_MSG_ID_SET_OBJECT (0x00000000U) - -#define NV_PMU_PMGR_MSG_ID_LOAD (0x00000004U) - -#define NV_PMU_PMGR_MSG_ID_UNLOAD (0x00000005U) - -struct nv_pmu_pmgr_msg_set_object { - u8 msg_type; - bool b_success; - flcn_status flcnstatus; - u8 object_type; -}; - -struct nv_pmu_pmgr_msg_query { - u8 msg_type; - bool b_success; - flcn_status flcnstatus; - u8 cmd_type; -}; - -struct nv_pmu_pmgr_msg_load { - u8 msg_type; - bool b_success; - flcn_status flcnstatus; -}; - -struct nv_pmu_pmgr_msg_unload { - u8 msg_type; -}; - -struct nv_pmu_pmgr_msg { - union { - u8 msg_type; - struct nv_pmu_pmgr_msg_set_object set_object; - struct nv_pmu_pmgr_msg_query query; - struct nv_pmu_pmgr_msg_load load; - struct nv_pmu_pmgr_msg_unload unload; - }; -}; - -#endif /* NVGPU_PMUIF_GPMUIFPMGR_H */ diff --git a/include/nvgpu/pmuif/gpmuifseq.h b/include/nvgpu/pmuif/gpmuifseq.h deleted file mode 100644 index af93a6e..0000000 --- a/include/nvgpu/pmuif/gpmuifseq.h +++ /dev/null @@ -1,82 +0,0 @@ -/* -* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. -* - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. -*/ -#ifndef NVGPU_PMUIF_GPMUIFSEQ_H -#define NVGPU_PMUIF_GPMUIFSEQ_H - -#include - -#define PMU_UNIT_SEQ (0x02) - -/*! -* @file gpmuifseq.h -* @brief PMU Command/Message Interfaces - Sequencer -*/ - -/*! -* Defines the identifiers various high-level types of sequencer commands. -* -* _RUN_SCRIPT @ref NV_PMU_SEQ_CMD_RUN_SCRIPT -*/ -enum { - NV_PMU_SEQ_CMD_ID_RUN_SCRIPT = 0, -}; - -struct nv_pmu_seq_cmd_run_script { - u8 cmd_type; - u8 pad[3]; - struct pmu_allocation_v3 script_alloc; - struct pmu_allocation_v3 reg_alloc; -}; - -#define NV_PMU_SEQ_CMD_ALLOC_OFFSET 4 - -#define NV_PMU_SEQ_MSG_ALLOC_OFFSET \ - (NV_PMU_SEQ_CMD_ALLOC_OFFSET + NV_PMU_CMD_ALLOC_SIZE) - -struct nv_pmu_seq_cmd { - struct pmu_hdr hdr; - union { - u8 cmd_type; - struct nv_pmu_seq_cmd_run_script run_script; - }; -}; - -enum { - NV_PMU_SEQ_MSG_ID_RUN_SCRIPT = 0, -}; - -struct nv_pmu_seq_msg_run_script { - u8 msg_type; - u8 error_code; - u16 error_pc; - u32 timeout_stat; -}; - -struct nv_pmu_seq_msg { - struct pmu_hdr hdr; - union { - u8 msg_type; - struct nv_pmu_seq_msg_run_script run_script; - }; -}; - -#endif /* NVGPU_PMUIF_GPMUIFSEQ_H */ diff --git a/include/nvgpu/pmuif/gpmuiftherm.h b/include/nvgpu/pmuif/gpmuiftherm.h deleted file mode 100644 index 115e7ab..0000000 --- a/include/nvgpu/pmuif/gpmuiftherm.h +++ /dev/null @@ -1,102 +0,0 @@ -/* -* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. -* - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. -*/ - -#ifndef NVGPU_PMUIF_GPMUIFTHERM_H -#define NVGPU_PMUIF_GPMUIFTHERM_H - -#include - -#define NV_PMU_THERM_CMD_ID_RPC 0x00000002 -#define NV_PMU_THERM_MSG_ID_RPC 0x00000002 -#define NV_PMU_THERM_RPC_ID_SLCT 0x00000000 -#define NV_PMU_THERM_RPC_ID_SLCT_EVENT_TEMP_TH_SET 0x00000006 -#define NV_PMU_THERM_EVENT_THERMAL_1 0x00000004 -#define NV_PMU_THERM_CMD_ID_HW_SLOWDOWN_NOTIFICATION 0x00000001 -#define NV_RM_PMU_THERM_HW_SLOWDOWN_NOTIFICATION_REQUEST_ENABLE 0x00000001 -#define NV_PMU_THERM_MSG_ID_EVENT_HW_SLOWDOWN_NOTIFICATION 0x00000001 - -struct nv_pmu_therm_rpc_slct_event_temp_th_set { - s32 temp_threshold; - u8 event_id; - flcn_status flcn_stat; -}; - -struct nv_pmu_therm_rpc_slct { - u32 mask_enabled; - flcn_status flcn_stat; -}; - -struct nv_pmu_therm_rpc { - u8 function; - bool b_supported; - union { - struct nv_pmu_therm_rpc_slct slct; - struct nv_pmu_therm_rpc_slct_event_temp_th_set slct_event_temp_th_set; - } params; -}; - -struct nv_pmu_therm_cmd_rpc { - u8 cmd_type; - u8 pad[3]; - struct nv_pmu_allocation request; -}; - -struct nv_pmu_therm_cmd_hw_slowdown_notification { - u8 cmd_type; - u8 request; -}; - -#define NV_PMU_THERM_CMD_RPC_ALLOC_OFFSET \ - offsetof(struct nv_pmu_therm_cmd_rpc, request) - -struct nv_pmu_therm_cmd { - union { - u8 cmd_type; - struct nv_pmu_therm_cmd_rpc rpc; - struct nv_pmu_therm_cmd_hw_slowdown_notification hw_slct_notification; - }; -}; - -struct nv_pmu_therm_msg_rpc { - u8 msg_type; - u8 rsvd[3]; - struct nv_pmu_allocation response; -}; - -struct nv_pmu_therm_msg_event_hw_slowdown_notification { - u8 msg_type; - u32 mask; -}; - -#define NV_PMU_THERM_MSG_RPC_ALLOC_OFFSET \ - offsetof(struct nv_pmu_therm_msg_rpc, response) - -struct nv_pmu_therm_msg { - union { - u8 msg_type; - struct nv_pmu_therm_msg_rpc rpc; - struct nv_pmu_therm_msg_event_hw_slowdown_notification hw_slct_msg; - }; -}; - -#endif /* NVGPU_PMUIF_GPMUIFTHERM_H */ - diff --git a/include/nvgpu/pmuif/gpmuifthermsensor.h b/include/nvgpu/pmuif/gpmuifthermsensor.h deleted file mode 100644 index 47d35da..0000000 --- a/include/nvgpu/pmuif/gpmuifthermsensor.h +++ /dev/null @@ -1,105 +0,0 @@ -/* -* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. -* - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. -*/ - -#ifndef NVGPU_PMUIF_GPMUIFTHERMSENSOR_H -#define NVGPU_PMUIF_GPMUIFTHERMSENSOR_H - -#include "ctrl/ctrltherm.h" -#include "gpmuifboardobj.h" -#include - -#define NV_PMU_THERM_BOARDOBJGRP_CLASS_ID_THERM_DEVICE 0x00 -#define NV_PMU_THERM_BOARDOBJGRP_CLASS_ID_THERM_CHANNEL 0x01 - -#define NV_PMU_THERM_CMD_ID_BOARDOBJ_GRP_SET 0x0000000B -#define NV_PMU_THERM_MSG_ID_BOARDOBJ_GRP_SET 0x00000008 - -struct nv_pmu_therm_therm_device_boardobjgrp_set_header { - struct nv_pmu_boardobjgrp_e32 super; -}; - -struct nv_pmu_therm_therm_device_boardobj_set { - struct nv_pmu_boardobj super; -}; - -struct nv_pmu_therm_therm_device_gpu_gpc_tsosc_boardobj_set { - struct nv_pmu_therm_therm_device_boardobj_set super; - u8 gpc_tsosc_idx; -}; - -struct nv_pmu_therm_therm_device_gpu_sci_boardobj_set { - struct nv_pmu_therm_therm_device_boardobj_set super; -}; - -struct nv_pmu_therm_therm_device_i2c_boardobj_set { - struct nv_pmu_therm_therm_device_boardobj_set super; - u8 i2c_dev_idx; -}; - -struct nv_pmu_therm_therm_device_hbm2_site_boardobj_set { - struct nv_pmu_therm_therm_device_boardobj_set super; - u8 site_idx; -}; - -struct nv_pmu_therm_therm_device_hbm2_combined_boardobj_set { - struct nv_pmu_therm_therm_device_boardobj_set super; -}; - -union nv_pmu_therm_therm_device_boardobj_set_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_therm_therm_device_boardobj_set therm_device; - struct nv_pmu_therm_therm_device_gpu_gpc_tsosc_boardobj_set gpu_gpc_tsosc; - struct nv_pmu_therm_therm_device_gpu_sci_boardobj_set gpu_sci; - struct nv_pmu_therm_therm_device_i2c_boardobj_set i2c; - struct nv_pmu_therm_therm_device_hbm2_site_boardobj_set hbm2_site; - struct nv_pmu_therm_therm_device_hbm2_combined_boardobj_set hbm2_combined; -}; - -NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(therm, therm_device); - -struct nv_pmu_therm_therm_channel_boardobjgrp_set_header { - struct nv_pmu_boardobjgrp_e32 super; -}; - -struct nv_pmu_therm_therm_channel_boardobj_set { - struct nv_pmu_boardobj super; - s16 scaling; - s16 offset; - s32 temp_min; - s32 temp_max; -}; - -struct nv_pmu_therm_therm_channel_device_boardobj_set { - struct nv_pmu_therm_therm_channel_boardobj_set super; - u8 therm_dev_idx; - u8 therm_dev_prov_idx; -}; - -union nv_pmu_therm_therm_channel_boardobj_set_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_therm_therm_channel_boardobj_set therm_channel; - struct nv_pmu_therm_therm_channel_device_boardobj_set device; -}; - -NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(therm, therm_channel); - -#endif /* NVGPU_PMUIF_GPMUIFTHERMSENSOR_H */ diff --git a/include/nvgpu/pmuif/gpmuifvolt.h b/include/nvgpu/pmuif/gpmuifvolt.h deleted file mode 100644 index 0161719..0000000 --- a/include/nvgpu/pmuif/gpmuifvolt.h +++ /dev/null @@ -1,402 +0,0 @@ -/* -* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. -* - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. -*/ -#ifndef NVGPU_PMUIF_GPMUIFVOLT_H -#define NVGPU_PMUIF_GPMUIFVOLT_H - -#include "gpmuifboardobj.h" -#include -#include "ctrl/ctrlvolt.h" - -#define NV_PMU_VOLT_VALUE_0V_IN_UV (0U) - -/* ------------- VOLT_RAIL's GRP_SET defines and structures ------------- */ - -#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_RAIL 0x00U -#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_DEVICE 0x01U -#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_POLICY 0x02U - - -struct nv_pmu_volt_volt_rail_boardobjgrp_set_header { - struct nv_pmu_boardobjgrp_e32 super; -}; - -struct nv_pmu_volt_volt_rail_boardobj_set { - - struct nv_pmu_boardobj super; - u8 rel_limit_vfe_equ_idx; - u8 alt_rel_limit_vfe_equ_idx; - u8 ov_limit_vfe_equ_idx; - u8 vmin_limit_vfe_equ_idx; - u8 volt_margin_limit_vfe_equ_idx; - u8 pwr_equ_idx; - u8 volt_dev_idx_default; - u8 volt_dev_idx_ipc_vmin; - u8 volt_scale_exp_pwr_equ_idx; - struct ctrl_boardobjgrp_mask_e32 volt_dev_mask; - s32 volt_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES]; -}; - -union nv_pmu_volt_volt_rail_boardobj_set_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_volt_volt_rail_boardobj_set super; -}; - -NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_rail); - -/* ------------ VOLT_DEVICE's GRP_SET defines and structures ------------ */ - -struct nv_pmu_volt_volt_device_boardobjgrp_set_header { - struct nv_pmu_boardobjgrp_e32 super; -}; - -struct nv_pmu_volt_volt_device_boardobj_set { - struct nv_pmu_boardobj super; - u32 switch_delay_us; - u32 voltage_min_uv; - u32 voltage_max_uv; - u32 volt_step_uv; -}; - -struct nv_pmu_volt_volt_device_vid_boardobj_set { - struct nv_pmu_volt_volt_device_boardobj_set super; - s32 voltage_base_uv; - s32 voltage_offset_scale_uv; - u8 gpio_pin[CTRL_VOLT_VOLT_DEV_VID_VSEL_MAX_ENTRIES]; - u8 vsel_mask; -}; - -struct nv_pmu_volt_volt_device_pwm_boardobj_set { - struct nv_pmu_volt_volt_device_boardobj_set super; - u32 raw_period; - s32 voltage_base_uv; - s32 voltage_offset_scale_uv; - enum nv_pmu_pmgr_pwm_source pwm_source; -}; - -union nv_pmu_volt_volt_device_boardobj_set_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_volt_volt_device_boardobj_set super; - struct nv_pmu_volt_volt_device_vid_boardobj_set vid; - struct nv_pmu_volt_volt_device_pwm_boardobj_set pwm; -}; - -NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_device); - -/* ------------ VOLT_POLICY's GRP_SET defines and structures ------------ */ -struct nv_pmu_volt_volt_policy_boardobjgrp_set_header { - struct nv_pmu_boardobjgrp_e32 super; - u8 perf_core_vf_seq_policy_idx; -}; - -struct nv_pmu_volt_volt_policy_boardobj_set { - struct nv_pmu_boardobj super; -}; -struct nv_pmu_volt_volt_policy_sr_boardobj_set { - struct nv_pmu_volt_volt_policy_boardobj_set super; - u8 rail_idx; -}; - -struct nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set { - struct nv_pmu_volt_volt_policy_sr_boardobj_set super; - u16 inter_switch_delay_us; - u32 ramp_up_step_size_uv; - u32 ramp_down_step_size_uv; -}; - -struct nv_pmu_volt_volt_policy_splt_r_boardobj_set { - struct nv_pmu_volt_volt_policy_boardobj_set super; - u8 rail_idx_master; - u8 rail_idx_slave; - u8 delta_min_vfe_equ_idx; - u8 delta_max_vfe_equ_idx; - s32 offset_delta_min_uv; - s32 offset_delta_max_uv; -}; - -struct nv_pmu_volt_volt_policy_srms_boardobj_set { - struct nv_pmu_volt_volt_policy_splt_r_boardobj_set super; - u16 inter_switch_delayus; -}; - -/* sr - > single_rail */ -struct nv_pmu_volt_volt_policy_srss_boardobj_set { - struct nv_pmu_volt_volt_policy_splt_r_boardobj_set super; -}; - -union nv_pmu_volt_volt_policy_boardobj_set_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_volt_volt_policy_boardobj_set super; - struct nv_pmu_volt_volt_policy_sr_boardobj_set single_rail; - struct nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set - single_rail_ms; - struct nv_pmu_volt_volt_policy_splt_r_boardobj_set split_rail; - struct nv_pmu_volt_volt_policy_srms_boardobj_set - split_rail_m_s; - struct nv_pmu_volt_volt_policy_srss_boardobj_set - split_rail_s_s; -}; - -NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_policy); - -/* ----------- VOLT_RAIL's GRP_GET_STATUS defines and structures ----------- */ -struct nv_pmu_volt_volt_rail_boardobjgrp_get_status_header { - struct nv_pmu_boardobjgrp_e32 super; -}; - -struct nv_pmu_volt_volt_rail_boardobj_get_status { - struct nv_pmu_boardobj_query super; - u32 curr_volt_defaultu_v; - u32 rel_limitu_v; - u32 alt_rel_limitu_v; - u32 ov_limitu_v; - u32 max_limitu_v; - u32 vmin_limitu_v; - s32 volt_margin_limitu_v; - u32 rsvd; -}; - -union nv_pmu_volt_volt_rail_boardobj_get_status_union { - struct nv_pmu_boardobj_query board_obj; - struct nv_pmu_volt_volt_rail_boardobj_get_status super; -}; - -NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(volt, volt_rail); - -/* ---------- VOLT_DEVICE's GRP_GET_STATUS defines and structures ---------- */ -struct nv_pmu_volt_volt_device_boardobjgrp_get_status_header { - struct nv_pmu_boardobjgrp_e32 super; -}; - -struct nv_pmu_volt_volt_device_boardobj_get_status { - struct nv_pmu_boardobj_query super; -}; - -union nv_pmu_volt_volt_device_boardobj_get_status_union { - struct nv_pmu_boardobj_query board_obj; - struct nv_pmu_volt_volt_device_boardobj_get_status super; -}; - -NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(volt, volt_device); - -/* ---------- VOLT_POLICY's GRP_GET_STATUS defines and structures ---------- */ -struct nv_pmu_volt_volt_policy_boardobjgrp_get_status_header { - struct nv_pmu_boardobjgrp_e32 super; -}; - -struct nv_pmu_volt_volt_policy_boardobj_get_status { - struct nv_pmu_boardobj_query super; - u32 offset_volt_requ_v; - u32 offset_volt_curru_v; -}; - -struct nv_pmu_volt_volt_policy_sr_boardobj_get_status { - struct nv_pmu_volt_volt_policy_boardobj_get_status super; - u32 curr_voltu_v; -}; - -struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status { - struct nv_pmu_volt_volt_policy_boardobj_get_status super; - s32 delta_minu_v; - s32 delta_maxu_v; - s32 orig_delta_minu_v; - s32 orig_delta_maxu_v; - u32 curr_volt_masteru_v; - u32 curr_volt_slaveu_v; - bool b_violation; -}; - -/* srms -> split_rail_multi_step */ -struct nv_pmu_volt_volt_policy_srms_boardobj_get_status { - struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status super; -}; - -/* srss -> split_rail_single_step */ -struct nv_pmu_volt_volt_policy_srss_boardobj_get_status { - struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status super; -}; - -union nv_pmu_volt_volt_policy_boardobj_get_status_union { - struct nv_pmu_boardobj_query board_obj; - struct nv_pmu_volt_volt_policy_boardobj_get_status super; - struct nv_pmu_volt_volt_policy_sr_boardobj_get_status single_rail; - struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status split_rail; - struct nv_pmu_volt_volt_policy_srms_boardobj_get_status - split_rail_m_s; - struct nv_pmu_volt_volt_policy_srss_boardobj_get_status - split_rail_s_s; -}; - -NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(volt, volt_policy); - -struct nv_pmu_volt_policy_voltage_data { - u8 policy_idx; - struct ctrl_perf_volt_rail_list - rail_list; -}; - -struct nv_pmu_volt_rail_get_voltage { - u8 rail_idx; - u32 voltage_uv; -}; - -struct nv_pmu_volt_volt_rail_set_noise_unaware_vmin { - u8 num_rails; - struct ctrl_volt_volt_rail_list - rail_list; -}; - -#define NV_PMU_VOLT_CMD_ID_BOARDOBJ_GRP_SET (0x00000000U) -#define NV_PMU_VOLT_CMD_ID_RPC (0x00000001U) -#define NV_PMU_VOLT_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002U) -#define NV_PMU_VOLT_RPC_ID_VOLT_RAIL_SET_NOISE_UNAWARE_VMIN (0x00000004U) - -/*! -* PMU VOLT RPC calls. -*/ -#define NV_PMU_VOLT_RPC_ID_LOAD (0x00000000U) -#define NV_PMU_VOLT_RPC_ID_VOLT_POLICY_SET_VOLTAGE (0x00000002U) -#define NV_PMU_VOLT_RPC_ID_VOLT_RAIL_GET_VOLTAGE (0x00000003U) - -struct nv_pmu_volt_cmd_rpc { - u8 cmd_type; - u8 pad[3]; - struct nv_pmu_allocation request; -}; - -#define NV_PMU_VOLT_CMD_RPC_ALLOC_OFFSET \ - offsetof(struct nv_pmu_volt_cmd_rpc, request) - -struct nv_pmu_volt_cmd { - union { - u8 cmd_type; - struct nv_pmu_boardobj_cmd_grp grp_set; - struct nv_pmu_volt_cmd_rpc rpc; - struct nv_pmu_boardobj_cmd_grp grp_get_status; - }; -}; - -struct nv_pmu_volt_rpc { - u8 function; - bool b_supported; - bool b_success; - flcn_status flcn_status; - union { - struct nv_pmu_volt_policy_voltage_data volt_policy_voltage_data; - struct nv_pmu_volt_rail_get_voltage volt_rail_get_voltage; - struct nv_pmu_volt_volt_rail_set_noise_unaware_vmin - volt_rail_set_noise_unaware_vmin; - } params; -}; - -/*! -* VOLT MSG ID definitions -*/ -#define NV_PMU_VOLT_MSG_ID_BOARDOBJ_GRP_SET (0x00000000U) -#define NV_PMU_VOLT_MSG_ID_RPC (0x00000001U) -#define NV_PMU_VOLT_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002U) - -/*! -* Message carrying the result of the VOLT RPC execution. -*/ -struct nv_pmu_volt_msg_rpc { - u8 msg_type; - u8 rsvd[3]; - struct nv_pmu_allocation response; -}; - -#define NV_PMU_VOLT_MSG_RPC_ALLOC_OFFSET \ - offsetof(struct nv_pmu_volt_msg_rpc, response) - -struct nv_pmu_volt_msg { - union { - u8 msg_type; - struct nv_pmu_boardobj_msg_grp grp_set; - struct nv_pmu_volt_msg_rpc rpc; - struct nv_pmu_boardobj_msg_grp grp_get_status; - }; -}; - -#define NV_PMU_VF_INJECT_MAX_VOLT_RAILS (2U) - -struct nv_pmu_volt_volt_rail_list { - u8 num_rails; - struct ctrl_perf_volt_rail_list_item - rails[NV_PMU_VF_INJECT_MAX_VOLT_RAILS]; -}; - -struct nv_pmu_volt_volt_rail_list_v1 { - u8 num_rails; - struct ctrl_volt_volt_rail_list_item_v1 - rails[NV_PMU_VF_INJECT_MAX_VOLT_RAILS]; -}; - -/* VOLT RPC */ -#define NV_PMU_RPC_ID_VOLT_BOARD_OBJ_GRP_CMD 0x00U -#define NV_PMU_RPC_ID_VOLT_VOLT_SET_VOLTAGE 0x01U -#define NV_PMU_RPC_ID_VOLT_LOAD 0x02U -#define NV_PMU_RPC_ID_VOLT_VOLT_RAIL_GET_VOLTAGE 0x03U -#define NV_PMU_RPC_ID_VOLT_VOLT_POLICY_SANITY_CHECK 0x04U -#define NV_PMU_RPC_ID_VOLT_TEST_EXECUTE 0x05U -#define NV_PMU_RPC_ID_VOLT__COUNT 0x06U - -/* - * Defines the structure that holds data - * used to execute LOAD RPC. - */ -struct nv_pmu_rpc_struct_volt_load { - /*[IN/OUT] Must be first field in RPC structure */ - struct nv_pmu_rpc_header hdr; - u32 scratch[1]; -}; - -/* - * Defines the structure that holds data - * used to execute VOLT_SET_VOLTAGE RPC. - */ -struct nv_pmu_rpc_struct_volt_volt_set_voltage { - /*[IN/OUT] Must be first field in RPC structure */ - struct nv_pmu_rpc_header hdr; - /*[IN] ID of the client that wants to set the voltage */ - u8 client_id; - /* - * [IN] The list containing target voltage and - * noise-unaware Vmin value for the VOLT_RAILs. - */ - struct ctrl_volt_volt_rail_list_v1 rail_list; - u32 scratch[1]; -}; - -/* - * Defines the structure that holds data - * used to execute VOLT_RAIL_GET_VOLTAGE RPC. - */ -struct nv_pmu_rpc_struct_volt_volt_rail_get_voltage { - /*[IN/OUT] Must be first field in RPC structure */ - struct nv_pmu_rpc_header hdr; - /* [OUT] Current voltage in uv */ - u32 voltage_uv; - /* [IN] Voltage Rail Table Index */ - u8 rail_idx; - u32 scratch[1]; -}; - -#endif /* NVGPU_PMUIF_GPMUIFVOLT_H*/ diff --git a/include/nvgpu/pmuif/nvgpu_gpmu_cmdif.h b/include/nvgpu/pmuif/nvgpu_gpmu_cmdif.h deleted file mode 100644 index ce55f67..0000000 --- a/include/nvgpu/pmuif/nvgpu_gpmu_cmdif.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_PMUIF_NVGPU_GPMU_CMDIF_H -#define NVGPU_PMUIF_NVGPU_GPMU_CMDIF_H - -#include -#include "gpmuif_cmn.h" -#include "gpmuif_pmu.h" -#include "gpmuif_ap.h" -#include "gpmuif_pg.h" -#include "gpmuif_perfmon.h" -#include "gpmuif_acr.h" -#include "gpmuifboardobj.h" -#include "gpmuifclk.h" -#include "gpmuifperf.h" -#include "gpmuifperfvfe.h" -#include "gpmuifpmgr.h" -#include "gpmuifvolt.h" -#include "gpmuiftherm.h" -#include "gpmuifthermsensor.h" -#include "gpmuifseq.h" -#include "gpmu_super_surf_if.h" - -/* - * Command requesting execution of the RPC (Remote Procedure Call) - */ -struct nv_pmu_rpc_cmd { - /* Must be set to @ref NV_PMU_RPC_CMD_ID */ - u8 cmd_type; - /* RPC call flags (@see PMU_RPC_FLAGS) */ - u8 flags; - /* Size of RPC structure allocated - * within NV managed DMEM heap - */ - u16 rpc_dmem_size; - /* - * DMEM pointer of RPC structure allocated - * within RM managed DMEM heap. - */ - u32 rpc_dmem_ptr; -}; - -#define NV_PMU_RPC_CMD_ID 0x80U - -/* Message carrying the result of the RPC execution */ -struct nv_pmu_rpc_msg { - /* Must be set to @ref NV_PMU_RPC_MSG_ID */ - u8 msg_type; - /* RPC call flags (@see PMU_RPC_FLAGS)*/ - u8 flags; - /* - * Size of RPC structure allocated - * within NV managed DMEM heap. - */ - u16 rpc_dmem_size; - /* - * DMEM pointer of RPC structure allocated - * within NV managed DMEM heap. - */ - u32 rpc_dmem_ptr; -}; - -#define NV_PMU_RPC_MSG_ID 0x80U - -struct pmu_cmd { - struct pmu_hdr hdr; - union { - struct pmu_perfmon_cmd perfmon; - struct pmu_pg_cmd pg; - struct pmu_zbc_cmd zbc; - struct pmu_acr_cmd acr; - struct nv_pmu_boardobj_cmd boardobj; - struct nv_pmu_perf_cmd perf; - struct nv_pmu_volt_cmd volt; - struct nv_pmu_clk_cmd clk; - struct nv_pmu_pmgr_cmd pmgr; - struct nv_pmu_therm_cmd therm; - struct nv_pmu_rpc_cmd rpc; - } cmd; -}; - -struct pmu_msg { - struct pmu_hdr hdr; - union { - struct pmu_init_msg init; - struct pmu_perfmon_msg perfmon; - struct pmu_pg_msg pg; - struct pmu_rc_msg rc; - struct pmu_acr_msg acr; - struct nv_pmu_boardobj_msg boardobj; - struct nv_pmu_perf_msg perf; - struct nv_pmu_volt_msg volt; - struct nv_pmu_clk_msg clk; - struct nv_pmu_pmgr_msg pmgr; - struct nv_pmu_therm_msg therm; - struct nv_pmu_rpc_msg rpc; - } msg; -}; - -#define PMU_UNIT_REWIND (0x00U) -#define PMU_UNIT_PG (0x03U) -#define PMU_UNIT_INIT (0x07U) -#define PMU_UNIT_ACR (0x0AU) -#define PMU_UNIT_PERFMON_T18X (0x11U) -#define PMU_UNIT_PERFMON (0x12U) -#define PMU_UNIT_PERF (0x13U) -#define PMU_UNIT_RC (0x1FU) -#define PMU_UNIT_FECS_MEM_OVERRIDE (0x1EU) -#define PMU_UNIT_CLK (0x0DU) -#define PMU_UNIT_THERM (0x14U) -#define PMU_UNIT_PMGR (0x18U) -#define PMU_UNIT_VOLT (0x0EU) - -#define PMU_UNIT_END (0x23U) -#define PMU_UNIT_INVALID (0xFFU) - -#define PMU_UNIT_TEST_START (0xFEU) -#define PMU_UNIT_END_SIM (0xFFU) -#define PMU_UNIT_TEST_END (0xFFU) - -#define PMU_UNIT_ID_IS_VALID(id) \ - (((id) < PMU_UNIT_END) || ((id) >= PMU_UNIT_TEST_START)) - -#endif /* NVGPU_PMUIF_NVGPU_GPMU_CMDIF_H*/ diff --git a/include/nvgpu/posix/atomic.h b/include/nvgpu/posix/atomic.h deleted file mode 100644 index c9d9212..0000000 --- a/include/nvgpu/posix/atomic.h +++ /dev/null @@ -1,191 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NVGPU_POSIX_ATOMIC_H__ -#define __NVGPU_POSIX_ATOMIC_H__ - -#include - -/* - * Note: this code uses the GCC builtins to implement atomics. - */ - -#define __atomic_cmpxchg(p, v, c) __sync_val_compare_and_swap(p, v, c) -#define __atomic_and(p, v) __sync_fetch_and_and(p, v) -#define __atomic_or(p, v) __sync_fetch_and_or(p, v) - -#define cmpxchg __atomic_cmpxchg - -/* - * Place holders until real atomics can be implemented... Yay for GCC builtins! - * We can use those eventually to define all the Linux atomic ops. - * - * TODO: make these _actually_ atomic! - */ -typedef struct __nvgpu_posix_atomic { - int v; -} nvgpu_atomic_t; - -typedef struct __nvgpu_posix_atomic64 { - long v; -} nvgpu_atomic64_t; - -#define __nvgpu_atomic_init(i) { i } -#define __nvgpu_atomic64_init(i) { i } - -static inline void __nvgpu_atomic_set(nvgpu_atomic_t *v, int i) -{ - v->v = i; -} - -static inline int __nvgpu_atomic_read(nvgpu_atomic_t *v) -{ - return v->v; -} - -static inline void __nvgpu_atomic_inc(nvgpu_atomic_t *v) -{ - v->v++; -} - -static inline int __nvgpu_atomic_inc_return(nvgpu_atomic_t *v) -{ - v->v++; - return v->v; -} - -static inline void __nvgpu_atomic_dec(nvgpu_atomic_t *v) -{ - v->v--; -} - -static inline int __nvgpu_atomic_dec_return(nvgpu_atomic_t *v) -{ - v->v--; - return v->v; -} - -static inline int __nvgpu_atomic_cmpxchg(nvgpu_atomic_t *v, int old, int new) -{ - if (v->v == old) - v->v = new; - - return v->v; -} - -static inline int __nvgpu_atomic_xchg(nvgpu_atomic_t *v, int new) -{ - v->v = new; - return new; -} - -static inline bool __nvgpu_atomic_inc_and_test(nvgpu_atomic_t *v) -{ - v->v++; - return v->v ? true : false; -} - -static inline bool __nvgpu_atomic_dec_and_test(nvgpu_atomic_t *v) -{ - v->v--; - return v->v ? true : false; -} - -static inline bool __nvgpu_atomic_sub_and_test(int i, nvgpu_atomic_t *v) -{ - v->v -= i; - return v->v ? true : false; -} - -static inline int __nvgpu_atomic_add_return(int i, nvgpu_atomic_t *v) -{ - v->v += i; - return v->v; -} - -static inline int __nvgpu_atomic_add_unless(nvgpu_atomic_t *v, int a, int u) -{ - if (v->v != u) - v->v += a; - - return v->v; -} - -static inline void __nvgpu_atomic64_set(nvgpu_atomic64_t *v, long i) -{ - v->v = i; -} - -static inline long __nvgpu_atomic64_read(nvgpu_atomic64_t *v) -{ - return v->v; -} - -static inline void __nvgpu_atomic64_add(long x, nvgpu_atomic64_t *v) -{ - v->v += x; -} - -static inline void __nvgpu_atomic64_inc(nvgpu_atomic64_t *v) -{ - v->v++; -} - -static inline long __nvgpu_atomic64_inc_return(nvgpu_atomic64_t *v) -{ - v->v++; - return v->v; -} - -static inline void __nvgpu_atomic64_dec(nvgpu_atomic64_t *v) -{ - v->v--; -} - -static inline long __nvgpu_atomic64_dec_return(nvgpu_atomic64_t *v) -{ - v->v--; - return v->v; -} - -static inline long __nvgpu_atomic64_cmpxchg(nvgpu_atomic64_t *v, - long old, long new) -{ - - if (v->v == old) - v->v = new; - - return v->v; -} - -static inline void __nvgpu_atomic64_sub(long x, nvgpu_atomic64_t *v) -{ - v->v -= x; -} - -static inline long __nvgpu_atomic64_sub_return(long x, nvgpu_atomic64_t *v) -{ - v->v -= x; - return v->v; -} - -#endif diff --git a/include/nvgpu/posix/barrier.h b/include/nvgpu/posix/barrier.h deleted file mode 100644 index edc7b12..0000000 --- a/include/nvgpu/posix/barrier.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NVGPU_POSIX_BARRIER_H__ -#define __NVGPU_POSIX_BARRIER_H__ - -#define ACCESS_ONCE(x) (*(volatile __typeof__(x) *)&x) - -/* - * TODO: implement all these! - */ -#define __nvgpu_mb() -#define __nvgpu_rmb() -#define __nvgpu_wmb() - -#define __nvgpu_smp_mb() -#define __nvgpu_smp_rmb() -#define __nvgpu_smp_wmb() - -#define __nvgpu_read_barrier_depends() -#define __nvgpu_smp_read_barrier_depends() - -#define __NV_ACCESS_ONCE(x) ACCESS_ONCE(x) - -#endif diff --git a/include/nvgpu/posix/bitops.h b/include/nvgpu/posix/bitops.h deleted file mode 100644 index e8c663b..0000000 --- a/include/nvgpu/posix/bitops.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NVGPU_POSIX_BITOPS_H__ -#define __NVGPU_POSIX_BITOPS_H__ - -#include - -/* - * Assume an 8 bit byte, of course. - */ -#define BITS_PER_BYTE 8UL -#define BITS_PER_LONG (__SIZEOF_LONG__ * BITS_PER_BYTE) -#define BITS_TO_LONGS(bits) \ - (bits + (BITS_PER_LONG - 1) / BITS_PER_LONG) - -/* - * Deprecated; use the explicit BITxx() macros instead. - */ -#define BIT(i) BIT64(i) - -#define GENMASK(h, l) \ - (((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) - -#define DECLARE_BITMAP(bmap, bits) \ - unsigned long bmap[BITS_TO_LONGS(bits)] - -#define for_each_set_bit(bit, addr, size) \ - for ((bit) = find_first_bit((addr), (size)); \ - (bit) < (size); \ - (bit) = find_next_bit((addr), (size), (bit) + 1)) - -#define ffs(word) __ffs(word) -#define ffz(word) __ffs(~(word)) -#define fls(word) __fls(word) - -/* - * Clashes with symbols in libc it seems. - */ -#define __ffs(word) __nvgpu_posix_ffs(word) -#define __fls(word) __nvgpu_posix_fls(word) - -unsigned long __nvgpu_posix_ffs(unsigned long word); -unsigned long __nvgpu_posix_fls(unsigned long word); - -unsigned long find_first_bit(const unsigned long *addr, unsigned long size); -unsigned long find_next_bit(const unsigned long *addr, unsigned long size, - unsigned long offset); -unsigned long find_first_zero_bit(const unsigned long *addr, - unsigned long size); - -bool test_bit(int nr, const volatile unsigned long *addr); -bool test_and_set_bit(int nr, volatile unsigned long *addr); -bool test_and_clear_bit(int nr, volatile unsigned long *addr); - -/* - * These two are atomic. - */ -void set_bit(int nr, volatile unsigned long *addr); -void clear_bit(int nr, volatile unsigned long *addr); - -void bitmap_set(unsigned long *map, unsigned int start, int len); -void bitmap_clear(unsigned long *map, unsigned int start, int len); -unsigned long bitmap_find_next_zero_area_off(unsigned long *map, - unsigned long size, - unsigned long start, - unsigned int nr, - unsigned long align_mask, - unsigned long align_offset); -unsigned long bitmap_find_next_zero_area(unsigned long *map, - unsigned long size, - unsigned long start, - unsigned int nr, - unsigned long align_mask); - -#endif diff --git a/include/nvgpu/posix/bug.h b/include/nvgpu/posix/bug.h deleted file mode 100644 index 04389a9..0000000 --- a/include/nvgpu/posix/bug.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NVGPU_POSIX_BUG_H__ -#define __NVGPU_POSIX_BUG_H__ - -#include - -/* - * TODO: make these actually useful! - */ - -#define BUG() __bug("") -#define BUG_ON(cond) \ - do { \ - if (cond) \ - BUG(); \ - } while (0) - -#define WARN(cond, msg, arg...) __warn(cond, msg, ##arg) -#define WARN_ON(cond) __warn(cond, "") - -#define WARN_ONCE(cond, msg, arg...) \ - ({static int __warned__ = 0; \ - if (!__warned__) { \ - WARN(cond, msg, ##arg); \ - __warned__ = 1; \ - } \ - cond; }) - - -void dump_stack(void); - -void __bug(const char *fmt, ...) __attribute__ ((noreturn)); -bool __warn(bool cond, const char *fmt, ...); - -#endif diff --git a/include/nvgpu/posix/circ_buf.h b/include/nvgpu/posix/circ_buf.h deleted file mode 100644 index 8d9b5ea..0000000 --- a/include/nvgpu/posix/circ_buf.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NVGPU_POSIX_CIRC_BUF_H__ -#define __NVGPU_POSIX_CIRC_BUF_H__ - -#include - -/* TODO: implement. */ - -#define CIRC_CNT(head, tail, size) \ - ({(void)head; \ - (void)tail; \ - (void)size; \ - BUG(); \ - 1; }) - -#define CIRC_SPACE(head, tail, size) \ - ({(void)head; \ - (void)tail; \ - (void)size; \ - BUG(); \ - 1; }) - -#endif diff --git a/include/nvgpu/posix/cond.h b/include/nvgpu/posix/cond.h deleted file mode 100644 index 3528388..0000000 --- a/include/nvgpu/posix/cond.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NVGPU_POSIX_COND_H__ -#define __NVGPU_POSIX_COND_H__ - -#include - -struct nvgpu_cond { - /* Place holder until this can be properly implemented. */ -}; - -/** - * NVGPU_COND_WAIT - Wait for a condition to be true - * - * @c - The condition variable to sleep on - * @condition - The condition that needs to be true - * @timeout_ms - Timeout in milliseconds, or 0 for infinite wait - * - * Wait for a condition to become true. Returns -ETIMEOUT if - * the wait timed out with condition false. - */ -#define NVGPU_COND_WAIT(c, condition, timeout_ms) \ - ({BUG(); 1; }) - -/** - * NVGPU_COND_WAIT_INTERRUPTIBLE - Wait for a condition to be true - * - * @c - The condition variable to sleep on - * @condition - The condition that needs to be true - * @timeout_ms - Timeout in milliseconds, or 0 for infinite wait - * - * Wait for a condition to become true. Returns -ETIMEOUT if - * the wait timed out with condition false or -ERESTARTSYS on - * signal. - */ -#define NVGPU_COND_WAIT_INTERRUPTIBLE(c, condition, timeout_ms) \ - ({BUG(); 1; }) - -#endif diff --git a/include/nvgpu/posix/io.h b/include/nvgpu/posix/io.h deleted file mode 100644 index 98be4d0..0000000 --- a/include/nvgpu/posix/io.h +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_POSIX_IO_H -#define NVGPU_POSIX_IO_H - -#include -#include - -struct gk20a; - -/** - * Here lies the interface for a unit test module to interact with the nvgpu IO - * accessors. This interface provides the ability for a module to react to nvgpu - * calling nvgpu IO accessors so that nvgpu can handle various HW sequences even - * when run in unit testing mode. - * - * The primary interface is simply callbacks to the unit test module which the - * module can handle how ever it wishes. - */ - -struct nvgpu_reg_access { - /* - * Address of the register write relative to the base of the register - * space. I.e you can compare this against values in the HW headers - * directly to check what register is being read/written to/from. - */ - u32 addr; - - /* - * Writes: this is the value being written. - * Reads: populate with the value to return. - */ - u32 value; -}; - -struct nvgpu_posix_io_callbacks { - void (*writel)(struct gk20a *g, struct nvgpu_reg_access *access); - void (*writel_check)(struct gk20a *g, struct nvgpu_reg_access *access); - void (*__readl)(struct gk20a *g, struct nvgpu_reg_access *access); - void (*readl)(struct gk20a *g, struct nvgpu_reg_access *access); - void (*bar1_writel)(struct gk20a *g, struct nvgpu_reg_access *access); - void (*bar1_readl)(struct gk20a *g, struct nvgpu_reg_access *access); - void (*usermode_writel)(struct gk20a *g, - struct nvgpu_reg_access *access); -}; - -struct nvgpu_posix_io_callbacks *nvgpu_posix_register_io( - struct gk20a *g, - struct nvgpu_posix_io_callbacks *io_callbacks); - -struct nvgpu_posix_io_reg_space { - u32 base; - u32 size; - u32 *data; - struct nvgpu_list_node link; -}; - -static inline struct nvgpu_posix_io_reg_space * -nvgpu_posix_io_reg_space_from_link(struct nvgpu_list_node *node) -{ - return (struct nvgpu_posix_io_reg_space *) - ((uintptr_t)node - offsetof(struct nvgpu_posix_io_reg_space, link)); -}; - -void nvgpu_posix_io_init_reg_space(struct gk20a *g); -int nvgpu_posix_io_get_error_code(struct gk20a *g); -void nvgpu_posix_io_reset_error_code(struct gk20a *g); -int nvgpu_posix_io_add_reg_space(struct gk20a *g, u32 base, u32 size); -struct nvgpu_posix_io_reg_space *nvgpu_posix_io_get_reg_space(struct gk20a *g, - u32 addr); -void nvgpu_posix_io_delete_reg_space(struct gk20a *g, u32 base); -void nvgpu_posix_io_writel_reg_space(struct gk20a *g, u32 addr, u32 data); -u32 nvgpu_posix_io_readl_reg_space(struct gk20a *g, u32 addr); - -struct nvgpu_posix_io_reg_access { - struct nvgpu_reg_access access; - struct nvgpu_list_node link; -}; - -static inline struct nvgpu_posix_io_reg_access * -nvgpu_posix_io_reg_access_from_link(struct nvgpu_list_node *node) -{ - return (struct nvgpu_posix_io_reg_access *) - ((uintptr_t)node - offsetof(struct nvgpu_posix_io_reg_access, link)); -}; - -void nvgpu_posix_io_start_recorder(struct gk20a *g); -void nvgpu_posix_io_reset_recorder(struct gk20a *g); -void nvgpu_posix_io_record_access(struct gk20a *g, - struct nvgpu_reg_access *access); -bool nvgpu_posix_io_check_sequence(struct gk20a *g, - struct nvgpu_reg_access *sequence, u32 size, bool strict); - -#endif diff --git a/include/nvgpu/posix/kmem.h b/include/nvgpu/posix/kmem.h deleted file mode 100644 index efcdd3d..0000000 --- a/include/nvgpu/posix/kmem.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NVGPU_POSIX_KMEM_H__ -#define __NVGPU_POSIX_KMEM_H__ - -#include - -void *__nvgpu_kmalloc(struct gk20a *g, size_t size, void *ip); -void *__nvgpu_kzalloc(struct gk20a *g, size_t size, void *ip); -void *__nvgpu_kcalloc(struct gk20a *g, size_t n, size_t size, void *ip); -void *__nvgpu_vmalloc(struct gk20a *g, unsigned long size, void *ip); -void *__nvgpu_vzalloc(struct gk20a *g, unsigned long size, void *ip); -void __nvgpu_kfree(struct gk20a *g, void *addr); -void __nvgpu_vfree(struct gk20a *g, void *addr); - -#endif diff --git a/include/nvgpu/posix/lock.h b/include/nvgpu/posix/lock.h deleted file mode 100644 index 82eddd0..0000000 --- a/include/nvgpu/posix/lock.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NVGPU_POSIX_LOCK_H__ -#define __NVGPU_POSIX_LOCK_H__ - -#include - -#include - -/* - * All locks for posix nvgpu are just pthread locks. There's not a lot of reason - * to have real spinlocks in userspace since we aren't using real HW or running - * perf critical code where a sleep could be devestating. - * - * This could be revisited later, though. - */ -struct __nvgpu_posix_lock { - pthread_mutex_t mutex; -}; - -static inline void __nvgpu_posix_lock_acquire(struct __nvgpu_posix_lock *lock) -{ - pthread_mutex_lock(&lock->mutex); -} - -static inline int __nvgpu_posix_lock_try_acquire( - struct __nvgpu_posix_lock *lock) -{ - return pthread_mutex_trylock(&lock->mutex); -} - -static inline void __nvgpu_posix_lock_release(struct __nvgpu_posix_lock *lock) -{ - pthread_mutex_unlock(&lock->mutex); -} - -struct nvgpu_mutex { - struct __nvgpu_posix_lock lock; -}; - -struct nvgpu_spinlock { - struct __nvgpu_posix_lock lock; -}; - -struct nvgpu_raw_spinlock { - struct __nvgpu_posix_lock lock; -}; - -#endif /* NVGPU_LOCK_LINUX_H */ diff --git a/include/nvgpu/posix/log2.h b/include/nvgpu/posix/log2.h deleted file mode 100644 index ca95c10..0000000 --- a/include/nvgpu/posix/log2.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NVGPU_POSIX_LOG2_H__ -#define __NVGPU_POSIX_LOG2_H__ - -#define ilog2(x) (fls(x) - 1) - -#define roundup_pow_of_two(x) (1UL << fls((x) - 1)) -#define rounddown_pow_of_two(x) (1UL << (fls(x) - 1)) - -#define is_power_of_2(x) \ - ({ \ - typeof(x) __x__ = (x); \ - (__x__ != 0 && ((__x__ & (__x__ - 1)) == 0)); \ - }) - -#endif diff --git a/include/nvgpu/posix/nvgpu_mem.h b/include/nvgpu/posix/nvgpu_mem.h deleted file mode 100644 index 30cdf60..0000000 --- a/include/nvgpu/posix/nvgpu_mem.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NVGPU_POSIX_NVGPU_MEM_H__ -#define __NVGPU_POSIX_NVGPU_MEM_H__ - -struct nvgpu_mem_priv { - /* - * Eventually this will require an implementation using nvmap. - */ -}; - -#endif diff --git a/include/nvgpu/posix/nvlink.h b/include/nvgpu/posix/nvlink.h deleted file mode 100644 index 99cf837..0000000 --- a/include/nvgpu/posix/nvlink.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef __NVGPU_POSIX_NVLINK_H__ -#define __NVGPU_POSIX_NVLINK_H__ - -/* - * Empty... - */ - -#endif diff --git a/include/nvgpu/posix/pci.h b/include/nvgpu/posix/pci.h deleted file mode 100644 index cd9fc14..0000000 --- a/include/nvgpu/posix/pci.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NVGPU_POSIX_PCI_H__ -#define __NVGPU_POSIX_PCI_H__ - -#define PCI_VENDOR_ID_NVIDIA 0x10de - -#endif diff --git a/include/nvgpu/posix/probe.h b/include/nvgpu/posix/probe.h deleted file mode 100644 index a9763aa..0000000 --- a/include/nvgpu/posix/probe.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NVGPU_POSIX_PROBE_H__ -#define __NVGPU_POSIX_PROBE_H__ - -struct gk20a; - -struct gk20a *nvgpu_posix_probe(void); -void nvgpu_posix_cleanup(struct gk20a *g); - -#endif diff --git a/include/nvgpu/posix/rwsem.h b/include/nvgpu/posix/rwsem.h deleted file mode 100644 index 65aa931..0000000 --- a/include/nvgpu/posix/rwsem.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NVGPU_POSIX_RWSEM_H__ -#define __NVGPU_POSIX_RWSEM_H__ - -#include - -struct nvgpu_rwsem { - struct nvgpu_spinlock lock; - - int readers; - int writers; -}; - -#endif diff --git a/include/nvgpu/posix/sizes.h b/include/nvgpu/posix/sizes.h deleted file mode 100644 index 3fda757..0000000 --- a/include/nvgpu/posix/sizes.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NVGPU_POSIX_SIZES_H__ -#define __NVGPU_POSIX_SIZES_H__ - -#define SZ_1K (1UL << 10) -#define SZ_4K (SZ_1K << 2) -#define SZ_64K (SZ_1K << 6) -#define SZ_128K (SZ_1K << 7) - -#define SZ_1M (1UL << 20) -#define SZ_16M (SZ_1M << 4) -#define SZ_256M (SZ_1M << 8) - -#define SZ_1G (1UL << 30) -#define SZ_4G (SZ_1G << 2) - -#endif diff --git a/include/nvgpu/posix/sort.h b/include/nvgpu/posix/sort.h deleted file mode 100644 index 6a6920e..0000000 --- a/include/nvgpu/posix/sort.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NVGPU_POSIX_SORT_H__ -#define __NVGPU_POSIX_SORT_H__ - -#include - -static void sort(void *base, size_t num, size_t size, - int (*cmp)(const void *, const void *), - void (*swap)(void *, void *, int)) -{ - __bug("sort() not implemented yet!"); -} - -#endif diff --git a/include/nvgpu/posix/thread.h b/include/nvgpu/posix/thread.h deleted file mode 100644 index a312cc1..0000000 --- a/include/nvgpu/posix/thread.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NVGPU_POSIX_THREAD_H__ -#define __NVGPU_POSIX_THREAD_H__ - -#include - -#include - -/* - * Handles passing an nvgpu thread function into a posix thread. - */ -struct nvgpu_posix_thread_data { - int (*fn)(void *data); - void *data; -}; - -/* - * For some reason POSIX only allows 16 bytes of name length. - */ -#define NVGPU_THREAD_POSIX_MAX_NAMELEN 16 - -struct nvgpu_thread { - bool running; - bool should_stop; - pthread_t thread; - struct nvgpu_posix_thread_data nvgpu; - char tname[16]; -}; - -#endif diff --git a/include/nvgpu/posix/types.h b/include/nvgpu/posix/types.h deleted file mode 100644 index 12078b9..0000000 --- a/include/nvgpu/posix/types.h +++ /dev/null @@ -1,221 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NVGPU_POSIX_TYPES_H__ -#define __NVGPU_POSIX_TYPES_H__ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * For endianness functions. - */ -#include - -typedef unsigned char u8; -typedef unsigned short u16; -typedef unsigned int u32; -typedef unsigned long long u64; - -typedef signed char s8; -typedef signed short s16; -typedef signed int s32; -typedef signed long long s64; - -#define min_t(type, a, b) \ - ({ \ - type __a = (a); \ - type __b = (b); \ - __a < __b ? __a : __b; \ - }) - -#if defined(min) -#undef min -#endif -#if defined(max) -#undef max -#endif - -#define min(a, b) \ - ({ \ - (a) < (b) ? a : b; \ - }) -#define max(a, b) \ - ({ \ - (a) > (b) ? a : b; \ - }) -#define min3(a, b, c) min(min(a, b), c) - -#define PAGE_SIZE 4096U - -#define ARRAY_SIZE(array) \ - (sizeof(array) / sizeof((array)[0])) - -#define MAX_SCHEDULE_TIMEOUT LONG_MAX - -#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) - -/* - * Only used in clk_gm20b.c which we will never unit test. Don't use! - */ -#define DIV_ROUND_CLOSEST(x, divisor) ({BUG(); 0; }) - -/* - * Joys of userspace: usually division just works since the compiler can link - * against external division functions implicitly. - */ -#define do_div(a, b) ((a) /= (b)) -#define div64_u64(a, b) ((a) / (b)) - -#define __round_mask(x, y) ((__typeof__(x))((y) - 1)) -#define round_up(x, y) ((((x) - 1) | __round_mask(x, y)) + 1) -#define roundup(x, y) round_up(x, y) -#define round_down(x, y) ((x) & ~__round_mask(x, y)) - -#define ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask)) -#define ALIGN(x, a) ALIGN_MASK(x, (typeof(x))(a) - 1) -#define PAGE_ALIGN(x) ALIGN(x, PAGE_SIZE) - -/* - * Caps return at the size of the buffer not what would have been written if buf - * were arbitrarily sized. - */ -static inline int scnprintf(char *buf, size_t size, const char *format, ...) -{ - size_t ret; - va_list args; - - va_start(args, format); - ret = vsnprintf(buf, size, format, args); - va_end(args); - - return ret <= size ? ret : size; -} - -static inline u32 be32_to_cpu(u32 x) -{ - /* - * Conveniently big-endian happens to be network byte order as well so - * we can use ntohl() for this. - */ - return ntohl(x); -} - -/* - * Hamming weights. - */ -static inline unsigned long __hweight8(uint8_t x) -{ - return (unsigned long)(!!(x & (1 << 0)) + - !!(x & (1 << 1)) + - !!(x & (1 << 2)) + - !!(x & (1 << 3)) + - !!(x & (1 << 4)) + - !!(x & (1 << 5)) + - !!(x & (1 << 6)) + - !!(x & (1 << 7))); -} - -static inline unsigned long __hweight16(uint16_t x) -{ - return __hweight8((uint8_t)x) + - __hweight8((uint8_t)((x & 0xff00) >> 8)); -} - -static inline unsigned long __hweight32(uint32_t x) -{ - return __hweight16((uint16_t)x) + - __hweight16((uint16_t)((x & 0xffff0000) >> 16)); -} - -static inline unsigned long __hweight64(uint64_t x) -{ - return __hweight32((uint32_t)x) + - __hweight32((uint32_t)((x & 0xffffffff00000000) >> 32)); -} - -#define hweight32 __hweight32 -#define hweight_long __hweight64 - -/* - * Better suited under a compiler.h type header file, but for now these can live - * here. - */ -#define __must_check -#define __maybe_unused __attribute__((unused)) -#define __iomem -#define __user -#define unlikely -#define likely - -#define __stringify(x) #x - -/* - * Prevent compiler optimizations from mangling writes. But likely most uses of - * this in nvgpu are incorrect (i.e unnecessary). - */ -#define WRITE_ONCE(p, v) \ - ({ \ - volatile typeof(p) *__p__ = &(p); \ - *__p__ = v; \ - }) - -#define container_of(ptr, type, member) ({ \ - const typeof( ((type *)0)->member ) *__mptr = (ptr); \ - (type *)( (char *)__mptr - offsetof(type,member) );}) - -#define __packed __attribute__((packed)) - -#define IS_ENABLED(config) 0 - -#define MAX_ERRNO 4095 - -#define IS_ERR_VALUE(x) ((x) >= (unsigned long)-MAX_ERRNO) - -static inline void *ERR_PTR(long error) -{ - return (void *) error; -} - -static inline long PTR_ERR(void *error) -{ - return (long)(uintptr_t)error; -} - -static inline bool IS_ERR(const void *ptr) -{ - return IS_ERR_VALUE((unsigned long)ptr); -} - -static inline bool IS_ERR_OR_NULL(const void *ptr) -{ - return (ptr == NULL) || IS_ERR_VALUE((unsigned long)ptr); -} - -#endif diff --git a/include/nvgpu/posix/vm.h b/include/nvgpu/posix/vm.h deleted file mode 100644 index ae997d3..0000000 --- a/include/nvgpu/posix/vm.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NVGPU_POSIX_VM_H__ -#define __NVGPU_POSIX_VM_H__ - -#include - -struct nvgpu_os_buffer { - /* - * We just use malloc() buffers in userspace. - */ - void *buf; - size_t size; -}; - -struct nvgpu_mapped_buf_priv { - void *buf; - size_t size; -}; - -#endif diff --git a/include/nvgpu/power_features/cg.h b/include/nvgpu/power_features/cg.h deleted file mode 100644 index d447d9b..0000000 --- a/include/nvgpu/power_features/cg.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - - -#ifndef NVGPU_POWER_FEATURES_CG_H -#define NVGPU_POWER_FEATURES_CG_H - -#include - -struct gk20a; -struct fifo_gk20a; - -void nvgpu_cg_init_gr_load_gating_prod(struct gk20a *g); -void nvgpu_cg_elcg_enable(struct gk20a *g); -void nvgpu_cg_elcg_disable(struct gk20a *g); -void nvgpu_cg_elcg_enable_no_wait(struct gk20a *g); -void nvgpu_cg_elcg_disable_no_wait(struct gk20a *g); -void nvgpu_cg_elcg_set_elcg_enabled(struct gk20a *g, bool enable); - -void nvgpu_cg_blcg_mode_enable(struct gk20a *g); -void nvgpu_cg_blcg_mode_disable(struct gk20a *g); -void nvgpu_cg_blcg_fb_ltc_load_enable(struct gk20a *g); -void nvgpu_cg_blcg_fifo_load_enable(struct gk20a *g); -void nvgpu_cg_blcg_pmu_load_enable(struct gk20a *g); -void nvgpu_cg_blcg_ce_load_enable(struct gk20a *g); -void nvgpu_cg_blcg_gr_load_enable(struct gk20a *g); -void nvgpu_cg_blcg_set_blcg_enabled(struct gk20a *g, bool enable); - -void nvgpu_cg_slcg_gr_perf_ltc_load_enable(struct gk20a *g); -void nvgpu_cg_slcg_gr_perf_ltc_load_disable(struct gk20a *g); -void nvgpu_cg_slcg_fb_ltc_load_enable(struct gk20a *g); -void nvgpu_cg_slcg_priring_load_enable(struct gk20a *g); -void nvgpu_cg_slcg_fifo_load_enable(struct gk20a *g); -void nvgpu_cg_slcg_pmu_load_enable(struct gk20a *g); -void nvgpu_cg_slcg_ce2_load_enable(struct gk20a *g); -void nvgpu_cg_slcg_set_slcg_enabled(struct gk20a *g, bool enable); - -#endif /*NVGPU_POWER_FEATURES_CG_H*/ diff --git a/include/nvgpu/power_features/pg.h b/include/nvgpu/power_features/pg.h deleted file mode 100644 index d735780..0000000 --- a/include/nvgpu/power_features/pg.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - - -#ifndef NVGPU_POWER_FEATURES_PG_H -#define NVGPU_POWER_FEATURES_PG_H - -#include - -struct gk20a; - -int nvgpu_pg_elpg_disable(struct gk20a *g); -int nvgpu_pg_elpg_enable(struct gk20a *g); -bool nvgpu_pg_elpg_is_enabled(struct gk20a *g); -int nvgpu_pg_elpg_set_elpg_enabled(struct gk20a *g, bool enable); - -#endif /*NVGPU_POWER_FEATURES_PG_H*/ diff --git a/include/nvgpu/power_features/power_features.h b/include/nvgpu/power_features/power_features.h deleted file mode 100644 index f6ffccf..0000000 --- a/include/nvgpu/power_features/power_features.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - - -#ifndef NVGPU_POWER_FEATURES_H -#define NVGPU_POWER_FEATURES_H - -#include - -struct gk20a; - -int nvgpu_cg_pg_disable(struct gk20a *g); -int nvgpu_cg_pg_enable(struct gk20a *g); - -#endif /*NVGPU_POWER_FEATURES_H*/ diff --git a/include/nvgpu/pramin.h b/include/nvgpu/pramin.h deleted file mode 100644 index b0914bc..0000000 --- a/include/nvgpu/pramin.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_PRAMIN_H -#define NVGPU_PRAMIN_H - -#include - -struct gk20a; -struct mm_gk20a; -struct nvgpu_mem; - - -void nvgpu_pramin_rd_n(struct gk20a *g, struct nvgpu_mem *mem, u32 start, u32 words, void *dest); -void nvgpu_pramin_wr_n(struct gk20a *g, struct nvgpu_mem *mem, u32 start, u32 words, void *src); -void nvgpu_pramin_memset(struct gk20a *g, struct nvgpu_mem *mem, u32 start, u32 words, u32 w); - -void nvgpu_init_pramin(struct mm_gk20a *mm); - -#endif /* NVGPU_PRAMIN_H */ diff --git a/include/nvgpu/ptimer.h b/include/nvgpu/ptimer.h deleted file mode 100644 index 3369eb2..0000000 --- a/include/nvgpu/ptimer.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_PTIMER_H -#define NVGPU_PTIMER_H - -#include - -struct gk20a; - -struct nvgpu_cpu_time_correlation_sample { - u64 cpu_timestamp; - u64 gpu_timestamp; -}; - -/* PTIMER_REF_FREQ_HZ corresponds to a period of 32 nanoseconds. - 32 ns is the resolution of ptimer. */ -#define PTIMER_REF_FREQ_HZ 31250000 - -static inline u32 ptimer_scalingfactor10x(u32 ptimer_src_freq) -{ - return (u32)(((u64)(PTIMER_REF_FREQ_HZ * 10)) / ptimer_src_freq); -} - -static inline u32 scale_ptimer(u32 timeout , u32 scale10x) -{ - if (((timeout*10) % scale10x) >= (scale10x/2)) { - return ((timeout * 10) / scale10x) + 1; - } else { - return (timeout * 10) / scale10x; - } -} - -int nvgpu_get_timestamps_zipper(struct gk20a *g, - u32 source_id, u32 count, - struct nvgpu_cpu_time_correlation_sample *samples); -#endif diff --git a/include/nvgpu/rbtree.h b/include/nvgpu/rbtree.h deleted file mode 100644 index bcbbabb..0000000 --- a/include/nvgpu/rbtree.h +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_RBTREE_H -#define NVGPU_RBTREE_H - -#include - -struct nvgpu_rbtree_node { - u64 key_start; - u64 key_end; - - bool is_red; /* !IsRed == IsBlack */ - - struct nvgpu_rbtree_node *parent; - struct nvgpu_rbtree_node *left; - struct nvgpu_rbtree_node *right; -}; - -/** - * nvgpu_rbtree_insert - insert a new node into rbtree - * - * @new_node Pointer to new node. - * @root Pointer to root of tree - * - * Nodes with duplicate key_start and overlapping ranges - * are not allowed - */ -void nvgpu_rbtree_insert(struct nvgpu_rbtree_node *new_node, - struct nvgpu_rbtree_node **root); - -/** - * nvgpu_rbtree_unlink - delete a node from rbtree - * - * @node Pointer to node to be deleted - * @root Pointer to root of tree - */ -void nvgpu_rbtree_unlink(struct nvgpu_rbtree_node *node, - struct nvgpu_rbtree_node **root); - -/** - * nvgpu_rbtree_search - search a given key in rbtree - * - * @key_start Key to be searched in rbtree - * @node Node pointer to be returned - * @root Pointer to root of tree - * - * This API will match given key against key_start of each node - * In case of a hit, node points to a node with given key - * In case of a miss, node is NULL - */ -void nvgpu_rbtree_search(u64 key_start, struct nvgpu_rbtree_node **node, - struct nvgpu_rbtree_node *root); - -/** - * nvgpu_rbtree_range_search - search a node with key falling in range - * - * @key Key to be searched in rbtree - * @node Node pointer to be returned - * @root Pointer to root of tree - * - * This API will match given key and find a node where key value - * falls within range of {start, end} keys - * In case of a hit, node points to a node with given key - * In case of a miss, node is NULL - */ -void nvgpu_rbtree_range_search(u64 key, - struct nvgpu_rbtree_node **node, - struct nvgpu_rbtree_node *root); - -/** - * nvgpu_rbtree_less_than_search - search a node with key lesser than given key - * - * @key_start Key to be searched in rbtree - * @node Node pointer to be returned - * @root Pointer to root of tree - * - * This API will match given key and find a node with highest - * key value lesser than given key - * In case of a hit, node points to a node with given key - * In case of a miss, node is NULL - */ -void nvgpu_rbtree_less_than_search(u64 key_start, - struct nvgpu_rbtree_node **node, - struct nvgpu_rbtree_node *root); - -/** - * nvgpu_rbtree_enum_start - enumerate tree starting at the node with specified value - * - * @key_start Key value to begin enumeration from - * @node Pointer to first node in the tree - * @root Pointer to root of tree - * - * This API returns node pointer pointing to first node in the rbtree - */ -void nvgpu_rbtree_enum_start(u64 key_start, - struct nvgpu_rbtree_node **node, - struct nvgpu_rbtree_node *root); - -/** - * nvgpu_rbtree_enum_next - find next node in enumeration - * - * @node Pointer to next node in the tree - * @root Pointer to root of tree - * - * This API returns node pointer pointing to next node in the rbtree - */ -void nvgpu_rbtree_enum_next(struct nvgpu_rbtree_node **node, - struct nvgpu_rbtree_node *root); - -#endif /* NVGPU_RBTREE_H */ diff --git a/include/nvgpu/rwsem.h b/include/nvgpu/rwsem.h deleted file mode 100644 index 3cca9c5..0000000 --- a/include/nvgpu/rwsem.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_RWSEM_H -#define NVGPU_RWSEM_H - -#ifdef __KERNEL__ -#include -#elif defined(__NVGPU_POSIX__) -#include -#else -#include -#endif - -/* - * struct nvgpu_rwsem - * - * Should be implemented per-OS in a separate library - * But implementation should adhere to rw_semaphore implementation - * as specified in Linux Documentation - */ -struct nvgpu_rwsem; - -void nvgpu_rwsem_init(struct nvgpu_rwsem *rwsem); -void nvgpu_rwsem_up_read(struct nvgpu_rwsem *rwsem); -void nvgpu_rwsem_down_read(struct nvgpu_rwsem *rwsem); -void nvgpu_rwsem_up_write(struct nvgpu_rwsem *rwsem); -void nvgpu_rwsem_down_write(struct nvgpu_rwsem *rwsem); - -#endif /* NVGPU_RWSEM_H */ diff --git a/include/nvgpu/sched.h b/include/nvgpu/sched.h deleted file mode 100644 index c49b7d1..0000000 --- a/include/nvgpu/sched.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef __NVGPU_SCHED_COMMON_H -#define __NVGPU_SCHED_COMMON_H - -struct nvgpu_sched_ctrl { - struct nvgpu_mutex control_lock; - bool control_locked; - bool sw_ready; - struct nvgpu_mutex status_lock; - struct nvgpu_mutex busy_lock; - - u64 status; - - size_t bitmap_size; - u64 *active_tsg_bitmap; - u64 *recent_tsg_bitmap; - u64 *ref_tsg_bitmap; - - struct nvgpu_cond readout_wq; -}; - -#endif /* __NVGPU_SCHED_COMMON_H */ diff --git a/include/nvgpu/sec2.h b/include/nvgpu/sec2.h deleted file mode 100644 index 7c75584..0000000 --- a/include/nvgpu/sec2.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_SEC2_H -#define NVGPU_SEC2_H - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#define NVGPU_SEC2_TRACE_BUFSIZE (32U*1024U) - -#define SEC2_MAX_NUM_SEQUENCES (256U) -#define SEC2_SEQ_BIT_SHIFT (5U) -#define SEC2_SEQ_TBL_SIZE \ - (SEC2_MAX_NUM_SEQUENCES >> SEC2_SEQ_BIT_SHIFT) - -#define SEC2_INVALID_SEQ_DESC (~0U) - -enum { - SEC2_SEQ_STATE_FREE = 0U, - SEC2_SEQ_STATE_PENDING, - SEC2_SEQ_STATE_USED, - SEC2_SEQ_STATE_CANCELLED -}; - -typedef void (*sec2_callback)(struct gk20a *, struct nv_flcn_msg_sec2 *, - void *, u32, u32); - -struct sec2_sequence { - u8 id; - u32 state; - u32 desc; - struct nv_flcn_msg_sec2 *msg; - u8 *out_payload; - sec2_callback callback; - void *cb_params; -}; - -struct nvgpu_sec2 { - struct gk20a *g; - struct nvgpu_falcon *flcn; - u32 falcon_id; - - struct nvgpu_falcon_queue queue[SEC2_QUEUE_NUM]; - - struct sec2_sequence *seq; - unsigned long sec2_seq_tbl[SEC2_SEQ_TBL_SIZE]; - u32 next_seq_desc; - struct nvgpu_mutex sec2_seq_lock; - - bool isr_enabled; - struct nvgpu_mutex isr_mutex; - - struct nvgpu_allocator dmem; - - /* set to true once init received */ - bool sec2_ready; - - struct nvgpu_mem trace_buf; - - void (*remove_support)(struct nvgpu_sec2 *sec2); - - u32 command_ack; -}; - -/* sec2 init */ -int nvgpu_init_sec2_support(struct gk20a *g); -int nvgpu_sec2_destroy(struct gk20a *g); - -#endif /* NVGPU_SEC2_H */ diff --git a/include/nvgpu/sec2if/sec2_cmd_if.h b/include/nvgpu/sec2if/sec2_cmd_if.h deleted file mode 100644 index 839743f..0000000 --- a/include/nvgpu/sec2if/sec2_cmd_if.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_SEC2_CMD_IF_H -#define NVGPU_SEC2_CMD_IF_H - -#include -#include - -struct nv_flcn_cmd_sec2 { - struct pmu_hdr hdr; - union { - union nv_sec2_acr_cmd acr; - } cmd; -}; - -struct nv_flcn_msg_sec2 { - struct pmu_hdr hdr; - - union { - union nv_flcn_msg_sec2_init init; - union nv_sec2_acr_msg acr; - } msg; -}; - -#define NV_SEC2_UNIT_REWIND NV_FLCN_UNIT_ID_REWIND -#define NV_SEC2_UNIT_INIT (0x01U) -#define NV_SEC2_UNIT_ACR (0x07U) -#define NV_SEC2_UNIT_END (0x0AU) - -#endif /* NVGPU_SEC2_CMD_IF_H */ diff --git a/include/nvgpu/sec2if/sec2_if_acr.h b/include/nvgpu/sec2if/sec2_if_acr.h deleted file mode 100644 index 5b41958..0000000 --- a/include/nvgpu/sec2if/sec2_if_acr.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_SEC2_IF_ACR_H -#define NVGPU_SEC2_IF_ACR_H - -#include - -/* - * ACR Command Types - * _BOOT_FALCON - * NVGPU sends a Falcon ID and LSB offset to SEC2 to boot - * the falcon in LS mode. - * SEC2 needs to hanlde the case since UCODE of falcons are - * stored in secured location on FB. - */ -#define NV_SEC2_ACR_CMD_ID_BOOTSTRAP_FALCON 0U - -/* nvgpu provides the Falcon ID to bootstrap */ -struct nv_sec2_acr_cmd_bootstrap_falcon { - /* Command must be first as this struct is the part of union */ - u8 cmd_type; - - /* Additional bootstrapping flags */ - u32 flags; - - /* ID to identify Falcon, ref LSF_FALCON_ID_ */ - u32 falcon_id; -}; - -#define NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET 0U -#define NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_NO 1U -#define NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0U - -/* A union of all ACR Commands */ -union nv_sec2_acr_cmd { - /* Command type */ - u8 cmd_type; - - /* Bootstrap Falcon */ - struct nv_sec2_acr_cmd_bootstrap_falcon bootstrap_falcon; -}; - -/* ACR Message Status */ - -/* Returns the Bootstrapped falcon ID to RM */ -#define NV_SEC2_ACR_MSG_ID_BOOTSTRAP_FALCON 0U - -/* Returns the Error Status for Invalid Command */ -#define NV_SEC2_ACR_MSG_ID_INVALID_COMMAND 2U - -/* - * SEC2 notifies nvgpu about bootstrap status of falcon - */ -struct nv_sec2_acr_msg_bootstrap_falcon { - /* Message must be at start */ - u8 msg_type; - - /* Falcon Error Code returned by message */ - u32 error_code; - - /* Bootstrapped falcon ID by ACR */ - u32 falcon_id; -} ; - -/* - * A union of all ACR Messages. - */ -union nv_sec2_acr_msg { - /* Message type */ - u8 msg_type; - - /* Bootstrap details of falcon and status code */ - struct nv_sec2_acr_msg_bootstrap_falcon msg_flcn; -}; - -#endif /* NVGPU_SEC2_IF_ACR_H */ diff --git a/include/nvgpu/sec2if/sec2_if_cmn.h b/include/nvgpu/sec2if/sec2_if_cmn.h deleted file mode 100644 index a40f8f9..0000000 --- a/include/nvgpu/sec2if/sec2_if_cmn.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_SEC2_IF_CMN_H -#define NVGPU_SEC2_IF_CMN_H - -/* - * Define the maximum number of command sequences that can be in flight at - * any given time. This is dictated by the width of the sequence number - * id ('seqNumId') stored in each sequence packet (currently 8-bits). - */ -#define NV_SEC2_MAX_NUM_SEQUENCES 256U - -/* - * Compares an unit id against the values in the unit_id enumeration and - * verifies that the id is valid. It is expected that the id is specified - * as an unsigned integer. - */ -#define NV_SEC2_UNITID_IS_VALID(id) (((id) < NV_SEC2_UNIT_END)) - -/* - * Defines the size of the surface/buffer that will be allocated to store - * debug spew from the SEC2 ucode application when falcon-trace is enabled. - */ -#define NV_SEC2_DEBUG_SURFACE_SIZE (32U*1024U) - -/* - * SEC2's frame-buffer interface block has several slots/indices which can - * be bound to support DMA to various surfaces in memory. This is an - * enumeration that gives name to each index based on type of memory-aperture - * the index is used to access. - * - * Pre-Turing, NV_SEC2_DMAIDX_PHYS_VID_FN0 == NV_SEC2_DMAIDX_GUEST_PHYS_VID_BOUND. - * From Turing, engine context is stored in GPA, requiring a separate aperture. - * - * Traditionally, video falcons have used the 6th index for ucode, and we will - * continue to use that to allow legacy ucode to work seamlessly. - * - * Note: DO NOT CHANGE THE VALUE OF NV_SEC2_DMAIDX_UCODE. That value is used by - * both the legacy SEC2 ucode, which assumes that it will use index 6, and by - * SEC2 RTOS. Changing it will break legacy SEC2 ucode, unless it is updated to - * reflect the new value. - */ - -#define NV_SEC2_DMAIDX_GUEST_PHYS_VID_BOUND 0U -#define NV_SEC2_DMAIDX_VIRT 1U -#define NV_SEC2_DMAIDX_PHYS_VID_FN0 2U -#define NV_SEC2_DMAIDX_PHYS_SYS_COH_FN0 3U -#define NV_SEC2_DMAIDX_PHYS_SYS_NCOH_FN0 4U -#define NV_SEC2_DMAIDX_GUEST_PHYS_SYS_COH_BOUND 5U -#define NV_SEC2_DMAIDX_UCODE 6U -#define NV_SEC2_DMAIDX_GUEST_PHYS_SYS_NCOH_BOUND 7U - -#endif /* NVGPU_SEC2_IF_CMN_H */ diff --git a/include/nvgpu/sec2if/sec2_if_sec2.h b/include/nvgpu/sec2if/sec2_if_sec2.h deleted file mode 100644 index c895c41..0000000 --- a/include/nvgpu/sec2if/sec2_if_sec2.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_SEC2_IF_SEC2_H -#define NVGPU_SEC2_IF_SEC2_H - -/* - * SEC2 Command/Message Interfaces - SEC2 Management - */ - -/* - * Defines the identifiers various high-level types of sequencer commands and - * messages. - * _SEC2_INIT - sec2_init_msg_sec2_init - */ -enum -{ - NV_SEC2_INIT_MSG_ID_SEC2_INIT = 0U, -}; - -/* - * Defines the logical queue IDs that must be used when submitting commands - * to or reading messages from SEC2. The identifiers must begin with zero and - * should increment sequentially. _CMDQ_LOG_ID__LAST must always be set to the - * last command queue identifier. _NUM must always be set to the last - * identifier plus one. - */ -#define SEC2_NV_CMDQ_LOG_ID 0U -#define SEC2_NV_CMDQ_LOG_ID__LAST 0U -#define SEC2_NV_MSGQ_LOG_ID 1U -#define SEC2_QUEUE_NUM 2U - -struct sec2_init_msg_sec2_init { - u8 msg_type; - u8 num_queues; - - u16 os_debug_entry_point; - - struct - { - u32 queue_offset; - u16 queue_size; - u8 queue_phy_id; - u8 queue_log_id; - } q_info[SEC2_QUEUE_NUM]; - - u32 nv_managed_area_offset; - u16 nv_managed_area_size; -}; - -union nv_flcn_msg_sec2_init { - u8 msg_type; - struct sec2_init_msg_sec2_init sec2_init; -}; - -#endif /* NVGPU_SEC2_IF_SEC2_H */ diff --git a/include/nvgpu/semaphore.h b/include/nvgpu/semaphore.h deleted file mode 100644 index 94e3be0..0000000 --- a/include/nvgpu/semaphore.h +++ /dev/null @@ -1,206 +0,0 @@ -/* - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef SEMAPHORE_GK20A_H -#define SEMAPHORE_GK20A_H - -#include -#include -#include -#include -#include - -#include "gk20a/mm_gk20a.h" - -struct gk20a; - -#define gpu_sema_dbg(g, fmt, args...) \ - nvgpu_log(g, gpu_dbg_sema, fmt, ##args) -#define gpu_sema_verbose_dbg(g, fmt, args...) \ - nvgpu_log(g, gpu_dbg_sema_v, fmt, ##args) - -/* - * Max number of channels that can be used is 512. This of course needs to be - * fixed to be dynamic but still fast. - */ -#define SEMAPHORE_POOL_COUNT 512U -#define SEMAPHORE_SIZE 16U -#define SEMAPHORE_SEA_GROWTH_RATE 32U - -struct nvgpu_semaphore_sea; - -struct nvgpu_semaphore_loc { - struct nvgpu_semaphore_pool *pool; /* Pool that owns this sema. */ - u32 offset; /* Byte offset into the pool. */ -}; - -/* - * Underlying semaphore data structure. This semaphore can be shared amongst - * other semaphore instances. - */ -struct nvgpu_semaphore_int { - struct nvgpu_semaphore_loc location; - nvgpu_atomic_t next_value; /* Next available value. */ - struct channel_gk20a *ch; /* Channel that owns this sema. */ -}; - -/* - * A semaphore which the rest of the driver actually uses. This consists of a - * pointer to a real semaphore and a value to wait for. This allows one physical - * semaphore to be shared among an essentially infinite number of submits. - */ -struct nvgpu_semaphore { - struct gk20a *g; - struct nvgpu_semaphore_loc location; - - nvgpu_atomic_t value; - bool incremented; - - struct nvgpu_ref ref; -}; - -/* - * A semaphore pool. Each address space will own exactly one of these. - */ -struct nvgpu_semaphore_pool { - struct nvgpu_list_node pool_list_entry; /* Node for list of pools. */ - u64 gpu_va; /* GPU access to the pool. */ - u64 gpu_va_ro; /* GPU access to the pool. */ - u64 page_idx; /* Index into sea bitmap. */ - - DECLARE_BITMAP(semas_alloced, PAGE_SIZE / SEMAPHORE_SIZE); - - struct nvgpu_semaphore_sea *sema_sea; /* Sea that owns this pool. */ - - struct nvgpu_mutex pool_lock; - - /* - * This is the address spaces's personal RW table. Other channels will - * ultimately map this page as RO. This is a sub-nvgpu_mem from the - * sea's mem. - */ - struct nvgpu_mem rw_mem; - - bool mapped; - - /* - * Sometimes a channel can be released before other channels are - * done waiting on it. This ref count ensures that the pool doesn't - * go away until all semaphores using this pool are cleaned up first. - */ - struct nvgpu_ref ref; -}; - -static inline struct nvgpu_semaphore_pool * -nvgpu_semaphore_pool_from_pool_list_entry(struct nvgpu_list_node *node) -{ - return (struct nvgpu_semaphore_pool *) - ((uintptr_t)node - - offsetof(struct nvgpu_semaphore_pool, pool_list_entry)); -}; - -/* - * A sea of semaphores pools. Each pool is owned by a single VM. Since multiple - * channels can share a VM each channel gets it's own HW semaphore from the - * pool. Channels then allocate regular semaphores - basically just a value that - * signifies when a particular job is done. - */ -struct nvgpu_semaphore_sea { - struct nvgpu_list_node pool_list; /* List of pools in this sea. */ - struct gk20a *gk20a; - - size_t size; /* Number of pages available. */ - u64 gpu_va; /* GPU virtual address of sema sea. */ - u64 map_size; /* Size of the mapping. */ - - /* - * TODO: - * List of pages that we use to back the pools. The number of pages - * can grow dynamically since allocating 512 pages for all channels at - * once would be a tremendous waste. - */ - int page_count; /* Pages allocated to pools. */ - - /* - * The read-only memory for the entire semaphore sea. Each semaphore - * pool needs a sub-nvgpu_mem that will be mapped as RW in its address - * space. This sea_mem cannot be freed until all semaphore_pools have - * been freed. - */ - struct nvgpu_mem sea_mem; - - /* - * Can't use a regular allocator here since the full range of pools are - * not always allocated. Instead just use a bitmap. - */ - DECLARE_BITMAP(pools_alloced, SEMAPHORE_POOL_COUNT); - - struct nvgpu_mutex sea_lock; /* Lock alloc/free calls. */ -}; - -/* - * Semaphore sea functions. - */ -struct nvgpu_semaphore_sea *nvgpu_semaphore_sea_create(struct gk20a *gk20a); -void nvgpu_semaphore_sea_destroy(struct gk20a *g); -int nvgpu_semaphore_sea_map(struct nvgpu_semaphore_pool *sea, - struct vm_gk20a *vm); -void nvgpu_semaphore_sea_unmap(struct nvgpu_semaphore_pool *sea, - struct vm_gk20a *vm); -struct nvgpu_semaphore_sea *nvgpu_semaphore_get_sea(struct gk20a *g); - -/* - * Semaphore pool functions. - */ -int nvgpu_semaphore_pool_alloc(struct nvgpu_semaphore_sea *sea, - struct nvgpu_semaphore_pool **pool); -int nvgpu_semaphore_pool_map(struct nvgpu_semaphore_pool *pool, - struct vm_gk20a *vm); -void nvgpu_semaphore_pool_unmap(struct nvgpu_semaphore_pool *pool, - struct vm_gk20a *vm); -u64 __nvgpu_semaphore_pool_gpu_va(struct nvgpu_semaphore_pool *p, bool global); -void nvgpu_semaphore_pool_get(struct nvgpu_semaphore_pool *p); -void nvgpu_semaphore_pool_put(struct nvgpu_semaphore_pool *p); - -/* - * Semaphore functions. - */ -struct nvgpu_semaphore *nvgpu_semaphore_alloc(struct channel_gk20a *ch); -void nvgpu_semaphore_put(struct nvgpu_semaphore *s); -void nvgpu_semaphore_get(struct nvgpu_semaphore *s); -void nvgpu_semaphore_free_hw_sema(struct channel_gk20a *ch); - -u64 nvgpu_semaphore_gpu_rw_va(struct nvgpu_semaphore *s); -u64 nvgpu_semaphore_gpu_ro_va(struct nvgpu_semaphore *s); -u64 nvgpu_hw_sema_addr(struct nvgpu_semaphore_int *hw_sema); - -u32 __nvgpu_semaphore_read(struct nvgpu_semaphore_int *hw_sema); -u32 nvgpu_semaphore_read(struct nvgpu_semaphore *s); -u32 nvgpu_semaphore_get_value(struct nvgpu_semaphore *s); -bool nvgpu_semaphore_is_released(struct nvgpu_semaphore *s); -bool nvgpu_semaphore_is_acquired(struct nvgpu_semaphore *s); - -bool nvgpu_semaphore_reset(struct nvgpu_semaphore_int *hw_sema); -void nvgpu_semaphore_prepare(struct nvgpu_semaphore *s, - struct nvgpu_semaphore_int *hw_sema); - -#endif diff --git a/include/nvgpu/sim.h b/include/nvgpu/sim.h deleted file mode 100644 index 1d6b15d..0000000 --- a/include/nvgpu/sim.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_SIM_H -#define NVGPU_SIM_H - -#include - -struct gk20a; -struct sim_nvgpu { - struct gk20a *g; - u32 send_ring_put; - u32 recv_ring_get; - u32 recv_ring_put; - u32 sequence_base; - struct nvgpu_mem send_bfr; - struct nvgpu_mem recv_bfr; - struct nvgpu_mem msg_bfr; - void (*sim_init_late)(struct gk20a *); - void (*remove_support)(struct gk20a *); - void (*esc_readl)( - struct gk20a *g, char *path, u32 index, u32 *data); -}; -#ifdef __KERNEL__ -#include "linux/sim.h" -#include "linux/sim_pci.h" -#elif defined(__NVGPU_POSIX__) -/* Nothing for POSIX-nvgpu. */ -#else -#include -#include -#endif -int nvgpu_init_sim_support(struct gk20a *g); -int nvgpu_init_sim_support_pci(struct gk20a *g); -int nvgpu_alloc_sim_buffer(struct gk20a *g, struct nvgpu_mem *mem); -void nvgpu_free_sim_buffer(struct gk20a *g, struct nvgpu_mem *mem); -void nvgpu_free_sim_support(struct gk20a *g); -void nvgpu_remove_sim_support(struct gk20a *g); - -#endif /* NVGPU_SIM_H */ diff --git a/include/nvgpu/sizes.h b/include/nvgpu/sizes.h deleted file mode 100644 index af5e4b2..0000000 --- a/include/nvgpu/sizes.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_SIZES_H -#define NVGPU_SIZES_H - -#ifdef __KERNEL__ -#include -#elif defined(__NVGPU_POSIX__) -#include -#else -#include -#endif - -#endif /* NVGPU_SIZES_H */ diff --git a/include/nvgpu/soc.h b/include/nvgpu/soc.h deleted file mode 100644 index 729d8af..0000000 --- a/include/nvgpu/soc.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_SOC_H -#define NVGPU_SOC_H - -#include - -struct gk20a; - -bool nvgpu_platform_is_silicon(struct gk20a *g); -bool nvgpu_platform_is_simulation(struct gk20a *g); -bool nvgpu_platform_is_fpga(struct gk20a *g); -bool nvgpu_is_hypervisor_mode(struct gk20a *g); -bool nvgpu_is_bpmp_running(struct gk20a *g); -bool nvgpu_is_soc_t194_a01(struct gk20a *g); -int nvgpu_init_soc_vars(struct gk20a *g); - -#endif /* NVGPU_SOC_H */ diff --git a/include/nvgpu/sort.h b/include/nvgpu/sort.h deleted file mode 100644 index 80bae4b..0000000 --- a/include/nvgpu/sort.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_SORT_H -#define NVGPU_SORT_H - -#ifdef __KERNEL__ -#include -#elif defined(__NVGPU_POSIX__) -#include -#else -#include -#endif - -#endif /* NVGPU_SORT_H */ diff --git a/include/nvgpu/therm.h b/include/nvgpu/therm.h deleted file mode 100644 index 41808de..0000000 --- a/include/nvgpu/therm.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_THERM_H -#define NVGPU_THERM_H - -struct gk20a; - -int nvgpu_init_therm_support(struct gk20a *g); - -#endif diff --git a/include/nvgpu/thread.h b/include/nvgpu/thread.h deleted file mode 100644 index eac06ef..0000000 --- a/include/nvgpu/thread.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_THREAD_H -#define NVGPU_THREAD_H - -#ifdef __KERNEL__ -#include -#elif defined(__NVGPU_POSIX__) -#include -#else -#include -#endif - -#include - -/** - * nvgpu_thread_create - Create and run a new thread. - * - * @thread - thread structure to use - * @data - data to pass to threadfn - * @threadfn - Thread function - * @name - name of the thread - * - * Create a thread and run threadfn in it. The thread stays alive as long as - * threadfn is running. As soon as threadfn returns the thread is destroyed. - * - * threadfn needs to continuously poll nvgpu_thread_should_stop() to determine - * if it should exit. - */ -int nvgpu_thread_create(struct nvgpu_thread *thread, - void *data, - int (*threadfn)(void *data), const char *name); - -/** - * nvgpu_thread_stop - Destroy or request to destroy a thread - * - * @thread - thread to stop - * - * Request a thread to stop by setting nvgpu_thread_should_stop() to - * true and wait for thread to exit. - */ -void nvgpu_thread_stop(struct nvgpu_thread *thread); - -/** - * nvgpu_thread_should_stop - Query if thread should stop - * - * @thread - * - * Return true if thread should exit. Can be run only in the thread's own - * context and with the thread as parameter. - */ -bool nvgpu_thread_should_stop(struct nvgpu_thread *thread); - -/** - * nvgpu_thread_is_running - Query if thread is running - * - * @thread - * - * Return true if thread is started. - */ -bool nvgpu_thread_is_running(struct nvgpu_thread *thread); - -/** - * nvgpu_thread_join - join a thread to reclaim resources - * after it has exited - * - * @thread - thread to join - * - */ -void nvgpu_thread_join(struct nvgpu_thread *thread); - -#endif /* NVGPU_THREAD_H */ diff --git a/include/nvgpu/timers.h b/include/nvgpu/timers.h deleted file mode 100644 index f69e234..0000000 --- a/include/nvgpu/timers.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_TIMERS_H -#define NVGPU_TIMERS_H - -#include -#include - -struct gk20a; - -/* - * struct nvgpu_timeout - define a timeout. - * - * There are two types of timer suported: - * - * o NVGPU_TIMER_CPU_TIMER - * Timer uses the CPU to measure the timeout. - * - * o NVGPU_TIMER_RETRY_TIMER - * Instead of measuring a time limit keep track of the number of times - * something has been attempted. After said limit, "expire" the timer. - * - * Available flags: - * - * o NVGPU_TIMER_NO_PRE_SI - * By default when the system is not running on silicon the timeout - * code will ignore the requested timeout. Specifying this flag will - * override that behavior and honor the timeout regardless of platform. - * - * o NVGPU_TIMER_SILENT_TIMEOUT - * Do not print any messages on timeout. Normally a simple message is - * printed that specifies where the timeout occurred. - */ -struct nvgpu_timeout { - struct gk20a *g; - - unsigned int flags; - - union { - s64 time; - struct { - u32 max; - u32 attempted; - } retries; - }; -}; - -/* - * Bit 0 specifies the type of timer: CPU or retry. - */ -#define NVGPU_TIMER_CPU_TIMER (0x0) -#define NVGPU_TIMER_RETRY_TIMER (0x1) - -/* - * Bits 1 through 7 are reserved; bits 8 and up are flags: - */ -#define NVGPU_TIMER_NO_PRE_SI (0x1 << 8) -#define NVGPU_TIMER_SILENT_TIMEOUT (0x1 << 9) - -#define NVGPU_TIMER_FLAG_MASK (NVGPU_TIMER_RETRY_TIMER | \ - NVGPU_TIMER_NO_PRE_SI | \ - NVGPU_TIMER_SILENT_TIMEOUT) - -int nvgpu_timeout_init(struct gk20a *g, struct nvgpu_timeout *timeout, - u32 duration, unsigned long flags); -int nvgpu_timeout_peek_expired(struct nvgpu_timeout *timeout); - -#define nvgpu_timeout_expired(__timeout) \ - __nvgpu_timeout_expired_msg(__timeout, _NVGPU_GET_IP_, "") - -#define nvgpu_timeout_expired_msg(__timeout, fmt, args...) \ - __nvgpu_timeout_expired_msg(__timeout, _NVGPU_GET_IP_, \ - fmt, ##args) - -/* - * Don't use this directly. - */ -int __nvgpu_timeout_expired_msg(struct nvgpu_timeout *timeout, - void *caller, const char *fmt, ...); - - -/* - * Waits and delays. - */ -void nvgpu_msleep(unsigned int msecs); -void nvgpu_usleep_range(unsigned int min_us, unsigned int max_us); -void nvgpu_udelay(unsigned int usecs); - -/* - * Timekeeping. - */ -s64 nvgpu_current_time_ms(void); -s64 nvgpu_current_time_ns(void); -u64 nvgpu_hr_timestamp(void); - -#endif /* NVGPU_TIMERS_H */ diff --git a/include/nvgpu/tsg.h b/include/nvgpu/tsg.h deleted file mode 100644 index f5391e7..0000000 --- a/include/nvgpu/tsg.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) 2014-2021, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef TSG_GK20A_H -#define TSG_GK20A_H - -#include -#include -#include - -#include "gk20a/gr_gk20a.h" - -#define NVGPU_INVALID_TSG_ID (U32_MAX) - -struct channel_gk20a; - -struct tsg_gk20a *gk20a_tsg_open(struct gk20a *g, pid_t pid); -void gk20a_tsg_release(struct nvgpu_ref *ref); - -int gk20a_init_tsg_support(struct gk20a *g, u32 tsgid); -struct tsg_gk20a *tsg_gk20a_from_ch(struct channel_gk20a *ch); - -struct nvgpu_tsg_sm_error_state { - u32 hww_global_esr; - u32 hww_warp_esr; - u64 hww_warp_esr_pc; - u32 hww_global_esr_report_mask; - u32 hww_warp_esr_report_mask; -}; - -struct tsg_gk20a { - struct gk20a *g; - - struct vm_gk20a *vm; - struct nvgpu_mem *eng_method_buffers; - - - struct nvgpu_gr_ctx gr_ctx; - struct nvgpu_ref refcount; - - struct nvgpu_list_node ch_list; - struct nvgpu_list_node event_id_list; - struct nvgpu_rwsem ch_list_lock; - struct nvgpu_mutex event_id_list_lock; - int num_active_channels; - - unsigned int timeslice_us; - unsigned int timeslice_timeout; - unsigned int timeslice_scale; - - u32 interleave_level; - u32 tsgid; - - u32 runlist_id; - pid_t tgid; - u32 num_active_tpcs; - u8 tpc_pg_enabled; - bool tpc_num_initialized; - bool in_use; - - /* MMU debug mode enabled if mmu_debug_mode_refcnt > 0 */ - u32 mmu_debug_mode_refcnt; - - struct nvgpu_tsg_sm_error_state *sm_error_states; - -#define NVGPU_SM_EXCEPTION_TYPE_MASK_NONE (0x0U) -#define NVGPU_SM_EXCEPTION_TYPE_MASK_FATAL (0x1U << 0) - u32 sm_exception_mask_type; -}; - -int gk20a_enable_tsg(struct tsg_gk20a *tsg); -int gk20a_disable_tsg(struct tsg_gk20a *tsg); -int gk20a_tsg_bind_channel(struct tsg_gk20a *tsg, - struct channel_gk20a *ch); -int gk20a_tsg_unbind_channel(struct channel_gk20a *ch, bool force); - -void gk20a_tsg_event_id_post_event(struct tsg_gk20a *tsg, - int event_id); -int gk20a_tsg_set_runlist_interleave(struct tsg_gk20a *tsg, u32 level); -int gk20a_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice); -u32 gk20a_tsg_get_timeslice(struct tsg_gk20a *tsg); -int gk20a_tsg_set_priority(struct gk20a *g, struct tsg_gk20a *tsg, - u32 priority); -int gk20a_tsg_alloc_sm_error_states_mem(struct gk20a *g, - struct tsg_gk20a *tsg, - u32 num_sm); -void gk20a_tsg_update_sm_error_state_locked(struct tsg_gk20a *tsg, - u32 sm_id, - struct nvgpu_tsg_sm_error_state *sm_error_state); - -struct gk20a_event_id_data { - struct gk20a *g; - - int id; /* ch or tsg */ - int pid; - u32 event_id; - - bool event_posted; - - struct nvgpu_cond event_id_wq; - struct nvgpu_mutex lock; - struct nvgpu_list_node event_id_node; -}; - -static inline struct gk20a_event_id_data * -gk20a_event_id_data_from_event_id_node(struct nvgpu_list_node *node) -{ - return (struct gk20a_event_id_data *) - ((uintptr_t)node - offsetof(struct gk20a_event_id_data, event_id_node)); -}; - -int nvgpu_tsg_set_mmu_debug_mode(struct channel_gk20a *ch, bool enable); - -#endif /* TSG_GK20A_H */ diff --git a/include/nvgpu/types.h b/include/nvgpu/types.h deleted file mode 100644 index 0cb847b..0000000 --- a/include/nvgpu/types.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_TYPES_H -#define NVGPU_TYPES_H - -#ifdef __KERNEL__ -#include -#elif defined(__NVGPU_POSIX__) -#include -#else -#include -#endif - -/* - * These macros exist to make integer literals used in certain arithmetic - * operations explicitly large enough to hold the results of that operation. - * The following is an example of this. - * - * In MISRA the destination for a bitwise shift must be able to hold the number - * of bits shifted. Otherwise the results are undefined. For example: - * - * 256U << 20U - * - * This is valid C code but the results of this _may_ be undefined if the size - * of an unsigned by default is less than 24 bits (i.e 16 bits). The MISRA - * checker sees the 256U and determines that the 256U fits in a 16 bit data type - * (i.e a u16). Since a u16 has 16 bits, which is less than 20, this is an - * issue. - * - * Of course most compilers these days use 32 bits for the default unsigned type - * this is not a requirement. Moreover this same problem could exist like so: - * - * 0xfffffU << 40U - * - * The 0xfffffU is a 32 bit unsigned type; but we are shifting 40 bits which - * overflows the 32 bit data type. So in this case we need an explicit cast to - * 64 bits in order to prevent undefined behavior. - */ -#define U8(x) ((u8)(x)) -#define U16(x) ((u16)(x)) -#define U32(x) ((u32)(x)) -#define U64(x) ((u64)(x)) - -/* Linux uses U8_MAX instead of UCHAR_MAX. We define it here for non-Linux - * OSes - */ -#if !defined(__KERNEL__) && !defined(U8_MAX) -#define U8_MAX ((u8)255) -#define U32_MAX ((u32)~0U) -#endif - -#endif /* NVGPU_TYPES_H */ diff --git a/include/nvgpu/unit.h b/include/nvgpu/unit.h deleted file mode 100644 index 11df652..0000000 --- a/include/nvgpu/unit.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_UNIT_H -#define NVGPU_UNIT_H - -/* - * Enumeration of all units intended to be used by any HAL that requires - * unit as parameter. - * - * Units are added to the enumeration as needed, so it is not complete. - */ -enum nvgpu_unit { - NVGPU_UNIT_FIFO, - NVGPU_UNIT_PERFMON, - NVGPU_UNIT_GRAPH, - NVGPU_UNIT_BLG, - NVGPU_UNIT_PWR, - NVGPU_UNIT_NVDEC, -}; - -#endif /* NVGPU_UNIT_H */ diff --git a/include/nvgpu/utils.h b/include/nvgpu/utils.h deleted file mode 100644 index 6184608..0000000 --- a/include/nvgpu/utils.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_UTILS_H -#define NVGPU_UTILS_H - -#include - -static inline u32 u64_hi32(u64 n) -{ - return (u32)((n >> 32) & ~(u32)0); -} - -static inline u32 u64_lo32(u64 n) -{ - return (u32)(n & ~(u32)0); -} - -static inline u64 hi32_lo32_to_u64(u32 hi, u32 lo) -{ - return (((u64)hi) << 32) | (u64)lo; -} - -static inline u32 set_field(u32 val, u32 mask, u32 field) -{ - return ((val & ~mask) | field); -} - -static inline u32 get_field(u32 reg, u32 mask) -{ - return (reg & mask); -} - -/* - * MISRA Rule 11.6 compliant IP address generator. - */ -#define _NVGPU_GET_IP_ ({ __label__ __here; __here: &&__here; }) - -#endif /* NVGPU_UTILS_H */ diff --git a/include/nvgpu/vgpu/tegra_vgpu.h b/include/nvgpu/vgpu/tegra_vgpu.h deleted file mode 100644 index e33dce9..0000000 --- a/include/nvgpu/vgpu/tegra_vgpu.h +++ /dev/null @@ -1,817 +0,0 @@ -/* - * Tegra GPU Virtualization Interfaces to Server - * - * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef TEGRA_VGPU_H -#define TEGRA_VGPU_H - -#include -#include /* For NVGPU_ECC_STAT_NAME_MAX_SIZE */ - -enum { - TEGRA_VGPU_MODULE_GPU = 0, -}; - -enum { - /* Needs to follow last entry in TEGRA_VHOST_QUEUE_* list, - * in tegra_vhost.h - */ - TEGRA_VGPU_QUEUE_CMD = 3, - TEGRA_VGPU_QUEUE_INTR -}; - -enum { - TEGRA_VGPU_CMD_CONNECT = 0, - TEGRA_VGPU_CMD_DISCONNECT = 1, - TEGRA_VGPU_CMD_ABORT = 2, - TEGRA_VGPU_CMD_CHANNEL_ALLOC_HWCTX = 3, - TEGRA_VGPU_CMD_CHANNEL_FREE_HWCTX = 4, - TEGRA_VGPU_CMD_GET_ATTRIBUTE = 5, - TEGRA_VGPU_CMD_MAP_BAR1 = 6, - TEGRA_VGPU_CMD_AS_ALLOC_SHARE = 7, - TEGRA_VGPU_CMD_AS_BIND_SHARE = 8, - TEGRA_VGPU_CMD_AS_FREE_SHARE = 9, - TEGRA_VGPU_CMD_AS_UNMAP = 11, - TEGRA_VGPU_CMD_CHANNEL_BIND = 13, - TEGRA_VGPU_CMD_CHANNEL_UNBIND = 14, - TEGRA_VGPU_CMD_CHANNEL_DISABLE = 15, - TEGRA_VGPU_CMD_CHANNEL_PREEMPT = 16, - TEGRA_VGPU_CMD_CHANNEL_SETUP_RAMFC = 17, - TEGRA_VGPU_CMD_CHANNEL_COMMIT_GR_CTX = 20, - TEGRA_VGPU_CMD_CHANNEL_ALLOC_GR_PATCH_CTX = 21, - TEGRA_VGPU_CMD_CHANNEL_FREE_GR_PATCH_CTX = 22, - TEGRA_VGPU_CMD_CHANNEL_MAP_GR_GLOBAL_CTX = 23, - TEGRA_VGPU_CMD_CHANNEL_UNMAP_GR_GLOBAL_CTX = 24, - TEGRA_VGPU_CMD_CHANNEL_COMMIT_GR_GLOBAL_CTX = 25, - TEGRA_VGPU_CMD_CHANNEL_LOAD_GR_GOLDEN_CTX = 26, - TEGRA_VGPU_CMD_CHANNEL_BIND_ZCULL = 27, - TEGRA_VGPU_CMD_CACHE_MAINT = 28, - TEGRA_VGPU_CMD_SUBMIT_RUNLIST = 29, - TEGRA_VGPU_CMD_GET_ZCULL_INFO = 30, - TEGRA_VGPU_CMD_ZBC_SET_TABLE = 31, - TEGRA_VGPU_CMD_ZBC_QUERY_TABLE = 32, - TEGRA_VGPU_CMD_AS_MAP_EX = 33, - TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS = 34, - TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE = 35, - TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE = 36, - TEGRA_VGPU_CMD_REG_OPS = 37, - TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY = 38, - TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE = 39, - TEGRA_VGPU_CMD_CHANNEL_SET_TIMESLICE = 40, - TEGRA_VGPU_CMD_FECS_TRACE_ENABLE = 41, - TEGRA_VGPU_CMD_FECS_TRACE_DISABLE = 42, - TEGRA_VGPU_CMD_FECS_TRACE_POLL = 43, - TEGRA_VGPU_CMD_FECS_TRACE_SET_FILTER = 44, - TEGRA_VGPU_CMD_CHANNEL_SET_SMPC_CTXSW_MODE = 45, - TEGRA_VGPU_CMD_CHANNEL_SET_HWPM_CTXSW_MODE = 46, - TEGRA_VGPU_CMD_CHANNEL_FREE_HWPM_CTX = 47, - TEGRA_VGPU_CMD_GR_CTX_ALLOC = 48, - TEGRA_VGPU_CMD_GR_CTX_FREE = 49, - TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTX = 50, - TEGRA_VGPU_CMD_TSG_BIND_GR_CTX = 51, - TEGRA_VGPU_CMD_TSG_BIND_CHANNEL = 52, - TEGRA_VGPU_CMD_TSG_UNBIND_CHANNEL = 53, - TEGRA_VGPU_CMD_TSG_PREEMPT = 54, - TEGRA_VGPU_CMD_TSG_SET_TIMESLICE = 55, - TEGRA_VGPU_CMD_TSG_SET_RUNLIST_INTERLEAVE = 56, - TEGRA_VGPU_CMD_CHANNEL_FORCE_RESET = 57, - TEGRA_VGPU_CMD_CHANNEL_ENABLE = 58, - TEGRA_VGPU_CMD_READ_PTIMER = 59, - TEGRA_VGPU_CMD_SET_POWERGATE = 60, - TEGRA_VGPU_CMD_SET_GPU_CLK_RATE = 61, - TEGRA_VGPU_CMD_GET_CONSTANTS = 62, - TEGRA_VGPU_CMD_CHANNEL_CYCLESTATS_SNAPSHOT = 63, - TEGRA_VGPU_CMD_TSG_OPEN = 64, - TEGRA_VGPU_CMD_GET_GPU_LOAD = 65, - TEGRA_VGPU_CMD_SUSPEND_CONTEXTS = 66, - TEGRA_VGPU_CMD_RESUME_CONTEXTS = 67, - TEGRA_VGPU_CMD_CLEAR_SM_ERROR_STATE = 68, - TEGRA_VGPU_CMD_GET_GPU_CLK_RATE = 69, - TEGRA_VGPU_CMD_GET_GPU_FREQ_TABLE = 70, - TEGRA_VGPU_CMD_CAP_GPU_CLK_RATE = 71, - TEGRA_VGPU_CMD_PROF_MGT = 72, - TEGRA_VGPU_CMD_PERFBUF_MGT = 73, - TEGRA_VGPU_CMD_GET_TIMESTAMPS_ZIPPER = 74, - TEGRA_VGPU_CMD_TSG_RELEASE = 75, - TEGRA_VGPU_CMD_GET_VSMS_MAPPING = 76, - TEGRA_VGPU_CMD_ALLOC_CTX_HEADER = 77, - TEGRA_VGPU_CMD_FREE_CTX_HEADER = 78, - TEGRA_VGPU_CMD_MAP_SYNCPT = 79, - TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX = 80, - TEGRA_VGPU_CMD_UPDATE_PC_SAMPLING = 81, - TEGRA_VGPU_CMD_SUSPEND = 82, - TEGRA_VGPU_CMD_RESUME = 83, - TEGRA_VGPU_CMD_GET_ECC_INFO = 84, - TEGRA_VGPU_CMD_GET_ECC_COUNTER_VALUE = 85, - TEGRA_VGPU_CMD_FB_SET_MMU_DEBUG_MODE = 88, - TEGRA_VGPU_CMD_GR_SET_MMU_DEBUG_MODE = 89, -}; - -struct tegra_vgpu_connect_params { - u32 module; - u64 handle; -}; - -struct tegra_vgpu_channel_hwctx_params { - u32 id; - u64 pid; - u64 handle; -}; - -struct tegra_vgpu_attrib_params { - u32 attrib; - u32 value; -}; - -struct tegra_vgpu_as_share_params { - u64 size; - u64 handle; - u32 big_page_size; -}; - -struct tegra_vgpu_as_bind_share_params { - u64 as_handle; - u64 chan_handle; -}; - -enum { - TEGRA_VGPU_MAP_PROT_NONE = 0, - TEGRA_VGPU_MAP_PROT_READ_ONLY, - TEGRA_VGPU_MAP_PROT_WRITE_ONLY -}; - -struct tegra_vgpu_as_map_params { - u64 handle; - u64 addr; - u64 gpu_va; - u64 size; - u8 pgsz_idx; - u8 iova; - u8 kind; - u8 cacheable; - u8 clear_ctags; - u8 prot; - u32 ctag_offset; -}; - -#define TEGRA_VGPU_MAP_CACHEABLE (1 << 0) -#define TEGRA_VGPU_MAP_IO_COHERENT (1 << 1) -#define TEGRA_VGPU_MAP_L3_ALLOC (1 << 2) -#define TEGRA_VGPU_MAP_PLATFORM_ATOMIC (1 << 3) - -struct tegra_vgpu_as_map_ex_params { - u64 handle; - u64 gpu_va; - u64 size; - u32 mem_desc_count; - u8 pgsz_idx; - u8 iova; - u8 kind; - u32 flags; - u8 clear_ctags; - u8 prot; - u32 ctag_offset; -}; - -struct tegra_vgpu_mem_desc { - u64 addr; - u64 length; -}; - -struct tegra_vgpu_channel_config_params { - u64 handle; -}; - -struct tegra_vgpu_ramfc_params { - u64 handle; - u64 gpfifo_va; - u32 num_entries; - u64 userd_addr; - u8 iova; -}; - -struct tegra_vgpu_ch_ctx_params { - u64 handle; - u64 gr_ctx_va; - u64 patch_ctx_va; - u64 cb_va; - u64 attr_va; - u64 page_pool_va; - u64 priv_access_map_va; - u64 fecs_trace_va; - u32 class_num; -}; - -struct tegra_vgpu_zcull_bind_params { - u64 handle; - u64 zcull_va; - u32 mode; -}; - -enum { - TEGRA_VGPU_L2_MAINT_FLUSH = 0, - TEGRA_VGPU_L2_MAINT_INV, - TEGRA_VGPU_L2_MAINT_FLUSH_INV, - TEGRA_VGPU_FB_FLUSH -}; - -struct tegra_vgpu_cache_maint_params { - u8 op; -}; - -struct tegra_vgpu_runlist_params { - u8 runlist_id; - u32 num_entries; -}; - -struct tegra_vgpu_golden_ctx_params { - u32 size; -}; - -struct tegra_vgpu_zcull_info_params { - u32 width_align_pixels; - u32 height_align_pixels; - u32 pixel_squares_by_aliquots; - u32 aliquot_total; - u32 region_byte_multiplier; - u32 region_header_size; - u32 subregion_header_size; - u32 subregion_width_align_pixels; - u32 subregion_height_align_pixels; - u32 subregion_count; -}; - -#define TEGRA_VGPU_ZBC_COLOR_VALUE_SIZE 4 -#define TEGRA_VGPU_ZBC_TYPE_INVALID 0 -#define TEGRA_VGPU_ZBC_TYPE_COLOR 1 -#define TEGRA_VGPU_ZBC_TYPE_DEPTH 2 - -struct tegra_vgpu_zbc_set_table_params { - u32 color_ds[TEGRA_VGPU_ZBC_COLOR_VALUE_SIZE]; - u32 color_l2[TEGRA_VGPU_ZBC_COLOR_VALUE_SIZE]; - u32 depth; - u32 format; - u32 type; /* color or depth */ -}; - -struct tegra_vgpu_zbc_query_table_params { - u32 color_ds[TEGRA_VGPU_ZBC_COLOR_VALUE_SIZE]; - u32 color_l2[TEGRA_VGPU_ZBC_COLOR_VALUE_SIZE]; - u32 depth; - u32 ref_cnt; - u32 format; - u32 type; /* color or depth */ - u32 index_size; /* [out] size, [in] index */ -}; - -enum { - TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN, - TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL, - TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL, - TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB, - TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_LAST -}; - -enum { - TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_WFI, - TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_GFX_GFXP, - TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CTA, - TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CILP, - TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_LAST -}; - -struct tegra_vgpu_gr_bind_ctxsw_buffers_params { - u64 handle; /* deprecated */ - u64 gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_LAST]; - u64 size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_LAST]; - u32 mode; - u64 gr_ctx_handle; -}; - -struct tegra_vgpu_mmu_debug_mode { - u32 enable; -}; - -struct tegra_vgpu_sm_debug_mode { - u64 handle; - u64 sms; - u32 enable; -}; - -struct tegra_vgpu_reg_op { - u8 op; - u8 type; - u8 status; - u8 quad; - u32 group_mask; - u32 sub_group_mask; - u32 offset; - u32 value_lo; - u32 value_hi; - u32 and_n_mask_lo; - u32 and_n_mask_hi; -}; - -struct tegra_vgpu_reg_ops_params { - u64 handle; - u64 num_ops; - u32 is_profiler; -}; - -struct tegra_vgpu_channel_priority_params { - u64 handle; - u32 priority; -}; - -/* level follows nvgpu.h definitions */ -struct tegra_vgpu_channel_runlist_interleave_params { - u64 handle; - u32 level; -}; - -struct tegra_vgpu_channel_timeslice_params { - u64 handle; - u32 timeslice_us; -}; - -#define TEGRA_VGPU_FECS_TRACE_FILTER_SIZE 256 -struct tegra_vgpu_fecs_trace_filter { - u64 tag_bits[(TEGRA_VGPU_FECS_TRACE_FILTER_SIZE + 63) / 64]; -}; - -enum { - TEGRA_VGPU_CTXSW_MODE_NO_CTXSW = 0, - TEGRA_VGPU_CTXSW_MODE_CTXSW, - TEGRA_VGPU_CTXSW_MODE_STREAM_OUT_CTXSW, -}; - -enum { - TEGRA_VGPU_DISABLE_SAMPLING = 0, - TEGRA_VGPU_ENABLE_SAMPLING, -}; -struct tegra_vgpu_channel_set_ctxsw_mode { - u64 handle; - u64 gpu_va; - u32 mode; -}; - -struct tegra_vgpu_channel_update_pc_sampling { - u64 handle; - u32 mode; -}; - -struct tegra_vgpu_channel_free_hwpm_ctx { - u64 handle; -}; - -struct tegra_vgpu_ecc_info_params { - u32 ecc_stats_count; -}; - -struct tegra_vgpu_ecc_info_entry { - u32 ecc_id; - char name[NVGPU_ECC_STAT_NAME_MAX_SIZE]; -}; - -struct tegra_vgpu_ecc_counter_params { - u32 ecc_id; - u32 value; -}; - -struct tegra_vgpu_gr_ctx_params { - u64 gr_ctx_handle; - u64 as_handle; - u64 gr_ctx_va; - u32 class_num; - u32 tsg_id; -}; - -struct tegra_vgpu_channel_bind_gr_ctx_params { - u64 ch_handle; - u64 gr_ctx_handle; -}; - -struct tegra_vgpu_tsg_bind_gr_ctx_params { - u32 tsg_id; - u64 gr_ctx_handle; -}; - -struct tegra_vgpu_tsg_bind_unbind_channel_params { - u32 tsg_id; - u64 ch_handle; -}; - -struct tegra_vgpu_tsg_preempt_params { - u32 tsg_id; -}; - -struct tegra_vgpu_tsg_timeslice_params { - u32 tsg_id; - u32 timeslice_us; -}; - -struct tegra_vgpu_tsg_open_rel_params { - u32 tsg_id; -}; - -/* level follows nvgpu.h definitions */ -struct tegra_vgpu_tsg_runlist_interleave_params { - u32 tsg_id; - u32 level; -}; - -struct tegra_vgpu_read_ptimer_params { - u64 time; -}; - -#define TEGRA_VGPU_GET_TIMESTAMPS_ZIPPER_MAX_COUNT 16 -#define TEGRA_VGPU_GET_TIMESTAMPS_ZIPPER_SRC_ID_TSC 1 -struct tegra_vgpu_get_timestamps_zipper_params { - /* timestamp pairs */ - struct { - /* gpu timestamp value */ - u64 cpu_timestamp; - /* raw GPU counter (PTIMER) value */ - u64 gpu_timestamp; - } samples[TEGRA_VGPU_GET_TIMESTAMPS_ZIPPER_MAX_COUNT]; - /* number of pairs to read */ - u32 count; - /* cpu clock source id */ - u32 source_id; -}; - -#define TEGRA_VGPU_POWERGATE_MODE_ENABLE 1 -#define TEGRA_VGPU_POWERGATE_MODE_DISABLE 2 -struct tegra_vgpu_set_powergate_params { - u32 mode; -}; - -struct tegra_vgpu_gpu_clk_rate_params { - u32 rate; /* in kHz */ -}; - -/* TEGRA_VGPU_MAX_ENGINES must be equal or greater than num_engines */ -#define TEGRA_VGPU_MAX_ENGINES 4 -struct tegra_vgpu_engines_info { - u32 num_engines; - struct engineinfo { - u32 engine_id; - u32 intr_mask; - u32 reset_mask; - u32 runlist_id; - u32 pbdma_id; - u32 inst_id; - u32 pri_base; - u32 engine_enum; - u32 fault_id; - } info[TEGRA_VGPU_MAX_ENGINES]; -}; - -#define TEGRA_VGPU_MAX_GPC_COUNT 16 -#define TEGRA_VGPU_MAX_TPC_COUNT_PER_GPC 16 -#define TEGRA_VGPU_L2_EN_MASK 32 - -struct tegra_vgpu_constants_params { - u32 arch; - u32 impl; - u32 rev; - u32 max_freq; - u32 num_channels; - u32 golden_ctx_size; - u32 zcull_ctx_size; - u32 l2_size; - u32 ltc_count; - u32 cacheline_size; - u32 slices_per_ltc; - u32 comptags_per_cacheline; - u32 comptag_lines; - u32 sm_arch_sm_version; - u32 sm_arch_spa_version; - u32 sm_arch_warp_count; - u32 max_gpc_count; - u32 gpc_count; - u32 max_tpc_per_gpc_count; - u32 num_fbps; - u32 fbp_en_mask; - u32 ltc_per_fbp; - u32 max_lts_per_ltc; - u8 gpc_tpc_count[TEGRA_VGPU_MAX_GPC_COUNT]; - /* mask bits should be equal or larger than - * TEGRA_VGPU_MAX_TPC_COUNT_PER_GPC - */ - u16 gpc_tpc_mask[TEGRA_VGPU_MAX_GPC_COUNT]; - u32 hwpm_ctx_size; - u8 force_preempt_mode; - u8 can_set_clkrate; - u32 default_timeslice_us; - u32 preempt_ctx_size; - u32 channel_base; - struct tegra_vgpu_engines_info engines_info; - u32 num_pce; - u32 sm_per_tpc; - u32 max_subctx_count; - u32 l2_en_mask[TEGRA_VGPU_L2_EN_MASK]; -}; - -enum { - TEGRA_VGPU_CYCLE_STATS_SNAPSHOT_CMD_FLUSH = 0, - TEGRA_VGPU_CYCLE_STATS_SNAPSHOT_CMD_ATTACH = 1, - TEGRA_VGPU_CYCLE_STATS_SNAPSHOT_CMD_DETACH = 2, -}; - -struct tegra_vgpu_channel_cyclestats_snapshot_params { - u64 handle; - u32 perfmon_start; - u32 perfmon_count; - u32 buf_info; /* client->srvr: get ptr; srvr->client: num pending */ - u8 subcmd; - u8 hw_overflow; -}; - -struct tegra_vgpu_gpu_load_params { - u32 load; -}; - -struct tegra_vgpu_suspend_resume_contexts { - u32 num_channels; - u16 resident_chid; -}; - -struct tegra_vgpu_clear_sm_error_state { - u64 handle; - u32 sm_id; -}; - -enum { - TEGRA_VGPU_PROF_GET_GLOBAL = 0, - TEGRA_VGPU_PROF_GET_CONTEXT, - TEGRA_VGPU_PROF_RELEASE -}; - -struct tegra_vgpu_prof_mgt_params { - u32 mode; -}; - -struct tegra_vgpu_perfbuf_mgt_params { - u64 vm_handle; - u64 offset; - u32 size; -}; - -#define TEGRA_VGPU_GPU_FREQ_TABLE_SIZE 25 - -struct tegra_vgpu_get_gpu_freq_table_params { - u32 num_freqs; -}; - -struct tegra_vgpu_vsms_mapping_params { - u32 num_sm; -}; - -struct tegra_vgpu_vsms_mapping_entry { - u32 gpc_index; - u32 tpc_index; - u32 sm_index; - u32 global_tpc_index; -}; - -struct tegra_vgpu_alloc_ctx_header_params { - u64 ch_handle; - u64 ctx_header_va; -}; - -struct tegra_vgpu_free_ctx_header_params { - u64 ch_handle; -}; - -struct tegra_vgpu_map_syncpt_params { - u64 as_handle; - u64 gpu_va; - u64 len; - u64 offset; - u8 prot; -}; - -struct tegra_vgpu_tsg_bind_channel_ex_params { - u32 tsg_id; - u64 ch_handle; - u32 subctx_id; - u32 runqueue_sel; -}; - -struct tegra_vgpu_fb_set_mmu_debug_mode_params { - u8 enable; -}; - -struct tegra_vgpu_gr_set_mmu_debug_mode_params { - u64 ch_handle; - u8 enable; -}; - -struct tegra_vgpu_cmd_msg { - u32 cmd; - int ret; - u64 handle; - union { - struct tegra_vgpu_connect_params connect; - struct tegra_vgpu_channel_hwctx_params channel_hwctx; - struct tegra_vgpu_attrib_params attrib; - struct tegra_vgpu_as_share_params as_share; - struct tegra_vgpu_as_bind_share_params as_bind_share; - struct tegra_vgpu_as_map_params as_map; - struct tegra_vgpu_as_map_ex_params as_map_ex; - struct tegra_vgpu_channel_config_params channel_config; - struct tegra_vgpu_ramfc_params ramfc; - struct tegra_vgpu_ch_ctx_params ch_ctx; - struct tegra_vgpu_zcull_bind_params zcull_bind; - struct tegra_vgpu_cache_maint_params cache_maint; - struct tegra_vgpu_runlist_params runlist; - struct tegra_vgpu_golden_ctx_params golden_ctx; - struct tegra_vgpu_zcull_info_params zcull_info; - struct tegra_vgpu_zbc_set_table_params zbc_set_table; - struct tegra_vgpu_zbc_query_table_params zbc_query_table; - struct tegra_vgpu_gr_bind_ctxsw_buffers_params gr_bind_ctxsw_buffers; - struct tegra_vgpu_mmu_debug_mode mmu_debug_mode; - struct tegra_vgpu_sm_debug_mode sm_debug_mode; - struct tegra_vgpu_reg_ops_params reg_ops; - struct tegra_vgpu_channel_priority_params channel_priority; - struct tegra_vgpu_channel_runlist_interleave_params channel_interleave; - struct tegra_vgpu_channel_timeslice_params channel_timeslice; - struct tegra_vgpu_fecs_trace_filter fecs_trace_filter; - struct tegra_vgpu_channel_set_ctxsw_mode set_ctxsw_mode; - struct tegra_vgpu_channel_free_hwpm_ctx free_hwpm_ctx; - struct tegra_vgpu_gr_ctx_params gr_ctx; - struct tegra_vgpu_channel_bind_gr_ctx_params ch_bind_gr_ctx; - struct tegra_vgpu_tsg_bind_gr_ctx_params tsg_bind_gr_ctx; - struct tegra_vgpu_tsg_bind_unbind_channel_params tsg_bind_unbind_channel; - struct tegra_vgpu_tsg_open_rel_params tsg_open; - struct tegra_vgpu_tsg_open_rel_params tsg_release; - struct tegra_vgpu_tsg_preempt_params tsg_preempt; - struct tegra_vgpu_tsg_timeslice_params tsg_timeslice; - struct tegra_vgpu_tsg_runlist_interleave_params tsg_interleave; - struct tegra_vgpu_read_ptimer_params read_ptimer; - struct tegra_vgpu_set_powergate_params set_powergate; - struct tegra_vgpu_gpu_clk_rate_params gpu_clk_rate; - struct tegra_vgpu_constants_params constants; - struct tegra_vgpu_channel_cyclestats_snapshot_params cyclestats_snapshot; - struct tegra_vgpu_gpu_load_params gpu_load; - struct tegra_vgpu_suspend_resume_contexts suspend_contexts; - struct tegra_vgpu_suspend_resume_contexts resume_contexts; - struct tegra_vgpu_clear_sm_error_state clear_sm_error_state; - struct tegra_vgpu_prof_mgt_params prof_management; - struct tegra_vgpu_perfbuf_mgt_params perfbuf_management; - struct tegra_vgpu_get_timestamps_zipper_params get_timestamps_zipper; - struct tegra_vgpu_get_gpu_freq_table_params get_gpu_freq_table; - struct tegra_vgpu_vsms_mapping_params vsms_mapping; - struct tegra_vgpu_alloc_ctx_header_params alloc_ctx_header; - struct tegra_vgpu_free_ctx_header_params free_ctx_header; - struct tegra_vgpu_map_syncpt_params map_syncpt; - struct tegra_vgpu_tsg_bind_channel_ex_params tsg_bind_channel_ex; - struct tegra_vgpu_channel_update_pc_sampling update_pc_sampling; - struct tegra_vgpu_ecc_info_params ecc_info; - struct tegra_vgpu_ecc_counter_params ecc_counter; - struct tegra_vgpu_fb_set_mmu_debug_mode_params fb_set_mmu_debug_mode; - struct tegra_vgpu_gr_set_mmu_debug_mode_params gr_set_mmu_debug_mode; - char padding[192]; - } params; -}; - -enum { - TEGRA_VGPU_GR_INTR_NOTIFY = 0, - TEGRA_VGPU_GR_INTR_SEMAPHORE_TIMEOUT = 1, - TEGRA_VGPU_GR_INTR_ILLEGAL_NOTIFY = 2, - TEGRA_VGPU_GR_INTR_ILLEGAL_METHOD = 3, - TEGRA_VGPU_GR_INTR_ILLEGAL_CLASS = 4, - TEGRA_VGPU_GR_INTR_FECS_ERROR = 5, - TEGRA_VGPU_GR_INTR_CLASS_ERROR = 6, - TEGRA_VGPU_GR_INTR_FIRMWARE_METHOD = 7, - TEGRA_VGPU_GR_INTR_EXCEPTION = 8, - TEGRA_VGPU_GR_INTR_SEMAPHORE = 9, - TEGRA_VGPU_FIFO_INTR_PBDMA = 10, - TEGRA_VGPU_FIFO_INTR_CTXSW_TIMEOUT = 11, - TEGRA_VGPU_FIFO_INTR_MMU_FAULT = 12, - TEGRA_VGPU_GR_INTR_SM_EXCEPTION = 16, -}; - -struct tegra_vgpu_gr_intr_info { - u32 type; - u32 chid; -}; - -struct tegra_vgpu_gr_nonstall_intr_info { - u32 type; -}; - -struct tegra_vgpu_fifo_intr_info { - u32 type; - u32 chid; -}; - -struct tegra_vgpu_fifo_nonstall_intr_info { - u32 type; -}; - -struct tegra_vgpu_ce2_nonstall_intr_info { - u32 type; -}; - -enum { - TEGRA_VGPU_FECS_TRACE_DATA_UPDATE = 0 -}; - -struct tegra_vgpu_fecs_trace_event_info { - u32 type; -}; - -#define TEGRA_VGPU_CHANNEL_EVENT_ID_MAX 6 -struct tegra_vgpu_channel_event_info { - u32 event_id; - u32 is_tsg; - u32 id; /* channel id or tsg id */ -}; - -struct tegra_vgpu_sm_esr_info { - u32 tsg_id; - u32 sm_id; - u32 hww_global_esr; - u32 hww_warp_esr; - u64 hww_warp_esr_pc; - u32 hww_global_esr_report_mask; - u32 hww_warp_esr_report_mask; -}; - -struct tegra_vgpu_semaphore_wakeup { - u32 post_events; -}; - -struct tegra_vgpu_channel_cleanup { - u32 chid; -}; - -struct tegra_vgpu_channel_set_error_notifier { - u32 chid; - u32 error; -}; - -enum { - - TEGRA_VGPU_INTR_GR = 0, - TEGRA_VGPU_INTR_FIFO = 1, - TEGRA_VGPU_INTR_CE2 = 2, -}; - -enum { - TEGRA_VGPU_EVENT_INTR = 0, - TEGRA_VGPU_EVENT_ABORT = 1, - TEGRA_VGPU_EVENT_FECS_TRACE = 2, - TEGRA_VGPU_EVENT_CHANNEL = 3, - TEGRA_VGPU_EVENT_SM_ESR = 4, - TEGRA_VGPU_EVENT_SEMAPHORE_WAKEUP = 5, - TEGRA_VGPU_EVENT_CHANNEL_CLEANUP = 6, - TEGRA_VGPU_EVENT_SET_ERROR_NOTIFIER = 7, -}; - -struct tegra_vgpu_intr_msg { - unsigned int event; - u32 unit; - union { - struct tegra_vgpu_gr_intr_info gr_intr; - struct tegra_vgpu_gr_nonstall_intr_info gr_nonstall_intr; - struct tegra_vgpu_fifo_intr_info fifo_intr; - struct tegra_vgpu_fifo_nonstall_intr_info fifo_nonstall_intr; - struct tegra_vgpu_ce2_nonstall_intr_info ce2_nonstall_intr; - struct tegra_vgpu_fecs_trace_event_info fecs_trace; - struct tegra_vgpu_channel_event_info channel_event; - struct tegra_vgpu_sm_esr_info sm_esr; - struct tegra_vgpu_semaphore_wakeup sem_wakeup; - struct tegra_vgpu_channel_cleanup ch_cleanup; - struct tegra_vgpu_channel_set_error_notifier set_error_notifier; - char padding[32]; - } info; -}; - -#define TEGRA_VGPU_QUEUE_SIZES \ - 512, \ - sizeof(struct tegra_vgpu_intr_msg) - -#endif diff --git a/include/nvgpu/vgpu/vgpu.h b/include/nvgpu/vgpu/vgpu.h deleted file mode 100644 index ecdb896..0000000 --- a/include/nvgpu/vgpu/vgpu.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __VGPU_COMMON_H__ -#define __VGPU_COMMON_H__ - -#include -#include -#include -#include -#include - -struct device; -struct tegra_vgpu_gr_intr_info; -struct tegra_vgpu_fifo_intr_info; -struct tegra_vgpu_cmd_msg; -struct nvgpu_mem; -struct gk20a; -struct vm_gk20a; -struct nvgpu_gr_ctx; -struct nvgpu_cpu_time_correlation_sample; -struct vgpu_ecc_stat; -struct channel_gk20a; - -struct vgpu_priv_data { - u64 virt_handle; - struct nvgpu_thread intr_handler; - struct tegra_vgpu_constants_params constants; - struct vgpu_ecc_stat *ecc_stats; - int ecc_stats_count; - u32 num_freqs; - unsigned long *freqs; - struct nvgpu_mutex vgpu_clk_get_freq_lock; -}; - -struct vgpu_priv_data *vgpu_get_priv_data(struct gk20a *g); - -static inline u64 vgpu_get_handle(struct gk20a *g) -{ - struct vgpu_priv_data *priv = vgpu_get_priv_data(g); - - if (unlikely(!priv)) { - nvgpu_err(g, "invalid vgpu_priv_data in %s", __func__); - return INT_MAX; - } - - return priv->virt_handle; -} - -int vgpu_comm_init(struct gk20a *g); -void vgpu_comm_deinit(void); -int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in, - size_t size_out); -u64 vgpu_connect(void); -int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value); -int vgpu_intr_thread(void *dev_id); -void vgpu_remove_support_common(struct gk20a *g); -void vgpu_detect_chip(struct gk20a *g); -int vgpu_init_gpu_characteristics(struct gk20a *g); -int vgpu_read_ptimer(struct gk20a *g, u64 *value); -int vgpu_get_timestamps_zipper(struct gk20a *g, - u32 source_id, u32 count, - struct nvgpu_cpu_time_correlation_sample *samples); -int vgpu_init_hal(struct gk20a *g); -int vgpu_get_constants(struct gk20a *g); -u64 vgpu_bar1_map(struct gk20a *g, struct nvgpu_mem *mem); -int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info); -int vgpu_gr_alloc_gr_ctx(struct gk20a *g, - struct nvgpu_gr_ctx *gr_ctx, - struct vm_gk20a *vm, - u32 class, - u32 flags); -void vgpu_gr_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, - struct nvgpu_gr_ctx *gr_ctx); -void vgpu_gr_handle_sm_esr_event(struct gk20a *g, - struct tegra_vgpu_sm_esr_info *info); -int vgpu_gr_init_ctx_state(struct gk20a *g); -int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info); -u32 vgpu_ce_get_num_pce(struct gk20a *g); -int vgpu_init_mm_support(struct gk20a *g); -int vgpu_init_gr_support(struct gk20a *g); -int vgpu_init_fifo_support(struct gk20a *g); - -int vgpu_gp10b_init_hal(struct gk20a *g); -int vgpu_gv11b_init_hal(struct gk20a *g); - -bool vgpu_is_reduced_bar1(struct gk20a *g); - -int vgpu_gr_set_mmu_debug_mode(struct gk20a *g, - struct channel_gk20a *ch, bool enable); -#endif diff --git a/include/nvgpu/vgpu/vgpu_ivc.h b/include/nvgpu/vgpu/vgpu_ivc.h deleted file mode 100644 index e7e4026..0000000 --- a/include/nvgpu/vgpu/vgpu_ivc.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __VGPU_IVC_H__ -#define __VGPU_IVC_H__ - -#include - -struct gk20a; - -int vgpu_ivc_init(struct gk20a *g, u32 elems, - const size_t *queue_sizes, u32 queue_start, u32 num_queues); -void vgpu_ivc_deinit(u32 queue_start, u32 num_queues); -void vgpu_ivc_release(void *handle); -u32 vgpu_ivc_get_server_vmid(void); -int vgpu_ivc_recv(u32 index, void **handle, void **data, - size_t *size, u32 *sender); -int vgpu_ivc_send(u32 peer, u32 index, void *data, size_t size); -int vgpu_ivc_sendrecv(u32 peer, u32 index, void **handle, - void **data, size_t *size); -u32 vgpu_ivc_get_peer_self(void); -void *vgpu_ivc_oob_get_ptr(u32 peer, u32 index, void **ptr, - size_t *size); -void vgpu_ivc_oob_put_ptr(void *handle); - -#endif diff --git a/include/nvgpu/vgpu/vgpu_ivm.h b/include/nvgpu/vgpu/vgpu_ivm.h deleted file mode 100644 index cecdd51..0000000 --- a/include/nvgpu/vgpu/vgpu_ivm.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __VGPU_IVM_H__ -#define __VGPU_IVM_H__ - -#include - -struct tegra_hv_ivm_cookie; - -struct tegra_hv_ivm_cookie *vgpu_ivm_mempool_reserve(unsigned int id); -int vgpu_ivm_mempool_unreserve(struct tegra_hv_ivm_cookie *cookie); -u64 vgpu_ivm_get_ipa(struct tegra_hv_ivm_cookie *cookie); -u64 vgpu_ivm_get_size(struct tegra_hv_ivm_cookie *cookie); -void *vgpu_ivm_mempool_map(struct tegra_hv_ivm_cookie *cookie); -void vgpu_ivm_mempool_unmap(struct tegra_hv_ivm_cookie *cookie, - void *addr); -#endif diff --git a/include/nvgpu/vgpu/vm.h b/include/nvgpu/vgpu/vm.h deleted file mode 100644 index fc0078d..0000000 --- a/include/nvgpu/vgpu/vm.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_VGPU_VM_H -#define NVGPU_VGPU_VM_H - -#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION -int vgpu_vm_init(struct gk20a *g, struct vm_gk20a *vm); -void vgpu_vm_remove(struct vm_gk20a *vm); -#endif - -#endif /* NVGPU_VGPU_VM_H */ diff --git a/include/nvgpu/vidmem.h b/include/nvgpu/vidmem.h deleted file mode 100644 index 4470232..0000000 --- a/include/nvgpu/vidmem.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_VIDMEM_H -#define NVGPU_VIDMEM_H - -#include -#include - -struct gk20a; -struct mm_gk20a; -struct nvgpu_mem; - -struct nvgpu_vidmem_buf { - /* - * Must be a pointer since control of this mem is passed over to the - * vidmem background clearing thread when the vidmem buf is freed. - */ - struct nvgpu_mem *mem; - - struct gk20a *g; - - /* - * Filled in by each OS - this holds the necessary data to export this - * buffer to userspace. This will eventually be replaced by a struct - * which shall be defined in the OS specific vidmem.h header file. - */ - void *priv; -}; - -#if defined(CONFIG_GK20A_VIDMEM) - -/** - * nvgpu_vidmem_user_alloc - Allocates a vidmem buffer for userspace - * - * @g - The GPU. - * @bytes - Size of the buffer in bytes. - * - * Allocate a generic (OS agnostic) vidmem buffer. This does not allocate the OS - * specific interfacing for userspace sharing. Instead is is expected that the - * OS specific code will allocate that OS specific data and add it to this - * buffer. - * - * The buffer allocated here is intended to use used by userspace, hence the - * extra struct over nvgpu_mem. If a vidmem buffer is needed by the kernel - * driver only then a simple nvgpu_dma_alloc_vid() or the like is sufficient. - * - * Returns a pointer to a vidmem buffer on success, 0 otherwise. - */ -struct nvgpu_vidmem_buf *nvgpu_vidmem_user_alloc(struct gk20a *g, size_t bytes); - -void nvgpu_vidmem_buf_free(struct gk20a *g, struct nvgpu_vidmem_buf *buf); - -int nvgpu_vidmem_clear_list_enqueue(struct gk20a *g, struct nvgpu_mem *mem); - -bool nvgpu_addr_is_vidmem_page_alloc(u64 addr); -int nvgpu_vidmem_get_space(struct gk20a *g, u64 *space); - -void nvgpu_vidmem_destroy(struct gk20a *g); -int nvgpu_vidmem_init(struct mm_gk20a *mm); - -int nvgpu_vidmem_clear(struct gk20a *g, struct nvgpu_mem *mem); - -void nvgpu_vidmem_thread_pause_sync(struct mm_gk20a *mm); -void nvgpu_vidmem_thread_unpause(struct mm_gk20a *mm); - -#else /* !defined(CONFIG_GK20A_VIDMEM) */ - -/* - * When VIDMEM support is not present this interface is used. - */ - -static inline bool nvgpu_addr_is_vidmem_page_alloc(u64 addr) -{ - return false; -} - -static inline int nvgpu_vidmem_buf_alloc(struct gk20a *g, size_t bytes) -{ - return -ENOSYS; -} - -static inline void nvgpu_vidmem_buf_free(struct gk20a *g, - struct nvgpu_vidmem_buf *buf) -{ -} - -static inline int nvgpu_vidmem_get_space(struct gk20a *g, u64 *space) -{ - return -ENOSYS; -} - -static inline void nvgpu_vidmem_destroy(struct gk20a *g) -{ -} - -static inline int nvgpu_vidmem_init(struct mm_gk20a *mm) -{ - return 0; -} - -static inline int nvgpu_vidmem_clear_all(struct gk20a *g) -{ - return -ENOSYS; -} - -static inline int nvgpu_vidmem_clear(struct gk20a *g, - struct nvgpu_mem *mem) -{ - return -ENOSYS; -} - -static inline void nvgpu_vidmem_thread_pause_sync(struct mm_gk20a *mm) -{ -} - -static inline void nvgpu_vidmem_thread_unpause(struct mm_gk20a *mm) -{ -} - -#endif /* !defined(CONFIG_GK20A_VIDMEM) */ - -/* - * Simple macro for VIDMEM debugging. - */ -#define vidmem_dbg(g, fmt, args...) \ - nvgpu_log(g, gpu_dbg_vidmem, fmt, ##args); \ - -#endif /* NVGPU_VIDMEM_H */ diff --git a/include/nvgpu/vm.h b/include/nvgpu/vm.h deleted file mode 100644 index 3867c74..0000000 --- a/include/nvgpu/vm.h +++ /dev/null @@ -1,330 +0,0 @@ -/* - * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_VM_H -#define NVGPU_VM_H - -#include -#include -#include -#include -#include -#include -#include - -struct vm_gk20a; -struct nvgpu_vm_area; -struct gk20a_comptag_allocator; - -/* - * Defined by each OS. Allows the common VM code do things to the OS specific - * buffer structures. - */ -struct nvgpu_os_buffer; - -#ifdef __KERNEL__ -#include -#elif defined(__NVGPU_POSIX__) -#include -#else -/* QNX include goes here. */ -#include -#endif - -/** - * This header contains the OS agnostic APIs for dealing with VMs. Most of the - * VM implementation is system specific - it must translate from a platform's - * representation of DMA'able memory to our nvgpu_mem notion. - * - * However, some stuff is platform agnostic. VM ref-counting and the VM struct - * itself are platform agnostic. Also, the initialization and destruction of - * VMs is the same across all platforms (for now). - * - * VM Architecture: - * ---------------- - * - * The VM managment in nvgpu is split up as follows: a vm_gk20a struct which - * defines an address space. Each address space is a set of page tables and a - * GPU Virtual Address (GVA) allocator. Any number of channels may bind to a VM. - * - * +----+ +----+ +----+ +-----+ +-----+ - * | C1 | | C2 | ... | Cn | | VM1 | ... | VMn | - * +-+--+ +-+--+ +-+--+ +--+--+ +--+--+ - * | | | | | - * | | +----->-----+ | - * | +---------------->-----+ | - * +------------------------>-----------------+ - * - * Each VM also manages a set of mapped buffers (struct nvgpu_mapped_buf) - * which corresponds to _user space_ buffers which have been mapped into this VM. - * Kernel space mappings (created by nvgpu_gmmu_map()) are not tracked by VMs. - * This may be an architectural bug, but for now it seems to be OK. VMs can be - * closed in various ways - refs counts hitting zero, direct calls to the remove - * routine, etc. Note: this is going to change. VM cleanup is going to be - * homogonized around ref-counts. When a VM is closed all mapped buffers in the - * VM are unmapped from the GMMU. This means that those mappings will no longer - * be valid and any subsequent access by the GPU will fault. That means one must - * ensure the VM is not in use before closing it. - * - * VMs may also contain VM areas (struct nvgpu_vm_area) which are created for - * the purpose of sparse and/or fixed mappings. If userspace wishes to create a - * fixed mapping it must first create a VM area - either with a fixed address or - * not. VM areas are reserved - other mapping operations will not use the space. - * Userspace may then create fixed mappings within that VM area. - */ - -/* map/unmap batch state */ -struct vm_gk20a_mapping_batch { - bool gpu_l2_flushed; - bool need_tlb_invalidate; -}; - -struct nvgpu_mapped_buf { - struct vm_gk20a *vm; - struct nvgpu_vm_area *vm_area; - - struct nvgpu_ref ref; - - struct nvgpu_rbtree_node node; - struct nvgpu_list_node buffer_list; - u64 addr; - u64 size; - - u32 pgsz_idx; - - u32 flags; - u32 kind; - bool va_allocated; - - /* - * Separate from the nvgpu_os_buffer struct to clearly distinguish - * lifetime. A nvgpu_mapped_buf_priv will _always_ be wrapped by a - * struct nvgpu_mapped_buf; however, there are times when a struct - * nvgpu_os_buffer would be separate. This aims to prevent dangerous - * usage of container_of() or the like in OS code. - */ - struct nvgpu_mapped_buf_priv os_priv; -}; - -static inline struct nvgpu_mapped_buf * -nvgpu_mapped_buf_from_buffer_list(struct nvgpu_list_node *node) -{ - return (struct nvgpu_mapped_buf *) - ((uintptr_t)node - offsetof(struct nvgpu_mapped_buf, - buffer_list)); -} - -static inline struct nvgpu_mapped_buf * -mapped_buffer_from_rbtree_node(struct nvgpu_rbtree_node *node) -{ - return (struct nvgpu_mapped_buf *) - ((uintptr_t)node - offsetof(struct nvgpu_mapped_buf, node)); -} - -struct vm_gk20a { - struct mm_gk20a *mm; - struct gk20a_as_share *as_share; /* as_share this represents */ - char name[20]; - - u64 va_start; - u64 va_limit; - - int num_user_mapped_buffers; - - bool big_pages; /* enable large page support */ - bool enable_ctag; - bool guest_managed; /* whether the vm addr space is managed by guest */ - - u32 big_page_size; - - bool userspace_managed; - - const struct gk20a_mmu_level *mmu_levels; - - struct nvgpu_ref ref; - - struct nvgpu_mutex update_gmmu_lock; - - struct nvgpu_gmmu_pd pdb; - - /* - * These structs define the address spaces. In some cases it's possible - * to merge address spaces (user and user_lp) and in other cases it's - * not. vma[] allows the code to be agnostic to this by always using - * address spaces through this pointer array. - */ - struct nvgpu_allocator *vma[GMMU_NR_PAGE_SIZES]; - struct nvgpu_allocator kernel; - struct nvgpu_allocator user; - struct nvgpu_allocator user_lp; - - struct nvgpu_rbtree_node *mapped_buffers; - - struct nvgpu_list_node vm_area_list; - -#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION - u64 handle; -#endif - u32 gmmu_page_sizes[GMMU_NR_PAGE_SIZES]; - - /* if non-NULL, kref_put will use this batch when - unmapping. Must hold vm->update_gmmu_lock. */ - struct vm_gk20a_mapping_batch *kref_put_batch; - - /* - * Each address space needs to have a semaphore pool. - */ - struct nvgpu_semaphore_pool *sema_pool; - - /* - * Create sync point read only map for sync point range. - * Channels sharing same vm will also share same sync point ro map - */ - u64 syncpt_ro_map_gpu_va; - /* Protect allocation of sync point map */ - struct nvgpu_mutex syncpt_ro_map_lock; -}; - -/* - * Mapping flags. - */ -#define NVGPU_VM_MAP_FIXED_OFFSET BIT32(0) -#define NVGPU_VM_MAP_CACHEABLE BIT32(1) -#define NVGPU_VM_MAP_IO_COHERENT BIT32(2) -#define NVGPU_VM_MAP_UNMAPPED_PTE BIT32(3) -#define NVGPU_VM_MAP_DIRECT_KIND_CTRL BIT32(4) -#define NVGPU_VM_MAP_L3_ALLOC BIT32(5) -#define NVGPU_VM_MAP_PLATFORM_ATOMIC BIT32(6) - -#define NVGPU_KIND_INVALID -1 - -void nvgpu_vm_get(struct vm_gk20a *vm); -void nvgpu_vm_put(struct vm_gk20a *vm); - -int vm_aspace_id(struct vm_gk20a *vm); -bool nvgpu_big_pages_possible(struct vm_gk20a *vm, u64 base, u64 size); - -int nvgpu_vm_pde_coverage_bit_count(struct vm_gk20a *vm); - -/* batching eliminates redundant cache flushes and invalidates */ -void nvgpu_vm_mapping_batch_start(struct vm_gk20a_mapping_batch *batch); -void nvgpu_vm_mapping_batch_finish( - struct vm_gk20a *vm, struct vm_gk20a_mapping_batch *batch); -/* called when holding vm->update_gmmu_lock */ -void nvgpu_vm_mapping_batch_finish_locked( - struct vm_gk20a *vm, struct vm_gk20a_mapping_batch *batch); - -/* get reference to all currently mapped buffers */ -int nvgpu_vm_get_buffers(struct vm_gk20a *vm, - struct nvgpu_mapped_buf ***mapped_buffers, - int *num_buffers); -/* put references on the given buffers */ -void nvgpu_vm_put_buffers(struct vm_gk20a *vm, - struct nvgpu_mapped_buf **mapped_buffers, - int num_buffers); - -struct nvgpu_mapped_buf *nvgpu_vm_find_mapping(struct vm_gk20a *vm, - struct nvgpu_os_buffer *os_buf, - u64 map_addr, - u32 flags, - int kind); - -struct nvgpu_mapped_buf *nvgpu_vm_map(struct vm_gk20a *vm, - struct nvgpu_os_buffer *os_buf, - struct nvgpu_sgt *sgt, - u64 map_addr, - u64 map_size, - u64 phys_offset, - int rw, - u32 flags, - s16 compr_kind, - s16 incompr_kind, - struct vm_gk20a_mapping_batch *batch, - enum nvgpu_aperture aperture); - -void nvgpu_vm_unmap(struct vm_gk20a *vm, u64 offset, - struct vm_gk20a_mapping_batch *batch); - -/* - * Implemented by each OS. Called from within the core VM code to handle OS - * specific components of an nvgpu_mapped_buf. - */ -void nvgpu_vm_unmap_system(struct nvgpu_mapped_buf *mapped_buffer); - -/* - * Don't use this outside of the core VM code! - */ -void __nvgpu_vm_unmap_ref(struct nvgpu_ref *ref); - -u64 nvgpu_os_buf_get_size(struct nvgpu_os_buffer *os_buf); - -/* - * These all require the VM update lock to be held. - */ -struct nvgpu_mapped_buf *__nvgpu_vm_find_mapped_buf( - struct vm_gk20a *vm, u64 addr); -struct nvgpu_mapped_buf *__nvgpu_vm_find_mapped_buf_range( - struct vm_gk20a *vm, u64 addr); -struct nvgpu_mapped_buf *__nvgpu_vm_find_mapped_buf_less_than( - struct vm_gk20a *vm, u64 addr); - -int nvgpu_insert_mapped_buf(struct vm_gk20a *vm, - struct nvgpu_mapped_buf *mapped_buffer); -void nvgpu_remove_mapped_buf(struct vm_gk20a *vm, - struct nvgpu_mapped_buf *mapped_buffer); - -/* - * Initialize a preallocated vm - */ -int __nvgpu_vm_init(struct mm_gk20a *mm, - struct vm_gk20a *vm, - u32 big_page_size, - u64 low_hole, - u64 kernel_reserved, - u64 aperture_size, - bool big_pages, - bool userspace_managed, - char *name); - -struct vm_gk20a *nvgpu_vm_init(struct gk20a *g, - u32 big_page_size, - u64 low_hole, - u64 kernel_reserved, - u64 aperture_size, - bool big_pages, - bool userspace_managed, - char *name); - -/* - * These are private to the VM code but are unfortunately used by the vgpu code. - * It appears to be used for an optimization in reducing the number of server - * requests to the vgpu server. Basically the vgpu implementation of - * map_global_ctx_buffers() sends a bunch of VA ranges over to the RM server. - * Ideally the RM server can just batch mappings but until such a time this - * will be used by the vgpu code. - */ -u64 __nvgpu_vm_alloc_va(struct vm_gk20a *vm, u64 size, - u32 pgsz_idx); -int __nvgpu_vm_free_va(struct vm_gk20a *vm, u64 addr, - u32 pgsz_idx); - -#endif /* NVGPU_VM_H */ diff --git a/include/nvgpu/vm_area.h b/include/nvgpu/vm_area.h deleted file mode 100644 index 8778e42..0000000 --- a/include/nvgpu/vm_area.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_VM_AREA_H -#define NVGPU_VM_AREA_H - -#include -#include - -struct vm_gk20a; -struct gk20a_as_share; -struct nvgpu_as_alloc_space_args; -struct nvgpu_as_free_space_args; - -struct nvgpu_vm_area { - /* - * Entry into the list of VM areas owned by a VM. - */ - struct nvgpu_list_node vm_area_list; - - /* - * List of buffers mapped into this vm_area. - */ - struct nvgpu_list_node buffer_list_head; - - u32 flags; - u32 pgsz_idx; - u64 addr; - u64 size; - bool sparse; -}; - -static inline struct nvgpu_vm_area * -nvgpu_vm_area_from_vm_area_list(struct nvgpu_list_node *node) -{ - return (struct nvgpu_vm_area *) - ((uintptr_t)node - offsetof(struct nvgpu_vm_area, - vm_area_list)); -}; - -/* - * Alloc space flags. - */ -#define NVGPU_VM_AREA_ALLOC_FIXED_OFFSET BIT(0) -#define NVGPU_VM_AREA_ALLOC_SPARSE BIT(1) - -int nvgpu_vm_area_alloc(struct vm_gk20a *vm, u32 pages, u32 page_size, - u64 *addr, u32 flags); -int nvgpu_vm_area_free(struct vm_gk20a *vm, u64 addr); - -struct nvgpu_vm_area *nvgpu_vm_area_find(struct vm_gk20a *vm, u64 addr); -int nvgpu_vm_area_validate_buffer(struct vm_gk20a *vm, - u64 map_offset, u64 map_size, u32 pgsz_idx, - struct nvgpu_vm_area **pvm_area); - -#endif /* NVGPU_VM_AREA_H */ diff --git a/include/nvgpu/vpr.h b/include/nvgpu/vpr.h deleted file mode 100644 index ae0ac1b..0000000 --- a/include/nvgpu/vpr.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_VPR_H -#define NVGPU_VPR_H - -#include - -bool nvgpu_is_vpr_resize_enabled(void); - -#endif /* NVGPU_VPR_H */ diff --git a/include/nvgpu/xve.h b/include/nvgpu/xve.h deleted file mode 100644 index 2d0d698..0000000 --- a/include/nvgpu/xve.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_XVE_H -#define NVGPU_XVE_H - -#include -#include - -/* - * For the available speeds bitmap. - */ -#define GPU_XVE_SPEED_2P5 (1 << 0) -#define GPU_XVE_SPEED_5P0 (1 << 1) -#define GPU_XVE_SPEED_8P0 (1 << 2) -#define GPU_XVE_NR_SPEEDS 3 - -#define GPU_XVE_SPEED_MASK (GPU_XVE_SPEED_2P5 | \ - GPU_XVE_SPEED_5P0 | \ - GPU_XVE_SPEED_8P0) - -/* - * The HW uses a 2 bit field where speed is defined by a number: - * - * NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED_2P5 = 1 - * NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED_5P0 = 2 - * NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED_8P0 = 3 - * - * This isn't ideal for a bitmap with available speeds. So the external - * APIs think about speeds as a bit in a bitmap and this function converts - * from those bits to the actual HW speed setting. - * - * @speed_bit must have only 1 bit set and must be one of the 3 available - * HW speeds. Not all chips support all speeds so use available_speeds() to - * determine what a given chip supports. - */ -static inline const char *xve_speed_to_str(u32 speed) -{ - if (!speed || !is_power_of_2(speed) || - !(speed & GPU_XVE_SPEED_MASK)) { - return "Unknown ???"; - } - - return speed & GPU_XVE_SPEED_2P5 ? "Gen1" : - speed & GPU_XVE_SPEED_5P0 ? "Gen2" : - speed & GPU_XVE_SPEED_8P0 ? "Gen3" : - "Unknown ???"; -} - -#endif /* NVGPU_XVE_H */ -- cgit v1.2.2