From 01e6fac4d61fdd7fff5433942ec93fc2ea1e4df1 Mon Sep 17 00:00:00 2001 From: Joshua Bakita Date: Wed, 28 Jun 2023 18:24:25 -0400 Subject: Include nvgpu headers These are needed to build on NVIDIA's Jetson boards for the time being. Only a couple structs are required, so it should be fairly easy to remove this dependency at some point in the future. --- include/nvgpu/posix/atomic.h | 191 ++++++++++++++++++++++++++++++++++ include/nvgpu/posix/barrier.h | 44 ++++++++ include/nvgpu/posix/bitops.h | 95 +++++++++++++++++ include/nvgpu/posix/bug.h | 56 ++++++++++ include/nvgpu/posix/circ_buf.h | 44 ++++++++ include/nvgpu/posix/cond.h | 59 +++++++++++ include/nvgpu/posix/io.h | 114 +++++++++++++++++++++ include/nvgpu/posix/kmem.h | 36 +++++++ include/nvgpu/posix/lock.h | 69 +++++++++++++ include/nvgpu/posix/log2.h | 37 +++++++ include/nvgpu/posix/nvgpu_mem.h | 32 ++++++ include/nvgpu/posix/nvlink.h | 24 +++++ include/nvgpu/posix/pci.h | 28 +++++ include/nvgpu/posix/probe.h | 31 ++++++ include/nvgpu/posix/rwsem.h | 35 +++++++ include/nvgpu/posix/sizes.h | 38 +++++++ include/nvgpu/posix/sort.h | 35 +++++++ include/nvgpu/posix/thread.h | 51 ++++++++++ include/nvgpu/posix/types.h | 221 ++++++++++++++++++++++++++++++++++++++++ include/nvgpu/posix/vm.h | 41 ++++++++ 20 files changed, 1281 insertions(+) create mode 100644 include/nvgpu/posix/atomic.h create mode 100644 include/nvgpu/posix/barrier.h create mode 100644 include/nvgpu/posix/bitops.h create mode 100644 include/nvgpu/posix/bug.h create mode 100644 include/nvgpu/posix/circ_buf.h create mode 100644 include/nvgpu/posix/cond.h create mode 100644 include/nvgpu/posix/io.h create mode 100644 include/nvgpu/posix/kmem.h create mode 100644 include/nvgpu/posix/lock.h create mode 100644 include/nvgpu/posix/log2.h create mode 100644 include/nvgpu/posix/nvgpu_mem.h create mode 100644 include/nvgpu/posix/nvlink.h create mode 100644 include/nvgpu/posix/pci.h create mode 100644 include/nvgpu/posix/probe.h create mode 100644 include/nvgpu/posix/rwsem.h create mode 100644 include/nvgpu/posix/sizes.h create mode 100644 include/nvgpu/posix/sort.h create mode 100644 include/nvgpu/posix/thread.h create mode 100644 include/nvgpu/posix/types.h create mode 100644 include/nvgpu/posix/vm.h (limited to 'include/nvgpu/posix') diff --git a/include/nvgpu/posix/atomic.h b/include/nvgpu/posix/atomic.h new file mode 100644 index 0000000..c9d9212 --- /dev/null +++ b/include/nvgpu/posix/atomic.h @@ -0,0 +1,191 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVGPU_POSIX_ATOMIC_H__ +#define __NVGPU_POSIX_ATOMIC_H__ + +#include + +/* + * Note: this code uses the GCC builtins to implement atomics. + */ + +#define __atomic_cmpxchg(p, v, c) __sync_val_compare_and_swap(p, v, c) +#define __atomic_and(p, v) __sync_fetch_and_and(p, v) +#define __atomic_or(p, v) __sync_fetch_and_or(p, v) + +#define cmpxchg __atomic_cmpxchg + +/* + * Place holders until real atomics can be implemented... Yay for GCC builtins! + * We can use those eventually to define all the Linux atomic ops. + * + * TODO: make these _actually_ atomic! + */ +typedef struct __nvgpu_posix_atomic { + int v; +} nvgpu_atomic_t; + +typedef struct __nvgpu_posix_atomic64 { + long v; +} nvgpu_atomic64_t; + +#define __nvgpu_atomic_init(i) { i } +#define __nvgpu_atomic64_init(i) { i } + +static inline void __nvgpu_atomic_set(nvgpu_atomic_t *v, int i) +{ + v->v = i; +} + +static inline int __nvgpu_atomic_read(nvgpu_atomic_t *v) +{ + return v->v; +} + +static inline void __nvgpu_atomic_inc(nvgpu_atomic_t *v) +{ + v->v++; +} + +static inline int __nvgpu_atomic_inc_return(nvgpu_atomic_t *v) +{ + v->v++; + return v->v; +} + +static inline void __nvgpu_atomic_dec(nvgpu_atomic_t *v) +{ + v->v--; +} + +static inline int __nvgpu_atomic_dec_return(nvgpu_atomic_t *v) +{ + v->v--; + return v->v; +} + +static inline int __nvgpu_atomic_cmpxchg(nvgpu_atomic_t *v, int old, int new) +{ + if (v->v == old) + v->v = new; + + return v->v; +} + +static inline int __nvgpu_atomic_xchg(nvgpu_atomic_t *v, int new) +{ + v->v = new; + return new; +} + +static inline bool __nvgpu_atomic_inc_and_test(nvgpu_atomic_t *v) +{ + v->v++; + return v->v ? true : false; +} + +static inline bool __nvgpu_atomic_dec_and_test(nvgpu_atomic_t *v) +{ + v->v--; + return v->v ? true : false; +} + +static inline bool __nvgpu_atomic_sub_and_test(int i, nvgpu_atomic_t *v) +{ + v->v -= i; + return v->v ? true : false; +} + +static inline int __nvgpu_atomic_add_return(int i, nvgpu_atomic_t *v) +{ + v->v += i; + return v->v; +} + +static inline int __nvgpu_atomic_add_unless(nvgpu_atomic_t *v, int a, int u) +{ + if (v->v != u) + v->v += a; + + return v->v; +} + +static inline void __nvgpu_atomic64_set(nvgpu_atomic64_t *v, long i) +{ + v->v = i; +} + +static inline long __nvgpu_atomic64_read(nvgpu_atomic64_t *v) +{ + return v->v; +} + +static inline void __nvgpu_atomic64_add(long x, nvgpu_atomic64_t *v) +{ + v->v += x; +} + +static inline void __nvgpu_atomic64_inc(nvgpu_atomic64_t *v) +{ + v->v++; +} + +static inline long __nvgpu_atomic64_inc_return(nvgpu_atomic64_t *v) +{ + v->v++; + return v->v; +} + +static inline void __nvgpu_atomic64_dec(nvgpu_atomic64_t *v) +{ + v->v--; +} + +static inline long __nvgpu_atomic64_dec_return(nvgpu_atomic64_t *v) +{ + v->v--; + return v->v; +} + +static inline long __nvgpu_atomic64_cmpxchg(nvgpu_atomic64_t *v, + long old, long new) +{ + + if (v->v == old) + v->v = new; + + return v->v; +} + +static inline void __nvgpu_atomic64_sub(long x, nvgpu_atomic64_t *v) +{ + v->v -= x; +} + +static inline long __nvgpu_atomic64_sub_return(long x, nvgpu_atomic64_t *v) +{ + v->v -= x; + return v->v; +} + +#endif diff --git a/include/nvgpu/posix/barrier.h b/include/nvgpu/posix/barrier.h new file mode 100644 index 0000000..edc7b12 --- /dev/null +++ b/include/nvgpu/posix/barrier.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVGPU_POSIX_BARRIER_H__ +#define __NVGPU_POSIX_BARRIER_H__ + +#define ACCESS_ONCE(x) (*(volatile __typeof__(x) *)&x) + +/* + * TODO: implement all these! + */ +#define __nvgpu_mb() +#define __nvgpu_rmb() +#define __nvgpu_wmb() + +#define __nvgpu_smp_mb() +#define __nvgpu_smp_rmb() +#define __nvgpu_smp_wmb() + +#define __nvgpu_read_barrier_depends() +#define __nvgpu_smp_read_barrier_depends() + +#define __NV_ACCESS_ONCE(x) ACCESS_ONCE(x) + +#endif diff --git a/include/nvgpu/posix/bitops.h b/include/nvgpu/posix/bitops.h new file mode 100644 index 0000000..e8c663b --- /dev/null +++ b/include/nvgpu/posix/bitops.h @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVGPU_POSIX_BITOPS_H__ +#define __NVGPU_POSIX_BITOPS_H__ + +#include + +/* + * Assume an 8 bit byte, of course. + */ +#define BITS_PER_BYTE 8UL +#define BITS_PER_LONG (__SIZEOF_LONG__ * BITS_PER_BYTE) +#define BITS_TO_LONGS(bits) \ + (bits + (BITS_PER_LONG - 1) / BITS_PER_LONG) + +/* + * Deprecated; use the explicit BITxx() macros instead. + */ +#define BIT(i) BIT64(i) + +#define GENMASK(h, l) \ + (((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) + +#define DECLARE_BITMAP(bmap, bits) \ + unsigned long bmap[BITS_TO_LONGS(bits)] + +#define for_each_set_bit(bit, addr, size) \ + for ((bit) = find_first_bit((addr), (size)); \ + (bit) < (size); \ + (bit) = find_next_bit((addr), (size), (bit) + 1)) + +#define ffs(word) __ffs(word) +#define ffz(word) __ffs(~(word)) +#define fls(word) __fls(word) + +/* + * Clashes with symbols in libc it seems. + */ +#define __ffs(word) __nvgpu_posix_ffs(word) +#define __fls(word) __nvgpu_posix_fls(word) + +unsigned long __nvgpu_posix_ffs(unsigned long word); +unsigned long __nvgpu_posix_fls(unsigned long word); + +unsigned long find_first_bit(const unsigned long *addr, unsigned long size); +unsigned long find_next_bit(const unsigned long *addr, unsigned long size, + unsigned long offset); +unsigned long find_first_zero_bit(const unsigned long *addr, + unsigned long size); + +bool test_bit(int nr, const volatile unsigned long *addr); +bool test_and_set_bit(int nr, volatile unsigned long *addr); +bool test_and_clear_bit(int nr, volatile unsigned long *addr); + +/* + * These two are atomic. + */ +void set_bit(int nr, volatile unsigned long *addr); +void clear_bit(int nr, volatile unsigned long *addr); + +void bitmap_set(unsigned long *map, unsigned int start, int len); +void bitmap_clear(unsigned long *map, unsigned int start, int len); +unsigned long bitmap_find_next_zero_area_off(unsigned long *map, + unsigned long size, + unsigned long start, + unsigned int nr, + unsigned long align_mask, + unsigned long align_offset); +unsigned long bitmap_find_next_zero_area(unsigned long *map, + unsigned long size, + unsigned long start, + unsigned int nr, + unsigned long align_mask); + +#endif diff --git a/include/nvgpu/posix/bug.h b/include/nvgpu/posix/bug.h new file mode 100644 index 0000000..04389a9 --- /dev/null +++ b/include/nvgpu/posix/bug.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVGPU_POSIX_BUG_H__ +#define __NVGPU_POSIX_BUG_H__ + +#include + +/* + * TODO: make these actually useful! + */ + +#define BUG() __bug("") +#define BUG_ON(cond) \ + do { \ + if (cond) \ + BUG(); \ + } while (0) + +#define WARN(cond, msg, arg...) __warn(cond, msg, ##arg) +#define WARN_ON(cond) __warn(cond, "") + +#define WARN_ONCE(cond, msg, arg...) \ + ({static int __warned__ = 0; \ + if (!__warned__) { \ + WARN(cond, msg, ##arg); \ + __warned__ = 1; \ + } \ + cond; }) + + +void dump_stack(void); + +void __bug(const char *fmt, ...) __attribute__ ((noreturn)); +bool __warn(bool cond, const char *fmt, ...); + +#endif diff --git a/include/nvgpu/posix/circ_buf.h b/include/nvgpu/posix/circ_buf.h new file mode 100644 index 0000000..8d9b5ea --- /dev/null +++ b/include/nvgpu/posix/circ_buf.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVGPU_POSIX_CIRC_BUF_H__ +#define __NVGPU_POSIX_CIRC_BUF_H__ + +#include + +/* TODO: implement. */ + +#define CIRC_CNT(head, tail, size) \ + ({(void)head; \ + (void)tail; \ + (void)size; \ + BUG(); \ + 1; }) + +#define CIRC_SPACE(head, tail, size) \ + ({(void)head; \ + (void)tail; \ + (void)size; \ + BUG(); \ + 1; }) + +#endif diff --git a/include/nvgpu/posix/cond.h b/include/nvgpu/posix/cond.h new file mode 100644 index 0000000..3528388 --- /dev/null +++ b/include/nvgpu/posix/cond.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVGPU_POSIX_COND_H__ +#define __NVGPU_POSIX_COND_H__ + +#include + +struct nvgpu_cond { + /* Place holder until this can be properly implemented. */ +}; + +/** + * NVGPU_COND_WAIT - Wait for a condition to be true + * + * @c - The condition variable to sleep on + * @condition - The condition that needs to be true + * @timeout_ms - Timeout in milliseconds, or 0 for infinite wait + * + * Wait for a condition to become true. Returns -ETIMEOUT if + * the wait timed out with condition false. + */ +#define NVGPU_COND_WAIT(c, condition, timeout_ms) \ + ({BUG(); 1; }) + +/** + * NVGPU_COND_WAIT_INTERRUPTIBLE - Wait for a condition to be true + * + * @c - The condition variable to sleep on + * @condition - The condition that needs to be true + * @timeout_ms - Timeout in milliseconds, or 0 for infinite wait + * + * Wait for a condition to become true. Returns -ETIMEOUT if + * the wait timed out with condition false or -ERESTARTSYS on + * signal. + */ +#define NVGPU_COND_WAIT_INTERRUPTIBLE(c, condition, timeout_ms) \ + ({BUG(); 1; }) + +#endif diff --git a/include/nvgpu/posix/io.h b/include/nvgpu/posix/io.h new file mode 100644 index 0000000..98be4d0 --- /dev/null +++ b/include/nvgpu/posix/io.h @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_POSIX_IO_H +#define NVGPU_POSIX_IO_H + +#include +#include + +struct gk20a; + +/** + * Here lies the interface for a unit test module to interact with the nvgpu IO + * accessors. This interface provides the ability for a module to react to nvgpu + * calling nvgpu IO accessors so that nvgpu can handle various HW sequences even + * when run in unit testing mode. + * + * The primary interface is simply callbacks to the unit test module which the + * module can handle how ever it wishes. + */ + +struct nvgpu_reg_access { + /* + * Address of the register write relative to the base of the register + * space. I.e you can compare this against values in the HW headers + * directly to check what register is being read/written to/from. + */ + u32 addr; + + /* + * Writes: this is the value being written. + * Reads: populate with the value to return. + */ + u32 value; +}; + +struct nvgpu_posix_io_callbacks { + void (*writel)(struct gk20a *g, struct nvgpu_reg_access *access); + void (*writel_check)(struct gk20a *g, struct nvgpu_reg_access *access); + void (*__readl)(struct gk20a *g, struct nvgpu_reg_access *access); + void (*readl)(struct gk20a *g, struct nvgpu_reg_access *access); + void (*bar1_writel)(struct gk20a *g, struct nvgpu_reg_access *access); + void (*bar1_readl)(struct gk20a *g, struct nvgpu_reg_access *access); + void (*usermode_writel)(struct gk20a *g, + struct nvgpu_reg_access *access); +}; + +struct nvgpu_posix_io_callbacks *nvgpu_posix_register_io( + struct gk20a *g, + struct nvgpu_posix_io_callbacks *io_callbacks); + +struct nvgpu_posix_io_reg_space { + u32 base; + u32 size; + u32 *data; + struct nvgpu_list_node link; +}; + +static inline struct nvgpu_posix_io_reg_space * +nvgpu_posix_io_reg_space_from_link(struct nvgpu_list_node *node) +{ + return (struct nvgpu_posix_io_reg_space *) + ((uintptr_t)node - offsetof(struct nvgpu_posix_io_reg_space, link)); +}; + +void nvgpu_posix_io_init_reg_space(struct gk20a *g); +int nvgpu_posix_io_get_error_code(struct gk20a *g); +void nvgpu_posix_io_reset_error_code(struct gk20a *g); +int nvgpu_posix_io_add_reg_space(struct gk20a *g, u32 base, u32 size); +struct nvgpu_posix_io_reg_space *nvgpu_posix_io_get_reg_space(struct gk20a *g, + u32 addr); +void nvgpu_posix_io_delete_reg_space(struct gk20a *g, u32 base); +void nvgpu_posix_io_writel_reg_space(struct gk20a *g, u32 addr, u32 data); +u32 nvgpu_posix_io_readl_reg_space(struct gk20a *g, u32 addr); + +struct nvgpu_posix_io_reg_access { + struct nvgpu_reg_access access; + struct nvgpu_list_node link; +}; + +static inline struct nvgpu_posix_io_reg_access * +nvgpu_posix_io_reg_access_from_link(struct nvgpu_list_node *node) +{ + return (struct nvgpu_posix_io_reg_access *) + ((uintptr_t)node - offsetof(struct nvgpu_posix_io_reg_access, link)); +}; + +void nvgpu_posix_io_start_recorder(struct gk20a *g); +void nvgpu_posix_io_reset_recorder(struct gk20a *g); +void nvgpu_posix_io_record_access(struct gk20a *g, + struct nvgpu_reg_access *access); +bool nvgpu_posix_io_check_sequence(struct gk20a *g, + struct nvgpu_reg_access *sequence, u32 size, bool strict); + +#endif diff --git a/include/nvgpu/posix/kmem.h b/include/nvgpu/posix/kmem.h new file mode 100644 index 0000000..efcdd3d --- /dev/null +++ b/include/nvgpu/posix/kmem.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVGPU_POSIX_KMEM_H__ +#define __NVGPU_POSIX_KMEM_H__ + +#include + +void *__nvgpu_kmalloc(struct gk20a *g, size_t size, void *ip); +void *__nvgpu_kzalloc(struct gk20a *g, size_t size, void *ip); +void *__nvgpu_kcalloc(struct gk20a *g, size_t n, size_t size, void *ip); +void *__nvgpu_vmalloc(struct gk20a *g, unsigned long size, void *ip); +void *__nvgpu_vzalloc(struct gk20a *g, unsigned long size, void *ip); +void __nvgpu_kfree(struct gk20a *g, void *addr); +void __nvgpu_vfree(struct gk20a *g, void *addr); + +#endif diff --git a/include/nvgpu/posix/lock.h b/include/nvgpu/posix/lock.h new file mode 100644 index 0000000..82eddd0 --- /dev/null +++ b/include/nvgpu/posix/lock.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVGPU_POSIX_LOCK_H__ +#define __NVGPU_POSIX_LOCK_H__ + +#include + +#include + +/* + * All locks for posix nvgpu are just pthread locks. There's not a lot of reason + * to have real spinlocks in userspace since we aren't using real HW or running + * perf critical code where a sleep could be devestating. + * + * This could be revisited later, though. + */ +struct __nvgpu_posix_lock { + pthread_mutex_t mutex; +}; + +static inline void __nvgpu_posix_lock_acquire(struct __nvgpu_posix_lock *lock) +{ + pthread_mutex_lock(&lock->mutex); +} + +static inline int __nvgpu_posix_lock_try_acquire( + struct __nvgpu_posix_lock *lock) +{ + return pthread_mutex_trylock(&lock->mutex); +} + +static inline void __nvgpu_posix_lock_release(struct __nvgpu_posix_lock *lock) +{ + pthread_mutex_unlock(&lock->mutex); +} + +struct nvgpu_mutex { + struct __nvgpu_posix_lock lock; +}; + +struct nvgpu_spinlock { + struct __nvgpu_posix_lock lock; +}; + +struct nvgpu_raw_spinlock { + struct __nvgpu_posix_lock lock; +}; + +#endif /* NVGPU_LOCK_LINUX_H */ diff --git a/include/nvgpu/posix/log2.h b/include/nvgpu/posix/log2.h new file mode 100644 index 0000000..ca95c10 --- /dev/null +++ b/include/nvgpu/posix/log2.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVGPU_POSIX_LOG2_H__ +#define __NVGPU_POSIX_LOG2_H__ + +#define ilog2(x) (fls(x) - 1) + +#define roundup_pow_of_two(x) (1UL << fls((x) - 1)) +#define rounddown_pow_of_two(x) (1UL << (fls(x) - 1)) + +#define is_power_of_2(x) \ + ({ \ + typeof(x) __x__ = (x); \ + (__x__ != 0 && ((__x__ & (__x__ - 1)) == 0)); \ + }) + +#endif diff --git a/include/nvgpu/posix/nvgpu_mem.h b/include/nvgpu/posix/nvgpu_mem.h new file mode 100644 index 0000000..30cdf60 --- /dev/null +++ b/include/nvgpu/posix/nvgpu_mem.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVGPU_POSIX_NVGPU_MEM_H__ +#define __NVGPU_POSIX_NVGPU_MEM_H__ + +struct nvgpu_mem_priv { + /* + * Eventually this will require an implementation using nvmap. + */ +}; + +#endif diff --git a/include/nvgpu/posix/nvlink.h b/include/nvgpu/posix/nvlink.h new file mode 100644 index 0000000..99cf837 --- /dev/null +++ b/include/nvgpu/posix/nvlink.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __NVGPU_POSIX_NVLINK_H__ +#define __NVGPU_POSIX_NVLINK_H__ + +/* + * Empty... + */ + +#endif diff --git a/include/nvgpu/posix/pci.h b/include/nvgpu/posix/pci.h new file mode 100644 index 0000000..cd9fc14 --- /dev/null +++ b/include/nvgpu/posix/pci.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVGPU_POSIX_PCI_H__ +#define __NVGPU_POSIX_PCI_H__ + +#define PCI_VENDOR_ID_NVIDIA 0x10de + +#endif diff --git a/include/nvgpu/posix/probe.h b/include/nvgpu/posix/probe.h new file mode 100644 index 0000000..a9763aa --- /dev/null +++ b/include/nvgpu/posix/probe.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVGPU_POSIX_PROBE_H__ +#define __NVGPU_POSIX_PROBE_H__ + +struct gk20a; + +struct gk20a *nvgpu_posix_probe(void); +void nvgpu_posix_cleanup(struct gk20a *g); + +#endif diff --git a/include/nvgpu/posix/rwsem.h b/include/nvgpu/posix/rwsem.h new file mode 100644 index 0000000..65aa931 --- /dev/null +++ b/include/nvgpu/posix/rwsem.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVGPU_POSIX_RWSEM_H__ +#define __NVGPU_POSIX_RWSEM_H__ + +#include + +struct nvgpu_rwsem { + struct nvgpu_spinlock lock; + + int readers; + int writers; +}; + +#endif diff --git a/include/nvgpu/posix/sizes.h b/include/nvgpu/posix/sizes.h new file mode 100644 index 0000000..3fda757 --- /dev/null +++ b/include/nvgpu/posix/sizes.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVGPU_POSIX_SIZES_H__ +#define __NVGPU_POSIX_SIZES_H__ + +#define SZ_1K (1UL << 10) +#define SZ_4K (SZ_1K << 2) +#define SZ_64K (SZ_1K << 6) +#define SZ_128K (SZ_1K << 7) + +#define SZ_1M (1UL << 20) +#define SZ_16M (SZ_1M << 4) +#define SZ_256M (SZ_1M << 8) + +#define SZ_1G (1UL << 30) +#define SZ_4G (SZ_1G << 2) + +#endif diff --git a/include/nvgpu/posix/sort.h b/include/nvgpu/posix/sort.h new file mode 100644 index 0000000..6a6920e --- /dev/null +++ b/include/nvgpu/posix/sort.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVGPU_POSIX_SORT_H__ +#define __NVGPU_POSIX_SORT_H__ + +#include + +static void sort(void *base, size_t num, size_t size, + int (*cmp)(const void *, const void *), + void (*swap)(void *, void *, int)) +{ + __bug("sort() not implemented yet!"); +} + +#endif diff --git a/include/nvgpu/posix/thread.h b/include/nvgpu/posix/thread.h new file mode 100644 index 0000000..a312cc1 --- /dev/null +++ b/include/nvgpu/posix/thread.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVGPU_POSIX_THREAD_H__ +#define __NVGPU_POSIX_THREAD_H__ + +#include + +#include + +/* + * Handles passing an nvgpu thread function into a posix thread. + */ +struct nvgpu_posix_thread_data { + int (*fn)(void *data); + void *data; +}; + +/* + * For some reason POSIX only allows 16 bytes of name length. + */ +#define NVGPU_THREAD_POSIX_MAX_NAMELEN 16 + +struct nvgpu_thread { + bool running; + bool should_stop; + pthread_t thread; + struct nvgpu_posix_thread_data nvgpu; + char tname[16]; +}; + +#endif diff --git a/include/nvgpu/posix/types.h b/include/nvgpu/posix/types.h new file mode 100644 index 0000000..12078b9 --- /dev/null +++ b/include/nvgpu/posix/types.h @@ -0,0 +1,221 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVGPU_POSIX_TYPES_H__ +#define __NVGPU_POSIX_TYPES_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * For endianness functions. + */ +#include + +typedef unsigned char u8; +typedef unsigned short u16; +typedef unsigned int u32; +typedef unsigned long long u64; + +typedef signed char s8; +typedef signed short s16; +typedef signed int s32; +typedef signed long long s64; + +#define min_t(type, a, b) \ + ({ \ + type __a = (a); \ + type __b = (b); \ + __a < __b ? __a : __b; \ + }) + +#if defined(min) +#undef min +#endif +#if defined(max) +#undef max +#endif + +#define min(a, b) \ + ({ \ + (a) < (b) ? a : b; \ + }) +#define max(a, b) \ + ({ \ + (a) > (b) ? a : b; \ + }) +#define min3(a, b, c) min(min(a, b), c) + +#define PAGE_SIZE 4096U + +#define ARRAY_SIZE(array) \ + (sizeof(array) / sizeof((array)[0])) + +#define MAX_SCHEDULE_TIMEOUT LONG_MAX + +#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) + +/* + * Only used in clk_gm20b.c which we will never unit test. Don't use! + */ +#define DIV_ROUND_CLOSEST(x, divisor) ({BUG(); 0; }) + +/* + * Joys of userspace: usually division just works since the compiler can link + * against external division functions implicitly. + */ +#define do_div(a, b) ((a) /= (b)) +#define div64_u64(a, b) ((a) / (b)) + +#define __round_mask(x, y) ((__typeof__(x))((y) - 1)) +#define round_up(x, y) ((((x) - 1) | __round_mask(x, y)) + 1) +#define roundup(x, y) round_up(x, y) +#define round_down(x, y) ((x) & ~__round_mask(x, y)) + +#define ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask)) +#define ALIGN(x, a) ALIGN_MASK(x, (typeof(x))(a) - 1) +#define PAGE_ALIGN(x) ALIGN(x, PAGE_SIZE) + +/* + * Caps return at the size of the buffer not what would have been written if buf + * were arbitrarily sized. + */ +static inline int scnprintf(char *buf, size_t size, const char *format, ...) +{ + size_t ret; + va_list args; + + va_start(args, format); + ret = vsnprintf(buf, size, format, args); + va_end(args); + + return ret <= size ? ret : size; +} + +static inline u32 be32_to_cpu(u32 x) +{ + /* + * Conveniently big-endian happens to be network byte order as well so + * we can use ntohl() for this. + */ + return ntohl(x); +} + +/* + * Hamming weights. + */ +static inline unsigned long __hweight8(uint8_t x) +{ + return (unsigned long)(!!(x & (1 << 0)) + + !!(x & (1 << 1)) + + !!(x & (1 << 2)) + + !!(x & (1 << 3)) + + !!(x & (1 << 4)) + + !!(x & (1 << 5)) + + !!(x & (1 << 6)) + + !!(x & (1 << 7))); +} + +static inline unsigned long __hweight16(uint16_t x) +{ + return __hweight8((uint8_t)x) + + __hweight8((uint8_t)((x & 0xff00) >> 8)); +} + +static inline unsigned long __hweight32(uint32_t x) +{ + return __hweight16((uint16_t)x) + + __hweight16((uint16_t)((x & 0xffff0000) >> 16)); +} + +static inline unsigned long __hweight64(uint64_t x) +{ + return __hweight32((uint32_t)x) + + __hweight32((uint32_t)((x & 0xffffffff00000000) >> 32)); +} + +#define hweight32 __hweight32 +#define hweight_long __hweight64 + +/* + * Better suited under a compiler.h type header file, but for now these can live + * here. + */ +#define __must_check +#define __maybe_unused __attribute__((unused)) +#define __iomem +#define __user +#define unlikely +#define likely + +#define __stringify(x) #x + +/* + * Prevent compiler optimizations from mangling writes. But likely most uses of + * this in nvgpu are incorrect (i.e unnecessary). + */ +#define WRITE_ONCE(p, v) \ + ({ \ + volatile typeof(p) *__p__ = &(p); \ + *__p__ = v; \ + }) + +#define container_of(ptr, type, member) ({ \ + const typeof( ((type *)0)->member ) *__mptr = (ptr); \ + (type *)( (char *)__mptr - offsetof(type,member) );}) + +#define __packed __attribute__((packed)) + +#define IS_ENABLED(config) 0 + +#define MAX_ERRNO 4095 + +#define IS_ERR_VALUE(x) ((x) >= (unsigned long)-MAX_ERRNO) + +static inline void *ERR_PTR(long error) +{ + return (void *) error; +} + +static inline long PTR_ERR(void *error) +{ + return (long)(uintptr_t)error; +} + +static inline bool IS_ERR(const void *ptr) +{ + return IS_ERR_VALUE((unsigned long)ptr); +} + +static inline bool IS_ERR_OR_NULL(const void *ptr) +{ + return (ptr == NULL) || IS_ERR_VALUE((unsigned long)ptr); +} + +#endif diff --git a/include/nvgpu/posix/vm.h b/include/nvgpu/posix/vm.h new file mode 100644 index 0000000..ae997d3 --- /dev/null +++ b/include/nvgpu/posix/vm.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVGPU_POSIX_VM_H__ +#define __NVGPU_POSIX_VM_H__ + +#include + +struct nvgpu_os_buffer { + /* + * We just use malloc() buffers in userspace. + */ + void *buf; + size_t size; +}; + +struct nvgpu_mapped_buf_priv { + void *buf; + size_t size; +}; + +#endif -- cgit v1.2.2