From 01e6fac4d61fdd7fff5433942ec93fc2ea1e4df1 Mon Sep 17 00:00:00 2001 From: Joshua Bakita Date: Wed, 28 Jun 2023 18:24:25 -0400 Subject: Include nvgpu headers These are needed to build on NVIDIA's Jetson boards for the time being. Only a couple structs are required, so it should be fairly easy to remove this dependency at some point in the future. --- include/nvgpu/hw/gp106/hw_bus_gp106.h | 223 ++ include/nvgpu/hw/gp106/hw_ccsr_gp106.h | 163 + include/nvgpu/hw/gp106/hw_ce_gp106.h | 87 + include/nvgpu/hw/gp106/hw_ctxsw_prog_gp106.h | 295 ++ include/nvgpu/hw/gp106/hw_falcon_gp106.h | 603 +++ include/nvgpu/hw/gp106/hw_fb_gp106.h | 563 +++ include/nvgpu/hw/gp106/hw_fbpa_gp106.h | 67 + include/nvgpu/hw/gp106/hw_fifo_gp106.h | 695 ++++ include/nvgpu/hw/gp106/hw_flush_gp106.h | 187 + include/nvgpu/hw/gp106/hw_fuse_gp106.h | 275 ++ include/nvgpu/hw/gp106/hw_gc6_gp106.h | 62 + include/nvgpu/hw/gp106/hw_gmmu_gp106.h | 331 ++ include/nvgpu/hw/gp106/hw_gr_gp106.h | 4163 ++++++++++++++++++++ include/nvgpu/hw/gp106/hw_ltc_gp106.h | 559 +++ include/nvgpu/hw/gp106/hw_mc_gp106.h | 251 ++ include/nvgpu/hw/gp106/hw_pbdma_gp106.h | 535 +++ include/nvgpu/hw/gp106/hw_perf_gp106.h | 219 + include/nvgpu/hw/gp106/hw_pram_gp106.h | 63 + include/nvgpu/hw/gp106/hw_pri_ringmaster_gp106.h | 151 + .../nvgpu/hw/gp106/hw_pri_ringstation_gpc_gp106.h | 79 + .../nvgpu/hw/gp106/hw_pri_ringstation_sys_gp106.h | 91 + include/nvgpu/hw/gp106/hw_proj_gp106.h | 179 + include/nvgpu/hw/gp106/hw_psec_gp106.h | 615 +++ include/nvgpu/hw/gp106/hw_pwr_gp106.h | 895 +++++ include/nvgpu/hw/gp106/hw_ram_gp106.h | 507 +++ include/nvgpu/hw/gp106/hw_therm_gp106.h | 183 + include/nvgpu/hw/gp106/hw_timer_gp106.h | 115 + include/nvgpu/hw/gp106/hw_top_gp106.h | 255 ++ include/nvgpu/hw/gp106/hw_trim_gp106.h | 195 + include/nvgpu/hw/gp106/hw_xp_gp106.h | 143 + include/nvgpu/hw/gp106/hw_xve_gp106.h | 207 + 31 files changed, 12956 insertions(+) create mode 100644 include/nvgpu/hw/gp106/hw_bus_gp106.h create mode 100644 include/nvgpu/hw/gp106/hw_ccsr_gp106.h create mode 100644 include/nvgpu/hw/gp106/hw_ce_gp106.h create mode 100644 include/nvgpu/hw/gp106/hw_ctxsw_prog_gp106.h create mode 100644 include/nvgpu/hw/gp106/hw_falcon_gp106.h create mode 100644 include/nvgpu/hw/gp106/hw_fb_gp106.h create mode 100644 include/nvgpu/hw/gp106/hw_fbpa_gp106.h create mode 100644 include/nvgpu/hw/gp106/hw_fifo_gp106.h create mode 100644 include/nvgpu/hw/gp106/hw_flush_gp106.h create mode 100644 include/nvgpu/hw/gp106/hw_fuse_gp106.h create mode 100644 include/nvgpu/hw/gp106/hw_gc6_gp106.h create mode 100644 include/nvgpu/hw/gp106/hw_gmmu_gp106.h create mode 100644 include/nvgpu/hw/gp106/hw_gr_gp106.h create mode 100644 include/nvgpu/hw/gp106/hw_ltc_gp106.h create mode 100644 include/nvgpu/hw/gp106/hw_mc_gp106.h create mode 100644 include/nvgpu/hw/gp106/hw_pbdma_gp106.h create mode 100644 include/nvgpu/hw/gp106/hw_perf_gp106.h create mode 100644 include/nvgpu/hw/gp106/hw_pram_gp106.h create mode 100644 include/nvgpu/hw/gp106/hw_pri_ringmaster_gp106.h create mode 100644 include/nvgpu/hw/gp106/hw_pri_ringstation_gpc_gp106.h create mode 100644 include/nvgpu/hw/gp106/hw_pri_ringstation_sys_gp106.h create mode 100644 include/nvgpu/hw/gp106/hw_proj_gp106.h create mode 100644 include/nvgpu/hw/gp106/hw_psec_gp106.h create mode 100644 include/nvgpu/hw/gp106/hw_pwr_gp106.h create mode 100644 include/nvgpu/hw/gp106/hw_ram_gp106.h create mode 100644 include/nvgpu/hw/gp106/hw_therm_gp106.h create mode 100644 include/nvgpu/hw/gp106/hw_timer_gp106.h create mode 100644 include/nvgpu/hw/gp106/hw_top_gp106.h create mode 100644 include/nvgpu/hw/gp106/hw_trim_gp106.h create mode 100644 include/nvgpu/hw/gp106/hw_xp_gp106.h create mode 100644 include/nvgpu/hw/gp106/hw_xve_gp106.h (limited to 'include/nvgpu/hw/gp106') diff --git a/include/nvgpu/hw/gp106/hw_bus_gp106.h b/include/nvgpu/hw/gp106/hw_bus_gp106.h new file mode 100644 index 0000000..ce3aafd --- /dev/null +++ b/include/nvgpu/hw/gp106/hw_bus_gp106.h @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_bus_gp106_h_ +#define _hw_bus_gp106_h_ + +static inline u32 bus_bar0_window_r(void) +{ + return 0x00001700U; +} +static inline u32 bus_bar0_window_base_f(u32 v) +{ + return (v & 0xffffffU) << 0U; +} +static inline u32 bus_bar0_window_target_vid_mem_f(void) +{ + return 0x0U; +} +static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) +{ + return 0x2000000U; +} +static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) +{ + return 0x3000000U; +} +static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) +{ + return 0x00000010U; +} +static inline u32 bus_bar1_block_r(void) +{ + return 0x00001704U; +} +static inline u32 bus_bar1_block_ptr_f(u32 v) +{ + return (v & 0xfffffffU) << 0U; +} +static inline u32 bus_bar1_block_target_vid_mem_f(void) +{ + return 0x0U; +} +static inline u32 bus_bar1_block_target_sys_mem_coh_f(void) +{ + return 0x20000000U; +} +static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void) +{ + return 0x30000000U; +} +static inline u32 bus_bar1_block_mode_virtual_f(void) +{ + return 0x80000000U; +} +static inline u32 bus_bar2_block_r(void) +{ + return 0x00001714U; +} +static inline u32 bus_bar2_block_ptr_f(u32 v) +{ + return (v & 0xfffffffU) << 0U; +} +static inline u32 bus_bar2_block_target_vid_mem_f(void) +{ + return 0x0U; +} +static inline u32 bus_bar2_block_target_sys_mem_coh_f(void) +{ + return 0x20000000U; +} +static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void) +{ + return 0x30000000U; +} +static inline u32 bus_bar2_block_mode_virtual_f(void) +{ + return 0x80000000U; +} +static inline u32 bus_bar1_block_ptr_shift_v(void) +{ + return 0x0000000cU; +} +static inline u32 bus_bar2_block_ptr_shift_v(void) +{ + return 0x0000000cU; +} +static inline u32 bus_bind_status_r(void) +{ + return 0x00001710U; +} +static inline u32 bus_bind_status_bar1_pending_v(u32 r) +{ + return (r >> 0U) & 0x1U; +} +static inline u32 bus_bind_status_bar1_pending_empty_f(void) +{ + return 0x0U; +} +static inline u32 bus_bind_status_bar1_pending_busy_f(void) +{ + return 0x1U; +} +static inline u32 bus_bind_status_bar1_outstanding_v(u32 r) +{ + return (r >> 1U) & 0x1U; +} +static inline u32 bus_bind_status_bar1_outstanding_false_f(void) +{ + return 0x0U; +} +static inline u32 bus_bind_status_bar1_outstanding_true_f(void) +{ + return 0x2U; +} +static inline u32 bus_bind_status_bar2_pending_v(u32 r) +{ + return (r >> 2U) & 0x1U; +} +static inline u32 bus_bind_status_bar2_pending_empty_f(void) +{ + return 0x0U; +} +static inline u32 bus_bind_status_bar2_pending_busy_f(void) +{ + return 0x4U; +} +static inline u32 bus_bind_status_bar2_outstanding_v(u32 r) +{ + return (r >> 3U) & 0x1U; +} +static inline u32 bus_bind_status_bar2_outstanding_false_f(void) +{ + return 0x0U; +} +static inline u32 bus_bind_status_bar2_outstanding_true_f(void) +{ + return 0x8U; +} +static inline u32 bus_intr_0_r(void) +{ + return 0x00001100U; +} +static inline u32 bus_intr_0_pri_squash_m(void) +{ + return 0x1U << 1U; +} +static inline u32 bus_intr_0_pri_fecserr_m(void) +{ + return 0x1U << 2U; +} +static inline u32 bus_intr_0_pri_timeout_m(void) +{ + return 0x1U << 3U; +} +static inline u32 bus_intr_en_0_r(void) +{ + return 0x00001140U; +} +static inline u32 bus_intr_en_0_pri_squash_m(void) +{ + return 0x1U << 1U; +} +static inline u32 bus_intr_en_0_pri_fecserr_m(void) +{ + return 0x1U << 2U; +} +static inline u32 bus_intr_en_0_pri_timeout_m(void) +{ + return 0x1U << 3U; +} +#endif diff --git a/include/nvgpu/hw/gp106/hw_ccsr_gp106.h b/include/nvgpu/hw/gp106/hw_ccsr_gp106.h new file mode 100644 index 0000000..cd63777 --- /dev/null +++ b/include/nvgpu/hw/gp106/hw_ccsr_gp106.h @@ -0,0 +1,163 @@ +/* + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ccsr_gp106_h_ +#define _hw_ccsr_gp106_h_ + +static inline u32 ccsr_channel_inst_r(u32 i) +{ + return 0x00800000U + i*8U; +} +static inline u32 ccsr_channel_inst__size_1_v(void) +{ + return 0x00001000U; +} +static inline u32 ccsr_channel_inst_ptr_f(u32 v) +{ + return (v & 0xfffffffU) << 0U; +} +static inline u32 ccsr_channel_inst_target_vid_mem_f(void) +{ + return 0x0U; +} +static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void) +{ + return 0x20000000U; +} +static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void) +{ + return 0x30000000U; +} +static inline u32 ccsr_channel_inst_bind_false_f(void) +{ + return 0x0U; +} +static inline u32 ccsr_channel_inst_bind_true_f(void) +{ + return 0x80000000U; +} +static inline u32 ccsr_channel_r(u32 i) +{ + return 0x00800004U + i*8U; +} +static inline u32 ccsr_channel__size_1_v(void) +{ + return 0x00001000U; +} +static inline u32 ccsr_channel_enable_v(u32 r) +{ + return (r >> 0U) & 0x1U; +} +static inline u32 ccsr_channel_enable_set_f(u32 v) +{ + return (v & 0x1U) << 10U; +} +static inline u32 ccsr_channel_enable_set_true_f(void) +{ + return 0x400U; +} +static inline u32 ccsr_channel_enable_clr_true_f(void) +{ + return 0x800U; +} +static inline u32 ccsr_channel_status_v(u32 r) +{ + return (r >> 24U) & 0xfU; +} +static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) +{ + return 0x00000002U; +} +static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) +{ + return 0x00000004U; +} +static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) +{ + return 0x0000000aU; +} +static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) +{ + return 0x0000000bU; +} +static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) +{ + return 0x0000000cU; +} +static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) +{ + return 0x0000000dU; +} +static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) +{ + return 0x0000000eU; +} +static inline u32 ccsr_channel_next_v(u32 r) +{ + return (r >> 1U) & 0x1U; +} +static inline u32 ccsr_channel_next_true_v(void) +{ + return 0x00000001U; +} +static inline u32 ccsr_channel_force_ctx_reload_true_f(void) +{ + return 0x100U; +} +static inline u32 ccsr_channel_busy_v(u32 r) +{ + return (r >> 28U) & 0x1U; +} +#endif diff --git a/include/nvgpu/hw/gp106/hw_ce_gp106.h b/include/nvgpu/hw/gp106/hw_ce_gp106.h new file mode 100644 index 0000000..8892f42 --- /dev/null +++ b/include/nvgpu/hw/gp106/hw_ce_gp106.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ce_gp106_h_ +#define _hw_ce_gp106_h_ + +static inline u32 ce_intr_status_r(u32 i) +{ + return 0x00104410U + i*128U; +} +static inline u32 ce_intr_status_blockpipe_pending_f(void) +{ + return 0x1U; +} +static inline u32 ce_intr_status_blockpipe_reset_f(void) +{ + return 0x1U; +} +static inline u32 ce_intr_status_nonblockpipe_pending_f(void) +{ + return 0x2U; +} +static inline u32 ce_intr_status_nonblockpipe_reset_f(void) +{ + return 0x2U; +} +static inline u32 ce_intr_status_launcherr_pending_f(void) +{ + return 0x4U; +} +static inline u32 ce_intr_status_launcherr_reset_f(void) +{ + return 0x4U; +} +#endif diff --git a/include/nvgpu/hw/gp106/hw_ctxsw_prog_gp106.h b/include/nvgpu/hw/gp106/hw_ctxsw_prog_gp106.h new file mode 100644 index 0000000..3387d23 --- /dev/null +++ b/include/nvgpu/hw/gp106/hw_ctxsw_prog_gp106.h @@ -0,0 +1,295 @@ +/* + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ctxsw_prog_gp106_h_ +#define _hw_ctxsw_prog_gp106_h_ + +static inline u32 ctxsw_prog_fecs_header_v(void) +{ + return 0x00000100U; +} +static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) +{ + return 0x00000008U; +} +static inline u32 ctxsw_prog_main_image_patch_count_o(void) +{ + return 0x00000010U; +} +static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) +{ + return 0x00000014U; +} +static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) +{ + return 0x00000018U; +} +static inline u32 ctxsw_prog_main_image_zcull_o(void) +{ + return 0x0000001cU; +} +static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) +{ + return 0x00000001U; +} +static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) +{ + return 0x00000002U; +} +static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) +{ + return 0x00000020U; +} +static inline u32 ctxsw_prog_main_image_pm_o(void) +{ + return 0x00000028U; +} +static inline u32 ctxsw_prog_main_image_pm_mode_m(void) +{ + return 0x7U << 0U; +} +static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) +{ + return 0x0U; +} +static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) +{ + return 0x7U << 3U; +} +static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) +{ + return 0x8U; +} +static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) +{ + return 0x0U; +} +static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) +{ + return 0x0000002cU; +} +static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) +{ + return 0x000000f4U; +} +static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void) +{ + return 0x000000d0U; +} +static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void) +{ + return 0x000000d4U; +} +static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void) +{ + return 0x000000d8U; +} +static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void) +{ + return 0x000000dcU; +} +static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) +{ + return 0x000000f8U; +} +static inline u32 ctxsw_prog_main_image_magic_value_o(void) +{ + return 0x000000fcU; +} +static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) +{ + return 0x600dc0deU; +} +static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) +{ + return 0x0000000cU; +} +static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) +{ + return (r >> 0U) & 0xffffU; +} +static inline u32 ctxsw_prog_local_image_ppc_info_o(void) +{ + return 0x000000f4U; +} +static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) +{ + return (r >> 0U) & 0xffffU; +} +static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) +{ + return (r >> 16U) & 0xffffU; +} +static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) +{ + return 0x000000f8U; +} +static inline u32 ctxsw_prog_local_magic_value_o(void) +{ + return 0x000000fcU; +} +static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) +{ + return 0xad0becabU; +} +static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) +{ + return 0x000000ecU; +} +static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) +{ + return (r >> 0U) & 0xffffU; +} +static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) +{ + return (r >> 16U) & 0xffU; +} +static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) +{ + return 0x00000100U; +} +static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) +{ + return 0x00000004U; +} +static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) +{ + return 0x00000000U; +} +static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) +{ + return 0x00000002U; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) +{ + return 0x000000a0U; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) +{ + return 2U; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) +{ + return (v & 0x3U) << 0U; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) +{ + return 0x3U << 0U; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) +{ + return (r >> 0U) & 0x3U; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) +{ + return 0x0U; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) +{ + return 0x2U; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) +{ + return 0x000000a4U; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) +{ + return 0x000000a8U; +} +static inline u32 ctxsw_prog_main_image_misc_options_o(void) +{ + return 0x0000003cU; +} +static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) +{ + return 0x1U << 3U; +} +static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) +{ + return 0x0U; +} +static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void) +{ + return 0x00000080U; +} +static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v) +{ + return (v & 0x3U) << 0U; +} +static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void) +{ + return 0x1U; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void) +{ + return 0x00000068U; +} +static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void) +{ + return 0x00000084U; +} +static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v) +{ + return (v & 0x3U) << 0U; +} +static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void) +{ + return 0x1U; +} +static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void) +{ + return 0x2U; +} +#endif diff --git a/include/nvgpu/hw/gp106/hw_falcon_gp106.h b/include/nvgpu/hw/gp106/hw_falcon_gp106.h new file mode 100644 index 0000000..d899e3f --- /dev/null +++ b/include/nvgpu/hw/gp106/hw_falcon_gp106.h @@ -0,0 +1,603 @@ +/* + * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_falcon_gp106_h_ +#define _hw_falcon_gp106_h_ + +static inline u32 falcon_falcon_irqsset_r(void) +{ + return 0x00000000U; +} +static inline u32 falcon_falcon_irqsset_swgen0_set_f(void) +{ + return 0x40U; +} +static inline u32 falcon_falcon_irqsclr_r(void) +{ + return 0x00000004U; +} +static inline u32 falcon_falcon_irqstat_r(void) +{ + return 0x00000008U; +} +static inline u32 falcon_falcon_irqstat_halt_true_f(void) +{ + return 0x10U; +} +static inline u32 falcon_falcon_irqstat_exterr_true_f(void) +{ + return 0x20U; +} +static inline u32 falcon_falcon_irqstat_swgen0_true_f(void) +{ + return 0x40U; +} +static inline u32 falcon_falcon_irqmode_r(void) +{ + return 0x0000000cU; +} +static inline u32 falcon_falcon_irqmset_r(void) +{ + return 0x00000010U; +} +static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v) +{ + return (v & 0x1U) << 0U; +} +static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v) +{ + return (v & 0x1U) << 1U; +} +static inline u32 falcon_falcon_irqmset_mthd_f(u32 v) +{ + return (v & 0x1U) << 2U; +} +static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v) +{ + return (v & 0x1U) << 3U; +} +static inline u32 falcon_falcon_irqmset_halt_f(u32 v) +{ + return (v & 0x1U) << 4U; +} +static inline u32 falcon_falcon_irqmset_exterr_f(u32 v) +{ + return (v & 0x1U) << 5U; +} +static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v) +{ + return (v & 0x1U) << 6U; +} +static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v) +{ + return (v & 0x1U) << 7U; +} +static inline u32 falcon_falcon_irqmclr_r(void) +{ + return 0x00000014U; +} +static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v) +{ + return (v & 0x1U) << 0U; +} +static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v) +{ + return (v & 0x1U) << 1U; +} +static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v) +{ + return (v & 0x1U) << 2U; +} +static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v) +{ + return (v & 0x1U) << 3U; +} +static inline u32 falcon_falcon_irqmclr_halt_f(u32 v) +{ + return (v & 0x1U) << 4U; +} +static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v) +{ + return (v & 0x1U) << 5U; +} +static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v) +{ + return (v & 0x1U) << 6U; +} +static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v) +{ + return (v & 0x1U) << 7U; +} +static inline u32 falcon_falcon_irqmclr_ext_f(u32 v) +{ + return (v & 0xffU) << 8U; +} +static inline u32 falcon_falcon_irqmask_r(void) +{ + return 0x00000018U; +} +static inline u32 falcon_falcon_irqdest_r(void) +{ + return 0x0000001cU; +} +static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v) +{ + return (v & 0x1U) << 0U; +} +static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v) +{ + return (v & 0x1U) << 1U; +} +static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v) +{ + return (v & 0x1U) << 2U; +} +static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v) +{ + return (v & 0x1U) << 3U; +} +static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v) +{ + return (v & 0x1U) << 4U; +} +static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v) +{ + return (v & 0x1U) << 5U; +} +static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v) +{ + return (v & 0x1U) << 6U; +} +static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v) +{ + return (v & 0x1U) << 7U; +} +static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v) +{ + return (v & 0xffU) << 8U; +} +static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v) +{ + return (v & 0x1U) << 16U; +} +static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v) +{ + return (v & 0x1U) << 17U; +} +static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v) +{ + return (v & 0x1U) << 18U; +} +static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v) +{ + return (v & 0x1U) << 19U; +} +static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v) +{ + return (v & 0x1U) << 20U; +} +static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v) +{ + return (v & 0x1U) << 21U; +} +static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v) +{ + return (v & 0x1U) << 22U; +} +static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v) +{ + return (v & 0x1U) << 23U; +} +static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v) +{ + return (v & 0xffU) << 24U; +} +static inline u32 falcon_falcon_curctx_r(void) +{ + return 0x00000050U; +} +static inline u32 falcon_falcon_nxtctx_r(void) +{ + return 0x00000054U; +} +static inline u32 falcon_falcon_mailbox0_r(void) +{ + return 0x00000040U; +} +static inline u32 falcon_falcon_mailbox1_r(void) +{ + return 0x00000044U; +} +static inline u32 falcon_falcon_itfen_r(void) +{ + return 0x00000048U; +} +static inline u32 falcon_falcon_itfen_ctxen_enable_f(void) +{ + return 0x1U; +} +static inline u32 falcon_falcon_idlestate_r(void) +{ + return 0x0000004cU; +} +static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r) +{ + return (r >> 0U) & 0x1U; +} +static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r) +{ + return (r >> 1U) & 0x7fffU; +} +static inline u32 falcon_falcon_os_r(void) +{ + return 0x00000080U; +} +static inline u32 falcon_falcon_engctl_r(void) +{ + return 0x000000a4U; +} +static inline u32 falcon_falcon_cpuctl_r(void) +{ + return 0x00000100U; +} +static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v) +{ + return (v & 0x1U) << 1U; +} +static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v) +{ + return (v & 0x1U) << 2U; +} +static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v) +{ + return (v & 0x1U) << 3U; +} +static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v) +{ + return (v & 0x1U) << 4U; +} +static inline u32 falcon_falcon_cpuctl_halt_intr_m(void) +{ + return 0x1U << 4U; +} +static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r) +{ + return (r >> 4U) & 0x1U; +} +static inline u32 falcon_falcon_cpuctl_stopped_m(void) +{ + return 0x1U << 5U; +} +static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v) +{ + return (v & 0x1U) << 6U; +} +static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void) +{ + return 0x1U << 6U; +} +static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r) +{ + return (r >> 6U) & 0x1U; +} +static inline u32 falcon_falcon_cpuctl_alias_r(void) +{ + return 0x00000130U; +} +static inline u32 falcon_falcon_cpuctl_alias_startcpu_f(u32 v) +{ + return (v & 0x1U) << 1U; +} +static inline u32 falcon_falcon_imemc_r(u32 i) +{ + return 0x00000180U + i*16U; +} +static inline u32 falcon_falcon_imemc_offs_f(u32 v) +{ + return (v & 0x3fU) << 2U; +} +static inline u32 falcon_falcon_imemc_blk_f(u32 v) +{ + return (v & 0xffU) << 8U; +} +static inline u32 falcon_falcon_imemc_aincw_f(u32 v) +{ + return (v & 0x1U) << 24U; +} +static inline u32 falcon_falcon_imemc_secure_f(u32 v) +{ + return (v & 0x1U) << 28U; +} +static inline u32 falcon_falcon_imemd_r(u32 i) +{ + return 0x00000184U + i*16U; +} +static inline u32 falcon_falcon_imemt_r(u32 i) +{ + return 0x00000188U + i*16U; +} +static inline u32 falcon_falcon_sctl_r(void) +{ + return 0x00000240U; +} +static inline u32 falcon_falcon_mmu_phys_sec_r(void) +{ + return 0x00100ce4U; +} +static inline u32 falcon_falcon_bootvec_r(void) +{ + return 0x00000104U; +} +static inline u32 falcon_falcon_bootvec_vec_f(u32 v) +{ + return (v & 0xffffffffU) << 0U; +} +static inline u32 falcon_falcon_dmactl_r(void) +{ + return 0x0000010cU; +} +static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void) +{ + return 0x1U << 1U; +} +static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void) +{ + return 0x1U << 2U; +} +static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v) +{ + return (v & 0x1U) << 0U; +} +static inline u32 falcon_falcon_hwcfg_r(void) +{ + return 0x00000108U; +} +static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r) +{ + return (r >> 0U) & 0x1ffU; +} +static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r) +{ + return (r >> 9U) & 0x1ffU; +} +static inline u32 falcon_falcon_dmatrfbase_r(void) +{ + return 0x00000110U; +} +static inline u32 falcon_falcon_dmatrfbase1_r(void) +{ + return 0x00000128U; +} +static inline u32 falcon_falcon_dmatrfmoffs_r(void) +{ + return 0x00000114U; +} +static inline u32 falcon_falcon_dmatrfcmd_r(void) +{ + return 0x00000118U; +} +static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v) +{ + return (v & 0x1U) << 4U; +} +static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v) +{ + return (v & 0x1U) << 5U; +} +static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v) +{ + return (v & 0x7U) << 8U; +} +static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v) +{ + return (v & 0x7U) << 12U; +} +static inline u32 falcon_falcon_dmatrffboffs_r(void) +{ + return 0x0000011cU; +} +static inline u32 falcon_falcon_imctl_debug_r(void) +{ + return 0x0000015cU; +} +static inline u32 falcon_falcon_imctl_debug_addr_blk_f(u32 v) +{ + return (v & 0xffffffU) << 0U; +} +static inline u32 falcon_falcon_imctl_debug_cmd_f(u32 v) +{ + return (v & 0x7U) << 24U; +} +static inline u32 falcon_falcon_imstat_r(void) +{ + return 0x00000144U; +} +static inline u32 falcon_falcon_traceidx_r(void) +{ + return 0x00000148U; +} +static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r) +{ + return (r >> 16U) & 0xffU; +} +static inline u32 falcon_falcon_traceidx_idx_f(u32 v) +{ + return (v & 0xffU) << 0U; +} +static inline u32 falcon_falcon_tracepc_r(void) +{ + return 0x0000014cU; +} +static inline u32 falcon_falcon_tracepc_pc_v(u32 r) +{ + return (r >> 0U) & 0xffffffU; +} +static inline u32 falcon_falcon_exterraddr_r(void) +{ + return 0x00000168U; +} +static inline u32 falcon_falcon_exterrstat_r(void) +{ + return 0x0000016cU; +} +static inline u32 falcon_falcon_exterrstat_valid_m(void) +{ + return 0x1U << 31U; +} +static inline u32 falcon_falcon_exterrstat_valid_v(u32 r) +{ + return (r >> 31U) & 0x1U; +} +static inline u32 falcon_falcon_exterrstat_valid_true_v(void) +{ + return 0x00000001U; +} +static inline u32 falcon_falcon_icd_cmd_r(void) +{ + return 0x00000200U; +} +static inline u32 falcon_falcon_icd_cmd_opc_s(void) +{ + return 4U; +} +static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v) +{ + return (v & 0xfU) << 0U; +} +static inline u32 falcon_falcon_icd_cmd_opc_m(void) +{ + return 0xfU << 0U; +} +static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r) +{ + return (r >> 0U) & 0xfU; +} +static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void) +{ + return 0x8U; +} +static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void) +{ + return 0xeU; +} +static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v) +{ + return (v & 0x1fU) << 8U; +} +static inline u32 falcon_falcon_icd_rdata_r(void) +{ + return 0x0000020cU; +} +static inline u32 falcon_falcon_dmemc_r(u32 i) +{ + return 0x000001c0U + i*8U; +} +static inline u32 falcon_falcon_dmemc_offs_f(u32 v) +{ + return (v & 0x3fU) << 2U; +} +static inline u32 falcon_falcon_dmemc_offs_m(void) +{ + return 0x3fU << 2U; +} +static inline u32 falcon_falcon_dmemc_blk_f(u32 v) +{ + return (v & 0xffU) << 8U; +} +static inline u32 falcon_falcon_dmemc_blk_m(void) +{ + return 0xffU << 8U; +} +static inline u32 falcon_falcon_dmemc_aincw_f(u32 v) +{ + return (v & 0x1U) << 24U; +} +static inline u32 falcon_falcon_dmemc_aincr_f(u32 v) +{ + return (v & 0x1U) << 25U; +} +static inline u32 falcon_falcon_dmemd_r(u32 i) +{ + return 0x000001c4U + i*8U; +} +static inline u32 falcon_falcon_debug1_r(void) +{ + return 0x00000090U; +} +static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void) +{ + return 1U; +} +static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v) +{ + return (v & 0x1U) << 16U; +} +static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void) +{ + return 0x1U << 16U; +} +static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r) +{ + return (r >> 16U) & 0x1U; +} +static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void) +{ + return 0x0U; +} +static inline u32 falcon_falcon_debuginfo_r(void) +{ + return 0x00000094U; +} +#endif diff --git a/include/nvgpu/hw/gp106/hw_fb_gp106.h b/include/nvgpu/hw/gp106/hw_fb_gp106.h new file mode 100644 index 0000000..1c2a1ac --- /dev/null +++ b/include/nvgpu/hw/gp106/hw_fb_gp106.h @@ -0,0 +1,563 @@ +/* + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_fb_gp106_h_ +#define _hw_fb_gp106_h_ + +static inline u32 fb_fbhub_num_active_ltcs_r(void) +{ + return 0x00100800U; +} +static inline u32 fb_mmu_ctrl_r(void) +{ + return 0x00100c80U; +} +static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) +{ + return (r >> 15U) & 0x1U; +} +static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) +{ + return 0x0U; +} +static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) +{ + return (r >> 16U) & 0xffU; +} +static inline u32 fb_priv_mmu_phy_secure_r(void) +{ + return 0x00100ce4U; +} +static inline u32 fb_mmu_invalidate_pdb_r(void) +{ + return 0x00100cb8U; +} +static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) +{ + return 0x0U; +} +static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void) +{ + return 0x2U; +} +static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) +{ + return (v & 0xfffffffU) << 4U; +} +static inline u32 fb_mmu_invalidate_r(void) +{ + return 0x00100cbcU; +} +static inline u32 fb_mmu_invalidate_all_va_true_f(void) +{ + return 0x1U; +} +static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) +{ + return 0x2U; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_s(void) +{ + return 1U; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v) +{ + return (v & 0x1U) << 2U; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_m(void) +{ + return 0x1U << 2U; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r) +{ + return (r >> 2U) & 0x1U; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void) +{ + return 0x4U; +} +static inline u32 fb_mmu_invalidate_replay_s(void) +{ + return 3U; +} +static inline u32 fb_mmu_invalidate_replay_f(u32 v) +{ + return (v & 0x7U) << 3U; +} +static inline u32 fb_mmu_invalidate_replay_m(void) +{ + return 0x7U << 3U; +} +static inline u32 fb_mmu_invalidate_replay_v(u32 r) +{ + return (r >> 3U) & 0x7U; +} +static inline u32 fb_mmu_invalidate_replay_none_f(void) +{ + return 0x0U; +} +static inline u32 fb_mmu_invalidate_replay_start_f(void) +{ + return 0x8U; +} +static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void) +{ + return 0x10U; +} +static inline u32 fb_mmu_invalidate_replay_cancel_targeted_f(void) +{ + return 0x18U; +} +static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void) +{ + return 0x20U; +} +static inline u32 fb_mmu_invalidate_replay_cancel_f(void) +{ + return 0x20U; +} +static inline u32 fb_mmu_invalidate_sys_membar_s(void) +{ + return 1U; +} +static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v) +{ + return (v & 0x1U) << 6U; +} +static inline u32 fb_mmu_invalidate_sys_membar_m(void) +{ + return 0x1U << 6U; +} +static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r) +{ + return (r >> 6U) & 0x1U; +} +static inline u32 fb_mmu_invalidate_sys_membar_true_f(void) +{ + return 0x40U; +} +static inline u32 fb_mmu_invalidate_ack_s(void) +{ + return 2U; +} +static inline u32 fb_mmu_invalidate_ack_f(u32 v) +{ + return (v & 0x3U) << 7U; +} +static inline u32 fb_mmu_invalidate_ack_m(void) +{ + return 0x3U << 7U; +} +static inline u32 fb_mmu_invalidate_ack_v(u32 r) +{ + return (r >> 7U) & 0x3U; +} +static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void) +{ + return 0x0U; +} +static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void) +{ + return 0x100U; +} +static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void) +{ + return 0x80U; +} +static inline u32 fb_mmu_invalidate_cancel_client_id_s(void) +{ + return 6U; +} +static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v) +{ + return (v & 0x3fU) << 9U; +} +static inline u32 fb_mmu_invalidate_cancel_client_id_m(void) +{ + return 0x3fU << 9U; +} +static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r) +{ + return (r >> 9U) & 0x3fU; +} +static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void) +{ + return 5U; +} +static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v) +{ + return (v & 0x1fU) << 15U; +} +static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void) +{ + return 0x1fU << 15U; +} +static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r) +{ + return (r >> 15U) & 0x1fU; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_s(void) +{ + return 1U; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v) +{ + return (v & 0x1U) << 20U; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_m(void) +{ + return 0x1U << 20U; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r) +{ + return (r >> 20U) & 0x1U; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void) +{ + return 0x0U; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void) +{ + return 0x100000U; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void) +{ + return 3U; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v) +{ + return (v & 0x7U) << 24U; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void) +{ + return 0x7U << 24U; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r) +{ + return (r >> 24U) & 0x7U; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void) +{ + return 0x0U; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void) +{ + return 0x1000000U; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void) +{ + return 0x2000000U; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void) +{ + return 0x3000000U; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void) +{ + return 0x4000000U; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void) +{ + return 0x5000000U; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void) +{ + return 0x6000000U; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void) +{ + return 0x7000000U; +} +static inline u32 fb_mmu_invalidate_trigger_s(void) +{ + return 1U; +} +static inline u32 fb_mmu_invalidate_trigger_f(u32 v) +{ + return (v & 0x1U) << 31U; +} +static inline u32 fb_mmu_invalidate_trigger_m(void) +{ + return 0x1U << 31U; +} +static inline u32 fb_mmu_invalidate_trigger_v(u32 r) +{ + return (r >> 31U) & 0x1U; +} +static inline u32 fb_mmu_invalidate_trigger_true_f(void) +{ + return 0x80000000U; +} +static inline u32 fb_mmu_debug_wr_r(void) +{ + return 0x00100cc8U; +} +static inline u32 fb_mmu_debug_wr_aperture_s(void) +{ + return 2U; +} +static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) +{ + return (v & 0x3U) << 0U; +} +static inline u32 fb_mmu_debug_wr_aperture_m(void) +{ + return 0x3U << 0U; +} +static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) +{ + return (r >> 0U) & 0x3U; +} +static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) +{ + return 0x0U; +} +static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void) +{ + return 0x2U; +} +static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void) +{ + return 0x3U; +} +static inline u32 fb_mmu_debug_wr_vol_false_f(void) +{ + return 0x0U; +} +static inline u32 fb_mmu_debug_wr_vol_true_v(void) +{ + return 0x00000001U; +} +static inline u32 fb_mmu_debug_wr_vol_true_f(void) +{ + return 0x4U; +} +static inline u32 fb_mmu_debug_wr_addr_f(u32 v) +{ + return (v & 0xfffffffU) << 4U; +} +static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) +{ + return 0x0000000cU; +} +static inline u32 fb_mmu_debug_rd_r(void) +{ + return 0x00100cccU; +} +static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) +{ + return 0x0U; +} +static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void) +{ + return 0x2U; +} +static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void) +{ + return 0x3U; +} +static inline u32 fb_mmu_debug_rd_vol_false_f(void) +{ + return 0x0U; +} +static inline u32 fb_mmu_debug_rd_addr_f(u32 v) +{ + return (v & 0xfffffffU) << 4U; +} +static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) +{ + return 0x0000000cU; +} +static inline u32 fb_mmu_debug_ctrl_r(void) +{ + return 0x00100cc4U; +} +static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) +{ + return (r >> 16U) & 0x1U; +} +static inline u32 fb_mmu_debug_ctrl_debug_m(void) +{ + return 0x1U << 16U; +} +static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) +{ + return 0x00000001U; +} +static inline u32 fb_mmu_debug_ctrl_debug_enabled_f(void) +{ + return 0x10000U; +} +static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) +{ + return 0x00000000U; +} +static inline u32 fb_mmu_debug_ctrl_debug_disabled_f(void) +{ + return 0x0U; +} +static inline u32 fb_mmu_priv_level_mask_r(void) +{ + return 0x00100cdcU; +} +static inline u32 fb_mmu_priv_level_mask_write_violation_m(void) +{ + return 0x1U << 7U; +} +static inline u32 fb_niso_flush_sysmem_addr_r(void) +{ + return 0x00100c10U; +} +static inline u32 fb_mmu_local_memory_range_r(void) +{ + return 0x00100ce0U; +} +static inline u32 fb_mmu_local_memory_range_lower_scale_v(u32 r) +{ + return (r >> 0U) & 0xfU; +} +static inline u32 fb_mmu_local_memory_range_lower_mag_v(u32 r) +{ + return (r >> 4U) & 0x3fU; +} +static inline u32 fb_mmu_local_memory_range_ecc_mode_v(u32 r) +{ + return (r >> 30U) & 0x1U; +} +static inline u32 fb_fbpa_fbio_delay_r(void) +{ + return 0x009a065cU; +} +static inline u32 fb_fbpa_fbio_delay_src_f(u32 v) +{ + return (v & 0xfU) << 0U; +} +static inline u32 fb_fbpa_fbio_delay_src_m(void) +{ + return 0xfU << 0U; +} +static inline u32 fb_fbpa_fbio_delay_src_v(u32 r) +{ + return (r >> 0U) & 0xfU; +} +static inline u32 fb_fbpa_fbio_delay_src_max_v(void) +{ + return 0x00000002U; +} +static inline u32 fb_fbpa_fbio_delay_priv_f(u32 v) +{ + return (v & 0xfU) << 4U; +} +static inline u32 fb_fbpa_fbio_delay_priv_m(void) +{ + return 0xfU << 4U; +} +static inline u32 fb_fbpa_fbio_delay_priv_v(u32 r) +{ + return (r >> 4U) & 0xfU; +} +static inline u32 fb_fbpa_fbio_delay_priv_max_v(void) +{ + return 0x00000002U; +} +static inline u32 fb_fbpa_fbio_cmd_delay_r(void) +{ + return 0x009a08e0U; +} +static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_f(u32 v) +{ + return (v & 0xfU) << 0U; +} +static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_m(void) +{ + return 0xfU << 0U; +} +static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_v(u32 r) +{ + return (r >> 0U) & 0xfU; +} +static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_max_v(void) +{ + return 0x00000001U; +} +static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_f(u32 v) +{ + return (v & 0xfU) << 4U; +} +static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_m(void) +{ + return 0xfU << 4U; +} +static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_v(u32 r) +{ + return (r >> 4U) & 0xfU; +} +static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_max_v(void) +{ + return 0x00000001U; +} +static inline u32 fb_niso_scrub_status_r(void) +{ + return 0x00100b20U; +} +static inline u32 fb_niso_scrub_status_flag_v(u32 r) +{ + return (r >> 0U) & 0x1U; +} +static inline u32 fb_fbpa_fbio_iref_byte_rx_ctrl_r(void) +{ + return 0x009a0eb0U; +} +#endif diff --git a/include/nvgpu/hw/gp106/hw_fbpa_gp106.h b/include/nvgpu/hw/gp106/hw_fbpa_gp106.h new file mode 100644 index 0000000..797a40c --- /dev/null +++ b/include/nvgpu/hw/gp106/hw_fbpa_gp106.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_fbpa_gp106_h_ +#define _hw_fbpa_gp106_h_ + +static inline u32 fbpa_cstatus_r(void) +{ + return 0x009a020cU; +} +static inline u32 fbpa_cstatus_ramamount_v(u32 r) +{ + return (r >> 0U) & 0x1ffffU; +} +#endif diff --git a/include/nvgpu/hw/gp106/hw_fifo_gp106.h b/include/nvgpu/hw/gp106/hw_fifo_gp106.h new file mode 100644 index 0000000..804e9e4 --- /dev/null +++ b/include/nvgpu/hw/gp106/hw_fifo_gp106.h @@ -0,0 +1,695 @@ +/* + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_fifo_gp106_h_ +#define _hw_fifo_gp106_h_ + +static inline u32 fifo_bar1_base_r(void) +{ + return 0x00002254U; +} +static inline u32 fifo_bar1_base_ptr_f(u32 v) +{ + return (v & 0xfffffffU) << 0U; +} +static inline u32 fifo_bar1_base_ptr_align_shift_v(void) +{ + return 0x0000000cU; +} +static inline u32 fifo_bar1_base_valid_false_f(void) +{ + return 0x0U; +} +static inline u32 fifo_bar1_base_valid_true_f(void) +{ + return 0x10000000U; +} +static inline u32 fifo_runlist_base_r(void) +{ + return 0x00002270U; +} +static inline u32 fifo_runlist_base_ptr_f(u32 v) +{ + return (v & 0xfffffffU) << 0U; +} +static inline u32 fifo_runlist_base_target_vid_mem_f(void) +{ + return 0x0U; +} +static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void) +{ + return 0x20000000U; +} +static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void) +{ + return 0x30000000U; +} +static inline u32 fifo_runlist_r(void) +{ + return 0x00002274U; +} +static inline u32 fifo_runlist_engine_f(u32 v) +{ + return (v & 0xfU) << 20U; +} +static inline u32 fifo_eng_runlist_base_r(u32 i) +{ + return 0x00002280U + i*8U; +} +static inline u32 fifo_eng_runlist_base__size_1_v(void) +{ + return 0x00000007U; +} +static inline u32 fifo_eng_runlist_r(u32 i) +{ + return 0x00002284U + i*8U; +} +static inline u32 fifo_eng_runlist__size_1_v(void) +{ + return 0x00000007U; +} +static inline u32 fifo_eng_runlist_length_f(u32 v) +{ + return (v & 0xffffU) << 0U; +} +static inline u32 fifo_eng_runlist_length_max_v(void) +{ + return 0x0000ffffU; +} +static inline u32 fifo_eng_runlist_pending_true_f(void) +{ + return 0x100000U; +} +static inline u32 fifo_pb_timeslice_r(u32 i) +{ + return 0x00002350U + i*4U; +} +static inline u32 fifo_pb_timeslice_timeout_16_f(void) +{ + return 0x10U; +} +static inline u32 fifo_pb_timeslice_timescale_0_f(void) +{ + return 0x0U; +} +static inline u32 fifo_pb_timeslice_enable_true_f(void) +{ + return 0x10000000U; +} +static inline u32 fifo_pbdma_map_r(u32 i) +{ + return 0x00002390U + i*4U; +} +static inline u32 fifo_intr_0_r(void) +{ + return 0x00002100U; +} +static inline u32 fifo_intr_0_bi