From 2c5337a24f7f2d02989dfb733c55d6d8c7e90493 Mon Sep 17 00:00:00 2001
From: Joshua Bakita <bakitajoshua@gmail.com>
Date: Sun, 29 Oct 2023 13:07:40 -0400
Subject: Update includes to L4T r32.7.4 and drop nvgpu/gk20a.h dependency

Also add instructions for updating `include/`. These files are now
only needed to build on Linux 4.9-based Tegra platforms.
---
 include/nvgpu/hw/gk20a/hw_gr_gk20a.h | 61 ++++++++++++++++++++++++++++++++++++
 1 file changed, 61 insertions(+)

(limited to 'include/nvgpu/hw/gk20a/hw_gr_gk20a.h')

diff --git a/include/nvgpu/hw/gk20a/hw_gr_gk20a.h b/include/nvgpu/hw/gk20a/hw_gr_gk20a.h
index 826108f..376cc8f 100644
--- a/include/nvgpu/hw/gk20a/hw_gr_gk20a.h
+++ b/include/nvgpu/hw/gk20a/hw_gr_gk20a.h
@@ -1380,6 +1380,10 @@ static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void)
 {
 	return 0x00502400U;
 }
+static inline u32 gr_gpc0_gpccs_ctxsw_mailbox__size_1_v(void)
+{
+	return 0x00000010U;
+}
 static inline u32 gr_fecs_ctxsw_idlestate_r(void)
 {
 	return 0x00409420U;
@@ -3804,4 +3808,61 @@ static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void)
 {
 	return 0x40000000U;
 }
+
+static inline u32 gr_gpc0_gpccs_falcon_irqstat_r(void)
+{
+	return 0x00502008U;
+}
+static inline u32 gr_gpc0_gpccs_falcon_irqmode_r(void)
+{
+	return 0x0050200cU;
+}
+static inline u32 gr_gpc0_gpccs_falcon_irqmask_r(void)
+{
+	return 0x00502018U;
+}
+static inline u32 gr_gpc0_gpccs_falcon_irqdest_r(void)
+{
+	return 0x0050201cU;
+}
+static inline u32 gr_gpc0_gpccs_falcon_debug1_r(void)
+{
+	return 0x00502090U;
+}
+static inline u32 gr_gpc0_gpccs_falcon_debuginfo_r(void)
+{
+	return 0x00502094U;
+}
+static inline u32 gr_gpc0_gpccs_falcon_engctl_r(void)
+{
+	return 0x005020a4U;
+}
+static inline u32 gr_gpc0_gpccs_falcon_curctx_r(void)
+{
+	return 0x00502050U;
+}
+static inline u32 gr_gpc0_gpccs_falcon_nxtctx_r(void)
+{
+	return 0x00502054U;
+}
+static inline u32 gr_gpc0_gpccs_ctxsw_mailbox_r(u32 i)
+{
+	return 0x00502800U + i*4U;
+}
+static inline u32 gr_gpc0_gpccs_falcon_icd_cmd_r(void)
+{
+	return 0x00502200U;
+}
+static inline u32 gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f(void)
+{
+	return 0x8U;
+}
+static inline u32 gr_gpc0_gpccs_falcon_icd_cmd_idx_f(u32 v)
+{
+	return (v & 0x1fU) << 8U;
+}
+static inline u32 gr_gpc_gpccs_falcon_icd_rdata_r(void)
+{
+	return 0x0050220cU;
+}
 #endif
-- 
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