From f347fde22f1297e4f022600d201780d5ead78114 Mon Sep 17 00:00:00 2001 From: Joshua Bakita Date: Wed, 25 Sep 2024 16:09:09 -0400 Subject: Delete no-longer-needed nvgpu headers The dependency on these was removed in commit 8340d234. --- include/nvgpu/acr/acr_flcnbl.h | 144 ------------------ include/nvgpu/acr/acr_lsfm.h | 328 ---------------------------------------- include/nvgpu/acr/acr_objflcn.h | 91 ----------- include/nvgpu/acr/acr_objlsfm.h | 97 ------------ include/nvgpu/acr/nvgpu_acr.h | 192 ----------------------- 5 files changed, 852 deletions(-) delete mode 100644 include/nvgpu/acr/acr_flcnbl.h delete mode 100644 include/nvgpu/acr/acr_lsfm.h delete mode 100644 include/nvgpu/acr/acr_objflcn.h delete mode 100644 include/nvgpu/acr/acr_objlsfm.h delete mode 100644 include/nvgpu/acr/nvgpu_acr.h (limited to 'include/nvgpu/acr') diff --git a/include/nvgpu/acr/acr_flcnbl.h b/include/nvgpu/acr/acr_flcnbl.h deleted file mode 100644 index ad697b2..0000000 --- a/include/nvgpu/acr/acr_flcnbl.h +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_ACR_FLCNBL_H -#define NVGPU_ACR_FLCNBL_H - -#include - -#ifndef NVGPU_ACR_H -#warning "acr_flcnbl.h not included from nvgpu_acr.h!" \ - "Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces" -#endif - -/* - * Structure used by the boot-loader to load the rest of the code. This has - * to be filled by NVGPU and copied into DMEM at offset provided in the - * hsflcn_bl_desc.bl_desc_dmem_load_off. - */ -struct flcn_bl_dmem_desc { - u32 reserved[4]; /*Should be the first element..*/ - u32 signature[4]; /*Should be the first element..*/ - u32 ctx_dma; - u32 code_dma_base; - u32 non_sec_code_off; - u32 non_sec_code_size; - u32 sec_code_off; - u32 sec_code_size; - u32 code_entry_point; - u32 data_dma_base; - u32 data_size; - u32 code_dma_base1; - u32 data_dma_base1; -}; - -struct flcn_bl_dmem_desc_v1 { - u32 reserved[4]; /*Should be the first element..*/ - u32 signature[4]; /*Should be the first element..*/ - u32 ctx_dma; - struct falc_u64 code_dma_base; - u32 non_sec_code_off; - u32 non_sec_code_size; - u32 sec_code_off; - u32 sec_code_size; - u32 code_entry_point; - struct falc_u64 data_dma_base; - u32 data_size; - u32 argc; - u32 argv; -}; - -/* - * The header used by NVGPU to figure out code and data sections of bootloader - * - * bl_code_off - Offset of code section in the image - * bl_code_size - Size of code section in the image - * bl_data_off - Offset of data section in the image - * bl_data_size - Size of data section in the image - */ -struct flcn_bl_img_hdr { - u32 bl_code_off; - u32 bl_code_size; - u32 bl_data_off; - u32 bl_data_size; -}; - -/* - * The descriptor used by NVGPU to figure out the requirements of bootloader - * - * bl_start_tag - Starting tag of bootloader - * bl_desc_dmem_load_off - Dmem offset where _def_rm_flcn_bl_dmem_desc - * to be loaded - * bl_img_hdr - Description of the image - */ -struct hsflcn_bl_desc { - u32 bl_start_tag; - u32 bl_desc_dmem_load_off; - struct flcn_bl_img_hdr bl_img_hdr; -}; - -/* - * Legacy structure used by the current PMU/DPU bootloader. - */ -struct loader_config { - u32 dma_idx; - u32 code_dma_base; /* upper 32-bits of 40-bit dma address */ - u32 code_size_total; - u32 code_size_to_load; - u32 code_entry_point; - u32 data_dma_base; /* upper 32-bits of 40-bit dma address */ - u32 data_size; /* initialized data of the application */ - u32 overlay_dma_base; /* upper 32-bits of the 40-bit dma address */ - u32 argc; - u32 argv; - u16 code_dma_base1; /* upper 7 bits of 47-bit dma address */ - u16 data_dma_base1; /* upper 7 bits of 47-bit dma address */ - u16 overlay_dma_base1; /* upper 7 bits of the 47-bit dma address */ -}; - -struct loader_config_v1 { - u32 reserved; - u32 dma_idx; - struct falc_u64 code_dma_base; - u32 code_size_total; - u32 code_size_to_load; - u32 code_entry_point; - struct falc_u64 data_dma_base; - u32 data_size; - struct falc_u64 overlay_dma_base; - u32 argc; - u32 argv; -}; - -/* - * Union of all supported structures used by bootloaders. - */ -union flcn_bl_generic_desc { - struct flcn_bl_dmem_desc bl_dmem_desc; - struct loader_config loader_cfg; -}; - -union flcn_bl_generic_desc_v1 { - struct flcn_bl_dmem_desc_v1 bl_dmem_desc_v1; - struct loader_config_v1 loader_cfg_v1; -}; - -#endif /* NVGPU_ACR_FLCNBL_H */ diff --git a/include/nvgpu/acr/acr_lsfm.h b/include/nvgpu/acr/acr_lsfm.h deleted file mode 100644 index ed58552..0000000 --- a/include/nvgpu/acr/acr_lsfm.h +++ /dev/null @@ -1,328 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_ACR_LSFM_H -#define NVGPU_ACR_LSFM_H - -#ifndef NVGPU_ACR_H -#warning "acr_lsfm.h not included from nvgpu_acr.h!" \ - "Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces" -#endif - -/* - * READ/WRITE masks for WPR region - */ -/* Readable only from level 2 and 3 client */ -#define LSF_WPR_REGION_RMASK (0xC) -/* Writable only from level 2 and 3 client */ -#define LSF_WPR_REGION_WMASK (0xC) -/* Readable only from level 3 client */ -#define LSF_WPR_REGION_RMASK_SUB_WPR_ENABLED (0x8) -/* Writable only from level 3 client */ -#define LSF_WPR_REGION_WMASK_SUB_WPR_ENABLED (0x8) -/* Disallow read mis-match for all clients */ -#define LSF_WPR_REGION_ALLOW_READ_MISMATCH_NO (0x0) -/* Disallow write mis-match for all clients */ -#define LSF_WPR_REGION_ALLOW_WRITE_MISMATCH_NO (0x0) - -/* - * Falcon Id Defines - * Defines a common Light Secure Falcon identifier. - */ -#define LSF_FALCON_ID_PMU (0) -#define LSF_FALCON_ID_GSPLITE (1) -#define LSF_FALCON_ID_FECS (2) -#define LSF_FALCON_ID_GPCCS (3) -#define LSF_FALCON_ID_SEC2 (7) -#define LSF_FALCON_ID_END (11) -#define LSF_FALCON_ID_INVALID (0xFFFFFFFF) - -/* - * Light Secure Falcon Ucode Description Defines - * This structure is prelim and may change as the ucode signing flow evolves. - */ -struct lsf_ucode_desc { - u8 prd_keys[2][16]; - u8 dbg_keys[2][16]; - u32 b_prd_present; - u32 b_dbg_present; - u32 falcon_id; -}; - -struct lsf_ucode_desc_v1 { - u8 prd_keys[2][16]; - u8 dbg_keys[2][16]; - u32 b_prd_present; - u32 b_dbg_present; - u32 falcon_id; - u32 bsupports_versioning; - u32 version; - u32 dep_map_count; - u8 dep_map[LSF_FALCON_ID_END * 2 * 4]; - u8 kdf[16]; -}; - -/* - * Light Secure WPR Header - * Defines state allowing Light Secure Falcon bootstrapping. - */ -struct lsf_wpr_header { - u32 falcon_id; - u32 lsb_offset; - u32 bootstrap_owner; - u32 lazy_bootstrap; - u32 status; -}; - -struct lsf_wpr_header_v1 { - u32 falcon_id; - u32 lsb_offset; - u32 bootstrap_owner; - u32 lazy_bootstrap; - u32 bin_version; - u32 status; -}; - - -/* - * LSF shared SubWpr Header - * - * use_case_id - Shared SubWpr use case ID (updated by nvgpu) - * start_addr - start address of subWpr (updated by nvgpu) - * size_4K - size of subWpr in 4K (updated by nvgpu) - */ -struct lsf_shared_sub_wpr_header { - u32 use_case_id; - u32 start_addr; - u32 size_4K; -}; - -/* shared sub_wpr use case IDs */ -enum { - LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_FRTS_VBIOS_TABLES = 1, - LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_PLAYREADY_SHARED_DATA = 2 -}; - -#define LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX \ - LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_PLAYREADY_SHARED_DATA - -#define LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_INVALID (0xFFFFFFFF) - -#define MAX_SUPPORTED_SHARED_SUB_WPR_USE_CASES \ - LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX - -/* Static sizes of shared subWPRs */ -/* Minimum granularity supported is 4K */ -/* 1MB in 4K */ -#define LSF_SHARED_DATA_SUB_WPR_FRTS_VBIOS_TABLES_SIZE_IN_4K (0x100) -/* 4K */ -#define LSF_SHARED_DATA_SUB_WPR_PLAYREADY_SHARED_DATA_SIZE_IN_4K (0x1) - -/* - * Bootstrap Owner Defines - */ -#define LSF_BOOTSTRAP_OWNER_DEFAULT (LSF_FALCON_ID_PMU) - -/* - * Image Status Defines - */ -#define LSF_IMAGE_STATUS_NONE (0) -#define LSF_IMAGE_STATUS_COPY (1) -#define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED (2) -#define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED (3) -#define LSF_IMAGE_STATUS_VALIDATION_DONE (4) -#define LSF_IMAGE_STATUS_VALIDATION_SKIPPED (5) -#define LSF_IMAGE_STATUS_BOOTSTRAP_READY (6) - -/*Light Secure Bootstrap header related defines*/ -#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_FALSE 0 -#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_TRUE 1 -#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_FALSE 0 -#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_TRUE 4 -#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_TRUE 8 -#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_FALSE 0 - -/* - * Light Secure Bootstrap Header - * Defines state allowing Light Secure Falcon bootstrapping. - */ -struct lsf_lsb_header { - struct lsf_ucode_desc signature; - u32 ucode_off; - u32 ucode_size; - u32 data_size; - u32 bl_code_size; - u32 bl_imem_off; - u32 bl_data_off; - u32 bl_data_size; - u32 app_code_off; - u32 app_code_size; - u32 app_data_off; - u32 app_data_size; - u32 flags; -}; - -struct lsf_lsb_header_v1 { - struct lsf_ucode_desc_v1 signature; - u32 ucode_off; - u32 ucode_size; - u32 data_size; - u32 bl_code_size; - u32 bl_imem_off; - u32 bl_data_off; - u32 bl_data_size; - u32 app_code_off; - u32 app_code_size; - u32 app_data_off; - u32 app_data_size; - u32 flags; -}; - -/* - * Light Secure WPR Content Alignments - */ -#define LSF_WPR_HEADER_ALIGNMENT (256U) -#define LSF_SUB_WPR_HEADER_ALIGNMENT (256U) -#define LSF_LSB_HEADER_ALIGNMENT (256U) -#define LSF_BL_DATA_ALIGNMENT (256U) -#define LSF_BL_DATA_SIZE_ALIGNMENT (256U) -#define LSF_BL_CODE_SIZE_ALIGNMENT (256U) -#define LSF_DATA_SIZE_ALIGNMENT (256U) -#define LSF_CODE_SIZE_ALIGNMENT (256U) - -/* MMU excepts sub_wpr sizes in units of 4K */ -#define SUB_WPR_SIZE_ALIGNMENT (4096U) - -/* - * Maximum WPR Header size - */ -#define LSF_WPR_HEADERS_TOTAL_SIZE_MAX \ - (ALIGN_UP((sizeof(struct lsf_wpr_header_v1) * LSF_FALCON_ID_END), \ - LSF_WPR_HEADER_ALIGNMENT)) -#define LSF_LSB_HEADER_TOTAL_SIZE_MAX (\ - ALIGN_UP(sizeof(struct lsf_lsb_header_v1), LSF_LSB_HEADER_ALIGNMENT)) - -/* Maximum SUB WPR header size */ -#define LSF_SUB_WPR_HEADERS_TOTAL_SIZE_MAX (ALIGN_UP( \ - (sizeof(struct lsf_shared_sub_wpr_header) * \ - LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX), \ - LSF_SUB_WPR_HEADER_ALIGNMENT)) - - -#define LSF_UCODE_DATA_ALIGNMENT 4096 - -/* Defined for 1MB alignment */ -#define SHIFT_1MB (20) -#define SHIFT_4KB (12) - -/* - * Supporting maximum of 2 regions. - * This is needed to pre-allocate space in DMEM - */ -#define NVGPU_FLCN_ACR_MAX_REGIONS (2) -#define LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE (0x200) - -/* - * start_addr - Starting address of region - * end_addr - Ending address of region - * region_id - Region ID - * read_mask - Read Mask - * write_mask - WriteMask - * client_mask - Bit map of all clients currently using this region - */ -struct flcn_acr_region_prop { - u32 start_addr; - u32 end_addr; - u32 region_id; - u32 read_mask; - u32 write_mask; - u32 client_mask; -}; - -struct flcn_acr_region_prop_v1 { - u32 start_addr; - u32 end_addr; - u32 region_id; - u32 read_mask; - u32 write_mask; - u32 client_mask; - u32 shadowmMem_startaddress; -}; - -/* - * no_regions - Number of regions used. - * region_props - Region properties - */ -struct flcn_acr_regions { - u32 no_regions; - struct flcn_acr_region_prop region_props[NVGPU_FLCN_ACR_MAX_REGIONS]; -}; - -struct flcn_acr_regions_v1 { - u32 no_regions; - struct flcn_acr_region_prop_v1 region_props[NVGPU_FLCN_ACR_MAX_REGIONS]; -}; -/* - * reserved_dmem-When the bootstrap owner has done bootstrapping other falcons, - * and need to switch into LS mode, it needs to have its own - * actual DMEM image copied into DMEM as part of LS setup. If - * ACR desc is at location 0, it will definitely get overwritten - * causing data corruption. Hence we are reserving 0x200 bytes - * to give room for any loading data. NOTE: This has to be the - * first member always - * signature - Signature of ACR ucode. - * wpr_region_id - Region ID holding the WPR header and its details - * wpr_offset - Offset from the WPR region holding the wpr header - * regions - Region descriptors - * nonwpr_ucode_blob_start -stores non-WPR start where kernel stores ucode blob - * nonwpr_ucode_blob_end -stores non-WPR end where kernel stores ucode blob - */ -struct flcn_acr_desc { - union { - u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)]; - u32 signatures[4]; - } ucode_reserved_space; - /*Always 1st*/ - u32 wpr_region_id; - u32 wpr_offset; - u32 mmu_mem_range; - struct flcn_acr_regions regions; - u32 nonwpr_ucode_blob_size; - u64 nonwpr_ucode_blob_start; -}; - -struct flcn_acr_desc_v1 { - union { - u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)]; - } ucode_reserved_space; - u32 signatures[4]; - /*Always 1st*/ - u32 wpr_region_id; - u32 wpr_offset; - u32 mmu_mem_range; - struct flcn_acr_regions_v1 regions; - u32 nonwpr_ucode_blob_size; - u64 nonwpr_ucode_blob_start; - u32 dummy[4]; /* ACR_BSI_VPR_DESC */ -}; - - -#endif /* NVGPU_ACR_LSFM_H */ diff --git a/include/nvgpu/acr/acr_objflcn.h b/include/nvgpu/acr/acr_objflcn.h deleted file mode 100644 index 57b43c8..0000000 --- a/include/nvgpu/acr/acr_objflcn.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_ACR_OBJFLCN_H -#define NVGPU_ACR_OBJFLCN_H - -#ifndef NVGPU_ACR_H -#warning "acr_objflcn.h not included from nvgpu_acr.h!" \ - "Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces" -#endif - -struct flcn_ucode_img { - u32 *header; /* only some falcons have header */ - u32 *data; - struct pmu_ucode_desc *desc; /* only some falcons have descriptor */ - u32 data_size; - void *fw_ver; /* CTRL_GPU_GET_FIRMWARE_VERSION_PARAMS struct */ - u8 load_entire_os_data; /* load the whole osData section at boot time.*/ - /* NULL if not a light secure falcon.*/ - struct lsf_ucode_desc *lsf_desc; - /* True if there a resources to freed by the client. */ - u8 free_res_allocs; - u32 flcn_inst; -}; - -struct flcn_ucode_img_v1 { - u32 *header; - u32 *data; - struct pmu_ucode_desc_v1 *desc; - u32 data_size; - void *fw_ver; - u8 load_entire_os_data; - struct lsf_ucode_desc_v1 *lsf_desc; - u8 free_res_allocs; - u32 flcn_inst; -}; - -/* - * Falcon UCODE header index. - */ -#define FLCN_NL_UCODE_HDR_OS_CODE_OFF_IND (0) -#define FLCN_NL_UCODE_HDR_OS_CODE_SIZE_IND (1) -#define FLCN_NL_UCODE_HDR_OS_DATA_OFF_IND (2) -#define FLCN_NL_UCODE_HDR_OS_DATA_SIZE_IND (3) -#define FLCN_NL_UCODE_HDR_NUM_APPS_IND (4) - -/* - * There are total N number of Apps with code and offset defined in UCODE header - * This macro provides the CODE and DATA offset and size of Ath application. - */ -#define FLCN_NL_UCODE_HDR_APP_CODE_START_IND (5) -#define FLCN_NL_UCODE_HDR_APP_CODE_OFF_IND(N, A) \ - (FLCN_NL_UCODE_HDR_APP_CODE_START_IND + (A*2)) -#define FLCN_NL_UCODE_HDR_APP_CODE_SIZE_IND(N, A) \ - (FLCN_NL_UCODE_HDR_APP_CODE_START_IND + (A*2) + 1) -#define FLCN_NL_UCODE_HDR_APP_CODE_END_IND(N) \ - (FLCN_NL_UCODE_HDR_APP_CODE_START_IND + (N*2) - 1) - -#define FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) \ - (FLCN_NL_UCODE_HDR_APP_CODE_END_IND(N) + 1) -#define FLCN_NL_UCODE_HDR_APP_DATA_OFF_IND(N, A) \ - (FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + (A*2)) -#define FLCN_NL_UCODE_HDR_APP_DATA_SIZE_IND(N, A) \ - (FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + (A*2) + 1) -#define FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) \ - (FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + (N*2) - 1) - -#define FLCN_NL_UCODE_HDR_OS_OVL_OFF_IND(N) \ - (FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) + 1) -#define FLCN_NL_UCODE_HDR_OS_OVL_SIZE_IND(N) \ - (FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) + 2) - -#endif /* NVGPU_ACR_OBJFLCN_H */ diff --git a/include/nvgpu/acr/acr_objlsfm.h b/include/nvgpu/acr/acr_objlsfm.h deleted file mode 100644 index e3769bb..0000000 --- a/include/nvgpu/acr/acr_objlsfm.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_ACR_OBJLSFM_H -#define NVGPU_ACR_OBJLSFM_H - -#ifndef NVGPU_ACR_H -#warning "acr_objlsfm.h not included from nvgpu_acr.h!" \ - "Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces" -#endif - -#include "acr_flcnbl.h" -#include "acr_objflcn.h" - -/* - * LSFM Managed Ucode Image - * next : Next image the list, NULL if last. - * wpr_header : WPR header for this ucode image - * lsb_header : LSB header for this ucode image - * bl_gen_desc : Bootloader generic desc structure for this ucode image - * bl_gen_desc_size : Sizeof bootloader desc structure for this ucode image - * full_ucode_size : Surface size required for final ucode image - * ucode_img : Ucode image info - */ -struct lsfm_managed_ucode_img { - struct lsfm_managed_ucode_img *next; - struct lsf_wpr_header wpr_header; - struct lsf_lsb_header lsb_header; - union flcn_bl_generic_desc bl_gen_desc; - u32 bl_gen_desc_size; - u32 full_ucode_size; - struct flcn_ucode_img ucode_img; -}; - -struct lsfm_managed_ucode_img_v2 { - struct lsfm_managed_ucode_img_v2 *next; - struct lsf_wpr_header_v1 wpr_header; - struct lsf_lsb_header_v1 lsb_header; - union flcn_bl_generic_desc_v1 bl_gen_desc; - u32 bl_gen_desc_size; - u32 full_ucode_size; - struct flcn_ucode_img_v1 ucode_img; -}; - -/* - * Defines the structure used to contain all generic information related to - * the LSFM. - * Contains the Light Secure Falcon Manager (LSFM) feature related data. - */ -struct ls_flcn_mgr { - u16 managed_flcn_cnt; - u32 wpr_size; - u32 disable_mask; - struct lsfm_managed_ucode_img *ucode_img_list; - void *wpr_client_req_state;/*PACR_CLIENT_REQUEST_STATE originally*/ -}; - -/* - * LSFM SUB WPRs struct - * pnext : Next entry in the list, NULL if last - * sub_wpr_header : SubWpr Header struct - */ -struct lsfm_sub_wpr { - struct lsfm_sub_wpr *pnext; - struct lsf_shared_sub_wpr_header sub_wpr_header; -}; - -struct ls_flcn_mgr_v1 { - u16 managed_flcn_cnt; - u32 wpr_size; - u32 disable_mask; - struct lsfm_managed_ucode_img_v2 *ucode_img_list; - void *wpr_client_req_state;/*PACR_CLIENT_REQUEST_STATE originally*/ - u16 managed_sub_wpr_count; - struct lsfm_sub_wpr *psub_wpr_list; -}; - - -#endif /* NVGPU_ACR_OBJLSFM_H */ diff --git a/include/nvgpu/acr/nvgpu_acr.h b/include/nvgpu/acr/nvgpu_acr.h deleted file mode 100644 index cdb7bb8..0000000 --- a/include/nvgpu/acr/nvgpu_acr.h +++ /dev/null @@ -1,192 +0,0 @@ -/* - * Copyright (c) 2016-2021, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_ACR_H -#define NVGPU_ACR_H - -#include - -#include "gk20a/mm_gk20a.h" - -#include "acr_lsfm.h" -#include "acr_flcnbl.h" -#include "acr_objlsfm.h" -#include "acr_objflcn.h" - -struct nvgpu_firmware; -struct gk20a; -struct hs_acr_ops; -struct hs_acr; -struct nvgpu_acr; - -#define HSBIN_ACR_BL_UCODE_IMAGE "pmu_bl.bin" -#define GM20B_HSBIN_ACR_PROD_UCODE "nv_acr_ucode_prod.bin" -#define GM20B_HSBIN_ACR_DBG_UCODE "nv_acr_ucode_dbg.bin" -#define HSBIN_ACR_UCODE_IMAGE "acr_ucode.bin" -#define HSBIN_ACR_PROD_UCODE "acr_ucode_prod.bin" -#define HSBIN_ACR_DBG_UCODE "acr_ucode_dbg.bin" -#define HSBIN_ACR_AHESASC_PROD_UCODE "acr_ahesasc_prod_ucode.bin" -#define HSBIN_ACR_ASB_PROD_UCODE "acr_asb_prod_ucode.bin" -#define HSBIN_ACR_AHESASC_DBG_UCODE "acr_ahesasc_dbg_ucode.bin" -#define HSBIN_ACR_ASB_DBG_UCODE "acr_asb_dbg_ucode.bin" - -#define LSF_SEC2_UCODE_IMAGE_BIN "sec2_ucode_image.bin" -#define LSF_SEC2_UCODE_DESC_BIN "sec2_ucode_desc.bin" -#define LSF_SEC2_UCODE_SIG_BIN "sec2_sig.bin" - -#define MAX_SUPPORTED_LSFM 3 /*PMU, FECS, GPCCS*/ - -#define ACR_COMPLETION_TIMEOUT_MS 10000 /*in msec */ - -#define PMU_SECURE_MODE (0x1) -#define PMU_LSFM_MANAGED (0x2) - -struct bin_hdr { - /* 0x10de */ - u32 bin_magic; - /* versioning of bin format */ - u32 bin_ver; - /* Entire image size including this header */ - u32 bin_size; - /* - * Header offset of executable binary metadata, - * start @ offset- 0x100 * - */ - u32 header_offset; - /* - * Start of executable binary data, start @ - * offset- 0x200 - */ - u32 data_offset; - /* Size of executable binary */ - u32 data_size; -}; - -struct acr_fw_header { - u32 sig_dbg_offset; - u32 sig_dbg_size; - u32 sig_prod_offset; - u32 sig_prod_size; - u32 patch_loc; - u32 patch_sig; - u32 hdr_offset; /* This header points to acr_ucode_header_t210_load */ - u32 hdr_size; /* Size of above header */ -}; - -struct wpr_carveout_info { - u64 wpr_base; - u64 nonwpr_base; - u64 size; -}; - -/* ACR interfaces */ - -struct hs_flcn_bl { - char *bl_fw_name; - struct nvgpu_firmware *hs_bl_fw; - struct hsflcn_bl_desc *hs_bl_desc; - struct bin_hdr *hs_bl_bin_hdr; - struct nvgpu_mem hs_bl_ucode; -}; - -struct hs_acr { - u32 acr_type; - - /* HS bootloader to validate & load ACR ucode */ - struct hs_flcn_bl acr_hs_bl; - - /* ACR ucode */ - char *acr_fw_name; - struct nvgpu_firmware *acr_fw; - struct nvgpu_mem acr_ucode; - - union { - struct flcn_bl_dmem_desc bl_dmem_desc; - struct flcn_bl_dmem_desc_v1 bl_dmem_desc_v1; - }; - - void *ptr_bl_dmem_desc; - u32 bl_dmem_desc_size; - - union{ - struct flcn_acr_desc *acr_dmem_desc; - struct flcn_acr_desc_v1 *acr_dmem_desc_v1; - }; - - /* Falcon used to execute ACR ucode */ - struct nvgpu_falcon *acr_flcn; - - int (*acr_flcn_setup_hw_and_bl_bootstrap)(struct gk20a *g, - struct hs_acr *acr_desc, - struct nvgpu_falcon_bl_info *bl_info); -}; - -#define ACR_DEFAULT 0U -#define ACR_AHESASC 1U -#define ACR_ASB 2U - -struct nvgpu_acr { - struct gk20a *g; - - u32 bootstrap_owner; - u32 max_supported_lsfm; - u32 capabilities; - - /* - * non-wpr space to hold LSF ucodes, - * ACR does copy ucode from non-wpr to wpr - */ - struct nvgpu_mem ucode_blob; - /* - * Even though this mem_desc wouldn't be used, - * the wpr region needs to be reserved in the - * allocator in dGPU case. - */ - struct nvgpu_mem wpr_dummy; - - /* ACR member for different types of ucode */ - /* For older dgpu/tegra ACR cuode */ - struct hs_acr acr; - /* ACR load split feature support */ - struct hs_acr acr_ahesasc; - struct hs_acr acr_asb; - - u32 pmu_args; - struct nvgpu_firmware *pmu_fw; - struct nvgpu_firmware *pmu_desc; - - int (*prepare_ucode_blob)(struct gk20a *g, struct nvgpu_acr *acr); - void (*get_wpr_info)(struct gk20a *g, struct wpr_carveout_info *inf); - int (*alloc_blob_space)(struct gk20a *g, size_t size, - struct nvgpu_mem *mem); - int (*patch_wpr_info_to_ucode)(struct gk20a *g, struct nvgpu_acr *acr, - struct hs_acr *acr_desc, bool is_recovery); - int (*acr_fill_bl_dmem_desc)(struct gk20a *g, - struct nvgpu_acr *acr, struct hs_acr *acr_desc, - u32 *acr_ucode_header); - int (*bootstrap_hs_acr)(struct gk20a *g, struct nvgpu_acr *acr, - struct hs_acr *acr_desc); - - void (*remove_support)(struct nvgpu_acr *acr); -}; -#endif /* NVGPU_ACR_H */ - -- cgit v1.2.2