From f347fde22f1297e4f022600d201780d5ead78114 Mon Sep 17 00:00:00 2001 From: Joshua Bakita Date: Wed, 25 Sep 2024 16:09:09 -0400 Subject: Delete no-longer-needed nvgpu headers The dependency on these was removed in commit 8340d234. --- include/gk20a/mm_gk20a.h | 155 ----------------------------------------------- 1 file changed, 155 deletions(-) delete mode 100644 include/gk20a/mm_gk20a.h (limited to 'include/gk20a/mm_gk20a.h') diff --git a/include/gk20a/mm_gk20a.h b/include/gk20a/mm_gk20a.h deleted file mode 100644 index 76a1621..0000000 --- a/include/gk20a/mm_gk20a.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef MM_GK20A_H -#define MM_GK20A_H - -#include -#include -#include -#include -#include -#include - -enum gk20a_mem_rw_flag; - -struct patch_desc { - struct nvgpu_mem mem; - u32 data_count; -}; - -struct zcull_ctx_desc { - u64 gpu_va; - u32 ctx_attr; - u32 ctx_sw_mode; -}; - -struct pm_ctx_desc { - struct nvgpu_mem mem; - u32 pm_mode; -}; - -struct compbit_store_desc { - struct nvgpu_mem mem; - - /* The value that is written to the hardware. This depends on - * on the number of ltcs and is not an address. */ - u64 base_hw; -}; - -struct gk20a_buffer_state { - struct nvgpu_list_node list; - - /* The valid compbits and the fence must be changed atomically. */ - struct nvgpu_mutex lock; - - /* Offset of the surface within the dma-buf whose state is - * described by this struct (one dma-buf can contain multiple - * surfaces with different states). */ - size_t offset; - - /* A bitmask of valid sets of compbits (0 = uncompressed). */ - u32 valid_compbits; - - /* The ZBC color used on this buffer. */ - u32 zbc_color; - - /* This struct reflects the state of the buffer when this - * fence signals. */ - struct gk20a_fence *fence; -}; - -static inline struct gk20a_buffer_state * -gk20a_buffer_state_from_list(struct nvgpu_list_node *node) -{ - return (struct gk20a_buffer_state *) - ((uintptr_t)node - offsetof(struct gk20a_buffer_state, list)); -}; - -struct gk20a; -struct channel_gk20a; - -int gk20a_mm_fb_flush(struct gk20a *g); -void gk20a_mm_l2_flush(struct gk20a *g, bool invalidate); -void gk20a_mm_cbc_clean(struct gk20a *g); -void gk20a_mm_l2_invalidate(struct gk20a *g); - -#define dev_from_vm(vm) dev_from_gk20a(vm->mm->g) - -void gk20a_mm_ltc_isr(struct gk20a *g); - -bool gk20a_mm_mmu_debug_mode_enabled(struct gk20a *g); - -int gk20a_alloc_inst_block(struct gk20a *g, struct nvgpu_mem *inst_block); -void gk20a_init_inst_block(struct nvgpu_mem *inst_block, struct vm_gk20a *vm, - u32 big_page_size); -int gk20a_init_mm_setup_hw(struct gk20a *g); - -u64 gk20a_locked_gmmu_map(struct vm_gk20a *vm, - u64 map_offset, - struct nvgpu_sgt *sgt, - u64 buffer_offset, - u64 size, - u32 pgsz_idx, - u8 kind_v, - u32 ctag_offset, - u32 flags, - enum gk20a_mem_rw_flag rw_flag, - bool clear_ctags, - bool sparse, - bool priv, - struct vm_gk20a_mapping_batch *batch, - enum nvgpu_aperture aperture); - -void gk20a_locked_gmmu_unmap(struct vm_gk20a *vm, - u64 vaddr, - u64 size, - u32 pgsz_idx, - bool va_allocated, - enum gk20a_mem_rw_flag rw_flag, - bool sparse, - struct vm_gk20a_mapping_batch *batch); - -/* vm-as interface */ -struct nvgpu_as_alloc_space_args; -struct nvgpu_as_free_space_args; -int gk20a_vm_release_share(struct gk20a_as_share *as_share); -int gk20a_vm_bind_channel(struct vm_gk20a *vm, struct channel_gk20a *ch); - -void pde_range_from_vaddr_range(struct vm_gk20a *vm, - u64 addr_lo, u64 addr_hi, - u32 *pde_lo, u32 *pde_hi); -u32 gk20a_mm_get_iommu_bit(struct gk20a *g); - -const struct gk20a_mmu_level *gk20a_mm_get_mmu_levels(struct gk20a *g, - u32 big_page_size); -void gk20a_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *mem, - struct vm_gk20a *vm); - -extern const struct gk20a_mmu_level gk20a_mm_levels_64k[]; -extern const struct gk20a_mmu_level gk20a_mm_levels_128k[]; - -u32 gk20a_get_pde_pgsz(struct gk20a *g, const struct gk20a_mmu_level *l, - struct nvgpu_gmmu_pd *pd, u32 pd_idx); -u32 gk20a_get_pte_pgsz(struct gk20a *g, const struct gk20a_mmu_level *l, - struct nvgpu_gmmu_pd *pd, u32 pd_idx); -#endif /* MM_GK20A_H */ -- cgit v1.2.2