From 2c5337a24f7f2d02989dfb733c55d6d8c7e90493 Mon Sep 17 00:00:00 2001 From: Joshua Bakita Date: Sun, 29 Oct 2023 13:07:40 -0400 Subject: Update includes to L4T r32.7.4 and drop nvgpu/gk20a.h dependency Also add instructions for updating `include/`. These files are now only needed to build on Linux 4.9-based Tegra platforms. --- include/gk20a/gr_gk20a.c | 108 +++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 100 insertions(+), 8 deletions(-) (limited to 'include/gk20a/gr_gk20a.c') diff --git a/include/gk20a/gr_gk20a.c b/include/gk20a/gr_gk20a.c index 7bcf528..1eda853 100644 --- a/include/gk20a/gr_gk20a.c +++ b/include/gk20a/gr_gk20a.c @@ -1,7 +1,7 @@ /* * GK20A Graphics * - * Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -121,6 +121,83 @@ int gr_gk20a_get_ctx_id(struct gk20a *g, return 0; } +void gk20a_gpccs_dump_falcon_stats(struct gk20a *g) +{ + unsigned int i; + + nvgpu_err(g, "gr_gpc0_gpccs_falcon_irqstat : %d", + gk20a_readl(g, gr_gpc0_gpccs_falcon_irqstat_r())); + nvgpu_err(g, "gr_gpc0_gpccs_falcon_irqmode : %d", + gk20a_readl(g, gr_gpc0_gpccs_falcon_irqmode_r())); + nvgpu_err(g, "gr_gpc0_gpccs_falcon_irqmask : %d", + gk20a_readl(g, gr_gpc0_gpccs_falcon_irqmask_r())); + nvgpu_err(g, "gr_gpc0_gpccs_falcon_irqdest : %d", + gk20a_readl(g, gr_gpc0_gpccs_falcon_irqdest_r())); + nvgpu_err(g, "gr_gpc0_gpccs_falcon_debug1 : %d", + gk20a_readl(g, gr_gpc0_gpccs_falcon_debug1_r())); + nvgpu_err(g, "gr_gpc0_gpccs_falcon_debuginfo : %d", + gk20a_readl(g, gr_gpc0_gpccs_falcon_debuginfo_r())); + nvgpu_err(g, "gr_gpc0_gpccs_falcon_engctl : %d", + gk20a_readl(g, gr_gpc0_gpccs_falcon_engctl_r())); + nvgpu_err(g, "gr_gpc0_gpccs_falcon_curctx : %d", + gk20a_readl(g, gr_gpc0_gpccs_falcon_curctx_r())); + nvgpu_err(g, "gr_gpc0_gpccs_falcon_nxtctx : %d", + gk20a_readl(g, gr_gpc0_gpccs_falcon_nxtctx_r())); + nvgpu_err(g, "gr_gpc0_gpccs_ctxsw_status_1 : %d", + gk20a_readl(g, gr_gpc0_gpccs_ctxsw_status_1_r())); + + for (i = 0; i < g->ops.gr.gpc0_gpccs_ctxsw_mailbox_size(); i++) { + nvgpu_err(g, "gr_gpc0_gpccs_ctxsw_mailbox_r(%d) : 0x%x", + i, gk20a_readl(g, gr_gpc0_gpccs_ctxsw_mailbox_r(i))); + } + + + gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(), + gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() | + gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_IMB)); + nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_IMB : 0x%x", + gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r())); + + gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(), + gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() | + gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_DMB)); + nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_DMB : 0x%x", + gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r())); + + gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(), + gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() | + gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_CSW)); + nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_CSW : 0x%x", + gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r())); + + gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(), + gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() | + gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_CTX)); + nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_CTX : 0x%x", + gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r())); + + gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(), + gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() | + gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_EXCI)); + nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_EXCI : 0x%x", + gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r())); + + + for (i = 0; i < 4U; i++) { + gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(), + gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() | + gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_PC)); + nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_PC : 0x%x", + gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r())); + + gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(), + gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() | + gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_SP)); + nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_SP : 0x%x", + gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r())); + } +} + void gk20a_fecs_dump_falcon_stats(struct gk20a *g) { unsigned int i; @@ -527,6 +604,7 @@ int gr_gk20a_ctx_wait_ucode(struct gk20a *g, u32 mailbox_id, "timeout waiting on mailbox=%d value=0x%08x", mailbox_id, reg); gk20a_fecs_dump_falcon_stats(g); + gk20a_gpccs_dump_falcon_stats(g); gk20a_gr_debug_dump(g); return -1; } else if (check == WAIT_UCODE_ERROR) { @@ -534,6 +612,7 @@ int gr_gk20a_ctx_wait_ucode(struct gk20a *g, u32 mailbox_id, "ucode method failed on mailbox=%d value=0x%08x", mailbox_id, reg); gk20a_fecs_dump_falcon_stats(g); + gk20a_gpccs_dump_falcon_stats(g); return -1; } @@ -1583,6 +1662,10 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g, sw_ctx_load->l[i].value); } + if (g->ops.gr.disable_rd_coalesce) { + g->ops.gr.disable_rd_coalesce(g); + } + if (g->ops.gr.init_preemption_state) { g->ops.gr.init_preemption_state(g); } @@ -4625,16 +4708,16 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g) g->ops.fb.init_cbc(g, gr); } - if (g->ops.gr.disable_rd_coalesce) { - g->ops.gr.disable_rd_coalesce(g); - } - /* load ctx init */ for (i = 0; i < sw_ctx_load->count; i++) { gk20a_writel(g, sw_ctx_load->l[i].addr, sw_ctx_load->l[i].value); } + if (g->ops.gr.disable_rd_coalesce) { + g->ops.gr.disable_rd_coalesce(g); + } + err = gr_gk20a_wait_idle(g, gk20a_get_gr_idle_timeout(g), GR_IDLE_CHECK_DEFAULT); if (err != 0U) { @@ -5297,9 +5380,10 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch, } else if ((gr_fecs_intr & gr_fecs_host_int_status_watchdog_active_f()) != 0U) { /* currently, recovery is not initiated */ - nvgpu_err(g, "fecs watchdog triggered for channel %u, " - "cannot ctxsw anymore !!", chid); + nvgpu_err(g, "fecs watchdog triggered for channel %u", chid); gk20a_fecs_dump_falcon_stats(g); + gk20a_gpccs_dump_falcon_stats(g); + gk20a_gr_debug_dump(g); } else if ((gr_fecs_intr & gr_fecs_host_int_status_ctxsw_intr_f(CTXSW_INTR0)) != 0U) { u32 mailbox_value = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(6)); @@ -5321,8 +5405,9 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch, } else { nvgpu_err(g, "unhandled fecs error interrupt 0x%08x for channel %u", - gr_fecs_intr, ch->chid); + gr_fecs_intr, chid); gk20a_fecs_dump_falcon_stats(g); + gk20a_gpccs_dump_falcon_stats(g); } gk20a_writel(g, gr_fecs_host_int_clear_r(), gr_fecs_intr); @@ -8851,6 +8936,10 @@ int gr_gk20a_wait_for_pause(struct gk20a *g, struct nvgpu_warpstate *w_state) u32 gpc, tpc, sm, sm_id; u32 global_mask; + if (!g->ops.gr.get_sm_no_lock_down_hww_global_esr_mask || + !g->ops.gr.lock_down_sm || !g->ops.gr.bpt_reg_info) + return -EINVAL; + /* Wait for the SMs to reach full stop. This condition is: * 1) All SMs with valid warps must be in the trap handler (SM_IN_TRAP_MODE) * 2) All SMs in the trap handler must have equivalent VALID and PAUSED warp @@ -8908,6 +8997,9 @@ int gr_gk20a_clear_sm_errors(struct gk20a *g) u32 global_esr; u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC); + if (!g->ops.gr.get_sm_hww_global_esr || !g->ops.gr.clear_sm_hww) + return -EINVAL; + for (gpc = 0; gpc < gr->gpc_count; gpc++) { /* check if any tpc has an exception */ -- cgit v1.2.2