From 01e6fac4d61fdd7fff5433942ec93fc2ea1e4df1 Mon Sep 17 00:00:00 2001 From: Joshua Bakita Date: Wed, 28 Jun 2023 18:24:25 -0400 Subject: Include nvgpu headers These are needed to build on NVIDIA's Jetson boards for the time being. Only a couple structs are required, so it should be fairly easy to remove this dependency at some point in the future. --- include/ctrl/ctrlboardobj.h | 89 +++++++++++++++++++ include/ctrl/ctrlclk.h | 212 ++++++++++++++++++++++++++++++++++++++++++++ include/ctrl/ctrlclkavfs.h | 112 +++++++++++++++++++++++ include/ctrl/ctrlperf.h | 103 +++++++++++++++++++++ include/ctrl/ctrlpmgr.h | 98 ++++++++++++++++++++ include/ctrl/ctrltherm.h | 33 +++++++ include/ctrl/ctrlvolt.h | 143 ++++++++++++++++++++++++++++++ 7 files changed, 790 insertions(+) create mode 100644 include/ctrl/ctrlboardobj.h create mode 100644 include/ctrl/ctrlclk.h create mode 100644 include/ctrl/ctrlclkavfs.h create mode 100644 include/ctrl/ctrlperf.h create mode 100644 include/ctrl/ctrlpmgr.h create mode 100644 include/ctrl/ctrltherm.h create mode 100644 include/ctrl/ctrlvolt.h (limited to 'include/ctrl') diff --git a/include/ctrl/ctrlboardobj.h b/include/ctrl/ctrlboardobj.h new file mode 100644 index 0000000..8f57e88 --- /dev/null +++ b/include/ctrl/ctrlboardobj.h @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_CTRLBOARDOBJ_H +#define NVGPU_CTRLBOARDOBJ_H + +struct ctrl_boardobj { + u8 type; +}; + +#define CTRL_BOARDOBJGRP_TYPE_INVALID 0x00U +#define CTRL_BOARDOBJGRP_TYPE_E32 0x01U +#define CTRL_BOARDOBJGRP_TYPE_E255 0x02U + +#define CTRL_BOARDOBJGRP_E32_MAX_OBJECTS 32U + +#define CTRL_BOARDOBJGRP_E255_MAX_OBJECTS 255U + +#define CTRL_BOARDOBJ_MAX_BOARD_OBJECTS \ + CTRL_BOARDOBJGRP_E32_MAX_OBJECTS + +#define CTRL_BOARDOBJ_IDX_INVALID 255U + +#define CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE 32U + +#define CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX(_bit) \ + ((_bit) / CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE) + +#define CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_OFFSET(_bit) \ + ((_bit) % CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE) + +#define CTRL_BOARDOBJGRP_MASK_DATA_SIZE(_bits) \ + (CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX((_bits) - 1U) + 1U) + + +#define CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE 1U +#define CTRL_BOARDOBJGRP_MASK_ARRAY_EXTENSION_SIZE(_bits) \ + (CTRL_BOARDOBJGRP_MASK_DATA_SIZE(_bits) - \ + CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE) + +struct ctrl_boardobjgrp_mask { + u32 data[1]; +}; + +struct ctrl_boardobjgrp_mask_e32 { + struct ctrl_boardobjgrp_mask super; +}; + +struct ctrl_boardobjgrp_mask_e255 { + struct ctrl_boardobjgrp_mask super; + u32 data_e255[7]; +}; + +struct ctrl_boardobjgrp_super { + struct ctrl_boardobjgrp_mask obj_mask; +}; + +struct ctrl_boardobjgrp_e32 { + struct ctrl_boardobjgrp_mask_e32 obj_mask; +}; + +struct CTRL_boardobjgrp_e255 { + struct ctrl_boardobjgrp_mask_e255 obj_mask; +}; + +struct ctrl_boardobjgrp { + u32 obj_mask; +}; + +#endif /* NVGPU_CTRLBOARDOBJ_H */ diff --git a/include/ctrl/ctrlclk.h b/include/ctrl/ctrlclk.h new file mode 100644 index 0000000..fbd5677 --- /dev/null +++ b/include/ctrl/ctrlclk.h @@ -0,0 +1,212 @@ +/* + * general p state infrastructure + * + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_CTRLCLK_H +#define NVGPU_CTRLCLK_H + +#include "ctrlboardobj.h" +#include "ctrlclkavfs.h" +#include "ctrlvolt.h" + +#define CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS 4 + +/* valid clock domain values */ +#define CTRL_CLK_DOMAIN_MCLK (0x00000010) +#define CTRL_CLK_DOMAIN_HOSTCLK (0x00000020) +#define CTRL_CLK_DOMAIN_DISPCLK (0x00000040) +#define CTRL_CLK_DOMAIN_GPC2CLK (0x00010000) +#define CTRL_CLK_DOMAIN_XBAR2CLK (0x00040000) +#define CTRL_CLK_DOMAIN_SYS2CLK (0x00800000) +#define CTRL_CLK_DOMAIN_HUB2CLK (0x01000000) +#define CTRL_CLK_DOMAIN_PWRCLK (0x00080000) +#define CTRL_CLK_DOMAIN_NVDCLK (0x00100000) +#define CTRL_CLK_DOMAIN_PCIEGENCLK (0x00200000) + +#define CTRL_CLK_DOMAIN_GPCCLK (0x00000001) +#define CTRL_CLK_DOMAIN_XBARCLK (0x00000002) +#define CTRL_CLK_DOMAIN_SYSCLK (0x00000004) +#define CTRL_CLK_DOMAIN_HUBCLK (0x00000008) + +#define CTRL_CLK_CLK_DOMAIN_TYPE_3X 0x01 +#define CTRL_CLK_CLK_DOMAIN_TYPE_3X_FIXED 0x02 +#define CTRL_CLK_CLK_DOMAIN_TYPE_3X_PROG 0x03 +#define CTRL_CLK_CLK_DOMAIN_TYPE_3X_MASTER 0x04 +#define CTRL_CLK_CLK_DOMAIN_TYPE_3X_SLAVE 0x05 +#define CTRL_CLK_CLK_DOMAIN_TYPE_30_PROG 0x06 +#define CTRL_CLK_CLK_DOMAIN_TYPE_35_MASTER 0x07 +#define CTRL_CLK_CLK_DOMAIN_TYPE_35_SLAVE 0x08 +#define CTRL_CLK_CLK_DOMAIN_TYPE_35_PROG 0x09 + +#define CTRL_CLK_CLK_DOMAIN_3X_PROG_ORDERING_INDEX_INVALID 0xFF +#define CTRL_CLK_CLK_DOMAIN_INDEX_INVALID 0xFF + +#define CTRL_CLK_CLK_PROG_TYPE_1X 0x01 +#define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER 0x02 +#define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_RATIO 0x03 +#define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_TABLE 0x04 +#define CTRL_CLK_CLK_PROG_TYPE_UNKNOWN 255 + +/*! + * Enumeration of CLK_PROG source types. + */ +#define CTRL_CLK_PROG_1X_SOURCE_PLL 0x00 +#define CTRL_CLK_PROG_1X_SOURCE_ONE_SOURCE 0x01 +#define CTRL_CLK_PROG_1X_SOURCE_FLL 0x02 +#define CTRL_CLK_PROG_1X_SOURCE_INVALID 255 + +#define CTRL_CLK_CLK_PROG_1X_MASTER_VF_ENTRY_MAX_ENTRIES 4 +#define CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES 6 + +#define CTRL_CLK_CLK_VF_POINT_IDX_INVALID 255 + +#define CTRL_CLK_CLK_VF_POINT_TYPE_FREQ 0x01 +#define CTRL_CLK_CLK_VF_POINT_TYPE_VOLT 0x02 +#define CTRL_CLK_CLK_VF_POINT_TYPE_UNKNOWN 255 + +struct ctrl_clk_clk_prog_1x_master_source_fll { + u32 base_vfsmooth_volt_uv; + u32 max_vf_ramprate; + u32 max_freq_stepsize_mhz; +}; + +union ctrl_clk_clk_prog_1x_master_source_data { + struct ctrl_clk_clk_prog_1x_master_source_fll fll; +}; + +struct ctrl_clk_clk_vf_point_info_freq { + u16 freq_mhz; +}; + +struct ctrl_clk_clk_vf_point_info_volt { + u32 sourceVoltageuV; + u8 vfGainVfeEquIdx; + u8 clkDomainIdx; +}; + +struct ctrl_clk_clk_prog_1x_master_vf_entry { + u8 vfe_idx; + u8 gain_vfe_idx; + u8 vf_point_idx_first; + u8 vf_point_idx_last; +}; + +struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry { + u8 clk_dom_idx; + u8 ratio; +}; + +struct ctrl_clk_clk_prog_1x_master_table_slave_entry { + u8 clk_dom_idx; + u16 freq_mhz; +}; + +struct ctrl_clk_clk_prog_1x_source_pll { + u8 pll_idx; + u8 freq_step_size_mhz; +}; + +union ctrl_clk_freq_delta_data { + s32 delta_khz; + s16 delta_percent; +}; +struct ctrl_clk_freq_delta { + u8 type; + union ctrl_clk_freq_delta_data data; +}; + +struct ctrl_clk_clk_delta { + struct ctrl_clk_freq_delta freq_delta; + int volt_deltauv[CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS]; +}; + +struct ctrl_clk_vin_v10 { + u32 slope; + u32 intercept; +}; + +struct ctrl_clk_vin_v20 { + s8 offset; + s8 gain; +}; + +union ctrl_clk_vin_data_v20 { + struct ctrl_clk_vin_v10 cal_v10; + struct ctrl_clk_vin_v20 cal_v20; +}; + +struct ctrl_clk_vin_device_info_data_v10 { + struct ctrl_clk_vin_v10 vin_cal; +}; + +struct ctrl_clk_vin_device_info_data_v20 { + u8 cal_type; + union ctrl_clk_vin_data_v20 vin_cal; +}; + +union ctrl_clk_clk_prog_1x_source_data { + struct ctrl_clk_clk_prog_1x_source_pll pll; +}; + +struct ctrl_clk_vf_pair { + u16 freq_mhz; + u32 voltage_uv; +}; + +struct ctrl_clk_clk_domain_list_item { + u32 clk_domain; + u32 clk_freq_khz; + u32 clk_flags; + u8 current_regime_id; + u8 target_regime_id; +}; + +struct ctrl_clk_clk_domain_list_item_v1 { + u32 clk_domain; + u32 clk_freq_khz; + u8 regime_id; + u8 source; +}; + +struct ctrl_clk_clk_domain_list { + u8 num_domains; + struct ctrl_clk_clk_domain_list_item_v1 + clk_domains[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS]; +}; + +#define CTRL_CLK_VF_PAIR_FREQ_MHZ_GET(pvfpair) \ + ((pvfpair)->freq_mhz) + +#define CTRL_CLK_VF_PAIR_VOLTAGE_UV_GET(pvfpair) \ + ((pvfpair)->voltage_uv) + +#define CTRL_CLK_VF_PAIR_FREQ_MHZ_SET(pvfpair, _freqmhz) \ + (((pvfpair)->freq_mhz) = (_freqmhz)) + +#define CTRL_CLK_VF_PAIR_FREQ_MHZ_SET(pvfpair, _freqmhz) \ + (((pvfpair)->freq_mhz) = (_freqmhz)) + + +#define CTRL_CLK_VF_PAIR_VOLTAGE_UV_SET(pvfpair, _voltageuv) \ + (((pvfpair)->voltage_uv) = (_voltageuv)) + +#endif /* NVGPU_CTRLCLK_H */ diff --git a/include/ctrl/ctrlclkavfs.h b/include/ctrl/ctrlclkavfs.h new file mode 100644 index 0000000..676ae7e --- /dev/null +++ b/include/ctrl/ctrlclkavfs.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_CTRLCLKAVFS_H +#define NVGPU_CTRLCLKAVFS_H + +#include "ctrlboardobj.h" +/*! + * Valid global VIN ID values + */ +#define CTRL_CLK_VIN_ID_SYS 0x00000000 +#define CTRL_CLK_VIN_ID_LTC 0x00000001 +#define CTRL_CLK_VIN_ID_XBAR 0x00000002 +#define CTRL_CLK_VIN_ID_GPC0 0x00000003 +#define CTRL_CLK_VIN_ID_GPC1 0x00000004 +#define CTRL_CLK_VIN_ID_GPC2 0x00000005 +#define CTRL_CLK_VIN_ID_GPC3 0x00000006 +#define CTRL_CLK_VIN_ID_GPC4 0x00000007 +#define CTRL_CLK_VIN_ID_GPC5 0x00000008 +#define CTRL_CLK_VIN_ID_GPCS 0x00000009 +#define CTRL_CLK_VIN_ID_SRAM 0x0000000A +#define CTRL_CLK_VIN_ID_UNDEFINED 0x000000FF + +#define CTRL_CLK_VIN_TYPE_DISABLED 0x00000000 +#define CTRL_CLK_VIN_TYPE_V10 0x00000001 +#define CTRL_CLK_VIN_TYPE_V20 0x00000002 + +/*! + * Various types of VIN calibration that the GPU can support + */ +#define CTRL_CLK_VIN_CAL_TYPE_V10 (0x00000000) +#define CTRL_CLK_VIN_CAL_TYPE_V20 (0x00000001) + +/*! + * Mask of all GPC VIN IDs supported by RM + */ +#define CTRL_CLK_VIN_MASK_UNICAST_GPC (BIT(CTRL_CLK_VIN_ID_GPC0) | \ + BIT(CTRL_CLK_VIN_ID_GPC1) | \ + BIT(CTRL_CLK_VIN_ID_GPC2) | \ + BIT(CTRL_CLK_VIN_ID_GPC3) | \ + BIT(CTRL_CLK_VIN_ID_GPC4) | \ + BIT(CTRL_CLK_VIN_ID_GPC5)) +#define CTRL_CLK_LUT_NUM_ENTRIES_MAX (128) +#define CTRL_CLK_LUT_NUM_ENTRIES_GV10x (128) +#define CTRL_CLK_LUT_NUM_ENTRIES_GP10x (100) +#define CTRL_CLK_VIN_STEP_SIZE_UV (10000) +#define CTRL_CLK_LUT_MIN_VOLTAGE_UV (450000) +#define CTRL_CLK_FLL_TYPE_DISABLED 0 + +#define CTRL_CLK_FLL_ID_SYS (0x00000000) +#define CTRL_CLK_FLL_ID_LTC (0x00000001) +#define CTRL_CLK_FLL_ID_XBAR (0x00000002) +#define CTRL_CLK_FLL_ID_GPC0 (0x00000003) +#define CTRL_CLK_FLL_ID_GPC1 (0x00000004) +#define CTRL_CLK_FLL_ID_GPC2 (0x00000005) +#define CTRL_CLK_FLL_ID_GPC3 (0x00000006) +#define CTRL_CLK_FLL_ID_GPC4 (0x00000007) +#define CTRL_CLK_FLL_ID_GPC5 (0x00000008) +#define CTRL_CLK_FLL_ID_GPCS (0x00000009) +#define CTRL_CLK_FLL_ID_UNDEFINED (0x000000FF) +#define CTRL_CLK_FLL_MASK_UNDEFINED (0x00000000) + +/*! + * Mask of all GPC FLL IDs supported by RM + */ +#define CTRL_CLK_FLL_MASK_UNICAST_GPC (BIT(CTRL_CLK_FLL_ID_GPC0) | \ + BIT(CTRL_CLK_FLL_ID_GPC1) | \ + BIT(CTRL_CLK_FLL_ID_GPC2) | \ + BIT(CTRL_CLK_FLL_ID_GPC3) | \ + BIT(CTRL_CLK_FLL_ID_GPC4) | \ + BIT(CTRL_CLK_FLL_ID_GPC5)) +/*! + * Mask of all FLL IDs supported by Nvgpu driver + */ +#define CTRL_CLK_FLL_ID_ALL_MASK (BIT(CTRL_CLK_FLL_ID_SYS) | \ + BIT(CTRL_CLK_FLL_ID_LTC) | \ + BIT(CTRL_CLK_FLL_ID_XBAR) | \ + BIT(CTRL_CLK_FLL_ID_GPC0) | \ + BIT(CTRL_CLK_FLL_ID_GPC1) | \ + BIT(CTRL_CLK_FLL_ID_GPC2) | \ + BIT(CTRL_CLK_FLL_ID_GPC3) | \ + BIT(CTRL_CLK_FLL_ID_GPC4) | \ + BIT(CTRL_CLK_FLL_ID_GPC5) | \ + BIT(CTRL_CLK_FLL_ID_GPCS)) + +#define CTRL_CLK_FLL_REGIME_ID_INVALID (0x00000000) +#define CTRL_CLK_FLL_REGIME_ID_FFR (0x00000001) +#define CTRL_CLK_FLL_REGIME_ID_FR (0x00000002) + +#define CTRL_CLK_FLL_LUT_VSELECT_LOGIC (0x00000000) +#define CTRL_CLK_FLL_LUT_VSELECT_MIN (0x00000001) +#define CTRL_CLK_FLL_LUT_VSELECT_SRAM (0x00000002) +#endif /* NVGPU_CTRLCLKAVFS_H */ diff --git a/include/ctrl/ctrlperf.h b/include/ctrl/ctrlperf.h new file mode 100644 index 0000000..2928cad --- /dev/null +++ b/include/ctrl/ctrlperf.h @@ -0,0 +1,103 @@ +/* + * general p state infrastructure + * + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_CTRLPERF_H +#define NVGPU_CTRLPERF_H + +struct ctrl_perf_volt_rail_list_item { + u8 volt_domain; + u32 voltage_uv; + u32 voltage_min_noise_unaware_uv; +}; + +struct ctrl_perf_volt_rail_list { + u8 num_rails; + struct ctrl_perf_volt_rail_list_item + rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS]; +}; + +union ctrl_perf_vfe_var_single_sensed_fuse_value_data { + int signed_value; + u32 unsigned_value; +}; + +struct ctrl_perf_vfe_var_single_sensed_fuse_value { + bool b_signed; + union ctrl_perf_vfe_var_single_sensed_fuse_value_data data; +}; + +struct ctrl_bios_vfield_register_segment_super { + u8 low_bit; + u8 high_bit; +}; + +struct ctrl_bios_vfield_register_segment_reg { + struct ctrl_bios_vfield_register_segment_super super; + u32 addr; +}; + +struct ctrl_bios_vfield_register_segment_index_reg { + struct ctrl_bios_vfield_register_segment_super super; + u32 addr; + u32 reg_index; + u32 index; +}; + +union ctrl_bios_vfield_register_segment_data { + struct ctrl_bios_vfield_register_segment_reg reg; + struct ctrl_bios_vfield_register_segment_index_reg index_reg; +}; + +struct ctrl_bios_vfield_register_segment { + u8 type; + union ctrl_bios_vfield_register_segment_data data; +}; + +#define NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX 1 + +struct ctrl_perf_vfe_var_single_sensed_fuse_info { + u8 segment_count; + struct ctrl_bios_vfield_register_segment segments[NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX]; +}; + +struct ctrl_perf_vfe_var_single_sensed_fuse_override_info { + u32 fuse_val_override; + u8 b_fuse_regkey_override; +}; + +struct ctrl_perf_vfe_var_single_sensed_fuse_vfield_info { + struct ctrl_perf_vfe_var_single_sensed_fuse_info fuse; + u32 fuse_val_default; + u32 hw_correction_scale; + int hw_correction_offset; + u8 v_field_id; +}; + +struct ctrl_perf_vfe_var_single_sensed_fuse_ver_vfield_info { + struct ctrl_perf_vfe_var_single_sensed_fuse_info fuse; + u8 ver_expected; + bool b_ver_check; + bool b_use_default_on_ver_check_fail; + u8 v_field_id_ver; +}; +#endif /* NVGPU_CTRLPERF_H */ diff --git a/include/ctrl/ctrlpmgr.h b/include/ctrl/ctrlpmgr.h new file mode 100644 index 0000000..90f6501 --- /dev/null +++ b/include/ctrl/ctrlpmgr.h @@ -0,0 +1,98 @@ +/* + * Control pmgr state infrastructure + * + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_CTRLPMGR_H +#define NVGPU_CTRLPMGR_H + +#include "ctrlboardobj.h" + +/* valid power domain values */ +#define CTRL_PMGR_PWR_DEVICES_MAX_DEVICES 32U +#define CTRL_PMGR_PWR_VIOLATION_MAX 0x06U + +#define CTRL_PMGR_PWR_DEVICE_TYPE_INA3221 0x4EU + +#define CTRL_PMGR_PWR_CHANNEL_INDEX_INVALID 0xFFU +#define CTRL_PMGR_PWR_CHANNEL_TYPE_SENSOR 0x08U + +#define CTRL_PMGR_PWR_POLICY_TABLE_VERSION_3X 0x30U +#define CTRL_PMGR_PWR_POLICY_TYPE_HW_THRESHOLD 0x04U +#define CTRL_PMGR_PWR_POLICY_TYPE_SW_THRESHOLD 0x0CU + +#define CTRL_PMGR_PWR_POLICY_MAX_LIMIT_INPUTS 0x8U +#define CTRL_PMGR_PWR_POLICY_IDX_NUM_INDEXES 0x08U +#define CTRL_PMGR_PWR_POLICY_INDEX_INVALID 0xFFU +#define CTRL_PMGR_PWR_POLICY_LIMIT_INPUT_CLIENT_IDX_RM 0xFEU +#define CTRL_PMGR_PWR_POLICY_LIMIT_MAX (0xFFFFFFFFU) + +struct ctrl_pmgr_pwr_device_info_rshunt { + bool use_fxp8_8; + u16 rshunt_value; +}; + +struct ctrl_pmgr_pwr_policy_info_integral { + u8 past_sample_count; + u8 next_sample_count; + u16 ratio_limit_min; + u16 ratio_limit_max; +}; + +enum ctrl_pmgr_pwr_policy_filter_type { + CTRL_PMGR_PWR_POLICY_FILTER_TYPE_NONE = 0, + CTRL_PMGR_PWR_POLICY_FILTER_TYPE_BLOCK, + CTRL_PMGR_PWR_POLICY_FILTER_TYPE_MOVING_AVERAGE, + CTRL_PMGR_PWR_POLICY_FILTER_TYPE_IIR +}; + +struct ctrl_pmgr_pwr_policy_filter_param_block { + u32 block_size; +}; + +struct ctrl_pmgr_pwr_policy_filter_param_moving_average { + u32 window_size; +}; + +struct ctrl_pmgr_pwr_policy_filter_param_iir { + u32 divisor; +}; + +union ctrl_pmgr_pwr_policy_filter_param { + struct ctrl_pmgr_pwr_policy_filter_param_block block; + struct ctrl_pmgr_pwr_policy_filter_param_moving_average moving_avg; + struct ctrl_pmgr_pwr_policy_filter_param_iir iir; +}; + +struct ctrl_pmgr_pwr_policy_limit_input { + u8 pwr_policy_idx; + u32 limit_value; +}; + +struct ctrl_pmgr_pwr_policy_limit_arbitration { + bool b_arb_max; + u8 num_inputs; + u32 output; + struct ctrl_pmgr_pwr_policy_limit_input + inputs[CTRL_PMGR_PWR_POLICY_MAX_LIMIT_INPUTS]; +}; + +#endif /* NVGPU_CTRLPMGR_H */ diff --git a/include/ctrl/ctrltherm.h b/include/ctrl/ctrltherm.h new file mode 100644 index 0000000..27af7b0 --- /dev/null +++ b/include/ctrl/ctrltherm.h @@ -0,0 +1,33 @@ +/* + * Control thermal infrastructure + * + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_CTRLTHERM_H +#define NVGPU_CTRLTHERM_H + +#include "ctrlboardobj.h" + +#define CTRL_THERMAL_THERM_DEVICE_CLASS_GPU 0x01 + +#define CTRL_THERMAL_THERM_CHANNEL_CLASS_DEVICE 0x01 + +#endif /* NVGPU_CTRLTHERM_H */ diff --git a/include/ctrl/ctrlvolt.h b/include/ctrl/ctrlvolt.h new file mode 100644 index 0000000..84994eb --- /dev/null +++ b/include/ctrl/ctrlvolt.h @@ -0,0 +1,143 @@ +/* + * general p state infrastructure + * + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_CTRLVOLT_H +#define NVGPU_CTRLVOLT_H + +#define CTRL_VOLT_VOLT_RAIL_MAX_RAILS \ + CTRL_BOARDOBJGRP_E32_MAX_OBJECTS + +#include "ctrlperf.h" +#include "ctrlboardobj.h" + +#define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES 0x04U +#define CTRL_VOLT_VOLT_DEV_VID_VSEL_MAX_ENTRIES (8U) +#define CTRL_VOLT_DOMAIN_INVALID 0x00U +#define CTRL_VOLT_DOMAIN_LOGIC 0x01U +#define CLK_PROG_VFE_ENTRY_LOGIC 0x00U +#define CLK_PROG_VFE_ENTRY_SRAM 0x01U + +/* + * Macros for Voltage Domain HAL. + */ +#define CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL 0x00U +#define CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL 0x01U + +/* + * Macros for Voltage Domains. + */ +#define CTRL_VOLT_DOMAIN_INVALID 0x00U +#define CTRL_VOLT_DOMAIN_LOGIC 0x01U +#define CTRL_VOLT_DOMAIN_SRAM 0x02U + +/*! + * Special value corresponding to an invalid Voltage Rail Index. + */ +#define CTRL_VOLT_RAIL_INDEX_INVALID \ + CTRL_BOARDOBJ_IDX_INVALID + +/*! + * Special value corresponding to an invalid Voltage Device Index. + */ +#define CTRL_VOLT_DEVICE_INDEX_INVALID \ + CTRL_BOARDOBJ_IDX_INVALID + +/*! + * Special value corresponding to an invalid Voltage Policy Index. + */ +#define CTRL_VOLT_POLICY_INDEX_INVALID \ + CTRL_BOARDOBJ_IDX_INVALID + +enum nv_pmu_pmgr_pwm_source { + NV_PMU_PMGR_PWM_SOURCE_INVALID = 0, + NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_0 = 4, + NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_1, + NV_PMU_PMGR_PWM_SOURCE_RSVD_0 = 7, + NV_PMU_PMGR_PWM_SOURCE_RSVD_1 = 8, +}; + +/*! + * Macros for Voltage Device Types. + */ +#define CTRL_VOLT_DEVICE_TYPE_INVALID 0x00U +#define CTRL_VOLT_DEVICE_TYPE_PWM 0x03U + +/* + * Macros for Volt Device Operation types. + */ +#define CTRL_VOLT_DEVICE_OPERATION_TYPE_INVALID 0x00U +#define CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT 0x01U +#define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_STEADY_STATE 0x02U +#define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_SLEEP_STATE 0x03U +#define CTRL_VOLT_VOLT_DEVICE_OPERATION_TYPE_IPC_VMIN 0x04U + +/*! + * Macros for Voltage Domains. + */ +#define CTRL_VOLT_DOMAIN_INVALID 0x00U +#define CTRL_VOLT_DOMAIN_LOGIC 0x01U +#define CTRL_VOLT_DOMAIN_SRAM 0x02U + +/*! + * Macros for Volt Policy types. + * + * Virtual VOLT_POLICY types are indexed starting from 0xFF. + */ +#define CTRL_VOLT_POLICY_TYPE_INVALID 0x00U +#define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL 0x01U +#define CTRL_VOLT_POLICY_TYPE_SR_MULTI_STEP 0x02U +#define CTRL_VOLT_POLICY_TYPE_SR_SINGLE_STEP 0x03U +#define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL_MULTI_STEP 0x04U +#define CTRL_VOLT_POLICY_TYPE_SPLIT_RAIL 0xFEU +#define CTRL_VOLT_POLICY_TYPE_UNKNOWN 0xFFU + +/*! + * Macros for Volt Policy Client types. + */ +#define CTRL_VOLT_POLICY_CLIENT_INVALID 0x00U +#define CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ 0x01U + +struct ctrl_volt_volt_rail_list_item { + u8 rail_idx; + u32 voltage_uv; +}; + +struct ctrl_volt_volt_rail_list { + u8 num_rails; + struct ctrl_volt_volt_rail_list_item + rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS]; +}; + +struct ctrl_volt_volt_rail_list_item_v1 { + u8 rail_idx; + u32 voltage_uv; + u32 voltage_min_noise_unaware_uv; +}; + +struct ctrl_volt_volt_rail_list_v1 { + u8 num_rails; + struct ctrl_volt_volt_rail_list_item_v1 + rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS]; +}; + +#endif /* NVGPU_CTRLVOLT_H */ -- cgit v1.2.2