From 3725b15d5da3e06ef202045d710aa5f15eb72fcc Mon Sep 17 00:00:00 2001 From: Benjamin Hadad IV Date: Mon, 3 Jul 2023 04:30:54 -0400 Subject: I modified nvdebug.h for Ampere. --- nvdebug.h | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/nvdebug.h b/nvdebug.h index 968a60b..126c5e3 100644 --- a/nvdebug.h +++ b/nvdebug.h @@ -9,6 +9,8 @@ #include // For KERNEL_VERSION and LINUX_VERSION_CODE #include +#define NV_BUILD_FOR_AMPERE + /* Runlist Channel A timeslice group (TSG) is composed of channels. Each channel is a FIFO queue of GPU commands. These commands are typically queued from userspace. @@ -551,6 +553,32 @@ static const char* const ENGINE_TYPES_NAMES[ENGINE_TYPES_LEN] = { Support: Kepler, Maxwell, Pascal, Volta, Ampere See dev_top.ref.txt of NVIDIA's open-gpu-doc for more info. */ + +#ifdef NV_BUILD_FOR_AMPERE +#define NV_PTOP_DEVICE_INFO(i) (0x00022800+(i)*4) +#define NV_PTOP_DEVICE_INFO__SIZE_1 64 +typedef union { + struct { + uint32_t fault_id:7; + uint32_t padding0:9; + uint32_t inst_id:4; + uint32_t padding1:4; + enum ENGINE_TYPES engine_type:7; + bool has_next_entry:1; + } __attribute__((packed)); + struct { + uint32_t reset_enum:5; + uint32_t padding2:7; + uint32_t pri_base:12; + } __attribute__((packed)); + struct { + uint32_t engine_enum:2; + uint32_t padding3:4; + uint32_t runlist_enum:14; + } __attribute__((packed)); + uint32_t raw; +} ptop_device_info_t; +#else #define NV_PTOP_DEVICE_INFO(i) (0x00022700+(i)*4) #define NV_PTOP_DEVICE_INFO__SIZE_1 64 typedef union { @@ -591,6 +619,7 @@ typedef union { } __attribute__((packed)); uint32_t raw; } ptop_device_info_t; +#endif #define NV_PTOP_SCAL_NUM_GPCS 0x00022430 #define NV_PTOP_SCAL_NUM_TPC_PER_GPC 0x00022434 -- cgit v1.2.2