1 files changed, 33 insertions, 11 deletions

diff --git a/nvdebug_entry.c b/nvdebug_entry.c
index d5df7db..3a10e13 100644
--- a/nvdebug_entry.c
+++ b/nvdebug_entry.c
@@ -7,6 +7,7 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/pci.h>  // For PCI device scanning
+#include <linux/platform_device.h>  // For platform_device struct
 #include <linux/proc_fs.h>  // So we can set up entries in /proc
 
 #include "nvdebug_linux.h"
@@ -114,17 +115,33 @@ int probe_and_cache_devices(void) {
         // TODO: Support other platform bus devices (gk20a - TK1)
         if (dev) {
                 mc_boot_0_t ids;
+                struct platform_device *platd = container_of(dev, struct platform_device, dev);
+                struct resource *regs = platform_get_resource(platd, IORESOURCE_MEM, 0);
                 g_nvdebug_state[i].g = get_gk20a(dev);
-                g_nvdebug_state[i].regs = gk20a_regs(g_nvdebug_state[i].g);
-                if (!g_nvdebug_state[i].regs)
+                if (!regs)
                         return -EADDRNOTAVAIL;
-                ids.raw = nvdebug_readl(&g_nvdebug_state[i], NV_MC_BOOT_0);
-                if (ids.raw == -1)
+                g_nvdebug_state[i].regs = ioremap(regs->start, resource_size(regs));
+                if (!g_nvdebug_state[i].regs) {
+                        printk(KERN_ERR "[nvdebug] Unable to map BAR0 on the integrated GPU\n");
                         return -EADDRNOTAVAIL;
-                g_nvdebug_state[i].chip_id = ids.chip_id;
+                }
+                // The Jetson TX1, TX2, Xavier, and Orin do not have a BAR2 (but do have
+                // BAR1). On the TX2+, all their platform resources are:
+                //   [nvdebug] Region 0: Memory at 17000000 [size=16777216]
+                //   [nvdebug] Region 1: Memory at 18000000 [size=16777216]
+                //   [nvdebug] Region 2: Memory at 3b41000 [size=4096]
+                // The TX1 has the same regions, but at different base addresses.
                 g_nvdebug_state[i].bar3 = NULL;
                 g_nvdebug_state[i].pcid = NULL;
+                g_nvdebug_state[i].platd = platd;
                 g_nvdebug_state[i].dev = dev;
+                // Don't check Chip ID until everything else is initalized
+                ids.raw = nvdebug_readl(&g_nvdebug_state[i], NV_MC_BOOT_0);
+                if (ids.raw == -1) {
+                        printk(KERN_ERR "[nvdebug] Unable to read config from Master Controller on the integrated GPU\n");
+                        return -EADDRNOTAVAIL;
+                }
+                g_nvdebug_state[i].chip_id = ids.chip_id;
                 printk(KERN_INFO "[nvdebug] Chip ID %x (architecture %s) detected on platform bus and initialized.",
                        ids.chip_id, ARCH2NAME(ids.architecture));
                 i++;
@@ -140,12 +157,6 @@ int probe_and_cache_devices(void) {
                         pci_err(pcid, "[nvdebug] Unable to map BAR0 on this GPU\n");
                         return -EADDRNOTAVAIL;
                 }
-                ids.raw = nvdebug_readl(&g_nvdebug_state[i], NV_MC_BOOT_0);
-                if (ids.raw == -1) {
-                        pci_err(pcid, "[nvdebug] Unable to read config from Master Controller on this GPU\n");
-                        return -EADDRNOTAVAIL;
-                }
-                g_nvdebug_state[i].chip_id = ids.chip_id;
                 // Map BAR3 (CPU-accessible mappings of GPU DRAM)
                 g_nvdebug_state[i].bar3 = pci_iomap(pcid, 3, 0);
                 // XXX: Try mapping only the lower half of BAR3 on fail
@@ -153,7 +164,15 @@ int probe_and_cache_devices(void) {
                 if (!g_nvdebug_state[i].bar3)
                         g_nvdebug_state[i].bar3 = pci_iomap(pcid, 3, pci_resource_len(pcid, 3)/2);
                 g_nvdebug_state[i].pcid = pcid;
+                g_nvdebug_state[i].platd = NULL;
                 g_nvdebug_state[i].dev = &pcid->dev;
+                // Don't check Chip ID until everything else is initalized
+                ids.raw = nvdebug_readl(&g_nvdebug_state[i], NV_MC_BOOT_0);
+                if (ids.raw == -1) {
+                        pci_err(pcid, "[nvdebug] Unable to read config from Master Controller on this GPU\n");
+                        return -EADDRNOTAVAIL;
+                }
+                g_nvdebug_state[i].chip_id = ids.chip_id;
                 printk(KERN_INFO "[nvdebug] Chip ID %x (architecture %s) detected on PCI bus and initialized.",
                        ids.chip_id, ARCH2NAME(ids.architecture));
 #if INTERRUPT_DEBUG
@@ -430,6 +449,9 @@ static void __exit nvdebug_exit(void) {
 #if INTERRUPT_DEBUG
                         free_irq(g->pcid->irq, g->pcid);
 #endif // INTERRUPT_DEBUG
+                } else {
+                        if (g->regs)
+                                iounmap(g->regs);
                 }
                 printk(KERN_INFO "[nvdebug] Chip ID %x deinitialized.", g->chip_id);
         }