1 files changed, 50 insertions, 9 deletions

diff --git a/nvdebug.h b/nvdebug.h
index 3860c2e..b79ede1 100644
--- a/nvdebug.h
+++ b/nvdebug.h
@@ -390,6 +390,7 @@ typedef union {
 #define NV_CHIP_ID_GV11B 0x15B // Jetson Xavier embedded GPU
 #define NV_CHIP_ID_KEPLER 0x0E0
 #define NV_CHIP_ID_VOLTA 0x140
+#define NV_CHIP_ID_AMPERE 0x170
 
 inline static const char* ARCH2NAME(uint32_t arch) {
         switch (arch) {
@@ -461,8 +462,7 @@ typedef union {
         } __attribute__((packed));
 } mc_boot_0_t;
 
-
-/* GPU engine information and control register offsets
+/* GPU engine information and control register offsets (GPU TOPology)
   Each engine is described by one or more entries (terminated by an entry with
   the `has_next_entry` flag unset) in the fixed-size PTOP_DEVICE_INFO table. A
   typical device, such as the graphics/compute engine and any copy engines, are
@@ -473,6 +473,12 @@ typedef union {
   code should check all NV_PTOP_DEVICE_INFO__SIZE_1 entries and not terminate
   upon reaching the first entry of INFO_TYPE_NOT_VALID.
 
+  The fields for the Ampere version of the GPU are a strict subset of those for
+  the earlier versions. They are in different positions within the struct and
+  have names ending in _ampere to distinguish them. Other than that, each
+  Ampere device info field is functionally identical to the equivalent field in
+  the previous version.
+
   INFO_TYPE          : Is this a DATA, ENUM, or ENGINE_TYPE table entry?
   HAS_NEXT_ENTRY     : Does the following entry refer to the same engine?
 
@@ -517,8 +523,11 @@ typedef union {
   Support: Kepler, Maxwell, Pascal, Volta, Ampere
   See dev_top.ref.txt of NVIDIA's open-gpu-doc for more info.
 */
-#define NV_PTOP_DEVICE_INFO(i) (0x00022700+(i)*4)
-#define NV_PTOP_DEVICE_INFO__SIZE_1 64
+
+#define NV_PTOP_DEVICE_INFO_GA100(i) (0x00022800+(i)*4)
+#define NV_PTOP_DEVICE_INFO_GK104(i) (0x00022700+(i)*4)
+#define NV_PTOP_DEVICE_INFO__SIZE_1_GA100(g) (nvdebug_readl(g, 0x0224fc) >> 20)
+#define NV_PTOP_DEVICE_INFO__SIZE_1_GK104 64
 enum DEVICE_INFO_TYPE {INFO_TYPE_NOT_VALID = 0, INFO_TYPE_DATA = 1, INFO_TYPE_ENUM = 2, INFO_TYPE_ENGINE_TYPE = 3};
 enum ENGINE_TYPES {
         ENGINE_GRAPHICS = 0, // GRAPHICS [/compute]
@@ -527,7 +536,7 @@ enum ENGINE_TYPES {
         ENGINE_COPY2 = 3, // [raw/physical] COPY #2
 
         ENGINE_MSPDEC = 8, // Picture DECoder
-        ENGINE_MSPPP = 9, // [Video] Post Processing
+        ENGINE_MSPPP = 9, // [Video] Picture Post Processor
         ENGINE_MSVLD = 10, // [Video] Variable Length Decoder
         ENGINE_MSENC = 11, // [Video] ENCoding
         ENGINE_VIC = 12, // Video Image Compositor
@@ -538,10 +547,12 @@ enum ENGINE_TYPES {
 
         ENGINE_IOCTRL = 18, // I/O ConTRoLler [of NVLINK at least]
         ENGINE_LCE = 19, // Logical Copy Engine
-        ENGINE_GSP = 20, // Gpu System Processor
-        ENGINE_NVJPG = 21, // NVidia JPeG [Decoder] (Ampere+)
+        ENGINE_GSP = 20, // Gpu System Processor (Volta+)
+        ENGINE_NVJPG = 21, // NVidia JPeG [Decoder] (Turing+)
+        ENGINE_OFA = 22, // Optical Flow Accelerator (Turing+)
+        ENGINE_FLA = 23, // [NVLink] Fabric Logical Addressing [?]
 };
-#define ENGINE_TYPES_LEN 22
+#define ENGINE_TYPES_LEN 24
 static const char* const ENGINE_TYPES_NAMES[ENGINE_TYPES_LEN] = {
         "Graphics/Compute",
         "COPY0",
@@ -565,8 +576,38 @@ static const char* const ENGINE_TYPES_NAMES[ENGINE_TYPES_LEN] = {
         "LCE: Logical Copy Engine",
         "GSP: GPU System Processor",
         "NVJPG: NVIDIA JPEG Decoder",
+        "OFA: Optical Flow Accelerator",
+        "FLA: Fabric Logical Addressing",
 };
 
+// These field are from nvgpu/include/nvgpu/hw/ga100/hw_top_ga100.h
+typedef union {
+        // _info type fields
+        struct {
+                uint32_t fault_id:11;
+                 uint32_t padding0:5;
+                uint32_t inst_id:8;
+                enum ENGINE_TYPES engine_type:7; // "type_enum"
+                bool has_next_entry:1;
+        } __attribute__((packed));
+        // _info2 type fields
+        struct {
+                uint32_t reset_id:8;
+                uint32_t pri_base:18; // "device_pri_base"
+                 uint32_t padding1:4;
+                uint32_t is_engine:1;
+                 uint32_t padding2:1;
+        } __attribute__((packed));
+        struct {
+                uint32_t rleng_id:2;
+                 uint32_t padding3:8;
+                uint32_t runlist_pri_base:16;
+                 uint32_t padding4:6;
+        } __attribute__((packed));
+        uint32_t raw;
+} ptop_device_info_ga100_t;
+
+// These field are from open-gpu-doc/manuals/volta/gv100/dev_top.ref.txt
 typedef union {
         // DATA type fields
         struct {
@@ -604,7 +645,7 @@ typedef union {
                  uint32_t padding9:1;
         } __attribute__((packed));
         uint32_t raw;
-} ptop_device_info_t;
+} ptop_device_info_gk104_t;
 
 /* Graphics Processing Cluster (GPC) information
   The GPU's Compute/Graphics engine is subdivided into Graphics Processing