1 files changed, 673 insertions, 46 deletions

diff --git a/nvdebug.h b/nvdebug.h
index 9ac71da..1882756 100644
--- a/nvdebug.h
+++ b/nvdebug.h
@@ -5,14 +5,18 @@
 // TODO(jbakita): Don't depend on these.
 #include <nvgpu/gk20a.h>  // For struct gk20a
 #include <os/linux/os_linux.h>  // For struct nvgpu_os_linux
+#include <linux/proc_fs.h>  // For PDE_DATA() macro
 
 /* Runlist Channel
   A timeslice group (TSG) is composed of channels. Each channel is a FIFO queue
   of GPU commands. These commands are typically queued from userspace.
 
-  `INST_PTR` points to a GPU Instance Block which contains pointers to the GPU
-  virtual address space for this context. All channels in a TSG point to the
-  same GPU Instance Block (?).
+  Prior to Volta, channels could also exist independent of a TSG. These are
+  called "bare channels" in the Jetson nvgpu driver.
+
+  `INST_PTR` points to a GPU Instance Block which contains FIFO states, virtual
+  address space configuration for this context, and a pointer to the page
+  tables. All channels in a TSG point to the same GPU Instance Block (?).
 
   "RUNQUEUE_SELECTOR determines to which runqueue the channel belongs, and
   thereby which PBDMA will run the channel.  Increasing values select
@@ -30,7 +34,13 @@
   ENTRY_TYPE (T)        : type of this entry: ENTRY_TYPE_CHAN
   CHID (ID)             : identifier of the channel to run (overlays ENTRY_ID)
   RUNQUEUE_SELECTOR (Q) : selects which PBDMA should run this channel if
-                          more than one PBDMA is supported by the runlist
+                          more than one PBDMA is supported by the runlist,
+                          additionally, "A value of 0 targets the first FE
+                          pipe, which can process all FE driven engines:
+                          Graphics, Compute, Inline2Memory, and TwoD.  A value
+                          of 1 targets the second FE pipe, which can only
+                          process Compute work.  Note that GRCE work is allowed
+                          on either runqueue.)"
 
   INST_PTR_LO           : lower 20 bits of the 4k-aligned instance block pointer
   INST_PTR_HI           : upper 32 bit of instance block pointer
@@ -39,6 +49,9 @@
   USERD_PTR_LO          : upper 24 bits of the low 32 bits, of the 512-byte-aligned USERD pointer
   USERD_PTR_HI          : upper 32 bits of USERD pointer
   USERD_TARGET (TGU)    : aperture of the USERD data structure
+
+  Channels were around since at least Fermi, but were rearranged with Volta to
+  add a USERD pointer, a longer INST pointer, and a runqueue selector flag.
 */
 enum ENTRY_TYPE {ENTRY_TYPE_CHAN = 0, ENTRY_TYPE_TSG = 1};
 enum INST_TARGET {TARGET_VID_MEM = 0, TARGET_SYS_MEM_COHERENT = 2, TARGET_SYS_MEM_NONCOHERENT = 3};
@@ -52,11 +65,12 @@ static inline char* target_to_text(enum INST_TARGET t) {
                         return "SYS_MEM_NONCOHERENT";
                 default:
                         printk(KERN_WARNING "[nvdebug] Invalid aperture!\n");
-                        return NULL;
+                        return "INVALID";
         }
 }
 
-struct runlist_chan {
+// Support: Volta, Ampere, Turing
+struct gv100_runlist_chan {
 // 0:63
         enum ENTRY_TYPE entry_type:1;
         uint32_t runqueue_selector:1;
@@ -71,6 +85,20 @@ struct runlist_chan {
         uint32_t inst_ptr_hi:32;
 } __attribute__((packed));
 
+// Support: Fermi, Kepler*, Maxwell, Pascal
+// *In Kepler, inst fields may be unpopulated?
+struct gm107_runlist_chan {
+        uint32_t chid:12;
+         uint32_t padding0:1;
+        enum ENTRY_TYPE entry_type:1;
+         uint32_t padding1:18;
+        uint32_t inst_ptr_lo:20;
+        enum INST_TARGET inst_target:2;  // Totally guessing on this
+         uint32_t padding2:10;
+} __attribute__((packed));
+
+#define gk110_runlist_chan gm107_runlist_chan
+
 /* Runlist TSG (TimeSlice Group)
   The runlist is composed of timeslice groups (TSG). Each TSG corresponds
   to a single virtual address space on the GPU and contains `TSG_LENGTH`
@@ -85,8 +113,15 @@ struct runlist_chan {
   TIMESLICE_TIMEOUT   : timeout amount for the TSG's timeslice
   TSG_LENGTH          : number of channels that are part of this timeslice group
   TSGID               : identifier of the Timeslice group (overlays ENTRY_ID)
+
+  TSGs appear to have been introduced with Kepler and stayed the same until
+  they were rearranged at the time of channel rearrangement to support longer
+  GPU instance addresses with Volta.
 */
-struct entry_tsg {
+
+// Support: Volta, Ampere*, Turing*
+// *These treat the top 8 bits of TSGID as GFID (unused)
+struct gv100_runlist_tsg {
 // 0:63
         enum ENTRY_TYPE entry_type:1;
          uint64_t padding:15;
@@ -101,14 +136,28 @@ struct entry_tsg {
 } __attribute__((packed));
 #define MAX_TSGID (1 << 12)
 
+// Support: Kepler (v2?), Maxwell, Pascal
+// Same fields as Volta except tsg_length is 6 bits rather than 8
+// Last 32 bits appear to contain an undocumented inst ptr
+struct gk110_runlist_tsg {
+        uint32_t tsgid:12;
+         uint32_t padding0:1;
+        enum ENTRY_TYPE entry_type:1;
+        uint32_t timeslice_scale:4;
+        uint32_t timeslice_timeout:8;
+        uint32_t tsg_length:6;
+         uint32_t padding1:32;
+} __attribute__((packed));
+
+
 enum PREEMPT_TYPE {PREEMPT_TYPE_CHANNEL = 0, PREEMPT_TYPE_TSG = 1};
 
 /* Preempt a TSG or Channel by ID
-  ID/CHID             : Id of TSG or channel to preempt
-  IS_PENDING          : ????
-  TYPE                : PREEMPT_TYPE_CHANNEL or PREEMPT_TYPE_TSG
+  ID/CHID     : Id of TSG or channel to preempt
+  IS_PENDING  : Is a context switch pending?
+  TYPE        : PREEMPT_TYPE_CHANNEL or PREEMPT_TYPE_TSG
 
-  Support: Kepler, Maxwell, Pascal, Volta
+  Support: Kepler, Maxwell, Pascal, Volta, Turing
 */
 #define NV_PFIFO_PREEMPT 0x00002634
 typedef union {
@@ -195,26 +244,36 @@ typedef union {
  */
 
 // Note: This is different with Turing
-// Support: Kepler, Maxwell, Pascal, Volta
+// Support: Fermi, Kepler, Maxwell, Pascal, Volta
 #define NV_PFIFO_RUNLIST_BASE 0x00002270
+#define NV_PFIFO_ENG_RUNLIST_BASE(i) (0x00002280+(i)*8)
 typedef union {
         struct {
                 uint32_t ptr:28;
-                uint32_t type:2;
+                enum INST_TARGET target:2;
                  uint32_t padding:2;
         } __attribute__((packed));
         uint32_t raw;
 } runlist_base_t;
 
 // Support: Kepler, Maxwell, Pascal, Volta
+// Works on Fermi, but id is one bit longer and is b11111
 #define NV_PFIFO_RUNLIST 0x00002274
+#define NV_PFIFO_ENG_RUNLIST(i) (0x00002284+(i)*8)
 typedef union {
+        // RUNLIST fields
         struct {
                 uint32_t len:16;
                  uint32_t padding:4;
-                uint32_t id:4;
+                uint32_t id:4; // Runlist ID (each engine may have a seperate runlist)
                  uint32_t padding2:8;
         } __attribute__((packed));
+        // ENG_RUNLIST fields that differ
+        struct {
+                 uint32_t padding3:20;
+                bool is_pending:1; // Is runlist not yet committed?
+                 uint32_t padding4:11;
+        } __attribute__((packed));
         uint32_t raw;
 } runlist_info_t;
 
@@ -301,63 +360,631 @@ typedef union {
         uint32_t raw;
 } runlist_disable_t;
 
+/* Read GPU descriptors from the Master Controller (MC)
+
+  MINOR_REVISION  : Legacy (only used with Celvin in Nouveau)
+  MAJOR_REVISION  : Legacy (only used with Celvin in Nouveau)
+  IMPLEMENTATION  : Which implementation of the GPU architecture
+  ARCHITECTURE    : Which GPU architecture
+
+  CHIP_ID = IMPLEMENTATION + ARCHITECTURE << 4
+  CHIP_ID         : Unique ID of all chips since Kelvin
+
+  Support: Kelvin, Rankline, Curie, Tesla, Fermi, Kepler, Maxwell, Pascal,
+           Volta, Turing, Ampere
+*/
+#define NV_MC_BOOT_0 0x00000000
+#define NV_CHIP_ID_GP106 0x136 // Discrete GeForce GTX 1060
+#define NV_CHIP_ID_GV11B 0x15B // Jetson Xavier embedded GPU
+#define NV_CHIP_ID_KEPLER 0x0E0
+#define NV_CHIP_ID_VOLTA 0x140
+
+inline static const char* ARCH2NAME(uint32_t arch) {
+        switch (arch) {
+        case 0x01: