diff options
Diffstat (limited to 'nvdebug.h')
-rw-r--r-- | nvdebug.h | 41 |
1 files changed, 34 insertions, 7 deletions
@@ -365,7 +365,32 @@ enum CHANNEL_STATUS { | |||
365 | 365 | ||
366 | 512-entry array of channel control and status data structures. | 366 | 512-entry array of channel control and status data structures. |
367 | 367 | ||
368 | Support: Fermi, Maxwell, Pascal, Volta, Turing, [more?] | 368 | === Read/Write Fields === |
369 | INST_PTR : Top 28 of 40 bits of page-aligned channel instance block. | ||
370 | Instance Block = (uint64_t)inst_ptr << 12. | ||
371 | INST_TARGET : Aperture of INST_PTR. | ||
372 | INST_BIND : Is the channel instance bound? | ||
373 | NEXT : Is this the next channel to be scheduled in the runlist? | ||
374 | |||
375 | === Read-Only Fields === | ||
376 | ENABLE : Is this channel enabled? (Disabled channels are skipped | ||
377 | over by the runlist scheduler.) | ||
378 | PBDMA_FAULTED^ : [UNKNOWN] | ||
379 | ENG_FAULTED^ : [UNKNOWN] | ||
380 | STATUS : Status of this channel in regards to hardware. See enum | ||
381 | CHANNEL_STATUS. | ||
382 | BUSY : [UNKNOWN] | ||
383 | ^Field can be reset with a non-zero write. | ||
384 | |||
385 | === Write-Only Fields === | ||
386 | FORCE_CTX_RELOAD : [UNKNOWN] | ||
387 | ENABLE_SET : Enables the channel upon non-zero write. | ||
388 | ENABLE_CLEAR : Disables the channel upon non-zero write. | ||
389 | FORCE_PBDMA_FAULTED* : [UNKNOWN] | ||
390 | FORCE_ENG_FAULTED* : [UNKNOWN] | ||
391 | *Field only available on Turing. | ||
392 | |||
393 | Support: Fermi, Maxwell, Pascal, Volta, Turing | ||
369 | */ | 394 | */ |
370 | #define NV_PCCSR_CHANNEL_INST(i) (0x00800000+(i)*8) | 395 | #define NV_PCCSR_CHANNEL_INST(i) (0x00800000+(i)*8) |
371 | #define MAX_CHID 512 | 396 | #define MAX_CHID 512 |
@@ -374,22 +399,24 @@ typedef union { | |||
374 | // 0:31 | 399 | // 0:31 |
375 | uint32_t inst_ptr:28; | 400 | uint32_t inst_ptr:28; |
376 | enum INST_TARGET inst_target:2; | 401 | enum INST_TARGET inst_target:2; |
377 | uint32_t padding0:1; | 402 | uint32_t :1; |
378 | bool inst_bind:1; | 403 | bool inst_bind:1; |
379 | // 32:64 | 404 | // 32:63 |
380 | bool enable:1; | 405 | bool enable:1; |
381 | bool next:1; | 406 | bool next:1; |
382 | uint32_t padding:6; | 407 | uint32_t :6; |
383 | bool force_ctx_reload:1; | 408 | bool force_ctx_reload:1; |
384 | uint32_t padding2:1; | 409 | uint32_t :1; |
385 | bool enable_set:1; | 410 | bool enable_set:1; |
386 | bool enable_clear:1; | 411 | bool enable_clear:1; |
387 | uint32_t padding3:10; | 412 | uint32_t :8; |
413 | bool force_pbdma_faulted:1; | ||
414 | bool force_eng_faulted:1; | ||
388 | bool pbdma_faulted:1; | 415 | bool pbdma_faulted:1; |
389 | bool eng_faulted:1; | 416 | bool eng_faulted:1; |
390 | enum CHANNEL_STATUS status:4; | 417 | enum CHANNEL_STATUS status:4; |
391 | bool busy:1; | 418 | bool busy:1; |
392 | uint32_t padding4:3; | 419 | uint32_t :3; |
393 | } __attribute__((packed)); | 420 | } __attribute__((packed)); |
394 | uint64_t raw; | 421 | uint64_t raw; |
395 | } channel_ctrl_t; | 422 | } channel_ctrl_t; |