1 files changed, 11 insertions, 7 deletions

diff --git a/nvdebug.h b/nvdebug.h
index a9366e0..ac254f0 100644
--- a/nvdebug.h
+++ b/nvdebug.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 Joshua Bakita
+/* Copyright 2024 Joshua Bakita
  * SPDX-License-Identifier: MIT
  *
  * File outline:
@@ -688,17 +688,20 @@ typedef union {
 
   SCAL_NUM_CES : Number of externally accessible copy engines
 
+  Errata: Incorrectly reports "3" on Jetson TX1 and TX2. Should report "1" to be
+  consistent with PTOP data.
+
   Support: Kepler through (at least) Blackwell
   Also see dev_ce.ref.txt of NVIDIA's open-gpu-doc for info.
 */
 #define NV_PTOP_SCAL_NUM_CES 0x00022444
-// Defined number of GRCEs for a GPU
-# define NV_GRCE_NUM 2
+// Defined max number of GRCEs for a GPU (TX2 has only one)
+# define NV_GRCE_MAX 2
 // Defined GRCE->CE mapping offsets from nvgpu
 #define NV_GRCE_FOR_CE_GP100(i) (0x00104034+(i)*4)
 #define NV_GRCE_FOR_CE_GA100(i) (0x001041c0+(i)*4)
 // Defined LCE->PCE mapping offset from nvgpu (same as ce_pce2lce_config_r(i) in nvgpu)
-#define NV_LCE_FOR_PCE_GP100(i) (0x0010402c+(i)/2)
+#define NV_LCE_FOR_PCE_GP100 0x0010402c
 #define NV_LCE_FOR_PCE_GV100(i) (0x00104040+(i)*4)
 #define NV_LCE_FOR_PCE_GA100(i) (0x00104100+(i)*4)
 // Struct for use with nvdebug_reg_range_read()
@@ -717,13 +720,14 @@ union reg_range {
 
   CE_PCE_MAP : A bitmask, where a set bit indicates that the PCE for that index
                is enabled (not floorswept) on this GPU. Count the number of set
-               bits to get the number of PCEs.
+               bits to get the number of PCEs. Note that this may be bogus if
+               the GPU has not been used since reset.
 
-  Support: Kepler through (at least) Blackwell
+  Support: Pascal through (at least) Blackwell
   Also see dev_ce.ref.txt of NVIDIA's open-gpu-doc for info.
 */
 #define NV_CE_PCE_MAP 0x00104028
-#define MAP_SIZE 32
+#define NV_CE_PCE_MAP_SIZE 32
 
 
 /* Location of the 1Kb instance block with page tables for BAR1 and BAR2.