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-rw-r--r--include/volt/volt_pmu.c384
1 files changed, 0 insertions, 384 deletions
diff --git a/include/volt/volt_pmu.c b/include/volt/volt_pmu.c
deleted file mode 100644
index 2249ae2..0000000
--- a/include/volt/volt_pmu.c
+++ /dev/null
@@ -1,384 +0,0 @@
1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/pmu.h>
24#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
25#include <nvgpu/gk20a.h>
26
27#include "boardobj/boardobjgrp.h"
28#include "boardobj/boardobjgrp_e32.h"
29#include "gp106/bios_gp106.h"
30#include "ctrl/ctrlvolt.h"
31#include "ctrl/ctrlperf.h"
32
33#include "volt.h"
34
35#define RAIL_COUNT_GP 2
36#define RAIL_COUNT_GV 1
37
38struct volt_rpc_pmucmdhandler_params {
39 struct nv_pmu_volt_rpc *prpc_call;
40 u32 success;
41};
42
43static void volt_rpc_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
44 void *param, u32 handle, u32 status)
45{
46 struct volt_rpc_pmucmdhandler_params *phandlerparams =
47 (struct volt_rpc_pmucmdhandler_params *)param;
48
49 nvgpu_log_info(g, " ");
50
51 if (msg->msg.volt.msg_type != NV_PMU_VOLT_MSG_ID_RPC) {
52 nvgpu_err(g, "unsupported msg for VOLT RPC %x",
53 msg->msg.volt.msg_type);
54 return;
55 }
56
57 if (phandlerparams->prpc_call->b_supported) {
58 phandlerparams->success = 1;
59 }
60}
61
62
63static u32 volt_pmu_rpc_execute(struct gk20a *g,
64 struct nv_pmu_volt_rpc *prpc_call)
65{
66 struct pmu_cmd cmd;
67 struct pmu_msg msg;
68 struct pmu_payload payload;
69 u32 status = 0;
70 u32 seqdesc;
71 struct volt_rpc_pmucmdhandler_params handler;
72
73 memset(&payload, 0, sizeof(struct pmu_payload));
74 memset(&cmd, 0, sizeof(struct pmu_cmd));
75 memset(&msg, 0, sizeof(struct pmu_msg));
76 memset(&handler, 0, sizeof(struct volt_rpc_pmucmdhandler_params));
77
78 cmd.hdr.unit_id = PMU_UNIT_VOLT;
79 cmd.hdr.size = (u32)sizeof(struct nv_pmu_volt_cmd) +
80 (u32)sizeof(struct pmu_hdr);
81 cmd.cmd.volt.cmd_type = NV_PMU_VOLT_CMD_ID_RPC;
82 msg.hdr.size = sizeof(struct pmu_msg);
83
84 payload.in.buf = (u8 *)prpc_call;
85 payload.in.size = (u32)sizeof(struct nv_pmu_volt_rpc);
86 payload.in.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
87 payload.in.offset = NV_PMU_VOLT_CMD_RPC_ALLOC_OFFSET;
88
89 payload.out.buf = (u8 *)prpc_call;
90 payload.out.size = (u32)sizeof(struct nv_pmu_volt_rpc);
91 payload.out.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
92 payload.out.offset = NV_PMU_VOLT_MSG_RPC_ALLOC_OFFSET;
93
94 handler.prpc_call = prpc_call;
95 handler.success = 0;
96
97 status = nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload,
98 PMU_COMMAND_QUEUE_LPQ,
99 volt_rpc_pmucmdhandler, (void *)&handler,
100 &seqdesc, ~0);
101 if (status) {
102 nvgpu_err(g, "unable to post volt RPC cmd %x",
103 cmd.cmd.volt.cmd_type);
104 goto volt_pmu_rpc_execute;
105 }
106
107 pmu_wait_message_cond(&g->pmu,
108 gk20a_get_gr_idle_timeout(g),
109 &handler.success, 1);
110
111 if (handler.success == 0U) {
112 status = -EINVAL;
113 nvgpu_err(g, "rpc call to volt failed");
114 }
115
116volt_pmu_rpc_execute:
117 return status;
118}
119
120u32 nvgpu_volt_send_load_cmd_to_pmu_gp10x(struct gk20a *g)
121{
122 struct nv_pmu_volt_rpc rpc_call = { 0 };
123 u32 status = 0;
124
125 rpc_call.function = NV_PMU_VOLT_RPC_ID_LOAD;
126
127 status = volt_pmu_rpc_execute(g, &rpc_call);
128 if (status) {
129 nvgpu_err(g,
130 "Error while executing LOAD RPC: status = 0x%08x.",
131 status);
132 }
133
134 return status;
135}
136
137u32 nvgpu_volt_send_load_cmd_to_pmu_gv10x(struct gk20a *g)
138{
139 struct nvgpu_pmu *pmu = &g->pmu;
140 struct nv_pmu_rpc_struct_volt_load rpc;
141 u32 status = 0;
142
143 memset(&rpc, 0, sizeof(struct nv_pmu_rpc_struct_volt_load));
144 PMU_RPC_EXECUTE(status, pmu, VOLT, LOAD, &rpc, 0);
145 if (status) {
146 nvgpu_err(g, "Failed to execute RPC status=0x%x",
147 status);
148 }
149
150 return status;
151}
152
153u32 nvgpu_volt_rail_get_voltage_gp10x(struct gk20a *g,
154 u8 volt_domain, u32 *pvoltage_uv)
155{
156 struct nv_pmu_volt_rpc rpc_call = { 0 };
157 u32 status = 0;
158 u8 rail_idx;
159
160 rail_idx = volt_rail_volt_domain_convert_to_idx(g, volt_domain);
161 if ((rail_idx == CTRL_VOLT_RAIL_INDEX_INVALID) ||
162 (!VOLT_RAIL_INDEX_IS_VALID(&g->perf_pmu.volt, rail_idx))) {
163 nvgpu_err(g,
164 "failed: volt_domain = %d, voltage rail table = %d.",
165 volt_domain, rail_idx);
166 return -EINVAL;
167 }
168
169 /* Set RPC parameters. */
170 rpc_call.function = NV_PMU_VOLT_RPC_ID_VOLT_RAIL_GET_VOLTAGE;
171 rpc_call.params.volt_rail_get_voltage.rail_idx = rail_idx;
172
173 /* Execute the voltage get request via PMU RPC. */
174 status = volt_pmu_rpc_execute(g, &rpc_call);
175 if (status) {
176 nvgpu_err(g,
177 "Error while executing volt_rail_get_voltage rpc");
178 return status;
179 }
180
181 /* Copy out the current voltage. */
182 *pvoltage_uv = rpc_call.params.volt_rail_get_voltage.voltage_uv;
183
184 return status;
185}
186
187u32 nvgpu_volt_rail_get_voltage_gv10x(struct gk20a *g,
188 u8 volt_domain, u32 *pvoltage_uv)
189{
190 struct nvgpu_pmu *pmu = &g->pmu;
191 struct nv_pmu_rpc_struct_volt_volt_rail_get_voltage rpc;
192 u32 status = 0;
193 u8 rail_idx;
194
195 rail_idx = volt_rail_volt_domain_convert_to_idx(g, volt_domain);
196 if ((rail_idx == CTRL_VOLT_RAIL_INDEX_INVALID) ||
197 (!VOLT_RAIL_INDEX_IS_VALID(&g->perf_pmu.volt, rail_idx))) {
198 nvgpu_err(g,
199 "failed: volt_domain = %d, voltage rail table = %d.",
200 volt_domain, rail_idx);
201 return -EINVAL;
202 }
203
204 memset(&rpc, 0,
205 sizeof(struct nv_pmu_rpc_struct_volt_volt_rail_get_voltage));
206 rpc.rail_idx = rail_idx;
207
208 PMU_RPC_EXECUTE_CPB(status, pmu, VOLT, VOLT_RAIL_GET_VOLTAGE, &rpc, 0);
209 if (status) {
210 nvgpu_err(g, "Failed to execute RPC status=0x%x",
211 status);
212 }
213
214 *pvoltage_uv = rpc.voltage_uv;
215
216 return status;
217}
218
219static u32 volt_policy_set_voltage(struct gk20a *g, u8 client_id,
220 struct ctrl_perf_volt_rail_list *prail_list)
221{
222 struct nv_pmu_volt_rpc rpc_call = { 0 };
223 struct obj_volt *pvolt = &g->perf_pmu.volt;
224 u32 status = 0;
225 u8 policy_idx = CTRL_VOLT_POLICY_INDEX_INVALID;
226 u8 i = 0;
227
228 /* Sanity check input rail list. */
229 for (i = 0; i < prail_list->num_rails; i++) {
230 if ((prail_list->rails[i].volt_domain ==
231 CTRL_VOLT_DOMAIN_INVALID) ||
232 (prail_list->rails[i].voltage_uv ==
233 NV_PMU_VOLT_VALUE_0V_IN_UV)) {
234 nvgpu_err(g, "Invalid voltage domain or target");
235 nvgpu_err(g, " client_id = %d, listEntry = %d",
236 client_id, i);
237 nvgpu_err(g, " volt_domain = %d, voltage_uv = %d uV.",
238 prail_list->rails[i].volt_domain,
239 prail_list->rails[i].voltage_uv);
240 status = -EINVAL;
241 goto exit;
242 }
243 }
244
245 /* Convert the client ID to index. */
246 if (client_id == CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ) {
247 policy_idx =
248 pvolt->volt_policy_metadata.perf_core_vf_seq_policy_idx;
249 }
250 else {
251 status = -EINVAL;
252 goto exit;
253 }
254
255 /* Set RPC parameters. */
256 rpc_call.function = NV_PMU_VOLT_RPC_ID_VOLT_POLICY_SET_VOLTAGE;
257 rpc_call.params.volt_policy_voltage_data.policy_idx = policy_idx;
258 memcpy(&rpc_call.params.volt_policy_voltage_data.rail_list, prail_list,
259 (sizeof(struct ctrl_perf_volt_rail_list)));
260
261 /* Execute the voltage change request via PMU RPC. */
262 status = volt_pmu_rpc_execute(g, &rpc_call);
263 if (status) {
264 nvgpu_err(g,
265 "Error while executing VOLT_POLICY_SET_VOLTAGE RPC");
266 }
267
268exit:
269 return status;
270}
271
272static u32 volt_set_voltage_gv10x_rpc(struct gk20a *g, u8 client_id,
273 struct ctrl_volt_volt_rail_list_v1 *prail_list)
274{
275 struct nvgpu_pmu *pmu = &g->pmu;
276 struct nv_pmu_rpc_struct_volt_volt_set_voltage rpc;
277 int status = 0;
278
279 memset(&rpc, 0, sizeof(struct nv_pmu_rpc_struct_volt_volt_set_voltage));
280 rpc.client_id = 0x1;
281 rpc.rail_list = *prail_list;
282
283 PMU_RPC_EXECUTE_CPB(status, pmu, VOLT, VOLT_SET_VOLTAGE, &rpc, 0);
284 if (status) {
285 nvgpu_err(g, "Failed to execute RPC status=0x%x",
286 status);
287 }
288
289 return status;
290}
291
292u32 nvgpu_volt_set_voltage_gv10x(struct gk20a *g, u32 logic_voltage_uv,
293 u32 sram_voltage_uv)
294{
295 int status = 0;
296 struct ctrl_volt_volt_rail_list_v1 rail_list = { 0 };
297
298 rail_list.num_rails = RAIL_COUNT_GV;
299 rail_list.rails[0].rail_idx =
300 volt_rail_volt_domain_convert_to_idx(g,
301 CTRL_VOLT_DOMAIN_LOGIC);
302 rail_list.rails[0].voltage_uv = logic_voltage_uv;
303 rail_list.rails[0].voltage_min_noise_unaware_uv = logic_voltage_uv;
304
305 status = volt_set_voltage_gv10x_rpc(g,
306 CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ, &rail_list);
307
308 return status;
309}
310
311u32 nvgpu_volt_set_voltage_gp10x(struct gk20a *g, u32 logic_voltage_uv,
312 u32 sram_voltage_uv)
313{
314 int status = 0;
315 struct ctrl_perf_volt_rail_list rail_list = { 0 };
316
317 rail_list.num_rails = RAIL_COUNT_GP;
318 rail_list.rails[0].volt_domain = CTRL_VOLT_DOMAIN_LOGIC;
319 rail_list.rails[0].voltage_uv = logic_voltage_uv;
320 rail_list.rails[0].voltage_min_noise_unaware_uv = logic_voltage_uv;
321 rail_list.rails[1].volt_domain = CTRL_VOLT_DOMAIN_SRAM;
322 rail_list.rails[1].voltage_uv = sram_voltage_uv;
323 rail_list.rails[1].voltage_min_noise_unaware_uv = sram_voltage_uv;
324
325 status = volt_policy_set_voltage(g,
326 CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ, &rail_list);
327
328 return status;
329}
330
331u32 volt_set_voltage(struct gk20a *g, u32 logic_voltage_uv, u32 sram_voltage_uv)
332{
333 return g->ops.pmu_ver.volt.volt_set_voltage(g,
334 logic_voltage_uv, sram_voltage_uv);
335}
336
337u32 volt_get_voltage(struct gk20a *g, u32 volt_domain, u32 *voltage_uv)
338{
339 return g->ops.pmu_ver.volt.volt_get_voltage(g,
340 volt_domain, voltage_uv);
341}
342
343static int volt_policy_set_noiseaware_vmin(struct gk20a *g,
344 struct ctrl_volt_volt_rail_list *prail_list)
345{
346 struct nv_pmu_volt_rpc rpc_call = { 0 };
347 u32 status = 0;
348
349 /* Set RPC parameters. */
350 rpc_call.function = NV_PMU_VOLT_RPC_ID_VOLT_RAIL_SET_NOISE_UNAWARE_VMIN;
351 rpc_call.params.volt_rail_set_noise_unaware_vmin.num_rails =
352 prail_list->num_rails;
353 memcpy(&rpc_call.params.volt_rail_set_noise_unaware_vmin.rail_list,
354 prail_list, (sizeof(struct ctrl_volt_volt_rail_list)));
355
356 /* Execute the voltage change request via PMU RPC. */
357 status = volt_pmu_rpc_execute(g, &rpc_call);
358 if (status) {
359 nvgpu_err(g,
360 "Error while executing VOLT_POLICY_SET_VOLTAGE RPC");
361 return -EINVAL;
362 }
363
364 return 0;
365}
366
367int volt_set_noiseaware_vmin(struct gk20a *g, u32 logic_voltage_uv,
368 u32 sram_voltage_uv)
369{
370 int status = 0;
371 struct ctrl_volt_volt_rail_list rail_list = { 0 };
372
373 rail_list.num_rails = RAIL_COUNT_GP;
374 rail_list.rails[0].rail_idx = 0;
375 rail_list.rails[0].voltage_uv = logic_voltage_uv;
376 rail_list.rails[1].rail_idx = 1;
377 rail_list.rails[1].voltage_uv = sram_voltage_uv;
378
379 status = volt_policy_set_noiseaware_vmin(g, &rail_list);
380
381 return status;
382
383}
384
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