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-rw-r--r--include/volt/volt_dev.c609
1 files changed, 0 insertions, 609 deletions
diff --git a/include/volt/volt_dev.c b/include/volt/volt_dev.c
deleted file mode 100644
index bb5d182..0000000
--- a/include/volt/volt_dev.c
+++ /dev/null
@@ -1,609 +0,0 @@
1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/types.h>
24#include <nvgpu/sort.h>
25#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
26#include <nvgpu/bios.h>
27#include <nvgpu/kmem.h>
28#include <nvgpu/gk20a.h>
29
30#include "gp106/bios_gp106.h"
31
32#include "boardobj/boardobjgrp.h"
33#include "boardobj/boardobjgrp_e32.h"
34#include "ctrl/ctrlvolt.h"
35
36#include "volt.h"
37
38#define VOLT_DEV_PWM_VOLTAGE_STEPS_INVALID 0U
39#define VOLT_DEV_PWM_VOLTAGE_STEPS_DEFAULT 1U
40
41static int volt_device_pmu_data_init_super(struct gk20a *g,
42 struct boardobj *pboard_obj, struct nv_pmu_boardobj *ppmudata)
43{
44 int status;
45 struct voltage_device *pdev;
46 struct nv_pmu_volt_volt_device_boardobj_set *pset;
47
48 status = boardobj_pmudatainit_super(g, pboard_obj, ppmudata);
49 if (status) {
50 return status;
51 }
52
53 pdev = (struct voltage_device *)pboard_obj;
54 pset = (struct nv_pmu_volt_volt_device_boardobj_set *)ppmudata;
55
56 pset->switch_delay_us = pdev->switch_delay_us;
57 pset->voltage_min_uv = pdev->voltage_min_uv;
58 pset->voltage_max_uv = pdev->voltage_max_uv;
59 pset->volt_step_uv = pdev->volt_step_uv;
60
61 return status;
62}
63
64static int volt_device_pmu_data_init_pwm(struct gk20a *g,
65 struct boardobj *pboard_obj, struct nv_pmu_boardobj *ppmudata)
66{
67 int status = 0;
68 struct voltage_device_pwm *pdev;
69 struct nv_pmu_volt_volt_device_pwm_boardobj_set *pset;
70
71 status = volt_device_pmu_data_init_super(g, pboard_obj, ppmudata);
72 if (status) {
73 return status;
74 }
75
76 pdev = (struct voltage_device_pwm *)pboard_obj;
77 pset = (struct nv_pmu_volt_volt_device_pwm_boardobj_set *)ppmudata;
78
79 pset->raw_period = pdev->raw_period;
80 pset->voltage_base_uv = pdev->voltage_base_uv;
81 pset->voltage_offset_scale_uv = pdev->voltage_offset_scale_uv;
82 pset->pwm_source = pdev->source;
83
84 return status;
85}
86
87static int construct_volt_device(struct gk20a *g,
88 struct boardobj **ppboardobj, u16 size, void *pargs)
89{
90 struct voltage_device *ptmp_dev = (struct voltage_device *)pargs;
91 struct voltage_device *pvolt_dev = NULL;
92 int status = 0;
93
94 status = boardobj_construct_super(g, ppboardobj, size, pargs);
95 if (status) {
96 return status;
97 }
98
99 pvolt_dev = (struct voltage_device *)*ppboardobj;
100
101 pvolt_dev->volt_domain = ptmp_dev->volt_domain;
102 pvolt_dev->i2c_dev_idx = ptmp_dev->i2c_dev_idx;
103 pvolt_dev->switch_delay_us = ptmp_dev->switch_delay_us;
104 pvolt_dev->rsvd_0 = VOLTAGE_DESCRIPTOR_TABLE_ENTRY_INVALID;
105 pvolt_dev->rsvd_1 =
106 VOLTAGE_DESCRIPTOR_TABLE_ENTRY_INVALID;
107 pvolt_dev->operation_type = ptmp_dev->operation_type;
108 pvolt_dev->voltage_min_uv = ptmp_dev->voltage_min_uv;
109 pvolt_dev->voltage_max_uv = ptmp_dev->voltage_max_uv;
110
111 pvolt_dev->super.pmudatainit = volt_device_pmu_data_init_super;
112
113 return status;
114}
115
116static int construct_pwm_volt_device(struct gk20a *g,
117 struct boardobj **ppboardobj,
118 u16 size, void *pargs)
119{
120 struct boardobj *pboard_obj = NULL;
121 struct voltage_device_pwm *ptmp_dev =
122 (struct voltage_device_pwm *)pargs;
123 struct voltage_device_pwm *pdev = NULL;
124 int status = 0;
125
126 status = construct_volt_device(g, ppboardobj, size, pargs);
127 if (status) {
128 return status;
129 }
130
131 pboard_obj = (*ppboardobj);
132 pdev = (struct voltage_device_pwm *)*ppboardobj;
133
134 pboard_obj->pmudatainit = volt_device_pmu_data_init_pwm;
135
136 /* Set VOLTAGE_DEVICE_PWM-specific parameters */
137 pdev->voltage_base_uv = ptmp_dev->voltage_base_uv;
138 pdev->voltage_offset_scale_uv = ptmp_dev->voltage_offset_scale_uv;
139 pdev->source = ptmp_dev->source;
140 pdev->raw_period = ptmp_dev->raw_period;
141
142 return status;
143}
144
145
146static struct voltage_device_entry *volt_dev_construct_dev_entry_pwm(
147 struct gk20a *g,
148 u32 voltage_uv, void *pargs)
149{
150 struct voltage_device_pwm_entry *pentry = NULL;
151 struct voltage_device_pwm_entry *ptmp_entry =
152 (struct voltage_device_pwm_entry *)pargs;
153
154 pentry = nvgpu_kzalloc(g, sizeof(struct voltage_device_pwm_entry));
155 if (pentry == NULL) {
156 return NULL;
157 }
158
159 memset(pentry, 0, sizeof(struct voltage_device_pwm_entry));
160
161 pentry->super.voltage_uv = voltage_uv;
162 pentry->duty_cycle = ptmp_entry->duty_cycle;
163
164 return (struct voltage_device_entry *)pentry;
165}
166
167static u8 volt_dev_operation_type_convert(u8 vbios_type)
168{
169 switch (vbios_type) {
170 case NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_DEFAULT:
171 return CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT;
172
173 case NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_LPWR_STEADY_STATE:
174 return CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_STEADY_STATE;
175
176 case NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_LPWR_SLEEP_STATE:
177 return CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_SLEEP_STATE;
178 }
179
180 return CTRL_VOLT_DEVICE_OPERATION_TYPE_INVALID;
181}
182
183static struct voltage_device *volt_volt_device_construct(struct gk20a *g,
184 void *pargs)
185{
186 struct boardobj *pboard_obj = NULL;
187
188 if (BOARDOBJ_GET_TYPE(pargs) == CTRL_VOLT_DEVICE_TYPE_PWM) {
189 int status = construct_pwm_volt_device(g, &pboard_obj,
190 sizeof(struct voltage_device_pwm), pargs);
191 if (status) {
192 nvgpu_err(g,
193 " Could not allocate memory for VOLTAGE_DEVICE type (%x).",
194 BOARDOBJ_GET_TYPE(pargs));
195 pboard_obj = NULL;
196 }
197 }
198
199 return (struct voltage_device *)pboard_obj;
200}
201
202static int volt_get_voltage_device_table_1x_psv(struct gk20a *g,
203 struct vbios_voltage_device_table_1x_entry *p_bios_entry,
204 struct voltage_device_metadata *p_Volt_Device_Meta_Data,
205 u8 entry_Idx)
206{
207 int status = 0;
208 u32 entry_cnt = 0;
209 struct voltage_device *pvolt_dev = NULL;
210 struct voltage_device_pwm *pvolt_dev_pwm = NULL;
211 struct voltage_device_pwm *ptmp_dev = NULL;
212 u32 duty_cycle;
213 u32 frequency_hz;
214 u32 voltage_uv;
215 u8 ext_dev_idx;
216 u8 steps;
217 u8 volt_domain = 0;
218 struct voltage_device_pwm_entry pwm_entry = { { 0 } };
219
220 ptmp_dev = nvgpu_kzalloc(g, sizeof(struct voltage_device_pwm));
221 if (ptmp_dev == NULL) {
222 return -ENOMEM;
223 }
224
225 frequency_hz = (u32)BIOS_GET_FIELD(p_bios_entry->param0,
226 NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_INPUT_FREQUENCY);
227
228 ext_dev_idx = (u8)BIOS_GET_FIELD(p_bios_entry->param0,
229 NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_EXT_DEVICE_INDEX);
230
231 ptmp_dev->super.operation_type = volt_dev_operation_type_convert(
232 (u8)BIOS_GET_FIELD(p_bios_entry->param1,
233 NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE));
234
235 if (ptmp_dev->super.operation_type ==
236 CTRL_VOLT_DEVICE_OPERATION_TYPE_INVALID) {
237 nvgpu_err(g, " Invalid Voltage Device Operation Type.");
238
239 status = -EINVAL;
240 goto done;
241 }
242
243 ptmp_dev->super.voltage_min_uv =
244 (u32)BIOS_GET_FIELD(p_bios_entry->param1,
245 NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_VOLTAGE_MINIMUM);
246
247 ptmp_dev->super.voltage_max_uv =
248 (u32)BIOS_GET_FIELD(p_bios_entry->param2,
249 NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_VOLTAGE_MAXIMUM);
250
251 ptmp_dev->voltage_base_uv = BIOS_GET_FIELD(p_bios_entry->param3,
252 NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_BASE);
253
254 steps = (u8)BIOS_GET_FIELD(p_bios_entry->param3,
255 NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_STEPS);
256 if (steps == VOLT_DEV_PWM_VOLTAGE_STEPS_INVALID) {
257 steps = VOLT_DEV_PWM_VOLTAGE_STEPS_DEFAULT;
258 }
259
260 ptmp_dev->voltage_offset_scale_uv =
261 BIOS_GET_FIELD(p_bios_entry->param4,
262 NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_OFFSET_SCALE);
263
264 volt_domain = volt_rail_vbios_volt_domain_convert_to_internal(g,
265 (u8)p_bios_entry->volt_domain);
266 if (volt_domain == CTRL_VOLT_DOMAIN_INVALID) {
267 nvgpu_err(g, "invalid voltage domain = %d",
268 (u8)p_bios_entry->volt_domain);
269 status = -EINVAL;
270 goto done;
271 }
272
273 if (ptmp_dev->super.operation_type ==
274 CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT) {
275 if (volt_domain == CTRL_VOLT_DOMAIN_LOGIC) {
276 ptmp_dev->source =
277 NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_0;
278 }
279 if (volt_domain == CTRL_VOLT_DOMAIN_SRAM) {
280 ptmp_dev->source =
281 NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_1;
282 }
283 ptmp_dev->raw_period =
284 g->ops.clk.get_crystal_clk_hz(g) / frequency_hz;
285 } else if (ptmp_dev->super.operation_type ==
286 CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_STEADY_STATE) {
287 ptmp_dev->source = NV_PMU_PMGR_PWM_SOURCE_RSVD_0;
288 ptmp_dev->raw_period = 0;
289 } else if (ptmp_dev->super.operation_type ==
290 CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_SLEEP_STATE) {
291 ptmp_dev->source = NV_PMU_PMGR_PWM_SOURCE_RSVD_1;
292 ptmp_dev->raw_period = 0;
293 }
294
295 /* Initialize data for parent class. */
296 ptmp_dev->super.super.type = CTRL_VOLT_DEVICE_TYPE_PWM;
297 ptmp_dev->super.volt_domain = volt_domain;
298 ptmp_dev->super.i2c_dev_idx = ext_dev_idx;
299 ptmp_dev->super.switch_delay_us = (u16)p_bios_entry->settle_time_us;
300
301 pvolt_dev = volt_volt_device_construct(g, ptmp_dev);
302 if (pvolt_dev == NULL) {
303 nvgpu_err(g, " Failure to construct VOLTAGE_DEVICE object.");
304
305 status = -EINVAL;
306 goto done;
307 }
308
309 status = boardobjgrp_objinsert(
310 &p_Volt_Device_Meta_Data->volt_devices.super,
311 (struct boardobj *)pvolt_dev, entry_Idx);
312 if (status) {
313 nvgpu_err(g,
314 "could not add VOLTAGE_DEVICE for entry %d into boardobjgrp ",
315 entry_Idx);
316 goto done;
317 }
318
319 pvolt_dev_pwm = (struct voltage_device_pwm *)pvolt_dev;
320
321 duty_cycle = 0;
322 do {
323 voltage_uv = (u32)(pvolt_dev_pwm->voltage_base_uv +
324 (s32)((((s64)((s32)duty_cycle)) *
325 pvolt_dev_pwm->voltage_offset_scale_uv)
326 / ((s64)((s32) pvolt_dev_pwm->raw_period))));
327
328 /* Skip creating entry for invalid voltage. */
329 if ((voltage_uv >= pvolt_dev_pwm->super.voltage_min_uv) &&
330 (voltage_uv <= pvolt_dev_pwm->super.voltage_max_uv)) {
331 if (pvolt_dev_pwm->voltage_offset_scale_uv < 0) {
332 pwm_entry.duty_cycle =
333 pvolt_dev_pwm->raw_period - duty_cycle;
334 } else {
335 pwm_entry.duty_cycle = duty_cycle;
336 }
337
338 /* Check if there is room left in the voltage table. */
339 if (entry_cnt == VOLTAGE_TABLE_MAX_ENTRIES) {
340 nvgpu_err(g, "Voltage table is full");
341 status = -EINVAL;
342 goto done;
343 }
344
345 pvolt_dev->pentry[entry_cnt] =
346 volt_dev_construct_dev_entry_pwm(g,
347 voltage_uv, &pwm_entry);
348 if (pvolt_dev->pentry[entry_cnt] == NULL) {
349 nvgpu_err(g,
350 " Error creating voltage_device_pwm_entry!");
351 status = -EINVAL;
352 goto done;
353 }
354
355 entry_cnt++;
356 }
357
358 /* Obtain next value after the specified steps. */
359 duty_cycle = duty_cycle + (u32)steps;
360
361 /* Cap duty cycle to PWM period. */
362 if (duty_cycle > pvolt_dev_pwm->raw_period) {
363 duty_cycle = pvolt_dev_pwm->raw_period;
364 }
365
366 } while (duty_cycle < pvolt_dev_pwm->raw_period);
367
368done:
369 if (pvolt_dev != NULL) {
370 pvolt_dev->num_entries = entry_cnt;
371 }
372
373 nvgpu_kfree(g, ptmp_dev);
374 return status;
375}
376
377static u32 volt_get_volt_devices_table(struct gk20a *g,
378 struct voltage_device_metadata *pvolt_device_metadata)
379{
380 u32 status = 0;
381 u8 *volt_device_table_ptr = NULL;
382 struct vbios_voltage_device_table_1x_header header = { 0 };
383 struct vbios_voltage_device_table_1x_entry entry = { 0 };
384 u8 entry_idx;
385 u8 *entry_offset;
386
387 volt_device_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
388 g->bios.perf_token, VOLTAGE_DEVICE_TABLE);
389 if (volt_device_table_ptr == NULL) {
390 status = -EINVAL;
391 goto done;
392 }
393
394 memcpy(&header, volt_device_table_ptr,
395 sizeof(struct vbios_voltage_device_table_1x_header));
396
397 /* Read in the entries. */
398 for (entry_idx = 0; entry_idx < header.num_table_entries; entry_idx++) {
399 entry_offset = (volt_device_table_ptr + header.header_size +
400 (entry_idx * header.table_entry_size));
401
402 memcpy(&entry, entry_offset,
403 sizeof(struct vbios_voltage_device_table_1x_entry));
404
405 if (entry.type == NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_PSV) {
406 status = volt_get_voltage_device_table_1x_psv(g,
407 &entry, pvolt_device_metadata,
408 entry_idx);
409 }
410 }
411
412done:
413 return status;
414}
415
416static int _volt_device_devgrp_pmudata_instget(struct gk20a *g,
417 struct nv_pmu_boardobjgrp *pmuboardobjgrp,
418 struct nv_pmu_boardobj **ppboardobjpmudata, u8 idx)
419{
420 struct nv_pmu_volt_volt_device_boardobj_grp_set *pgrp_set =
421 (struct nv_pmu_volt_volt_device_boardobj_grp_set *)
422 pmuboardobjgrp;
423
424 nvgpu_log_info(g, " ");
425
426 /*check whether pmuboardobjgrp has a valid boardobj in index*/
427 if (((u32)BIT(idx) &
428 pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0U) {
429 return -EINVAL;
430 }
431
432 *ppboardobjpmudata = (struct nv_pmu_boardobj *)
433 &pgrp_set->objects[idx].data.board_obj;
434 nvgpu_log_info(g, "Done");
435 return 0;
436}
437
438static int _volt_device_devgrp_pmustatus_instget(struct gk20a *g,
439 void *pboardobjgrppmu,
440 struct nv_pmu_boardobj_query **ppboardobjpmustatus, u8 idx)
441{
442 struct nv_pmu_volt_volt_device_boardobj_grp_get_status *pgrp_get_status
443 = (struct nv_pmu_volt_volt_device_boardobj_grp_get_status *)
444 pboardobjgrppmu;
445
446 /*check whether pmuboardobjgrp has a valid boardobj in index*/
447 if (((u32)BIT(idx) &
448 pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0U) {
449 return -EINVAL;
450 }
451
452 *ppboardobjpmustatus = (struct nv_pmu_boardobj_query *)
453 &pgrp_get_status->objects[idx].data.board_obj;
454 return 0;
455}
456
457static int volt_device_volt_cmp(const void *a, const void *b)
458{
459 const struct voltage_device_entry *a_entry = *(const struct voltage_device_entry **)a;
460 const struct voltage_device_entry *b_entry = *(const struct voltage_device_entry **)b;
461
462 return (int)a_entry->voltage_uv - (int)b_entry->voltage_uv;
463}
464
465static u32 volt_device_state_init(struct gk20a *g,
466 struct voltage_device *pvolt_dev)
467{
468 u32 status = 0;
469 struct voltage_rail *pRail = NULL;
470 u8 rail_idx = 0;
471
472 sort(pvolt_dev->pentry, pvolt_dev->num_entries,
473 sizeof(*pvolt_dev->pentry), volt_device_volt_cmp,
474 NULL);
475
476 /* Initialize VOLT_DEVICE step size. */
477 if (pvolt_dev->num_entries <= VOLTAGE_TABLE_MAX_ENTRIES_ONE) {
478 pvolt_dev->volt_step_uv = NV_PMU_VOLT_VALUE_0V_IN_UV;
479 } else {
480 pvolt_dev->volt_step_uv = (pvolt_dev->pentry[1]->voltage_uv -
481 pvolt_dev->pentry[0]->voltage_uv);
482 }
483
484 /* Build VOLT_RAIL SW state from VOLT_DEVICE SW state. */
485 /* If VOLT_RAIL isn't supported, exit. */
486 if (VOLT_RAIL_VOLT_3X_SUPPORTED(&g->perf_pmu.volt)) {
487 rail_idx = volt_rail_volt_domain_convert_to_idx(g,
488 pvolt_dev->volt_domain);
489 if (rail_idx == CTRL_BOARDOBJ_IDX_INVALID) {
490 nvgpu_err(g,
491 " could not convert voltage domain to rail index.");
492 status = -EINVAL;
493 goto done;
494 }
495
496 pRail = VOLT_GET_VOLT_RAIL(&g->perf_pmu.volt, rail_idx);
497 if (pRail == NULL) {
498 nvgpu_err(g,
499 "could not obtain ptr to rail object from rail index");
500 status = -EINVAL;
501 goto done;
502 }
503
504 status = volt_rail_volt_dev_register(g, pRail,
505 BOARDOBJ_GET_IDX(pvolt_dev), pvolt_dev->operation_type);
506 if (status) {
507 nvgpu_err(g,
508 "Failed to register the device with rail obj");
509 goto done;
510 }
511 }
512
513done:
514 if (status) {
515 nvgpu_err(g, "Error in building rail sw state device sw");
516 }
517
518 return status;
519}
520
521int volt_dev_pmu_setup(struct gk20a *g)
522{
523 int status;
524 struct boardobjgrp *pboardobjgrp = NULL;
525
526 nvgpu_log_info(g, " ");
527
528 pboardobjgrp = &g->perf_pmu.volt.volt_dev_metadata.volt_devices.super;
529
530 if (!pboardobjgrp->bconstructed) {
531 return -EINVAL;
532 }
533
534 status = pboardobjgrp->pmuinithandle(g, pboardobjgrp);
535
536 nvgpu_log_info(g, "Done");
537 return status;
538}
539
540u32 volt_dev_sw_setup(struct gk20a *g)
541{
542 u32 status = 0;
543 struct boardobjgrp *pboardobjgrp = NULL;
544 struct voltage_device *pvolt_device;
545 u8 i;
546
547 nvgpu_log_info(g, " ");
548
549 status = boardobjgrpconstruct_e32(g,
550 &g->perf_pmu.volt.volt_dev_metadata.volt_devices);
551 if (status) {
552 nvgpu_err(g,
553 "error creating boardobjgrp for volt rail, status - 0x%x",
554 status);
555 goto done;
556 }
557
558 pboardobjgrp = &g->perf_pmu.volt.volt_dev_metadata.volt_devices.super;
559
560 pboardobjgrp->pmudatainstget = _volt_device_devgrp_pmudata_instget;
561 pboardobjgrp->pmustatusinstget = _volt_device_devgrp_pmustatus_instget;
562
563 /* Obtain Voltage Rail Table from VBIOS */
564 status = volt_get_volt_devices_table(g, &g->perf_pmu.volt.
565 volt_dev_metadata);
566 if (status) {
567 goto done;
568 }
569
570 /* Populate data for the VOLT_RAIL PMU interface */
571 BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, VOLT, VOLT_DEVICE);
572
573 status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp,
574 volt, VOLT, volt_device, VOLT_DEVICE);
575 if (status) {
576 nvgpu_err(g,
577 "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x",
578 status);
579 goto done;
580 }
581
582 status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g,
583 &g->perf_pmu.volt.volt_dev_metadata.volt_devices.super,
584 volt, VOLT, volt_device, VOLT_DEVICE);
585 if (status) {
586 nvgpu_err(g,
587 "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x",
588 status);
589 goto done;
590 }
591
592 /* update calibration to fuse */
593 BOARDOBJGRP_FOR_EACH(&(g->perf_pmu.volt.volt_dev_metadata.volt_devices.
594 super),
595 struct voltage_device *, pvolt_device, i) {
596 status = volt_device_state_init(g, pvolt_device);
597 if (status) {
598 nvgpu_err(g,
599 "failure while executing devices's state init interface");
600 nvgpu_err(g,
601 " railIdx = %d, status = 0x%x", i, status);
602 goto done;
603 }
604 }
605
606done:
607 nvgpu_log_info(g, " done status %x", status);
608 return status;
609}
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 16:24:38 -0400