diff options
Diffstat (limited to 'include/therm/thrmchannel.c')
| -rw-r--r-- | include/therm/thrmchannel.c | 256 |
1 files changed, 256 insertions, 0 deletions
diff --git a/include/therm/thrmchannel.c b/include/therm/thrmchannel.c new file mode 100644 index 0000000..419ce0b --- /dev/null +++ b/include/therm/thrmchannel.c | |||
| @@ -0,0 +1,256 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. | ||
| 3 | * | ||
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
| 5 | * copy of this software and associated documentation files (the "Software"), | ||
| 6 | * to deal in the Software without restriction, including without limitation | ||
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
| 8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
| 9 | * Software is furnished to do so, subject to the following conditions: | ||
| 10 | * | ||
| 11 | * The above copyright notice and this permission notice shall be included in | ||
| 12 | * all copies or substantial portions of the Software. | ||
| 13 | * | ||
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
| 17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
| 18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
| 19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
| 20 | * DEALINGS IN THE SOFTWARE. | ||
| 21 | */ | ||
| 22 | |||
| 23 | #include <nvgpu/bios.h> | ||
| 24 | #include <nvgpu/gk20a.h> | ||
| 25 | #include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h> | ||
| 26 | |||
| 27 | #include "thrmchannel.h" | ||
| 28 | #include "boardobj/boardobjgrp.h" | ||
| 29 | #include "boardobj/boardobjgrp_e32.h" | ||
| 30 | #include "gp106/bios_gp106.h" | ||
| 31 | |||
| 32 | static int _therm_channel_pmudatainit_device(struct gk20a *g, | ||
| 33 | struct boardobj *board_obj_ptr, | ||
| 34 | struct nv_pmu_boardobj *ppmudata) | ||
| 35 | { | ||
| 36 | int status = 0; | ||
| 37 | struct therm_channel *pchannel; | ||
| 38 | struct therm_channel_device *ptherm_channel; | ||
| 39 | struct nv_pmu_therm_therm_channel_device_boardobj_set *pset; | ||
| 40 | |||
| 41 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); | ||
| 42 | if (status) { | ||
| 43 | nvgpu_err(g, | ||
| 44 | "error updating pmu boardobjgrp for therm channel 0x%x", | ||
| 45 | status); | ||
| 46 | status = -ENOMEM; | ||
| 47 | goto done; | ||
| 48 | } | ||
| 49 | |||
| 50 | pchannel = (struct therm_channel *)board_obj_ptr; | ||
| 51 | pset = (struct nv_pmu_therm_therm_channel_device_boardobj_set *)ppmudata; | ||
| 52 | ptherm_channel = (struct therm_channel_device *)board_obj_ptr; | ||
| 53 | |||
| 54 | pset->super.scaling = pchannel->scaling; | ||
| 55 | pset->super.offset = pchannel->offset; | ||
| 56 | pset->super.temp_min = pchannel->temp_min; | ||
| 57 | pset->super.temp_max = pchannel->temp_max; | ||
| 58 | |||
| 59 | pset->therm_dev_idx = ptherm_channel->therm_dev_idx; | ||
| 60 | pset->therm_dev_prov_idx = ptherm_channel->therm_dev_prov_idx; | ||
| 61 | |||
| 62 | done: | ||
| 63 | return status; | ||
| 64 | } | ||
| 65 | static struct boardobj *construct_channel_device(struct gk20a *g, | ||
| 66 | void *pargs, u16 pargs_size, u8 type) | ||
| 67 | { | ||
| 68 | struct boardobj *board_obj_ptr = NULL; | ||
| 69 | struct therm_channel *pchannel; | ||
| 70 | struct therm_channel_device *pchannel_device; | ||
| 71 | int status; | ||
| 72 | struct therm_channel_device *therm_device = (struct therm_channel_device*)pargs; | ||
| 73 | |||
| 74 | status = boardobj_construct_super(g, &board_obj_ptr, | ||
| 75 | pargs_size, pargs); | ||
| 76 | if (status) { | ||
| 77 | return NULL; | ||
| 78 | } | ||
| 79 | |||
| 80 | /* Set Super class interfaces */ | ||
| 81 | board_obj_ptr->pmudatainit = _therm_channel_pmudatainit_device; | ||
| 82 | |||
| 83 | pchannel = (struct therm_channel *)board_obj_ptr; | ||
| 84 | pchannel_device = (struct therm_channel_device *)board_obj_ptr; | ||
| 85 | |||
| 86 | g->ops.therm.get_internal_sensor_limits(&pchannel->temp_max, | ||
| 87 | &pchannel->temp_min); | ||
| 88 | pchannel->scaling = (1 << 8); | ||
| 89 | pchannel->offset = 0; | ||
| 90 | |||
| 91 | pchannel_device->therm_dev_idx = therm_device->therm_dev_idx; | ||
| 92 | pchannel_device->therm_dev_prov_idx = therm_device->therm_dev_prov_idx; | ||
| 93 | |||
| 94 | nvgpu_log_info(g, " Done"); | ||
| 95 | |||
| 96 | return board_obj_ptr; | ||
| 97 | } | ||
| 98 | |||
| 99 | static int _therm_channel_pmudata_instget(struct gk20a *g, | ||
| 100 | struct nv_pmu_boardobjgrp *pmuboardobjgrp, | ||
| 101 | struct nv_pmu_boardobj **ppboardobjpmudata, | ||
| 102 | u8 idx) | ||
| 103 | { | ||
| 104 | struct nv_pmu_therm_therm_channel_boardobj_grp_set *pgrp_set = | ||
| 105 | (struct nv_pmu_therm_therm_channel_boardobj_grp_set *) | ||
| 106 | pmuboardobjgrp; | ||
| 107 | |||
| 108 | nvgpu_log_info(g, " "); | ||
| 109 | |||
| 110 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | ||
| 111 | if (((u32)BIT(idx) & | ||
| 112 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) { | ||
| 113 | return -EINVAL; | ||
| 114 | } | ||
| 115 | |||
| 116 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) | ||
| 117 | &pgrp_set->objects[idx].data.board_obj; | ||
| 118 | |||
| 119 | nvgpu_log_info(g, " Done"); | ||
| 120 | |||
| 121 | return 0; | ||
| 122 | } | ||
| 123 | |||
| 124 | static int devinit_get_therm_channel_table(struct gk20a *g, | ||
| 125 | struct therm_channels *pthermchannelobjs) | ||
| 126 | { | ||
| 127 | int status = 0; | ||
| 128 | u8 *therm_channel_table_ptr = NULL; | ||
| 129 | u8 *curr_therm_channel_table_ptr = NULL; | ||
| 130 | struct boardobj *boardobj; | ||
| 131 | struct therm_channel_1x_header therm_channel_table_header = { 0 }; | ||
| 132 | struct therm_channel_1x_entry *therm_channel_table_entry = NULL; | ||
| 133 | u32 index; | ||
| 134 | u32 obj_index = 0; | ||
| 135 | u16 therm_channel_size = 0; | ||
| 136 | union { | ||
| 137 | struct boardobj boardobj; | ||
| 138 | struct therm_channel therm_channel; | ||
| 139 | struct therm_channel_device device; | ||
| 140 | } therm_channel_data; | ||
| 141 | |||
| 142 | nvgpu_log_info(g, " "); | ||
| 143 | |||
| 144 | therm_channel_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, | ||
| 145 | g->bios.perf_token, THERMAL_CHANNEL_TABLE); | ||
| 146 | if (therm_channel_table_ptr == NULL) { | ||
| 147 | status = -EINVAL; | ||
| 148 | goto done; | ||
| 149 | } | ||
| 150 | |||
| 151 | memcpy(&therm_channel_table_header, therm_channel_table_ptr, | ||
| 152 | VBIOS_THERM_CHANNEL_1X_HEADER_SIZE_09); | ||
| 153 | |||
| 154 | if (therm_channel_table_header.version != | ||
| 155 | VBIOS_THERM_CHANNEL_VERSION_1X) { | ||
| 156 | status = -EINVAL; | ||
| 157 | goto done; | ||
| 158 | } | ||
| 159 | |||
| 160 | if (therm_channel_table_header.header_size < | ||
| 161 | VBIOS_THERM_CHANNEL_1X_HEADER_SIZE_09) { | ||
| 162 | status = -EINVAL; | ||
| 163 | goto done; | ||
| 164 | } | ||
| 165 | |||
| 166 | curr_therm_channel_table_ptr = (therm_channel_table_ptr + | ||
| 167 | VBIOS_THERM_CHANNEL_1X_HEADER_SIZE_09); | ||
| 168 | |||
| 169 | for (index = 0; index < therm_channel_table_header.num_table_entries; | ||
| 170 | index++) { | ||
| 171 | therm_channel_table_entry = (struct therm_channel_1x_entry *) | ||
| 172 | (curr_therm_channel_table_ptr + | ||
| 173 | (therm_channel_table_header.table_entry_size * index)); | ||
| 174 | |||
| 175 | if (therm_channel_table_entry->class_id != | ||
| 176 | NV_VBIOS_THERM_CHANNEL_1X_ENTRY_CLASS_DEVICE) { | ||
| 177 | continue; | ||
| 178 | } | ||
| 179 | |||
| 180 | therm_channel_data.device.therm_dev_idx = therm_channel_table_entry->param0; | ||
| 181 | therm_channel_data.device.therm_dev_prov_idx = therm_channel_table_entry->param1; | ||
| 182 | |||
| 183 | therm_channel_size = sizeof(struct therm_channel_device); | ||
| 184 | therm_channel_data.boardobj.type = CTRL_THERMAL_THERM_CHANNEL_CLASS_DEVICE; | ||
| 185 | |||
| 186 | boardobj = construct_channel_device(g, &therm_channel_data, | ||
| 187 | therm_channel_size, therm_channel_data.boardobj.type); | ||
| 188 | |||
| 189 | if (!boardobj) { | ||
| 190 | nvgpu_err(g, | ||
| 191 | "unable to create thermal device for %d type %d", | ||
| 192 | index, therm_channel_data.boardobj.type); | ||
| 193 | status = -EINVAL; | ||
| 194 | goto done; | ||
| 195 | } | ||
| 196 | |||
| 197 | status = boardobjgrp_objinsert(&pthermchannelobjs->super.super, | ||
| 198 | boardobj, obj_index); | ||
| 199 | |||
| 200 | if (status) { | ||
| 201 | nvgpu_err(g, | ||
| 202 | "unable to insert thermal device boardobj for %d", index); | ||
| 203 | status = -EINVAL; | ||
| 204 | goto done; | ||
| 205 | } | ||
| 206 | |||
| 207 | ++obj_index; | ||
| 208 | } | ||
| 209 | |||
| 210 | done: | ||
| 211 | nvgpu_log_info(g, " done status %x", status); | ||
| 212 | return status; | ||
| 213 | } | ||
| 214 | |||
| 215 | int therm_channel_sw_setup(struct gk20a *g) | ||
| 216 | { | ||
| 217 | int status; | ||
