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Diffstat (limited to 'include/pmgr/pmgrpmu.h')
| -rw-r--r-- | include/pmgr/pmgrpmu.h | 39 |
1 files changed, 0 insertions, 39 deletions
diff --git a/include/pmgr/pmgrpmu.h b/include/pmgr/pmgrpmu.h deleted file mode 100644 index f4ffaef..0000000 --- a/include/pmgr/pmgrpmu.h +++ /dev/null | |||
| @@ -1,39 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * general power device control structures & definitions | ||
| 3 | * | ||
| 4 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. | ||
| 5 | * | ||
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
| 7 | * copy of this software and associated documentation files (the "Software"), | ||
| 8 | * to deal in the Software without restriction, including without limitation | ||
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
| 10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
| 11 | * Software is furnished to do so, subject to the following conditions: | ||
| 12 | * | ||
| 13 | * The above copyright notice and this permission notice shall be included in | ||
| 14 | * all copies or substantial portions of the Software. | ||
| 15 | * | ||
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
| 21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
| 22 | * DEALINGS IN THE SOFTWARE. | ||
| 23 | */ | ||
| 24 | #ifndef NVGPU_PMGRPMU_H | ||
| 25 | #define NVGPU_PMGRPMU_H | ||
| 26 | |||
| 27 | #include <nvgpu/gk20a.h> | ||
| 28 | |||
| 29 | #include "pwrdev.h" | ||
| 30 | #include "pwrmonitor.h" | ||
| 31 | |||
| 32 | int pmgr_send_pmgr_tables_to_pmu(struct gk20a *g); | ||
| 33 | |||
| 34 | u32 pmgr_pmu_pwr_devices_query_blocking( | ||
| 35 | struct gk20a *g, | ||
| 36 | u32 pwr_dev_mask, | ||
| 37 | struct nv_pmu_pmgr_pwr_devices_query_payload *ppayload); | ||
| 38 | |||
| 39 | #endif /* NVGPU_PMGRPMU_H */ | ||
