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-rw-r--r--include/pmgr/pmgrpmu.c546
1 files changed, 0 insertions, 546 deletions
diff --git a/include/pmgr/pmgrpmu.c b/include/pmgr/pmgrpmu.c
deleted file mode 100644
index b6947f2..0000000
--- a/include/pmgr/pmgrpmu.c
+++ /dev/null
@@ -1,546 +0,0 @@
1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/kmem.h>
24#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
25#include <nvgpu/pmu.h>
26#include <nvgpu/gk20a.h>
27
28#include "gp106/bios_gp106.h"
29
30#include "boardobj/boardobjgrp.h"
31#include "boardobj/boardobjgrp_e32.h"
32
33#include "pwrdev.h"
34#include "pmgrpmu.h"
35
36struct pmgr_pmucmdhandler_params {
37 u32 success;
38};
39
40static void pmgr_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
41 void *param, u32 handle, u32 status)
42{
43 struct pmgr_pmucmdhandler_params *phandlerparams =
44 (struct pmgr_pmucmdhandler_params *)param;
45
46 if ((msg->msg.pmgr.msg_type != NV_PMU_PMGR_MSG_ID_SET_OBJECT) &&
47 (msg->msg.pmgr.msg_type != NV_PMU_PMGR_MSG_ID_QUERY) &&
48 (msg->msg.pmgr.msg_type != NV_PMU_PMGR_MSG_ID_LOAD)) {
49 nvgpu_err(g, "unknow msg %x", msg->msg.pmgr.msg_type);
50 return;
51 }
52
53 if (msg->msg.pmgr.msg_type == NV_PMU_PMGR_MSG_ID_SET_OBJECT) {
54 if ((msg->msg.pmgr.set_object.b_success != 1) ||
55 (msg->msg.pmgr.set_object.flcnstatus != 0U)) {
56 nvgpu_err(g, "pmgr msg failed %x %x %x %x",
57 msg->msg.pmgr.set_object.msg_type,
58 msg->msg.pmgr.set_object.b_success,
59 msg->msg.pmgr.set_object.flcnstatus,
60 msg->msg.pmgr.set_object.object_type);
61 return;
62 }
63 } else if (msg->msg.pmgr.msg_type == NV_PMU_PMGR_MSG_ID_QUERY) {
64 if ((msg->msg.pmgr.query.b_success != 1) ||
65 (msg->msg.pmgr.query.flcnstatus != 0U)) {
66 nvgpu_err(g, "pmgr msg failed %x %x %x %x",
67 msg->msg.pmgr.query.msg_type,
68 msg->msg.pmgr.query.b_success,
69 msg->msg.pmgr.query.flcnstatus,
70 msg->msg.pmgr.query.cmd_type);
71 return;
72 }
73 } else if (msg->msg.pmgr.msg_type == NV_PMU_PMGR_MSG_ID_LOAD) {
74 if ((msg->msg.pmgr.query.b_success != 1) ||
75 (msg->msg.pmgr.query.flcnstatus != 0U)) {
76 nvgpu_err(g, "pmgr msg failed %x %x %x",
77 msg->msg.pmgr.load.msg_type,
78 msg->msg.pmgr.load.b_success,
79 msg->msg.pmgr.load.flcnstatus);
80 return;
81 }
82 }
83
84 phandlerparams->success = 1;
85}
86
87static u32 pmgr_pmu_set_object(struct gk20a *g,
88 u8 type,
89 u16 dmem_size,
90 u16 fb_size,
91 void *pobj)
92{
93 struct pmu_cmd cmd;
94 struct pmu_payload payload;
95 struct nv_pmu_pmgr_cmd_set_object *pcmd;
96 u32 status;
97 u32 seqdesc;
98 struct pmgr_pmucmdhandler_params handlerparams;
99
100 memset(&payload, 0, sizeof(struct pmu_payload));
101 memset(&cmd, 0, sizeof(struct pmu_cmd));
102 memset(&handlerparams, 0, sizeof(struct pmgr_pmucmdhandler_params));
103
104 cmd.hdr.unit_id = PMU_UNIT_PMGR;
105 cmd.hdr.size = (u32)sizeof(struct nv_pmu_pmgr_cmd_set_object) +
106 (u32)sizeof(struct pmu_hdr);;
107
108 pcmd = &cmd.cmd.pmgr.set_object;
109 pcmd->cmd_type = NV_PMU_PMGR_CMD_ID_SET_OBJECT;
110 pcmd->object_type = type;
111
112 payload.in.buf = pobj;
113 payload.in.size = dmem_size;
114 payload.in.fb_size = fb_size;
115 payload.in.offset = NV_PMU_PMGR_SET_OBJECT_ALLOC_OFFSET;
116
117 /* Setup the handler params to communicate back results.*/
118 handlerparams.success = 0;
119
120 status = nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload,
121 PMU_COMMAND_QUEUE_LPQ,
122 pmgr_pmucmdhandler,
123 (void *)&handlerparams,
124 &seqdesc, ~0);
125 if (status) {
126 nvgpu_err(g,
127 "unable to post pmgr cmd for unit %x cmd id %x obj type %x",
128 cmd.hdr.unit_id, pcmd->cmd_type, pcmd->object_type);
129 goto exit;
130 }
131
132 pmu_wait_message_cond(&g->pmu,
133 gk20a_get_gr_idle_timeout(g),
134 &handlerparams.success, 1);
135
136 if (handlerparams.success == 0U) {
137 nvgpu_err(g, "could not process cmd");
138 status = -ETIMEDOUT;
139 goto exit;
140 }
141
142exit:
143 return status;
144}
145
146static u32 pmgr_send_i2c_device_topology_to_pmu(struct gk20a *g)
147{
148 struct nv_pmu_pmgr_i2c_device_desc_table i2c_desc_table;
149 u32 idx = g->ina3221_dcb_index;
150 u32 status = 0;
151
152 /* INA3221 I2C device info */
153 i2c_desc_table.dev_mask = (1UL << idx);
154
155 /* INA3221 */
156 i2c_desc_table.devices[idx].super.type = 0x4E;
157
158 i2c_desc_table.devices[idx].dcb_index = idx;
159 i2c_desc_table.devices[idx].i2c_address = g->ina3221_i2c_address;
160 i2c_desc_table.devices[idx].i2c_flags = 0xC2F;
161 i2c_desc_table.devices[idx].i2c_port = g->ina3221_i2c_port;
162
163 /* Pass the table down the PMU as an object */
164 status = pmgr_pmu_set_object(
165 g,
166 NV_PMU_PMGR_OBJECT_I2C_DEVICE_DESC_TABLE,
167 (u16)sizeof(struct nv_pmu_pmgr_i2c_device_desc_table),
168 PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED,
169 &i2c_desc_table);
170
171 if (status) {
172 nvgpu_err(g, "pmgr_pmu_set_object failed %x",
173 status);
174 }
175
176 return status;
177}
178
179static int pmgr_send_pwr_device_topology_to_pmu(struct gk20a *g)
180{
181 struct nv_pmu_pmgr_pwr_device_desc_table *pwr_desc_table;
182 struct nv_pmu_pmgr_pwr_device_desc_table_header *ppwr_desc_header;
183 int status = 0;
184
185 /* Set the BA-device-independent HW information */
186 pwr_desc_table = nvgpu_kzalloc(g, sizeof(*pwr_desc_table));
187 if (!pwr_desc_table) {
188 return -ENOMEM;
189 }
190
191 ppwr_desc_header = &(pwr_desc_table->hdr.data);
192 ppwr_desc_header->ba_info.b_initialized_and_used = false;
193
194 /* populate the table */
195 boardobjgrpe32hdrset((struct nv_pmu_boardobjgrp *)&ppwr_desc_header->super,
196 g->pmgr_pmu.pmgr_deviceobjs.super.super.objmask);
197
198 status = boardobjgrp_pmudatainit_legacy(g,
199 &g->pmgr_pmu.pmgr_deviceobjs.super.super,
200 (struct nv_pmu_boardobjgrp_super *)pwr_desc_table);
201
202 if (status) {
203 nvgpu_err(g, "boardobjgrp_pmudatainit_legacy failed %x",
204 status);
205 goto exit;
206 }
207
208 /* Pass the table down the PMU as an object */
209 status = pmgr_pmu_set_object(
210 g,
211 NV_PMU_PMGR_OBJECT_PWR_DEVICE_DESC_TABLE,
212 (u16)sizeof(
213 union nv_pmu_pmgr_pwr_device_dmem_size),
214 (u16)sizeof(struct nv_pmu_pmgr_pwr_device_desc_table),
215 pwr_desc_table);
216
217 if (status) {
218 nvgpu_err(g, "pmgr_pmu_set_object failed %x",
219 status);
220 }